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Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
5 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +00006 * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
Carl-Daniel Hailfinger92242622007-09-27 14:29:57 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00008 *
Uwe Hermannd1107642007-08-29 17:52:32 +00009 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000012 *
Uwe Hermannd1107642007-08-29 17:52:32 +000013 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000017 */
18
19/*
20 * Contains the board specific flash enables.
21 */
22
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000023#include <strings.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000024#include <string.h>
Felix Singerd1ab7d22022-08-19 03:03:47 +020025#include <stdbool.h>
Stefan Taunerb4e06bd2012-08-20 00:24:22 +000026#include <stdlib.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000027#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000028#include "programmer.h"
Thomas Heijligend96c97c2021-11-02 21:03:00 +010029#include "platform/pci.h"
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000030
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000031#if defined(__i386__) || defined(__x86_64__)
Peter Marheinedf3672d2022-01-19 17:11:09 +110032
33#include "hwaccess_x86_io.h"
34#include "hwaccess_x86_msr.h"
35
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000036/*
Uwe Hermannffec5f32007-08-23 16:08:21 +000037 * Helper functions for many Winbond Super I/Os of the W836xx range.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000038 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000039/* Enter extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000040void w836xx_ext_enter(uint16_t port)
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000041{
Andriy Gapon65c1b862008-05-22 13:22:45 +000042 OUTB(0x87, port);
43 OUTB(0x87, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000044}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000045
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000046/* Leave extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000047void w836xx_ext_leave(uint16_t port)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000048{
Andriy Gapon65c1b862008-05-22 13:22:45 +000049 OUTB(0xAA, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000050}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000051
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000052/* Generic Super I/O helper functions */
53uint8_t sio_read(uint16_t port, uint8_t reg)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000054{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000055 OUTB(reg, port);
56 return INB(port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000057}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000058
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000059void sio_write(uint16_t port, uint8_t reg, uint8_t data)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000060{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000061 OUTB(reg, port);
62 OUTB(data, port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000063}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000064
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000065void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000066{
Ronald G. Minnichfa496922007-10-12 21:22:40 +000067 uint8_t tmp;
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000068
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000069 OUTB(reg, port);
70 tmp = INB(port + 1) & ~mask;
71 OUTB(tmp | (data & mask), port + 1);
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000072}
73
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +000074/* Winbond W83697 documentation indicates that the index register has to be written for each access. */
Jacob Garberbeeb8bc2019-06-21 15:24:17 -060075static void sio_mask_alzheimer(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +000076{
77 uint8_t tmp;
78
79 OUTB(reg, port);
80 tmp = INB(port + 1) & ~mask;
81 OUTB(reg, port);
82 OUTB(tmp | (data & mask), port + 1);
83}
84
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000085/* Not used yet. */
86#if 0
87static int enable_flash_decode_superio(void)
88{
89 int ret;
90 uint8_t tmp;
91
92 switch (superio.vendor) {
93 case SUPERIO_VENDOR_NONE:
94 ret = -1;
95 break;
96 case SUPERIO_VENDOR_ITE:
97 enter_conf_mode_ite(superio.port);
Uwe Hermann43959702010-03-13 17:28:29 +000098 /* Enable flash mapping. Works for most old ITE style Super I/O. */
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000099 tmp = sio_read(superio.port, 0x24);
100 tmp |= 0xfc;
101 sio_write(superio.port, 0x24, tmp);
102 exit_conf_mode_ite(superio.port);
103 ret = 0;
104 break;
105 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000106 msg_pdbg("Unhandled Super I/O type!\n");
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +0000107 ret = -1;
108 break;
109 }
110 return ret;
111}
112#endif
113
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000114/*
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000115 * SMSC FDC37B787: Raise GPIO50
116 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000117static int fdc37b787_gpio50_raise(uint16_t port)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000118{
119 uint8_t id, val;
120
121 OUTB(0x55, port); /* enter conf mode */
122 id = sio_read(port, 0x20);
123 if (id != 0x44) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000124 msg_perr("\nERROR: FDC37B787: Wrong ID 0x%02X.\n", id);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000125 OUTB(0xAA, port); /* leave conf mode */
126 return -1;
127 }
128
129 sio_write(port, 0x07, 0x08); /* Select Aux I/O subdevice */
130
131 val = sio_read(port, 0xC8); /* GP50 */
132 if ((val & 0x1B) != 0x10) /* output, no invert, GPIO */
133 {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000134 msg_perr("\nERROR: GPIO50 mode 0x%02X unexpected.\n", val);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000135 OUTB(0xAA, port);
136 return -1;
137 }
138
139 sio_mask(port, 0xF9, 0x01, 0x01);
140
141 OUTB(0xAA, port); /* Leave conf mode */
142 return 0;
143}
144
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000145/*
146 * Suited for:
147 * - Nokia IP530: Intel 440BX + PIIX4 + FDC37B787
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000148 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000149static int fdc37b787_gpio50_raise_3f0(void)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000150{
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000151 return fdc37b787_gpio50_raise(0x3f0);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000152}
153
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000154struct winbond_mux {
155 uint8_t reg; /* 0 if the corresponding pin is not muxed */
156 uint8_t data; /* reg/data/mask may be directly ... */
157 uint8_t mask; /* ... passed to sio_mask */
158};
159
160struct winbond_port {
161 const struct winbond_mux *mux; /* NULL or pointer to mux info for the 8 bits */
162 uint8_t ldn; /* LDN this GPIO register is located in */
Elyes HAOUAS124ef382018-03-27 12:15:09 +0200163 uint8_t enable_bit; /* bit in 0x30 of that LDN to enable
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000164 the GPIO port */
165 uint8_t base; /* base register in that LDN for the port */
166};
167
168struct winbond_chip {
169 uint8_t device_id; /* reg 0x20 of the expected w83626x */
170 uint8_t gpio_port_count;
171 const struct winbond_port *port;
172};
173
174
175#define UNIMPLEMENTED_PORT {NULL, 0, 0, 0}
176
177enum winbond_id {
178 WINBOND_W83627HF_ID = 0x52,
Michael Karcherea36c9c2010-06-27 15:07:52 +0000179 WINBOND_W83627EHF_ID = 0x88,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000180 WINBOND_W83627THF_ID = 0x82,
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000181 WINBOND_W83697HF_ID = 0x60,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000182};
183
184static const struct winbond_mux w83627hf_port2_mux[8] = {
185 {0x2A, 0x01, 0x01}, /* or MIDI */
186 {0x2B, 0x80, 0x80}, /* or SPI */
187 {0x2B, 0x40, 0x40}, /* or SPI */
188 {0x2B, 0x20, 0x20}, /* or power LED */
189 {0x2B, 0x10, 0x10}, /* or watchdog */
190 {0x2B, 0x08, 0x08}, /* or infra red */
191 {0x2B, 0x04, 0x04}, /* or infra red */
192 {0x2B, 0x03, 0x03} /* or IRQ1 input */
193};
194
195static const struct winbond_port w83627hf[3] = {
196 UNIMPLEMENTED_PORT,
197 {w83627hf_port2_mux, 0x08, 0, 0xF0},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000198 UNIMPLEMENTED_PORT,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000199};
200
Michael Karcherea36c9c2010-06-27 15:07:52 +0000201static const struct winbond_mux w83627ehf_port2_mux[8] = {
202 {0x29, 0x06, 0x02}, /* or MIDI */
203 {0x29, 0x06, 0x02},
204 {0x24, 0x02, 0x00}, /* or SPI ROM interface */
205 {0x24, 0x02, 0x00},
206 {0x2A, 0x01, 0x01}, /* or keyboard/mouse interface */
207 {0x2A, 0x01, 0x01},
208 {0x2A, 0x01, 0x01},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000209 {0x2A, 0x01, 0x01},
Michael Karcherea36c9c2010-06-27 15:07:52 +0000210};
211
212static const struct winbond_port w83627ehf[6] = {
213 UNIMPLEMENTED_PORT,
214 {w83627ehf_port2_mux, 0x09, 0, 0xE3},
215 UNIMPLEMENTED_PORT,
216 UNIMPLEMENTED_PORT,
217 UNIMPLEMENTED_PORT,
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000218 UNIMPLEMENTED_PORT,
Michael Karcherea36c9c2010-06-27 15:07:52 +0000219};
220
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000221static const struct winbond_mux w83627thf_port4_mux[8] = {
222 {0x2D, 0x01, 0x01}, /* or watchdog or VID level strap */
223 {0x2D, 0x02, 0x02}, /* or resume reset */
224 {0x2D, 0x04, 0x04}, /* or S3 input */
225 {0x2D, 0x08, 0x08}, /* or PSON# */
226 {0x2D, 0x10, 0x10}, /* or PWROK */
227 {0x2D, 0x20, 0x20}, /* or suspend LED */
228 {0x2D, 0x40, 0x40}, /* or panel switch input */
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000229 {0x2D, 0x80, 0x80}, /* or panel switch output */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000230};
231
232static const struct winbond_port w83627thf[5] = {
233 UNIMPLEMENTED_PORT, /* GPIO1 */
234 UNIMPLEMENTED_PORT, /* GPIO2 */
235 UNIMPLEMENTED_PORT, /* GPIO3 */
236 {w83627thf_port4_mux, 0x09, 1, 0xF4},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000237 UNIMPLEMENTED_PORT, /* GPIO5 */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000238};
239
240static const struct winbond_chip winbond_chips[] = {
241 {WINBOND_W83627HF_ID, ARRAY_SIZE(w83627hf), w83627hf },
Michael Karcherea36c9c2010-06-27 15:07:52 +0000242 {WINBOND_W83627EHF_ID, ARRAY_SIZE(w83627ehf), w83627ehf},
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000243 {WINBOND_W83627THF_ID, ARRAY_SIZE(w83627thf), w83627thf},
244};
245
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000246#define WINBOND_SUPERIO_PORT1 0x2e
247#define WINBOND_SUPERIO_PORT2 0x4e
248
249/* We don't really care about the hardware monitor, but it offers better (more specific) device ID info than
250 * the simple device ID in the normal configuration registers.
251 * Note: This function expects to be called while the Super I/O is in config mode.
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000252 */
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000253static uint8_t w836xx_deviceid_hwmon(uint16_t sio_port)
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000254{
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000255 uint16_t hwmport;
256 uint16_t hwm_vendorid;
257 uint8_t hwm_deviceid;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000258
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000259 sio_write(sio_port, 0x07, 0x0b); /* Select LDN 0xb (HWM). */
260 if ((sio_read(sio_port, 0x30) & (1 << 0)) != (1 << 0)) {
261 msg_pinfo("W836xx hardware monitor disabled or does not exist.\n");
262 return 0;
263 }
264 /* Get HWM base address (stored in LDN 0xb, index 0x60/0x61). */
265 hwmport = sio_read(sio_port, 0x60) << 8;
266 hwmport |= sio_read(sio_port, 0x61);
267 /* HWM address register = HWM base address + 5. */
268 hwmport += 5;
269 msg_pdbg2("W836xx Hardware Monitor at port %04x\n", hwmport);
270 /* FIXME: This busy check should happen before each HWM access. */
271 if (INB(hwmport) & 0x80) {
272 msg_pinfo("W836xx hardware monitor busy, ignoring it.\n");
273 return 0;
274 }
275 /* Set HBACS=1. */
276 sio_mask_alzheimer(hwmport, 0x4e, 0x80, 0x80);
277 /* Read upper byte of vendor ID. */
278 hwm_vendorid = sio_read(hwmport, 0x4f) << 8;
279 /* Set HBACS=0. */
280 sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x80);
281 /* Read lower byte of vendor ID. */
282 hwm_vendorid |= sio_read(hwmport, 0x4f);
283 if (hwm_vendorid != 0x5ca3) {
284 msg_pinfo("W836xx hardware monitor vendor ID weirdness: expected 0x5ca3, got %04x\n",
285 hwm_vendorid);
286 return 0;
287 }
288 /* Set Bank=0. */
289 sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x07);
290 /* Read "chip" ID. We call this one the device ID. */
291 hwm_deviceid = sio_read(hwmport, 0x58);
292 return hwm_deviceid;
293}
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000294
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000295void probe_superio_winbond(void)
296{
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +0000297 struct superio s = {0};
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000298 uint16_t winbond_ports[] = {WINBOND_SUPERIO_PORT1, WINBOND_SUPERIO_PORT2, 0};
299 uint16_t *i = winbond_ports;
300 uint8_t model;
301 uint8_t tmp;
302
303 s.vendor = SUPERIO_VENDOR_WINBOND;
304 for (; *i; i++) {
305 s.port = *i;
306 /* If we're already in Super I/O config more, the W836xx enter sequence won't hurt. */
307 w836xx_ext_enter(s.port);
308 model = sio_read(s.port, 0x20);
309 /* No response, no point leaving the config mode. */
310 if (model == 0xff)
311 continue;
312 /* Try to leave config mode. If the ID register is still readable, it's not a Winbond chip. */
313 w836xx_ext_leave(s.port);
314 if (model == sio_read(s.port, 0x20)) {
315 msg_pdbg("W836xx enter config mode worked or we were already in config mode. W836xx "
316 "leave config mode had no effect.\n");
317 if (model == 0x87) {
318 /* ITE IT8707F and IT8710F are special: They need the W837xx enter sequence,
319 * but they want the ITE exit sequence. Handle them here.
320 */
321 tmp = sio_read(s.port, 0x21);
322 switch (tmp) {
323 case 0x07:
324 case 0x10:
325 s.vendor = SUPERIO_VENDOR_ITE;
326 s.model = (0x87 << 8) | tmp ;
327 msg_pdbg("Found ITE Super I/O, ID 0x%04hx on port "
328 "0x%x\n", s.model, s.port);
329 register_superio(s);
330 /* Exit ITE config mode. */
331 exit_conf_mode_ite(s.port);
332 /* Restore vendor for next loop iteration. */
333 s.vendor = SUPERIO_VENDOR_WINBOND;
334 continue;
335 }
336 }
Stefan Tauner23e10b82016-01-23 16:16:49 +0000337 msg_pdbg("Active config mode, unknown reg 0x20 ID: %02x.\n", model);
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000338 continue;
Stefan Tauner23e10b82016-01-23 16:16:49 +0000339 }
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000340 /* The Super I/O reacts to W836xx enter and exit config mode, it's probably Winbond. */
341 w836xx_ext_enter(s.port);
342 s.model = sio_read(s.port, 0x20);
343 switch (s.model) {
344 case WINBOND_W83627HF_ID:
345 case WINBOND_W83627EHF_ID:
346 case WINBOND_W83627THF_ID:
Stefan Taunereb582572012-09-21 12:52:50 +0000347 msg_pdbg("Found Winbond Super I/O, id 0x%02hx\n", s.model);
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000348 register_superio(s);
349 break;
350 case WINBOND_W83697HF_ID:
351 /* This code is extremely paranoid. */
352 tmp = sio_read(s.port, 0x26) & 0x40;
353 if (((tmp == 0x00) && (s.port != WINBOND_SUPERIO_PORT1)) ||
354 ((tmp == 0x40) && (s.port != WINBOND_SUPERIO_PORT2))) {
355 msg_pdbg("Winbond Super I/O probe weirdness: Port mismatch for ID "
Stefan Taunereb582572012-09-21 12:52:50 +0000356 "0x%02x at port 0x%04x\n", s.model, s.port);
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000357 break;
358 }
359 tmp = w836xx_deviceid_hwmon(s.port);
360 /* FIXME: This might be too paranoid... */
361 if (!tmp) {
362 msg_pdbg("Probably not a Winbond Super I/O\n");
363 break;
364 }
365 if (tmp != s.model) {
Stefan Taunereb582572012-09-21 12:52:50 +0000366 msg_pinfo("W83 series hardware monitor device ID weirdness: expected 0x%02x, "
367 "got 0x%02x\n", WINBOND_W83697HF_ID, tmp);
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000368 break;
369 }
Stefan Taunereb582572012-09-21 12:52:50 +0000370 msg_pinfo("Found Winbond Super I/O, id 0x%02hx\n", s.model);
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000371 register_superio(s);
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000372 break;
373 }
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000374 w836xx_ext_leave(s.port);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000375 }
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000376 return;
377}
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000378
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000379static const struct winbond_chip *winbond_superio_chipdef(void)
380{
Nico Huber519be662018-12-23 20:03:35 +0100381 int i;
382 unsigned int j;
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000383
384 for (i = 0; i < superio_count; i++) {
385 if (superios[i].vendor != SUPERIO_VENDOR_WINBOND)
386 continue;
387 for (j = 0; j < ARRAY_SIZE(winbond_chips); j++)
388 if (winbond_chips[j].device_id == superios[i].model)
389 return &winbond_chips[j];
390 }
391 return NULL;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000392}
393
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000394/*
395 * The chipid parameter goes away as soon as we have Super I/O matching in the
396 * board enable table. The call to winbond_superio_detect() goes away as
397 * soon as we have generic Super I/O detection code.
398 */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000399static int winbond_gpio_set(uint16_t base, enum winbond_id chipid,
400 int pin, int raise)
401{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000402 const struct winbond_chip *chip = NULL;
403 const struct winbond_port *gpio;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000404 int port = pin / 10;
405 int bit = pin % 10;
406
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000407 chip = winbond_superio_chipdef();
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000408 if (!chip) {
409 msg_perr("\nERROR: No supported Winbond Super I/O found\n");
410 return -1;
411 }
Michael Karcher979d9252010-06-29 14:44:40 +0000412 if (chip->device_id != chipid) {
413 msg_perr("\nERROR: Found Winbond chip with ID 0x%x, "
414 "expected %x\n", chip->device_id, chipid);
415 return -1;
416 }
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000417 if (bit >= 8 || port == 0 || port > chip->gpio_port_count) {
418 msg_perr("\nERROR: winbond_gpio_set: Invalid GPIO number %d\n",
419 pin);
420 return -1;
421 }
422
423 gpio = &chip->port[port - 1];
424
425 if (gpio->ldn == 0) {
426 msg_perr("\nERROR: GPIO%d is not supported yet on this"
427 " winbond chip\n", port);
428 return -1;
429 }
430
431 w836xx_ext_enter(base);
432
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000433 /* Select logical device. */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000434 sio_write(base, 0x07, gpio->ldn);
435
436 /* Activate logical device. */
437 sio_mask(base, 0x30, 1 << gpio->enable_bit, 1 << gpio->enable_bit);
438
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000439 /* Select GPIO function of that pin. */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000440 if (gpio->mux && gpio->mux[bit].reg)
441 sio_mask(base, gpio->mux[bit].reg,
442 gpio->mux[bit].data, gpio->mux[bit].mask);
443
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000444 sio_mask(base, gpio->base + 0, 0, 1 << bit); /* Make pin output */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000445 sio_mask(base, gpio->base + 2, 0, 1 << bit); /* Clear inversion */
446 sio_mask(base, gpio->base + 1, raise << bit, 1 << bit);
447
448 w836xx_ext_leave(base);
449
450 return 0;
451}
452
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000453/*
Uwe Hermannffec5f32007-08-23 16:08:21 +0000454 * Winbond W83627HF: Raise GPIO24.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000455 *
456 * Suited for:
Uwe Hermannffec5f32007-08-23 16:08:21 +0000457 * - Agami Aruma
458 * - IWILL DK8-HTX
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000459 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000460static int w83627hf_gpio24_raise_2e(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000461{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000462 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 24, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000463}
464
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000465/*
Joshua Roysf280a382010-08-07 21:49:11 +0000466 * Winbond W83627HF: Raise GPIO25.
467 *
468 * Suited for:
469 * - MSI MS-6577
470 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000471static int w83627hf_gpio25_raise_2e(void)
Joshua Roysf280a382010-08-07 21:49:11 +0000472{
473 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 25, 1);
474}
475
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000476/*
Stefan Taunerff80e682011-07-20 16:34:18 +0000477 * Winbond W83627EHF: Raise GPIO22.
Michael Karcherea36c9c2010-06-27 15:07:52 +0000478 *
479 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000480 * - ASUS A8N-VM CSM: AMD Socket 939 + GeForce 6150 (C51) + MCP51
Michael Karcherea36c9c2010-06-27 15:07:52 +0000481 */
Stefan Taunerff80e682011-07-20 16:34:18 +0000482static int w83627ehf_gpio22_raise_2e(void)
Michael Karcherea36c9c2010-06-27 15:07:52 +0000483{
Stefan Taunerff80e682011-07-20 16:34:18 +0000484 return winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, 22, 1);
Michael Karcherea36c9c2010-06-27 15:07:52 +0000485}
486
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000487/*
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000488 * Winbond W83627THF: Raise GPIO 44.
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000489 *
490 * Suited for:
Stefan Taunerc2eec2c2014-05-03 21:33:01 +0000491 * - MSI K8T Neo2-F V2.0
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000492 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000493static int w83627thf_gpio44_raise_2e(void)
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000494{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000495 return winbond_gpio_set(0x2e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000496}
497
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000498/*
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000499 * Winbond W83627THF: Raise GPIO 44.
500 *
501 * Suited for:
502 * - MSI K8N Neo3
503 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000504static int w83627thf_gpio44_raise_4e(void)
Peter Stugecce26822008-07-21 17:48:40 +0000505{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000506 return winbond_gpio_set(0x4e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000507}
Uwe Hermann372eeb52007-12-04 21:49:06 +0000508
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000509/*
David Borgb6417a62010-08-02 08:29:34 +0000510 * Enable MEMW# and set ROM size to max.
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000511 * Supported chips: W83L517D, W83697HF/F/HG, W83697SF/UF/UG
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000512 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000513static void w836xx_memw_enable(uint16_t port)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000514{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000515 w836xx_ext_enter(port);
516 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000517 /* Enable MEMW# and set ROM size select to max. (4M). */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000518 sio_mask(port, 0x24, 0x28, 0x28);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000519 }
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000520 w836xx_ext_leave(port);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000521}
522
David Borgb02c62b2012-05-05 20:43:42 +0000523/**
524 * Enable MEMW# and set ROM size to max.
525 * Supported chips:
526 * W83697HF/F/HG, W83697SF/UF/UG
527 */
Jacob Garberbeeb8bc2019-06-21 15:24:17 -0600528static void w83697xx_memw_enable(uint16_t port)
David Borgb02c62b2012-05-05 20:43:42 +0000529{
530 w836xx_ext_enter(port);
531 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
532 if((sio_read(port, 0x2A) & 0xF0) == 0xF0) {
533
534 /* CR24 Bits 7 & 2 must be set to 0 enable the flash ROM */
535 /* address segments 000E0000h ~ 000FFFFFh on W83697SF/UF/UG */
Elyes HAOUASac01baa2018-05-28 16:52:21 +0200536 /* These bits are reserved on W83697HF/F/HG */
537 /* Shouldn't be needed though. */
David Borgb02c62b2012-05-05 20:43:42 +0000538
Elyes HAOUASac01baa2018-05-28 16:52:21 +0200539 /* CR28 Bit3 must be set to 1 to enable flash access to */
David Borgb02c62b2012-05-05 20:43:42 +0000540 /* FFE80000h ~ FFEFFFFFh on W83697SF/UF/UG. */
541 /* This bit is reserved on W83697HF/F/HG which default to 0 */
542 sio_mask(port, 0x28, 0x08, 0x08);
543
544 /* Enable MEMW# and set ROM size select to max. (4M)*/
545 sio_mask(port, 0x24, 0x28, 0x38);
546
547 } else {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +0000548 msg_pwarn("Warning: Flash interface in use by GPIO!\n");
David Borgb02c62b2012-05-05 20:43:42 +0000549 }
550 } else {
551 msg_pinfo("BIOS ROM is disabled\n");
Elyes HAOUAS124ef382018-03-27 12:15:09 +0200552 }
553 w836xx_ext_leave(port);
David Borgb02c62b2012-05-05 20:43:42 +0000554}
555
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000556/*
Luc Verhaegen73d21192009-12-23 00:54:26 +0000557 * Suited for:
Stefan Taunerb6304c12012-08-09 23:25:27 +0000558 * - Biostar M7VIQ: VIA KM266 + VT8235
559 */
560static int w83697xx_memw_enable_2e(void)
561{
562 w83697xx_memw_enable(0x2E);
563
564 return 0;
565}
566
567
568/*
569 * Suited for:
Tadas Slotkus3dcdc032012-08-25 03:53:12 +0000570 * - DFI AD77: VIA KT400 + VT8235 + W83697HF
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000571 * - EPoX EP-8K5A2: VIA KT333 + VT8235
572 * - Albatron PM266A Pro: VIA P4M266A + VT8235
573 * - Shuttle AK31 (all versions): VIA KT266 + VT8233
574 * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
575 * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237
Mattias Mattssone295eee2010-08-15 10:21:29 +0000576 * - MSI KM4M-V and KM4AM-V: VIA KM400/KM400A + VT8237
Mattias Mattssone8388242010-09-11 15:25:48 +0000577 * - MSI MS-6561 (745 Ultra): SiS 745 + W83697HF
Sergey A Lichackf3a4bff2010-09-07 18:14:53 +0000578 * - MSI MS-6787 (P4MAM-V/P4MAM-L): VIA P4M266 + VT8235
Uwe Hermann17da61e2010-10-05 21:48:43 +0000579 * - ASRock K7S41: SiS 741 + SiS 963 + W83697HF
Pawel Rozanski1d233072011-06-19 16:52:48 +0000580 * - ASRock K7S41GX: SiS 741GX + SiS 963L + W83697HF
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000581 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000582static int w836xx_memw_enable_2e(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000583{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000584 w836xx_memw_enable(0x2E);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000585
Luc Verhaegen73d21192009-12-23 00:54:26 +0000586 return 0;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000587}
588
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000589/*
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000590 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000591 * - Termtek TK-3370 (rev. 2.5b)
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000592 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000593static int w836xx_memw_enable_4e(void)
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000594{
595 w836xx_memw_enable(0x4E);
596
597 return 0;
598}
599
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000600/*
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000601 * Suited for all boards with ITE IT8705F.
602 * The SIS950 Super I/O probably requires a similar flash write enable.
Luc Verhaegen21f54962010-01-20 14:45:07 +0000603 */
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000604int it8705f_write_enable(uint8_t port)
Luc Verhaegen21f54962010-01-20 14:45:07 +0000605{
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000606 uint8_t tmp;
607 int ret = 0;
608
Nico Huber2e50cdc2018-09-23 20:20:26 +0200609 if (!(internal_buses_supported & BUS_PARALLEL))
610 return 1;
611
Luc Verhaegen21f54962010-01-20 14:45:07 +0000612 enter_conf_mode_ite(port);
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000613 tmp = sio_read(port, 0x24);
614 /* Check if at least one flash segment is enabled. */
615 if (tmp & 0xf0) {
616 /* The IT8705F will respond to LPC cycles and translate them. */
Nico Huber2e50cdc2018-09-23 20:20:26 +0200617 internal_buses_supported &= BUS_PARALLEL;
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000618 /* Flash ROM I/F Writes Enable */
619 tmp |= 0x04;
620 msg_pdbg("Enabling IT8705F flash ROM interface write.\n");
621 if (tmp & 0x02) {
622 /* The data sheet contradicts itself about max size. */
623 max_rom_decode.parallel = 1024 * 1024;
Stefan Taunerc2eec2c2014-05-03 21:33:01 +0000624 msg_pinfo("IT8705F with very unusual settings.\n"
Nico Huberac90af62022-12-18 00:22:47 +0000625 "Please send the output of \"flashrom -V -p internal\" to\n"
626 "flashrom-stable@flashrom.org with \"IT8705: your board name: flashrom -V\"\n"
627 "as the subject to help us finish support for your Super I/O. Thanks.\n");
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000628 ret = 1;
629 } else if (tmp & 0x08) {
630 max_rom_decode.parallel = 512 * 1024;
631 } else {
632 max_rom_decode.parallel = 256 * 1024;
633 }
634 /* Safety checks. The data sheet is unclear here: Segments 1+3
635 * overlap, no segment seems to cover top - 1MB to top - 512kB.
636 * We assume that certain combinations make no sense.
637 */
638 if (((tmp & 0x02) && !(tmp & 0x08)) || /* 1 MB en, 512 kB dis */
639 (!(tmp & 0x10)) || /* 128 kB dis */
640 (!(tmp & 0x40))) { /* 256/512 kB dis */
641 msg_perr("Inconsistent IT8705F decode size!\n");
642 ret = 1;
643 }
644 if (sio_read(port, 0x25) != 0) {
645 msg_perr("IT8705F flash data pins disabled!\n");
646 ret = 1;
647 }
648 if (sio_read(port, 0x26) != 0) {
649 msg_perr("IT8705F flash address pins 0-7 disabled!\n");
650 ret = 1;
651 }
652 if (sio_read(port, 0x27) != 0) {
653 msg_perr("IT8705F flash address pins 8-15 disabled!\n");
654 ret = 1;
655 }
656 if ((sio_read(port, 0x29) & 0x10) != 0) {
657 msg_perr("IT8705F flash write enable pin disabled!\n");
658 ret = 1;
659 }
660 if ((sio_read(port, 0x29) & 0x08) != 0) {
661 msg_perr("IT8705F flash chip select pin disabled!\n");
662 ret = 1;
663 }
664 if ((sio_read(port, 0x29) & 0x04) != 0) {
665 msg_perr("IT8705F flash read strobe pin disabled!\n");
666 ret = 1;
667 }
668 if ((sio_read(port, 0x29) & 0x03) != 0) {
669 msg_perr("IT8705F flash address pins 16-17 disabled!\n");
670 /* Not really an error if you use flash chips smaller
671 * than 256 kByte, but such a configuration is unlikely.
672 */
673 ret = 1;
674 }
675 msg_pdbg("Maximum IT8705F parallel flash decode size is %u.\n",
676 max_rom_decode.parallel);
677 if (ret) {
678 msg_pinfo("Not enabling IT8705F flash write.\n");
679 } else {
680 sio_write(port, 0x24, tmp);
681 }
682 } else {
683 msg_pdbg("No IT8705F flash segment enabled.\n");
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000684 ret = 0;
685 }
Luc Verhaegen21f54962010-01-20 14:45:07 +0000686 exit_conf_mode_ite(port);
687
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000688 return ret;
Luc Verhaegen21f54962010-01-20 14:45:07 +0000689}
Luc Verhaegen73d21192009-12-23 00:54:26 +0000690
Mattias Mattssonfb60cec2010-09-13 19:39:25 +0000691/*
692 * The ITE IT8707F is a custom chip made by ITE exclusively for ASUS.
693 * It uses the Winbond command sequence to enter extended configuration
694 * mode and the ITE sequence to exit.
695 *
696 * Registers seems similar to the ones on ITE IT8710F.
697 */
698static int it8707f_write_enable(uint8_t port)
699{
700 uint8_t tmp;
701
702 w836xx_ext_enter(port);
703
704 /* Set bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A rw */
705 tmp = sio_read(port, 0x23);
706 tmp |= (1 << 3);
707 sio_write(port, 0x23, tmp);
708
709 /* Set bit 2 (FLASH_WE) and bit 3 (FLASH_IF_EN) of reg 0x24 */
710 tmp = sio_read(port, 0x24);
711 tmp |= (1 << 2) | (1 << 3);
712 sio_write(port, 0x24, tmp);
713
714 /* Clear bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A ro */
715 tmp = sio_read(port, 0x23);
716 tmp &= ~(1 << 3);
717 sio_write(port, 0x23, tmp);
718
719 exit_conf_mode_ite(port);
720
721 return 0;
722}
723
724/*
725 * Suited for:
726 * - ASUS P4SC-E: SiS 651 + 962 + ITE IT8707F
727 */
728static int it8707f_write_enable_2e(void)
729{
730 return it8707f_write_enable(0x2e);
731}
732
Michael Karchercba52de2011-03-06 12:07:19 +0000733#define PC87360_ID 0xE1
734#define PC87364_ID 0xE4
735
736static int pc8736x_gpio_set(uint8_t chipid, uint8_t gpio, int raise)
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000737{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000738 static const int bankbase[] = {0, 4, 8, 10, 12};
739 int gpio_bank = gpio / 8;
740 int gpio_pin = gpio % 8;
741 uint16_t baseport;
742 uint8_t id, val;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000743
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000744 if (gpio_bank > 4) {
Michael Karchercba52de2011-03-06 12:07:19 +0000745 msg_perr("PC8736x: Invalid GPIO %d\n", gpio);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000746 return -1;
747 }
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000748
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000749 id = sio_read(0x2E, 0x20);
Michael Karchercba52de2011-03-06 12:07:19 +0000750 if (id != chipid) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000751 msg_perr("PC8736x: unexpected ID %02x (expected %02x)\n",
752 id, chipid);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000753 return -1;
754 }
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000755
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000756 sio_write(0x2E, 0x07, 0x07); /* Select GPIO device. */
757 baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
758 if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) {
759 msg_perr("PC87360: invalid GPIO base address %04x\n",
760 baseport);
761 return -1;
762 }
763 sio_mask (0x2E, 0x30, 0x01, 0x01); /* Enable logical device. */
764 sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin);
765 sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output. */
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000766
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000767 val = INB(baseport + bankbase[gpio_bank]);
768 if (raise)
769 val |= 1 << gpio_pin;
770 else
771 val &= ~(1 << gpio_pin);
772 OUTB(val, baseport + bankbase[gpio_bank]);
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000773
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000774 return 0;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000775}
776
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000777/*
778 * VIA VT823x: Set one of the GPIO pins.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000779 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000780static int via_vt823x_gpio_set(uint8_t gpio, int raise)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000781{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000782 struct pci_dev *dev;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000783 uint16_t base;
David Bartleyf58d3642009-12-09 07:53:01 +0000784 uint8_t val, bit, offset;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000785
Luc Verhaegen73d21192009-12-23 00:54:26 +0000786 dev = pci_dev_find_vendorclass(0x1106, 0x0601);
787 switch (dev->device_id) {
788 case 0x3177: /* VT8235 */
Helge Wagnerdd73d832012-08-24 23:03:46 +0000789 case 0x3227: /* VT8237/VT8237R */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000790 case 0x3337: /* VT8237A */
791 break;
792 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000793 msg_perr("\nERROR: VT823x ISA bridge not found.\n");
Luc Verhaegen73d21192009-12-23 00:54:26 +0000794 return -1;
795 }
796
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000797 if ((gpio >= 12) && (gpio <= 15)) {
798 /* GPIO12-15 -> output */
799 val = pci_read_byte(dev, 0xE4);
800 val |= 0x10;
801 pci_write_byte(dev, 0xE4, val);
802 } else if (gpio == 9) {
803 /* GPIO9 -> Output */
804 val = pci_read_byte(dev, 0xE4);
805 val |= 0x20;
806 pci_write_byte(dev, 0xE4, val);
David Bartleyf58d3642009-12-09 07:53:01 +0000807 } else if (gpio == 5) {
808 val = pci_read_byte(dev, 0xE4);
809 val |= 0x01;
810 pci_write_byte(dev, 0xE4, val);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000811 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000812 msg_perr("\nERROR: "
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000813 "VT823x GPIO%02d is not implemented.\n", gpio);
Luc Verhaegen73d21192009-12-23 00:54:26 +0000814 return -1;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000815 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000816
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000817 /* We need the I/O Base Address for this board's flash enable. */
818 base = pci_read_word(dev, 0x88) & 0xff80;
819
David Bartleyf58d3642009-12-09 07:53:01 +0000820 offset = 0x4C + gpio / 8;
821 bit = 0x01 << (gpio % 8);
822
823 val = INB(base + offset);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000824 if (raise)
825 val |= bit;
826 else
827 val &= ~bit;
David Bartleyf58d3642009-12-09 07:53:01 +0000828 OUTB(val, base + offset);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000829
Uwe Hermanna7e05482007-05-09 10:17:44 +0000830 return 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000831}
832
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000833/*
834 * Suited for:
835 * - ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000836 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000837static int via_vt823x_gpio5_raise(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000838{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000839 /* On M2V-MX: GPO5 is connected to WP# and TBL#. */
840 return via_vt823x_gpio_set(5, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000841}
842
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000843/*
844 * Suited for:
845 * - VIA EPIA EK & N & NL
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000846 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000847static int via_vt823x_gpio9_raise(void)
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000848{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000849 return via_vt823x_gpio_set(9, 1);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000850}
851
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000852/*
853 * Suited for:
854 * - VIA EPIA M and MII (and maybe other CLE266 based EPIAs)
Luc Verhaegen73d21192009-12-23 00:54:26 +0000855 *
856 * We don't need to do this for EPIA M when using coreboot, GPIO15 is never
857 * lowered there.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000858 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000859static int via_vt823x_gpio15_raise(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000860{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000861 return via_vt823x_gpio_set(15, 1);
862}
863
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000864/*
Luc Verhaegen73d21192009-12-23 00:54:26 +0000865 * Winbond W83697HF Super I/O + VIA VT8235 southbridge
866 *
867 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000868 * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
869 * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
Luc Verhaegen73d21192009-12-23 00:54:26 +0000870 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000871static int board_msi_kt4v(void)
Luc Verhaegen73d21192009-12-23 00:54:26 +0000872{
873 int ret;
874
875 ret = via_vt823x_gpio_set(12, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000876 w836xx_memw_enable(0x2E);
Luc Verhaegen97866082008-02-09 02:03:06 +0000877
Luc Verhaegen73d21192009-12-23 00:54:26 +0000878 return ret;
Luc Verhaegen97866082008-02-09 02:03:06 +0000879}
880
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000881/*
882 * Suited for:
Keith Hui91486202020-05-12 21:43:58 -0400883 * - ASUS P3B-F
884 *
885 * We are talking to a proprietary device on SMBus: the AS99127F which does
886 * much more than the Winbond W83781D it tries to be compatible with.
887 */
888static int board_asus_p3b_f(void)
889{
890 /*
891 * Find where the SMBus host is. ASUS sets it to 0xE800; coreboot sets it to 0x0F00.
892 */
893 struct pci_dev *dev;
894 uint16_t smbba;
895 uint8_t b;
896
897 dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4, PM/SMBus function. */
898 if (!dev) {
899 msg_perr("\nERROR: Intel PIIX4 PM not found.\n");
900 return -1;
901 }
902
903 smbba = pci_read_word(dev, 0x90) & 0xfff0;
904
905 OUTB(0xFF, smbba); /* Clear previous SMBus status. */
906 OUTB(0x48 << 1, smbba + 4);
907 OUTB(0x80, smbba + 3);
908 OUTB(0x80, smbba + 5);
909 OUTB(0x48, smbba + 2);
910
911 /* Wait until SMBus transaction is complete. */
912 b = 0x1;
913 while (b & 0x01) {
aaryac9c7d522022-03-13 00:05:56 +0530914 INB(0x80);
Keith Hui91486202020-05-12 21:43:58 -0400915 b = INB(smbba);
916 }
917
918 /* Write failed if any status is set. */
919 if (b & 0x1e) {
920 msg_perr("Failed to write to device.\n");
921 return -1;
922 }
923
924 return 0;
925}
926
927/*
928 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000929 * - ASUS P5A
Luc Verhaegen6b141752007-05-20 16:16:13 +0000930 *
931 * This is rather nasty code, but there's no way to do this cleanly.
932 * We're basically talking to some unknown device on SMBus, my guess
933 * is that it is the Winbond W83781D that lives near the DIP BIOS.
934 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000935static int board_asus_p5a(void)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000936{
937 uint8_t tmp;
938 int i;
939
940#define ASUSP5A_LOOP 5000
941
Andriy Gapon65c1b862008-05-22 13:22:45 +0000942 OUTB(0x00, 0xE807);
943 OUTB(0xEF, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000944
Andriy Gapon65c1b862008-05-22 13:22:45 +0000945 OUTB(0xFF, 0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000946
947 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000948 OUTB(0xE1, 0xFF);
949 if (INB(0xE800) & 0x04)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000950 break;
951 }
952
953 if (i == ASUSP5A_LOOP) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000954 msg_perr("Unable to contact device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000955 return -1;
956 }
957
Andriy Gapon65c1b862008-05-22 13:22:45 +0000958 OUTB(0x20, 0xE801);
959 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000960
Andriy Gapon65c1b862008-05-22 13:22:45 +0000961 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000962
963 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000964 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000965 if (tmp & 0x70)
966 break;
967 }
968
969 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000970 msg_perr("Failed to read device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000971 return -1;
972 }
973
Andriy Gapon65c1b862008-05-22 13:22:45 +0000974 tmp = INB(0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000975 tmp &= ~0x02;
976
Andriy Gapon65c1b862008-05-22 13:22:45 +0000977 OUTB(0x00, 0xE807);
978 OUTB(0xEE, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000979
Andriy Gapon65c1b862008-05-22 13:22:45 +0000980 OUTB(tmp, 0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000981
Andriy Gapon65c1b862008-05-22 13:22:45 +0000982 OUTB(0xFF, 0xE800);
983 OUTB(0xE1, 0xFF);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000984
Andriy Gapon65c1b862008-05-22 13:22:45 +0000985 OUTB(0x20, 0xE801);
986 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000987
Andriy Gapon65c1b862008-05-22 13:22:45 +0000988 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000989
990 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000991 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000992 if (tmp & 0x70)
993 break;
994 }
995
996 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000997 msg_perr("Failed to write to device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000998 return -1;
999 }
1000
1001 return 0;
1002}
1003
Luc Verhaegena7e30502009-12-09 11:39:02 +00001004/*
1005 * Set GPIO lines in the Broadcom HT-1000 southbridge.
1006 *
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001007 * It's not a Super I/O but it uses the same index/data port method.
Luc Verhaegena7e30502009-12-09 11:39:02 +00001008 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001009static int board_hp_dl145_g3_enable(void)
Luc Verhaegena7e30502009-12-09 11:39:02 +00001010{
1011 /* GPIO 0 reg from PM regs */
1012 /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
1013 sio_mask(0xcd6, 0x44, 0x24, 0x24);
1014
1015 return 0;
1016}
1017
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +00001018/*
1019 * Set GPIO lines in the Broadcom HT-1000 southbridge.
1020 *
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001021 * It's not a Super I/O but it uses the same index/data port method.
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +00001022 */
1023static int board_hp_dl165_g6_enable(void)
1024{
1025 /* Variant of DL145, with slightly different pin placement. */
1026 sio_mask(0xcd6, 0x44, 0x80, 0x80); /* TBL# */
1027 sio_mask(0xcd6, 0x46, 0x04, 0x04); /* WP# */
1028
1029 return 0;
1030}
1031
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001032static int board_ibm_x3455(void)
Stefan Reinauer1c283f42007-06-05 12:51:52 +00001033{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001034 /* Raise GPIO13. */
Carl-Daniel Hailfinger500b4232009-06-01 21:30:42 +00001035 sio_mask(0xcd6, 0x45, 0x20, 0x20);
Stefan Reinauer1c283f42007-06-05 12:51:52 +00001036
1037 return 0;
1038}
1039
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001040/*
1041 * Suited for:
Mattias Mattssonf4925162010-09-16 22:09:18 +00001042 * - Elitegroup GeForce6100SM-M: NVIDIA MCP61 + ITE IT8726F
1043 */
Mattias Mattssonf4925162010-09-16 22:09:18 +00001044static int board_ecs_geforce6100sm_m(void)
1045{
1046 struct pci_dev *dev;
1047 uint32_t tmp;
1048
1049 dev = pci_dev_find(0x10DE, 0x03EB); /* NVIDIA MCP61 SMBus. */
1050 if (!dev) {
1051 msg_perr("\nERROR: NVIDIA MCP61 SMBus not found.\n");
1052 return -1;
1053 }
1054
1055 tmp = pci_read_byte(dev, 0xE0);
1056 tmp &= ~(1 << 3);
1057 pci_write_byte(dev, 0xE0, tmp);
1058
1059 return 0;
1060}
1061
1062/*
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001063 * Very similar to AMD 8111 IO Hub.
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001064 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001065static int nvidia_mcp_gpio_set(int gpio, int raise)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001066{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001067 struct pci_dev *dev;
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001068 uint16_t base, devclass;
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001069 uint8_t tmp;
1070
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001071 if ((gpio < 0) || (gpio >= 0x40)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001072 msg_perr("\nERROR: unsupported GPIO: %d.\n", gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +00001073 return -1;
1074 }
1075
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001076 /* Check for the ISA bridge first. */
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001077 dev = pci_dev_find_vendorclass(0x10DE, 0x0601);
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001078 switch (dev->device_id) {
1079 case 0x0030: /* CK804 */
1080 case 0x0050: /* MCP04 */
1081 case 0x0060: /* MCP2 */
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001082 case 0x00E0: /* CK8 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001083 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +00001084 case 0x0260: /* MCP51 */
Michael Karcher242efd42011-03-06 12:09:05 +00001085 case 0x0261: /* MCP51 */
Joshua Roys6e48a022012-06-29 23:07:14 +00001086 case 0x0360: /* MCP55 */
Michael Karcher2ead2e22010-06-01 16:09:06 +00001087 case 0x0364: /* MCP55 */
1088 /* find SMBus controller on *this* southbridge */
1089 /* The infamous Tyan S2915-E has two south bridges; they are
Elyes HAOUAS124ef382018-03-27 12:15:09 +02001090 easily told apart from each other by the class of the
Michael Karcher2ead2e22010-06-01 16:09:06 +00001091 LPC bridge, but have the same SMBus bridge IDs */
1092 if (dev->func != 0) {
1093 msg_perr("MCP LPC bridge at unexpected function"
1094 " number %d\n", dev->func);
1095 return -1;
1096 }
1097
Stefan Tauner56734502015-02-08 21:58:04 +00001098#if !defined(OLD_PCI_GET_DEV)
Michael Karcher2ead2e22010-06-01 16:09:06 +00001099 dev = pci_get_dev(pacc, dev->domain, dev->bus, dev->dev, 1);
Carl-Daniel Hailfinger44cd9ab2010-07-17 22:28:05 +00001100#else
1101 /* pciutils/libpci before version 2.2 is too old to support
1102 * PCI domains. Such old machines usually don't have domains
1103 * besides domain 0, so this is not a problem.
1104 */
1105 dev = pci_get_dev(pacc, dev->bus, dev->dev, 1);
1106#endif
Michael Karcher2ead2e22010-06-01 16:09:06 +00001107 if (!dev) {
1108 msg_perr("MCP SMBus controller could not be found\n");
1109 return -1;
1110 }
1111 devclass = pci_read_word(dev, PCI_CLASS_DEVICE);
1112 if (devclass != 0x0C05) {
1113 msg_perr("Unexpected device class %04x for SMBus"
1114 " controller\n", devclass);
1115 return -1;
1116 }
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001117 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +00001118 default:
Sean Nelson316a29f2010-05-07 20:09:04 +00001119 msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n");
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001120 return -1;
1121 }
1122
1123 base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */
1124 base += 0xC0;
1125
1126 tmp = INB(base + gpio);
1127 tmp &= ~0x0F; /* null lower nibble */
1128 tmp |= 0x04; /* gpio -> output. */
1129 if (raise)
1130 tmp |= 0x01;
1131 OUTB(tmp, base + gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +00001132
1133 return 0;
1134}
1135
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001136/*
1137 * Suited for:
Stefan Taunera9cbbac2011-08-07 13:17:20 +00001138 * - ASUS A8M2N-LA (HP OEM "NodusM3-GL8E"): NVIDIA MCP51
Sean Nelson0a247512010-08-15 14:36:18 +00001139 * - ASUS A8N-LA (HP OEM "Nagami-GL8E"): NVIDIA MCP51
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001140 * - ASUS M2NBP-VM CSM: NVIDIA MCP51
Michael Karcherb2184c12010-03-07 16:42:55 +00001141 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001142static int nvidia_mcp_gpio0_raise(void)
Michael Karcherb2184c12010-03-07 16:42:55 +00001143{
1144 return nvidia_mcp_gpio_set(0x00, 1);
1145}
1146
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001147/*
1148 * Suited for:
1149 * - abit KN8 Ultra: NVIDIA CK804
Stefan Tauner74dc73f2015-03-01 22:04:38 +00001150 * - abit KN9 Ultra: NVIDIA MCP55
Sean Nelson92bc6bd2010-03-19 22:37:29 +00001151 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001152static int nvidia_mcp_gpio2_lower(void)
Sean Nelson92bc6bd2010-03-19 22:37:29 +00001153{
1154 return nvidia_mcp_gpio_set(0x02, 0);
1155}
1156
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001157/*
1158 * Suited for:
Michael Karcher2842db32011-04-14 23:14:27 +00001159 * - Foxconn 6150K8MD-8EKRSH: Socket 939 + NVIDIA MCP51
Stefan Taunerc2eec2c2014-05-03 21:33:01 +00001160 * - MSI K8N Neo4(-F/-FI/-FX/Platinum): NVIDIA CK804
Uwe Hermannead705f2010-08-15 15:26:30 +00001161 * - MSI K8NGM2-L: NVIDIA MCP51
Joshua Roys6e48a022012-06-29 23:07:14 +00001162 * - MSI K9N SLI: NVIDIA MCP55
Luc Verhaegen6c5f7332009-12-23 03:01:36 +00001163 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001164static int nvidia_mcp_gpio2_raise(void)
Luc Verhaegen6c5f7332009-12-23 03:01:36 +00001165{
1166 return nvidia_mcp_gpio_set(0x02, 1);
1167}
1168
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001169/*
1170 * Suited for:
Uwe Hermann83d349a2010-10-18 22:32:03 +00001171 * - EPoX EP-8NPA7I: Socket 754 + NVIDIA nForce4 4X
Jonathan Kollaschf8db9592010-10-15 23:02:15 +00001172 */
1173static int nvidia_mcp_gpio4_raise(void)
1174{
1175 return nvidia_mcp_gpio_set(0x04, 1);
1176}
1177
1178/*
1179 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001180 * - HP xw9400 (Tyan S2915-E OEM): Dual(!) NVIDIA MCP55
1181 *
1182 * Notes: a) There are two MCP55 chips, so also two SMBus bridges on that
1183 * board. We can't tell the SMBus logical devices apart, but we
1184 * can tell the LPC bridge functions apart.
1185 * We need to choose the SMBus bridge next to the LPC bridge with
1186 * ID 0x364 and the "LPC bridge" class.
1187 * b) #TBL is hardwired on that board to a pull-down. It can be
1188 * overridden by connecting the two solder points next to F2.
Michael Karcher2ead2e22010-06-01 16:09:06 +00001189 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001190static int nvidia_mcp_gpio5_raise(void)
Michael Karcher2ead2e22010-06-01 16:09:06 +00001191{
1192 return nvidia_mcp_gpio_set(0x05, 1);
1193}
1194
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001195/*
1196 * Suited for:
1197 * - abit NF7-S: NVIDIA CK804
Michael Karcher8f10d242010-04-11 21:01:06 +00001198 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001199static int nvidia_mcp_gpio8_raise(void)
Michael Karcher8f10d242010-04-11 21:01:06 +00001200{
1201 return nvidia_mcp_gpio_set(0x08, 1);
1202}
1203
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001204/*
1205 * Suited for:
Cristian Măgherușan-Stanciu9932c7b2011-07-07 19:56:58 +00001206 * - GIGABYTE GA-K8NS Pro-939: Socket 939 + NVIDIA nForce3 + CK8
Stefan Tauner23e10b82016-01-23 16:16:49 +00001207 * - Probably other versions of the GA-K8NS
Idwer Volleringd8a00a02011-06-13 16:58:54 +00001208 */
1209static int nvidia_mcp_gpio0a_raise(void)
1210{
1211 return nvidia_mcp_gpio_set(0x0a, 1);
1212}
1213
1214/*
1215 * Suited for:
Stefan Tauner33366a02012-09-15 15:51:09 +00001216 * - MSI K8N Neo Platinum: Socket 754 + nForce3 Ultra + CK8
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001217 * - MSI K8N Neo2 Platinum: Socket 939 + nForce3 Ultra + CK8
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001218 */
Michael Karcher51825082010-06-12 23:14:03 +00001219static int nvidia_mcp_gpio0c_raise(void)
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001220{
1221 return nvidia_mcp_gpio_set(0x0c, 1);
1222}
1223
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001224/*
1225 * Suited for:
1226 * - abit NF-M2 nView: Socket AM2 + NVIDIA MCP51
Michael Karcherefd8af32010-07-24 22:50:54 +00001227 */
1228static int nvidia_mcp_gpio4_lower(void)
1229{
1230 return nvidia_mcp_gpio_set(0x04, 0);
1231}
1232
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001233/*
1234 * Suited for:
1235 * - ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001236 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001237static int nvidia_mcp_gpio10_raise(void)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001238{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001239 return nvidia_mcp_gpio_set(0x10, 1);
1240}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001241
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001242/*
1243 * Suited for:
1244 * - GIGABYTE GA-K8N-SLI: AMD socket 939 + NVIDIA CK804 + ITE IT8712F
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001245 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001246static int nvidia_mcp_gpio21_raise(void)
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001247{
1248 return nvidia_mcp_gpio_set(0x21, 0x01);
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001249}
1250
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001251/*
1252 * Suited for:
1253 * - EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001254 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001255static int nvidia_mcp_gpio31_raise(void)
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001256{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001257 return nvidia_mcp_gpio_set(0x31, 0x01);
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001258}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001259
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001260/*
1261 * Suited for:
Michael Karcher242efd42011-03-06 12:09:05 +00001262 * - GIGABYTE GA-K8N51GMF: Socket 754 + Geforce 6100 + MCP51
1263 * - GIGABYTE GA-K8N51GMF-9: Socket 939 + Geforce 6100 + MCP51
Joshua Roys2ee137f2010-09-07 17:52:09 +00001264 */
1265static int nvidia_mcp_gpio3b_raise(void)
1266{
1267 return nvidia_mcp_gpio_set(0x3b, 1);
1268}
1269
1270/*
1271 * Suited for:
Joshua Roysb992d342011-11-02 14:31:18 +00001272 * - Sun Ultra 40 M2: Dual Socket F (1207) + MCP55
1273 */
1274static int board_sun_ultra_40_m2(void)
1275{
1276 int ret;
1277 uint8_t reg;
1278 uint16_t base;
1279 struct pci_dev *dev;
1280
1281 ret = nvidia_mcp_gpio4_lower();
1282 if (ret)
1283 return ret;
1284
1285 dev = pci_dev_find(0x10de, 0x0364); /* NVIDIA MCP55 LPC bridge */
1286 if (!dev) {
1287 msg_perr("\nERROR: NVIDIA MCP55 LPC bridge not found.\n");
1288 return -1;
1289 }
1290
1291 base = pci_read_word(dev, 0xb4); /* some IO BAR? */
1292 if (!base)
1293 return -1;
1294
1295 reg = INB(base + 0x4b);
1296 reg |= 0x10;
1297 OUTB(reg, base + 0x4b);
1298
1299 return 0;
1300}
1301
1302/*
1303 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001304 * - Artec Group DBE61 and DBE62
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001305 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001306static int board_artecgroup_dbe6x(void)
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001307{
1308#define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001309#define DBE6x_PRI_BOOT_LOC_SHIFT 2
1310#define DBE6x_BOOT_OP_LATCHED_SHIFT 8
1311#define DBE6x_SEC_BOOT_LOC_SHIFT 10
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001312#define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT)
1313#define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT)
1314#define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT)
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001315#define DBE6x_BOOT_LOC_FLASH 2
1316#define DBE6x_BOOT_LOC_FWHUB 3
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001317
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001318 msr_t msr;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001319 unsigned long boot_loc;
1320
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001321 /* Geode only has a single core */
1322 if (setup_cpu_msr(0))
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001323 return -1;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001324
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001325 msr = rdmsr(DBE6x_MSR_DIVIL_BALL_OPTS);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001326
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001327 if ((msr.lo & (DBE6x_BOOT_OP_LATCHED)) ==
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001328 (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT))
1329 boot_loc = DBE6x_BOOT_LOC_FWHUB;
1330 else
1331 boot_loc = DBE6x_BOOT_LOC_FLASH;
1332
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001333 msr.lo &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC);
1334 msr.lo |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) |
Uwe Hermann394131e2008-10-18 21:14:13 +00001335 (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001336
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001337 wrmsr(DBE6x_MSR_DIVIL_BALL_OPTS, msr);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001338
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001339 cleanup_cpu_msr();
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001340
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001341 return 0;
1342}
1343
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001344/*
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001345 * Suited for:
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001346 * - ASUS A8AE-LE (Codename AmberineM; used in Compaq Presario 061)
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001347 * Datasheet(s) used:
1348 * - AMD document 43009 "AMD SB700/710/750 Register Reference Guide" rev. 1.00
1349 */
1350static int amd_sbxxx_gpio9_raise(void)
1351{
1352 struct pci_dev *dev;
1353 uint32_t reg;
1354
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001355 dev = pci_dev_find(0x1002, 0x4372); /* AMD SMBus controller */
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001356 if (!dev) {
1357 msg_perr("\nERROR: AMD SMBus Controller (0x4372) not found.\n");
1358 return -1;
1359 }
1360
1361 reg = pci_read_long(dev, 0xA8); /* GPIO_12_to_4_Cntrl CI_Reg: A8h-ABh */
1362 /* enable output (0: enable, 1: tristate):
1363 GPIO9 output enable is at bit 5 in 0xA9 */
1364 reg &= ~((uint32_t)1<<(8+5));
1365 /* raise:
1366 GPIO9 output register is at bit 5 in 0xA8 */
1367 reg |= (1<<5);
1368 pci_write_long(dev, 0xA8, reg);
1369
1370 return 0;
1371}
1372
1373/*
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001374 * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}.
Luc Verhaegenf5226912009-12-14 10:41:58 +00001375 */
1376static int intel_piix4_gpo_set(unsigned int gpo, int raise)
1377{
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001378 unsigned int gpo_byte, gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001379 struct pci_dev *dev;
1380 uint32_t tmp, base;
1381
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001382 /* GPO{0,8,27,28,30} are always available. */
1383 static const uint32_t nonmuxed_gpos = 0x58000101;
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001384
1385 static const struct {unsigned int reg, mask, value; } piix4_gpo[] = {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001386 {0},
1387 {0xB0, 0x0001, 0x0000}, /* GPO1... */
1388 {0xB0, 0x0001, 0x0000},
1389 {0xB0, 0x0001, 0x0000},
1390 {0xB0, 0x0001, 0x0000},
1391 {0xB0, 0x0001, 0x0000},
1392 {0xB0, 0x0001, 0x0000},
1393 {0xB0, 0x0001, 0x0000}, /* ...GPO7: GENCFG bit 0 */
1394 {0},
1395 {0xB0, 0x0100, 0x0000}, /* GPO9: GENCFG bit 8 */
1396 {0xB0, 0x0200, 0x0000}, /* GPO10: GENCFG bit 9 */
1397 {0xB0, 0x0400, 0x0000}, /* GPO11: GENCFG bit 10 */
1398 {0x4E, 0x0100, 0x0000}, /* GPO12... */
1399 {0x4E, 0x0100, 0x0000},
1400 {0x4E, 0x0100, 0x0000}, /* ...GPO14: XBCS bit 8 */
1401 {0xB2, 0x0002, 0x0002}, /* GPO15... */
1402 {0xB2, 0x0002, 0x0002}, /* ...GPO16: GENCFG bit 17 */
1403 {0xB2, 0x0004, 0x0004}, /* GPO17: GENCFG bit 18 */
1404 {0xB2, 0x0008, 0x0008}, /* GPO18: GENCFG bit 19 */
1405 {0xB2, 0x0010, 0x0010}, /* GPO19: GENCFG bit 20 */
1406 {0xB2, 0x0020, 0x0020}, /* GPO20: GENCFG bit 21 */
1407 {0xB2, 0x0040, 0x0040}, /* GPO21: GENCFG bit 22 */
1408 {0xB2, 0x1000, 0x1000}, /* GPO22... */
1409 {0xB2, 0x1000, 0x1000}, /* ...GPO23: GENCFG bit 28 */
1410 {0xB2, 0x2000, 0x2000}, /* GPO24: GENCFG bit 29 */
1411 {0xB2, 0x4000, 0x4000}, /* GPO25: GENCFG bit 30 */
1412 {0xB2, 0x8000, 0x8000}, /* GPO26: GENCFG bit 31 */
1413 {0},
1414 {0},
1415 {0x4E, 0x0100, 0x0000}, /* ...GPO29: XBCS bit 8 */
1416 {0}
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001417 };
1418
Luc Verhaegenf5226912009-12-14 10:41:58 +00001419 dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */
1420 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001421 msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +00001422 return -1;
1423 }
1424
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001425 /* Sanity check. */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001426 if (gpo > 30) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001427 msg_perr("\nERROR: Intel PIIX4 has no GPO%d.\n", gpo);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001428 return -1;
1429 }
1430
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001431 if ((((1 << gpo) & nonmuxed_gpos) == 0) &&
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001432 ((pci_read_word(dev, piix4_gpo[gpo].reg) & piix4_gpo[gpo].mask) !=
1433 piix4_gpo[gpo].value)) {
1434 msg_perr("\nERROR: PIIX4 GPO%d not programmed for output.\n", gpo);
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001435 return -1;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001436 }
1437
Luc Verhaegenf5226912009-12-14 10:41:58 +00001438 dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */
1439 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001440 msg_perr("\nERROR: Intel PIIX4 PM not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +00001441 return -1;
1442 }
1443
1444 /* PM IO base */
1445 base = pci_read_long(dev, 0x40) & 0x0000FFC0;
1446
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001447 gpo_byte = gpo >> 3;
1448 gpo_bit = gpo & 7;
1449 tmp = INB(base + 0x34 + gpo_byte); /* GPO register */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001450 if (raise)
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001451 tmp |= 0x01 << gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001452 else
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001453 tmp &= ~(0x01 << gpo_bit);
1454 OUTB(tmp, base + 0x34 + gpo_byte);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001455
1456 return 0;
1457}
1458
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001459/*
1460 * Suited for:
Joshua Roysd708fad2012-02-17 14:51:15 +00001461 * - ASUS OPLX-M
Mattias Mattsson85016b92010-09-01 01:21:34 +00001462 * - ASUS P2B-N
1463 */
1464static int intel_piix4_gpo18_lower(void)
1465{
1466 return intel_piix4_gpo_set(18, 0);
1467}
1468
1469/*
1470 * Suited for:
Mattias Mattssonc8ca3de2010-09-13 18:22:36 +00001471 * - MSI MS-6163 v2 (MS-6163 Pro): Intel 440BX + PIIX4E + Winbond W83977EF
1472 */
1473static int intel_piix4_gpo14_raise(void)
1474{
1475 return intel_piix4_gpo_set(14, 1);
1476}
1477
1478/*
1479 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001480 * - EPoX EP-BX3
Luc Verhaegenf5226912009-12-14 10:41:58 +00001481 */
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001482static int intel_piix4_gpo22_raise(void)
Luc Verhaegenf5226912009-12-14 10:41:58 +00001483{
1484 return intel_piix4_gpo_set(22, 1);
1485}
1486
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001487/*
1488 * Suited for:
Tim ter Laak4b933f02010-09-13 23:00:57 +00001489 * - abit BM6
1490 */
1491static int intel_piix4_gpo26_lower(void)
1492{
1493 return intel_piix4_gpo_set(26, 0);
1494}
1495
1496/*
1497 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001498 * - Intel SE440BX-2
Michael Karcher51cd0c92010-03-19 22:35:21 +00001499 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001500static int intel_piix4_gpo27_lower(void)
Michael Karcher51cd0c92010-03-19 22:35:21 +00001501{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001502 return intel_piix4_gpo_set(27, 0);
Michael Karcher51cd0c92010-03-19 22:35:21 +00001503}
1504
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001505/*
Mattias Mattsson2eaad632010-10-05 21:32:29 +00001506 * Suited for:
1507 * - Dell OptiPlex GX1
1508 */
1509static int intel_piix4_gpo30_lower(void)
1510{
1511 return intel_piix4_gpo_set(30, 0);
1512}
1513
1514/*
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001515 * Set a GPIO line on a given Intel ICH LPC controller.
Uwe Hermann93f66db2008-05-22 21:19:38 +00001516 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001517static int intel_ich_gpio_set(int gpio, int raise)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001518{
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001519 /* Table mapping the different Intel ICH LPC chipsets. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001520 static struct {
1521 uint16_t id;
1522 uint8_t base_reg;
1523 uint32_t bank0;
1524 uint32_t bank1;
1525 uint32_t bank2;
1526 } intel_ich_gpio_table[] = {
1527 {0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */
1528 {0x2420, 0x58, 0x0FE30000, 0, 0}, /* 82801AB (ICH0) */
1529 {0x2440, 0x58, 0x1BFF391B, 0, 0}, /* 82801BA (ICH2) */
1530 {0x244C, 0x58, 0x1A23399B, 0, 0}, /* 82801BAM (ICH2M) */
1531 {0x2450, 0x58, 0x1BFF0000, 0, 0}, /* 82801E (C-ICH) */
1532 {0x2480, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801CA (ICH3-S) */
1533 {0x248C, 0x58, 0x1A230000, 0x00000FFF, 0}, /* 82801CAM (ICH3-M) */
1534 {0x24C0, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801DB/DBL (ICH4/ICH4-L) */
1535 {0x24CC, 0x58, 0x1A030000, 0x00000FFF, 0}, /* 82801DBM (ICH4-M) */
1536 {0x24D0, 0x58, 0x1BFF0000, 0x00030305, 0}, /* 82801EB/ER (ICH5/ICH5R) */
1537 {0x2640, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FB/FR (ICH6/ICH6R) */
1538 {0x2641, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FBM (ICH6M) */
Stefan Tauner309dd2c2013-11-21 15:59:52 +00001539 {0x27B0, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GDH (ICH7 DH) */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001540 {0x27B8, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GB/GR (ICH7 Family) */
1541 {0x27B9, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GBM (ICH7-M) */
1542 {0x27BD, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GHM (ICH7-M DH) */
1543 {0x2810, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HB/HR (ICH8/R) */
1544 {0x2811, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HBM (ICH8M-E) */
1545 {0x2812, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HH (ICH8DH) */
1546 {0x2814, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HO (ICH8DO) */
1547 {0x2815, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HEM (ICH8M) */
1548 {0x2912, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IH (ICH9DH) */
1549 {0x2914, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IO (ICH9DO) */
1550 {0x2916, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IR (ICH9R) */
1551 {0x2917, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IEM (ICH9M-E) */
1552 {0x2918, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IB (ICH9) */
1553 {0x2919, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IBM (ICH9M) */
1554 {0x3A14, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JDO (ICH10DO) */
1555 {0x3A16, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIR (ICH10R) */
1556 {0x3A18, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIB (ICH10) */
1557 {0x3A1A, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JD (ICH10D) */
1558 {0, 0, 0, 0, 0} /* end marker */
1559 };
Uwe Hermann93f66db2008-05-22 21:19:38 +00001560
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001561 struct pci_dev *dev;
1562 uint16_t base;
1563 uint32_t tmp;
1564 int i, allowed;
1565
1566 /* First, look for a known LPC bridge */
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001567 for (dev = pacc->devices; dev; dev = dev->next) {
Nico Huber380090f2022-05-23 01:45:11 +02001568 pci_fill_info(dev, PCI_FILL_IDENT);
Carl-Daniel Hailfingerd175e062010-05-21 23:00:56 +00001569 uint16_t device_class;
1570 /* libpci before version 2.2.4 does not store class info. */
1571 device_class = pci_read_word(dev, PCI_CLASS_DEVICE);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001572 if ((dev->vendor_id == 0x8086) &&
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001573 (device_class == 0x0601)) { /* ISA bridge */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001574 /* Is this device in our list? */
1575 for (i = 0; intel_ich_gpio_table[i].id; i++)
1576 if (dev->device_id == intel_ich_gpio_table[i].id)
1577 break;
1578
1579 if (intel_ich_gpio_table[i].id)
1580 break;
1581 }
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001582 }
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001583
Uwe Hermann93f66db2008-05-22 21:19:38 +00001584 if (!dev) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001585 msg_perr("\nERROR: No known Intel LPC bridge found.\n");
Uwe Hermann93f66db2008-05-22 21:19:38 +00001586 return -1;
1587 }
1588
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001589 /*
1590 * According to the datasheets, all Intel ICHs have the GPIO bar 5:1
1591 * strapped to zero. From some mobile ICH9 version on, this becomes
1592 * 6:1. The mask below catches all.
1593 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001594 base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0;
Uwe Hermann93f66db2008-05-22 21:19:38 +00001595
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001596 /* Check whether the line is allowed. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001597 if (gpio < 32)
1598 allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01;
1599 else if (gpio < 64)
1600 allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01;
1601 else
1602 allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01;
1603
1604 if (!allowed) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001605 msg_perr("\nERROR: This Intel LPC bridge does not allow"
1606 " setting GPIO%02d\n", gpio);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001607 return -1;
1608 }
1609
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001610 msg_pdbg("\nIntel ICH LPC bridge: %sing GPIO%02d.\n",
1611 raise ? "Rais" : "Dropp", gpio);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001612
1613 if (gpio < 32) {
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001614 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001615 tmp = INL(base);
1616 /* ICH/ICH0 multiplexes 27/28 on the line set. */
1617 if ((gpio == 28) &&
1618 ((dev->device_id == 0x2410) || (dev->device_id == 0x2420)))
1619 tmp |= 1 << 27;
1620 else
1621 tmp |= 1 << gpio;
1622 OUTL(tmp, base);
1623
1624 /* As soon as we are talking to ICH8 and above, this register
1625 decides whether we can set the gpio or not. */
1626 if (dev->device_id > 0x2800) {
1627 tmp = INL(base);
1628 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001629 msg_perr("\nERROR: This Intel LPC bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001630 " does not allow setting GPIO%02d\n",
1631 gpio);
1632 return -1;
1633 }
1634 }
1635
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001636 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001637 tmp = INL(base + 0x04);
1638 tmp &= ~(1 << gpio);
1639 OUTL(tmp, base + 0x04);
1640
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001641 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001642 tmp = INL(base + 0x0C);
1643 if (raise)
1644 tmp |= 1 << gpio;
1645 else
1646 tmp &= ~(1 << gpio);
1647 OUTL(tmp, base + 0x0C);
1648 } else if (gpio < 64) {
1649 gpio -= 32;
1650
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001651 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001652 tmp = INL(base + 0x30);
1653 tmp |= 1 << gpio;
1654 OUTL(tmp, base + 0x30);
1655
1656 /* As soon as we are talking to ICH8 and above, this register
1657 decides whether we can set the gpio or not. */
1658 if (dev->device_id > 0x2800) {
1659 tmp = INL(base + 30);
1660 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001661 msg_perr("\nERROR: This Intel LPC bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001662 " does not allow setting GPIO%02d\n",
1663 gpio + 32);
1664 return -1;
1665 }
1666 }
1667
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001668 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001669 tmp = INL(base + 0x34);
1670 tmp &= ~(1 << gpio);
1671 OUTL(tmp, base + 0x34);
1672
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001673 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001674 tmp = INL(base + 0x38);
1675 if (raise)
1676 tmp |= 1 << gpio;
1677 else
1678 tmp &= ~(1 << gpio);
1679 OUTL(tmp, base + 0x38);
1680 } else {
1681 gpio -= 64;
1682
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001683 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001684 tmp = INL(base + 0x40);
1685 tmp |= 1 << gpio;
1686 OUTL(tmp, base + 0x40);
1687
1688 tmp = INL(base + 40);
1689 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001690 msg_perr("\nERROR: This Intel LPC bridge does "
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001691 "not allow setting GPIO%02d\n", gpio + 64);
1692 return -1;
1693 }
1694
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001695 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001696 tmp = INL(base + 0x44);
1697 tmp &= ~(1 << gpio);
1698 OUTL(tmp, base + 0x44);
1699
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001700 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001701 tmp = INL(base + 0x48);
1702 if (raise)
1703 tmp |= 1 << gpio;
1704 else
1705 tmp &= ~(1 << gpio);
1706 OUTL(tmp, base + 0x48);
1707 }
Uwe Hermann93f66db2008-05-22 21:19:38 +00001708
1709 return 0;
1710}
1711
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001712/*
1713 * Suited for:
1714 * - abit IP35: Intel P35 + ICH9R
1715 * - abit IP35 Pro: Intel P35 + ICH9R
Joshua Roysac8b2a12011-08-11 04:21:34 +00001716 * - ASUS P5LD2
Dima Veselov9d8f53d2014-07-14 18:04:15 +00001717 * - ASUS P5LD2-MQ
Idwer Vollering4d0cde12012-09-07 08:27:46 +00001718 * - ASUS P5LD2-VM
Stefan Tauner309dd2c2013-11-21 15:59:52 +00001719 * - ASUS P5LD2-VM DH
Tasos Sahanidis58cf5192022-04-20 09:30:42 +03001720 * - ASUS P5W DH Deluxe
Uwe Hermann93f66db2008-05-22 21:19:38 +00001721 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001722static int intel_ich_gpio16_raise(void)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001723{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001724 return intel_ich_gpio_set(16, 1);
Uwe Hermann93f66db2008-05-22 21:19:38 +00001725}
1726
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001727/*
1728 * Suited for:
1729 * - HP Puffer2-UL8E (ASUS PTGD-LA OEM): LGA775 + 915 + ICH6
Michael Karchere57957c2010-07-24 11:14:37 +00001730 */
1731static int intel_ich_gpio18_raise(void)
1732{
1733 return intel_ich_gpio_set(18, 1);
1734}
1735
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001736/*
1737 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001738 * - MSI MS-7046: LGA775 + 915P + ICH6
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001739 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001740static int intel_ich_gpio19_raise(void)
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001741{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001742 return intel_ich_gpio_set(19, 1);
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001743}
1744
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001745/*
Luc Verhaegen6c5d4cc2009-11-28 18:26:21 +00001746 * Suited for:
Stefan Tauner027e0182012-05-02 19:48:21 +00001747 * - ASUS P5BV-R: LGA775 + 3200 + ICH7
Luc Verhaegen3f7e3412018-03-28 12:31:22 +02001748 * - AOpen i965GMt-LA: Intel Socket479 + 965GM + ICH8M
Stefan Tauner027e0182012-05-02 19:48:21 +00001749 */
1750static int intel_ich_gpio20_raise(void)
1751{
1752 return intel_ich_gpio_set(20, 1);
1753}
1754
1755/*
1756 * Suited for:
Stefan Taunereb582572012-09-21 12:52:50 +00001757 * - ASUS CUSL2-C: Intel socket370 + 815 + ICH2
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001758 * - ASUS P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2
1759 * - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5
Michael Karcherf4b58792010-09-10 14:54:18 +00001760 * - ASUS P4P800: Intel socket478 + 865PE + ICH5R
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001761 * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R
Diego Elio Pettenòc6f71462011-03-06 22:52:55 +00001762 * - ASUS P4P800-VM: Intel socket478 + 865PE + ICH5R
Stefan Taunereb582572012-09-21 12:52:50 +00001763 * - ASUS P4P800-X: Intel socket478 + 865PE + ICH5R
Miklós Mártonde77ad42019-08-06 22:43:19 +02001764 * - ASUS P4P800SE: Intel socket478 + 865PE + ICH5R
Michael Karcher4a23e442010-09-10 14:46:46 +00001765 * - ASUS P5GD1 Pro: Intel LGA 775 + 915P + ICH6R
Joshua Roys1fd4f9e2011-08-11 05:47:32 +00001766 * - ASUS P5GD2 Premium: Intel LGA775 + 915G + ICH6R
Joshua Roysb1d980f2010-09-13 14:02:22 +00001767 * - ASUS P5GDC Deluxe: Intel socket775 + 915P + ICH6R
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001768 * - ASUS P5PE-VM: Intel LGA775 + 865G + ICH5
Stefan Taunerded71e52012-03-10 19:22:13 +00001769 * - ASUS TUSL2-C: Intel socket370 + 815 + ICH2
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001770 * - Samsung Polaris 32: socket478 + 865P + ICH5
Peter Stuge09c13332009-02-02 22:55:26 +00001771 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001772static int intel_ich_gpio21_raise(void)
Peter Stuge09c13332009-02-02 22:55:26 +00001773{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001774 return intel_ich_gpio_set(21, 1);
Peter Stuge09c13332009-02-02 22:55:26 +00001775}
1776
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001777/*
Michael Karcher03b80e92010-03-07 16:32:32 +00001778 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001779 * - ASUS P4B266: socket478 + Intel 845D + ICH2
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001780 * - ASUS P4B533-E: socket478 + 845E + ICH4
1781 * - ASUS P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2
Michael Karcherbfd89a52012-02-12 00:13:14 +00001782 * - TriGem Anaheim-3: socket370 + Intel 810 + ICH
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001783 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001784static int intel_ich_gpio22_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001785{
1786 return intel_ich_gpio_set(22, 1);
1787}
1788
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001789/*
1790 * Suited for:
Stefan Tauner716e0982011-07-25 20:38:52 +00001791 * - ASUS A8Jm (laptop): Intel 945 + ICH7
Michael Karcher14ab8d42011-08-25 14:06:50 +00001792 * - ASUS P5LP-LE used in ...
1793 * - HP Media Center m7270.fr Desktop PC as "Lithium-UL8E"
1794 * - Epson Endeavor MT7700
Stefan Tauner716e0982011-07-25 20:38:52 +00001795 */
1796static int intel_ich_gpio34_raise(void)
1797{
1798 return intel_ich_gpio_set(34, 1);
1799}
1800
1801/*
1802 * Suited for:
Stefan Taunerc6782182012-01-19 17:50:32 +00001803 * - AOpen i945GMx-VFX: Intel 945GM + ICH7-M used in ...
Paul Menzelac427b22012-02-16 21:07:07 +00001804 * - FSC ESPRIMO Q5010 (SMBIOS: D2544-B1)
Stefan Taunerc6782182012-01-19 17:50:32 +00001805 */
1806static int intel_ich_gpio38_raise(void)
1807{
1808 return intel_ich_gpio_set(38, 1);
1809}
1810
1811/*
1812 * Suited for:
Joshua Roysc73e2812011-07-09 19:46:53 +00001813 * - ASUS M6Ne (laptop): socket 479M (guessed) + Intel 855PM + ICH4-M
1814 */
1815static int intel_ich_gpio43_raise(void)
1816{
1817 return intel_ich_gpio_set(43, 1);
1818}
1819
1820/*
1821 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001822 * - HP Vectra VL400: 815 + ICH + PC87360
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001823 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001824static int board_hp_vl400(void)
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001825{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001826 int ret;
1827 ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */
1828 if (!ret)
Michael Karchercba52de2011-03-06 12:07:19 +00001829 ret = pc8736x_gpio_set(PC87360_ID, 0x09, 1); /* #WP ? */
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001830 if (!ret)
Michael Karchercba52de2011-03-06 12:07:19 +00001831 ret = pc8736x_gpio_set(PC87360_ID, 0x27, 1); /* #TBL */
1832 return ret;
1833}
1834
1835/*
1836 * Suited for:
1837 * - HP e-Vectra P2706T: 810E + ICH + PC87364
1838 */
1839static int board_hp_p2706t(void)
1840{
1841 int ret;
1842 ret = pc8736x_gpio_set(PC87364_ID, 0x25, 1);
1843 if (!ret)
1844 ret = pc8736x_gpio_set(PC87364_ID, 0x26, 1);
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001845 return ret;
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001846}
1847
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001848/*
Luc Verhaegen1265d8d2009-11-28 18:16:31 +00001849 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001850 * - Dell PowerEdge 1850: Intel PPGA604 + E7520 + ICH5R
1851 * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R
1852 * - ASRock 775i65G: Intel LGA 775 + 865G + ICH5
Uwe Hermann742999c2010-12-02 21:57:42 +00001853 * - MSI MS-6391 (845 Pro4): Intel Socket478 + 845 + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001854 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001855static int intel_ich_gpio23_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001856{
1857 return intel_ich_gpio_set(23, 1);
1858}
1859
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001860/*
1861 * Suited for:
Michael Karcher39dcdec2010-10-05 17:29:35 +00001862 * - GIGABYTE GA-6IEM: Intel Socket370 + i815 + ICH2
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001863 * - GIGABYTE GA-8IRML: Intel Socket478 + i845 + ICH2
Michael Karcherc7a1ffb2010-07-24 22:27:29 +00001864 */
1865static int intel_ich_gpio25_raise(void)
1866{
1867 return intel_ich_gpio_set(25, 1);
1868}
1869
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001870/*
1871 * Suited for:
1872 * - IBASE MB899: i945GM + ICH7
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001873 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001874static int intel_ich_gpio26_raise(void)
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001875{
1876 return intel_ich_gpio_set(26, 1);
1877}
1878
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001879/*
1880 * Suited for:
Stefan Tauner98546c92012-11-05 12:20:29 +00001881 * - ASUS DSAN-DX
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001882 * - P4SD-LA (HP OEM): i865 + ICH5
Joshua Roys9d9a1042011-06-13 16:59:01 +00001883 * - GIGABYTE GA-8IP775: 865P + ICH5
Michael Karcherc8613242010-08-13 12:49:01 +00001884 * - GIGABYTE GA-8PE667 Ultra 2: socket 478 + i845PE + ICH4
Maciej Pijanka6add0942011-06-09 20:59:30 +00001885 * - MSI MS-6788-40 (aka 848P Neo-V)
Michael Karcher87c90992010-07-24 11:03:48 +00001886 */
Idwer Vollering19dceac2010-07-24 18:47:45 +00001887static int intel_ich_gpio32_raise(void)
Michael Karcher87c90992010-07-24 11:03:48 +00001888{
1889 return intel_ich_gpio_set(32, 1);
1890}
1891
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001892/*
1893 * Suited for:
Joshua Roys7225ccd2011-05-18 01:32:16 +00001894 * - AOpen i975Xa-YDG: i975X + ICH7 + W83627EHF
1895 */
1896static int board_aopen_i975xa_ydg(void)
1897{
1898 int ret;
1899
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001900 /* Vendor BIOS ends up in LDN6... maybe the board enable is wrong,
Joshua Roys7225ccd2011-05-18 01:32:16 +00001901 * or perhaps it's not needed at all?
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001902 * The regs it tries to touch are 0xF0, 0xF1, 0xF2 which means if it
1903 * were in the right LDN, it would have to be GPIO1 or GPIO3.
Joshua Roys7225ccd2011-05-18 01:32:16 +00001904 */
1905/*
1906 ret = winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, x, 0)
1907 if (!ret)
1908*/
1909 ret = intel_ich_gpio_set(33, 1);
1910
1911 return ret;
1912}
1913
1914/*
1915 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001916 * - Acorp 6A815EPD: socket 370 + intel 815 + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001917 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001918static int board_acorp_6a815epd(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001919{
1920 int ret;
1921
1922 /* Lower Blocks Lock -- pin 7 of PLCC32 */
1923 ret = intel_ich_gpio_set(22, 1);
1924 if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */
1925 ret = intel_ich_gpio_set(23, 1);
1926
1927 return ret;
1928}
1929
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001930/*
1931 * Suited for:
1932 * - Kontron 986LCD-M: Socket478 + 915GM + ICH7R
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001933 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001934static int board_kontron_986lcd_m(void)
Stefan Reinauerac378972008-03-17 22:59:40 +00001935{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001936 int ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001937
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001938 ret = intel_ich_gpio_set(34, 1); /* #TBL */
1939 if (!ret)
1940 ret = intel_ich_gpio_set(35, 1); /* #WP */
Stefan Reinauerac378972008-03-17 22:59:40 +00001941
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001942 return ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001943}
1944
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001945/*
1946 * Suited for:
1947 * - Soyo SY-7VCA: Pro133A + VT82C686
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001948 */
Michael Karcher06477332010-03-19 22:49:09 +00001949static int via_apollo_gpo_set(int gpio, int raise)
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001950{
Michael Karcher06477332010-03-19 22:49:09 +00001951 struct pci_dev *dev;
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001952 uint32_t base, tmp;
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001953
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001954 /* VT82C686 power management */
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001955 dev = pci_dev_find(0x1106, 0x3057);
1956 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001957 msg_perr("\nERROR: VT82C686 PM device not found.\n");
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001958 return -1;
1959 }
1960
Sean Nelson316a29f2010-05-07 20:09:04 +00001961 msg_pdbg("\nVIA Apollo ACPI: %sing GPIO%02d.\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001962 raise ? "Rais" : "Dropp", gpio);
Michael Karcher06477332010-03-19 22:49:09 +00001963
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001964 /* Select GPO function on multiplexed pins. */
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001965 tmp = pci_read_byte(dev, 0x54);
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001966 switch (gpio) {
1967 case 0:
1968 tmp &= ~0x03;
1969 break;
1970 case 1:
1971 tmp |= 0x04;
1972 break;
1973 case 2:
1974 tmp |= 0x08;
1975 break;
1976 case 3:
1977 tmp |= 0x10;
1978 break;
Michael Karcher06477332010-03-19 22:49:09 +00001979 }
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001980 pci_write_byte(dev, 0x54, tmp);
1981
1982 /* PM IO base */
1983 base = pci_read_long(dev, 0x48) & 0x0000FF00;
1984
1985 /* Drop GPO0 */
Michael Karcher06477332010-03-19 22:49:09 +00001986 tmp = INL(base + 0x4C);
1987 if (raise)
1988 tmp |= 1U << gpio;
1989 else
1990 tmp &= ~(1U << gpio);
1991 OUTL(tmp, base + 0x4C);
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001992
1993 return 0;
1994}
1995
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001996/*
1997 * Suited for:
1998 * - abit VT6X4: Pro133x + VT82C686A
Mattias Mattssone3df96e2010-08-15 22:43:23 +00001999 * - abit VA6: Pro133x + VT82C686A
Michael Karcher187a46a2010-03-19 22:30:49 +00002000 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00002001static int via_apollo_gpo4_lower(void)
Michael Karcher187a46a2010-03-19 22:30:49 +00002002{
2003 return via_apollo_gpo_set(4, 0);
2004}
2005
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002006/*
2007 * Suited for:
2008 * - Soyo SY-7VCA: Pro133A + VT82C686
Michael Karcher06477332010-03-19 22:49:09 +00002009 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00002010static int via_apollo_gpo0_lower(void)
Michael Karcher06477332010-03-19 22:49:09 +00002011{
2012 return via_apollo_gpo_set(0, 0);
2013}
2014
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002015/*
Michael Karchera08d0f22011-07-25 17:25:24 +00002016 * Enable some GPIO pin on SiS southbridge and enables SIO flash writes.
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002017 *
2018 * Suited for:
2019 * - MSI 651M-L: SiS651 / SiS962
Stefan Tauner7fbbbb82014-11-30 22:31:12 +00002020 * - GIGABYTE GA-8SIMLFS 2.0
Michael Karchera08d0f22011-07-25 17:25:24 +00002021 * - GIGABYTE GA-8SIMLH
Michael Karcher9f9e6132010-01-09 17:36:06 +00002022 */
Michael Karchera08d0f22011-07-25 17:25:24 +00002023static int sis_gpio0_raise_and_w836xx_memw(void)
Michael Karcher9f9e6132010-01-09 17:36:06 +00002024{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002025 struct pci_dev *dev;
Uwe Hermann43959702010-03-13 17:28:29 +00002026 uint16_t base, temp;
Michael Karcher9f9e6132010-01-09 17:36:06 +00002027
2028 dev = pci_dev_find(0x1039, 0x0962);
2029 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002030 msg_perr("Expected south bridge not found\n");
Michael Karcher9f9e6132010-01-09 17:36:06 +00002031 return 1;
2032 }
2033
Michael Karcher9f9e6132010-01-09 17:36:06 +00002034 base = pci_read_word(dev, 0x74);
2035 temp = INW(base + 0x68);
2036 temp &= ~(1 << 0); /* Make pin output? */
Michael Karcher0435dfd2010-01-09 23:31:13 +00002037 OUTW(temp, base + 0x68);
Michael Karcher9f9e6132010-01-09 17:36:06 +00002038
2039 temp = INW(base + 0x64);
2040 temp |= (1 << 0); /* Raise output? */
2041 OUTW(temp, base + 0x64);
2042
2043 w836xx_memw_enable(0x2E);
2044
2045 return 0;
2046}
2047
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002048/*
Michael Gold6d52e472009-06-19 13:00:24 +00002049 * Find the runtime registers of an SMSC Super I/O, after verifying its
2050 * chip ID.
2051 *
2052 * Returns the base port of the runtime register block, or 0 on error.
2053 */
2054static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id,
2055 uint8_t logical_device)
2056{
2057 uint16_t rt_port = 0;
2058
2059 /* Verify the chip ID. */
Uwe Hermann1432a602009-06-28 23:26:37 +00002060 OUTB(0x55, sio_port); /* Enable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00002061 if (sio_read(sio_port, 0x20) != chip_id) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002062 msg_perr("\nERROR: SMSC Super I/O not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +00002063 goto out;
2064 }
2065
2066 /* If the runtime block is active, get its address. */
2067 sio_write(sio_port, 0x07, logical_device);
2068 if (sio_read(sio_port, 0x30) & 1) {
2069 rt_port = (sio_read(sio_port, 0x60) << 8)
2070 | sio_read(sio_port, 0x61);
2071 }
2072
2073 if (rt_port == 0) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002074 msg_perr("\nERROR: "
Michael Gold6d52e472009-06-19 13:00:24 +00002075 "Super I/O runtime interface not available.\n");
2076 }
2077out:
Uwe Hermann1432a602009-06-28 23:26:37 +00002078 OUTB(0xaa, sio_port); /* Disable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00002079 return rt_port;
2080}
2081
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002082/*
2083 * Disable write protection on the Mitac 6513WU. WP# on the FWH is
Michael Gold6d52e472009-06-19 13:00:24 +00002084 * connected to GP30 on the Super I/O, and TBL# is always high.
2085 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00002086static int board_mitac_6513wu(void)
Michael Gold6d52e472009-06-19 13:00:24 +00002087{
2088 struct pci_dev *dev;
2089 uint16_t rt_port;
2090 uint8_t val;
2091
2092 dev = pci_dev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */
2093 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002094 msg_perr("\nERROR: Intel 82801AA ISA bridge not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +00002095 return -1;
2096 }
2097
Uwe Hermann1432a602009-06-28 23:26:37 +00002098 rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa);
Michael Gold6d52e472009-06-19 13:00:24 +00002099 if (rt_port == 0)
2100 return -1;
2101
2102 /* Configure the GPIO pin. */
2103 val = INB(rt_port + 0x33); /* GP30 config */
Uwe Hermann1432a602009-06-28 23:26:37 +00002104 val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */
Michael Gold6d52e472009-06-19 13:00:24 +00002105 OUTB(val, rt_port + 0x33);
2106
2107 /* Disable write protection. */
2108 val = INB(rt_port + 0x4d); /* GP3 values */
Uwe Hermann1432a602009-06-28 23:26:37 +00002109 val |= 0x01; /* Set GP30 high. */
Michael Gold6d52e472009-06-19 13:00:24 +00002110 OUTB(val, rt_port + 0x4d);
2111
2112 return 0;
2113}
2114
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002115/*
2116 * Suited for:
Christoph Grenzd13a3942011-10-21 13:20:11 +00002117 * - abit AV8: Socket939 + K8T800Pro + VT8237
2118 */
2119static int board_abit_av8(void)
2120{
2121 uint8_t val;
2122
2123 /* Raise GPO pins GP22 & GP23 */
2124 val = INB(0x404E);
2125 val |= 0xC0;
2126 OUTB(val, 0x404E);
2127
2128 return 0;
2129}
2130
2131/*
2132 * Suited for:
Uwe Hermann45bd1442010-09-14 23:20:35 +00002133 * - ASUS A7V333: VIA KT333 + VT8233A + IT8703F
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002134 * - ASUS A7V8X: VIA KT400 + VT8235 + IT8703F
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002135 */
Uwe Hermann45bd1442010-09-14 23:20:35 +00002136static int it8703f_gpio51_raise(void)
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002137{
2138 uint16_t id, base;
2139 uint8_t tmp;
2140
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002141 /* Find the IT8703F. */
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002142 w836xx_ext_enter(0x2E);
2143 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
2144 w836xx_ext_leave(0x2E);
2145
2146 if (id != 0x8701) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002147 msg_perr("\nERROR: IT8703F Super I/O not found.\n");
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002148 return -1;
2149 }
2150
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002151 /* Get the GP567 I/O base. */
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002152 w836xx_ext_enter(0x2E);
2153 sio_write(0x2E, 0x07, 0x0C);
2154 base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
2155 w836xx_ext_leave(0x2E);
2156
2157 if (!base) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002158 msg_perr("\nERROR: Failed to read IT8703F Super I/O GPIO"
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002159 " Base.\n");
2160 return -1;
2161 }
2162
2163 /* Raise GP51. */
2164 tmp = INB(base);
2165 tmp |= 0x02;
2166 OUTB(tmp, base);
2167
2168 return 0;
2169}
2170
Luc Verhaegen72272912009-09-01 21:22:23 +00002171/*
Joshua Roysa2f37222011-11-14 13:00:12 +00002172 * General routine for raising/dropping GPIO lines on the ITE IT87xx.
Luc Verhaegen72272912009-09-01 21:22:23 +00002173 */
Joshua Roysa2f37222011-11-14 13:00:12 +00002174static int it87_gpio_set(unsigned int gpio, int raise)
Luc Verhaegen72272912009-09-01 21:22:23 +00002175{
Joshua Roysa2f37222011-11-14 13:00:12 +00002176 int allowed, sio;
Luc Verhaegen72272912009-09-01 21:22:23 +00002177 unsigned int port;
Joshua Roysa2f37222011-11-14 13:00:12 +00002178 uint16_t base, sioport;
Luc Verhaegen72272912009-09-01 21:22:23 +00002179 uint8_t tmp;
2180
Joshua Roysa2f37222011-11-14 13:00:12 +00002181 /* IT87 GPIO configuration table */
2182 static const struct it87cfg {
2183 uint16_t id;
2184 uint8_t base_reg;
2185 uint32_t bank0;
2186 uint32_t bank1;
2187 uint32_t bank2;
2188 } it87_gpio_table[] = {
2189 {0x8712, 0x62, 0xCFF3FC00, 0x00FCFF3F, 0},
2190 {0x8718, 0x62, 0xCFF37C00, 0xF3FCDF3F, 0x0000000F},
2191 {0, 0, 0, 0, 0} /* end marker */
2192 };
2193 const struct it87cfg *cfg = NULL;
Luc Verhaegen72272912009-09-01 21:22:23 +00002194
Joshua Roysa2f37222011-11-14 13:00:12 +00002195 /* Find the Super I/O in the probed list */
2196 for (sio = 0; sio < superio_count; sio++) {
2197 int i;
2198 if (superios[sio].vendor != SUPERIO_VENDOR_ITE)
2199 continue;
2200
2201 /* Is this device in our list? */
2202 for (i = 0; it87_gpio_table[i].id; i++)
2203 if (superios[sio].model == it87_gpio_table[i].id) {
2204 cfg = &it87_gpio_table[i];
2205 goto found;
2206 }
2207 }
2208
2209 if (cfg == NULL) {
2210 msg_perr("\nERROR: No IT87 Super I/O GPIO configuration "
2211 "found.\n");
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002212 return -1;
Luc Verhaegen72272912009-09-01 21:22:23 +00002213 }
2214
Joshua Roysa2f37222011-11-14 13:00:12 +00002215found:
2216 /* Check whether the gpio is allowed. */
2217 if (gpio < 32)
2218 allowed = (cfg->bank0 >> gpio) & 0x01;
2219 else if (gpio < 64)
2220 allowed = (cfg->bank1 >> (gpio - 32)) & 0x01;
2221 else if (gpio < 96)
2222 allowed = (cfg->bank2 >> (gpio - 64)) & 0x01;
2223 else
2224 allowed = 0;
Luc Verhaegen72272912009-09-01 21:22:23 +00002225
Joshua Roysa2f37222011-11-14 13:00:12 +00002226 if (!allowed) {
2227 msg_perr("\nERROR: IT%02X does not allow setting GPIO%02u.\n",
2228 cfg->id, gpio);
Luc Verhaegen72272912009-09-01 21:22:23 +00002229 return -1;
2230 }
2231
Joshua Roysa2f37222011-11-14 13:00:12 +00002232 /* Read the Simple I/O Base Address Register */
2233 sioport = superios[sio].port;
2234 enter_conf_mode_ite(sioport);
2235 sio_write(sioport, 0x07, 0x07);
2236 base = (sio_read(sioport, cfg->base_reg) << 8) |
2237 sio_read(sioport, cfg->base_reg + 1);
2238 exit_conf_mode_ite(sioport);
Luc Verhaegen72272912009-09-01 21:22:23 +00002239
2240 if (!base) {
Joshua Roysa2f37222011-11-14 13:00:12 +00002241 msg_perr("\nERROR: Failed to read IT87 Super I/O GPIO Base.\n");
Luc Verhaegen72272912009-09-01 21:22:23 +00002242 return -1;
2243 }
2244
Joshua Roysa2f37222011-11-14 13:00:12 +00002245 msg_pdbg("Using IT87 GPIO base 0x%04x\n", base);
2246
2247 port = gpio / 10 - 1;
2248 gpio %= 10;
2249
2250 /* set GPIO. */
Luc Verhaegen72272912009-09-01 21:22:23 +00002251 tmp = INB(base + port);
2252 if (raise)
Joshua Roysa2f37222011-11-14 13:00:12 +00002253 tmp |= 1 << gpio;
Luc Verhaegen72272912009-09-01 21:22:23 +00002254 else
Joshua Roysa2f37222011-11-14 13:00:12 +00002255 tmp &= ~(1 << gpio);
Luc Verhaegen72272912009-09-01 21:22:23 +00002256 OUTB(tmp, base + port);
2257
2258 return 0;
2259}
2260
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002261/*
Russ Dillbd622d12010-03-09 16:57:06 +00002262 * Suited for:
Joshua Roys8ca42552011-11-19 19:31:17 +00002263 * - ASUS A7N8X-VM/400: NVIDIA nForce2 IGP2 + IT8712F
2264 */
2265static int it8712f_gpio12_raise(void)
2266{
2267 return it87_gpio_set(12, 1);
2268}
2269
2270/*
2271 * Suited for:
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00002272 * - ASUS A7V600-X: VIA KT600 + VT8237 + IT8712F
2273 * - ASUS A7V8X-X: VIA KT400 + VT8235 + IT8712F
Luc Verhaegen72272912009-09-01 21:22:23 +00002274 */
Joshua Roysa2f37222011-11-14 13:00:12 +00002275static int it8712f_gpio31_raise(void)
Luc Verhaegen72272912009-09-01 21:22:23 +00002276{
Joshua Roysa2f37222011-11-14 13:00:12 +00002277 return it87_gpio_set(32, 1);
2278}
2279
2280/*
2281 * Suited for:
2282 * - ASUS P5N-D: NVIDIA MCP51 + IT8718F
2283 * - ASUS P5N-E SLI: NVIDIA MCP51 + IT8718F
2284 */
2285static int it8718f_gpio63_raise(void)
2286{
2287 return it87_gpio_set(63, 1);
Luc Verhaegen72272912009-09-01 21:22:23 +00002288}
2289
Ingo Feldschmid8a0f9b02012-01-31 06:51:56 +00002290/*
2291 * Suited for all boards with ambiguous DMI chassis information, which should be
2292 * whitelisted because they are known to work:
Stefan Tauner463dd692013-08-08 12:00:19 +00002293 * - ASRock IMB-A180(-H)
Stefan Taunerdbac46c2013-08-13 22:10:41 +00002294 * - Intel D945GCNL
Ingo Feldschmid8a0f9b02012-01-31 06:51:56 +00002295 * - MSC Q7 Tunnel Creek Module (Q7-TCTC)
2296 */
2297static int p2_not_a_laptop(void)
2298{
2299 /* label this board as not a laptop */
2300 is_laptop = 0;
2301 msg_pdbg("Laptop detection overridden by P2 board enable.\n");
2302 return 0;
2303}
2304
Stefan Tauner98feaa52012-09-25 21:08:41 +00002305/*
2306 * Suited for all laptops, which are known to *not* have interfering embedded controllers.
2307 */
2308static int p2_whitelist_laptop(void)
2309{
2310 is_laptop = 1;
Felix Singerd1ab7d22022-08-19 03:03:47 +02002311 laptop_ok = true;
Stefan Tauner98feaa52012-09-25 21:08:41 +00002312 msg_pdbg("Whitelisted laptop detected.\n");
2313 return 0;
2314}
2315
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00002316#endif
2317
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002318/*
Uwe Hermannd0e347d2009-10-06 13:00:00 +00002319 * Below is the list of boards which need a special "board enable" code in
2320 * flashrom before their ROM chip can be accessed/written to.
2321 *
2322 * NOTE: Please add boards that _don't_ need such enables or don't work yet
2323 * to the respective tables in print.c. Thanks!
2324 *
Stefan Tauner2c5b65e2013-10-26 17:02:03 +00002325 * We use 2 sets of PCI IDs here, you're free to choose which is which. This
Uwe Hermannffec5f32007-08-23 16:08:21 +00002326 * is to provide a very high degree of certainty when matching a board on
2327 * the basis of subsystem/card IDs. As not every vendor handles
2328 * subsystem/card IDs in a sane manner.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002329 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00002330 * Keep the second set NULLed if it should be ignored. Keep the subsystem IDs
Stefan Tauner2c5b65e2013-10-26 17:02:03 +00002331 * and the dmi identifier NULLed if they don't identify the board fully to disable autodetection.
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00002332 * But please take care to provide an as complete set of pci ids as possible;
2333 * autodetection is the preferred behaviour and we would like to make sure that
2334 * matches are unique.
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00002335 *
Michael Karcher6701ee82010-01-20 14:14:11 +00002336 * If PCI IDs are not sufficient for board matching, the match can be further
2337 * constrained by a string that has to be present in the DMI database for
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00002338 * the baseboard or the system entry. The pattern is matched by case sensitive
Michael Karcher6701ee82010-01-20 14:14:11 +00002339 * substring match, unless it is anchored to the beginning (with a ^ in front)
2340 * or the end (with a $ at the end). Both anchors may be specified at the
2341 * same time to match the full field.
2342 *
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00002343 * When a board is matched through DMI, the first and second main PCI IDs
2344 * and the first subsystem PCI ID have to match as well. If you specify the
2345 * first subsystem ID as 0x0:0x0, the DMI matching code expects that the
2346 * subsystem ID of that device is indeed zero.
2347 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00002348 * The coreboot ids are used two fold. When running with a coreboot firmware,
2349 * the ids uniquely matches the coreboot board identification string. When a
2350 * legacy bios is installed and when autodetection is not possible, these ids
Carl-Daniel Hailfinger2d927fb2012-01-04 00:48:27 +00002351 * can be used to identify the board through the -p internal:mainboard=
2352 * programmer parameter.
Luc Verhaegenc5210162009-04-20 12:38:17 +00002353 *
2354 * When a board is identified through its coreboot ids (in both cases), the
2355 * main pci ids are still required to match, as a safeguard.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002356 */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002357
Uwe Hermanndeeebe22009-05-08 16:23:34 +00002358/* Please keep this list alphabetically ordered by vendor/board name. */
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002359const struct board_match board_matches[] = {
Uwe Hermann5ab88892009-06-21 20:50:22 +00002360
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002361 /* first pci-id set [4], second pci-id set [4], dmi identifier, coreboot id [2], phase, vendor name, board name max_rom_... OK? flash enable */
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00002362#if defined(__i386__) || defined(__x86_64__)
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002363 {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, P3, "abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise},
Christoph Grenzd13a3942011-10-21 13:20:11 +00002364 {0x1106, 0x0282, 0x147B, 0x1415, 0x1106, 0x3227, 0x147B, 0x1415, "^AV8 ", NULL, NULL, P3, "abit", "AV8", 0, OK, board_abit_av8},
Stefan Tauner2c5b65e2013-10-26 17:02:03 +00002365 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, NULL /* "^I440BX-W977$" */, "abit", "bf6", P3, "abit", "BF6", 0, OK, intel_piix4_gpo26_lower},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002366 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^i440BX-W977 (BM6)$", NULL, NULL, P3, "abit", "BM6", 0, OK, intel_piix4_gpo26_lower},
2367 {0x8086, 0x24d3, 0x147b, 0x1014, 0x8086, 0x2578, 0x147b, 0x1014, NULL, NULL, NULL, P3, "abit", "IC7", 0, NT, intel_ich_gpio23_raise},
2368 {0x8086, 0x2930, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, P3, "abit", "IP35", 0, OK, intel_ich_gpio16_raise},
2369 {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, P3, "abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise},
Stefan Tauner24c38df2012-08-11 02:33:20 +00002370 {0x10de, 0x0050, 0x147b, 0x1c1a, 0x10de, 0x0052, 0x147b, 0x1c1a, NULL, NULL, NULL, P3, "abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower},
Stefan Tauner74dc73f2015-03-01 22:04:38 +00002371 {0x10de, 0x0369, 0x147b, 0x1c20, 0x10de, 0x0360, 0x147b, 0x1c20, "^KN9(NF-MCP55 series)$", NULL, NULL, P3, "abit", "KN9 Ultra", 0, OK, nvidia_mcp_gpio2_lower},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002372 {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, P3, "abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise},
Paul Menzelac427b22012-02-16 21:07:07 +00002373 {0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0260, 0x147b, 0x1c26, NULL, NULL, NULL, P3, "abit", "NF-M2 nView", 0, OK, nvidia_mcp_gpio4_lower},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002374 {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, "(VA6)$", NULL, NULL, P3, "abit", "VA6", 0, OK, via_apollo_gpo4_lower},
2375 {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", P3, "abit", "VT6X4", 0, OK, via_apollo_gpo4_lower},
2376 {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, P3, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd},
Stefan Tauner24c38df2012-08-11 02:33:20 +00002377 {0x1022, 0x746B, 0, 0, 0x1022, 0x7460, 0, 0, NULL, "AGAMI", "ARUMA", P3, "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002378 {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, P3, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e},
2379 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", P3, "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x},
2380 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", P3, "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x},
Stefan Taunerc6782182012-01-19 17:50:32 +00002381 {0x8086, 0x27b9, 0xa0a0, 0x0632, 0x8086, 0x27da, 0xa0a0, 0x0632, NULL, NULL, NULL, P3, "AOpen", "i945GMx-VFX", 0, OK, intel_ich_gpio38_raise},
Luc Verhaegen3f7e3412018-03-28 12:31:22 +02002382 {0x8086, 0x2a00, 0xa0a0, 0x063e, 0x8086, 0x2815, 0xa0a0, 0x063e, NULL, NULL, NULL, P3, "AOpen", "i965GMt-LA", 0, OK, intel_ich_gpio20_raise},
Joshua Roys7225ccd2011-05-18 01:32:16 +00002383 {0x8086, 0x277c, 0xa0a0, 0x060b, 0x8086, 0x27da, 0xa0a0, 0x060b, NULL, NULL, NULL, P3, "AOpen", "i975Xa-YDG", 0, OK, board_aopen_i975xa_ydg},
Arthur Heymanscd8329f2017-03-22 17:50:43 +01002384 {0x8086, 0x27A0, 0x8086, 0x7270, 0x8086, 0x27B9, 0x8086, 0x7270, "^iMac5,2$", NULL, NULL, P2, "Apple", "iMac5,2", 0, OK, p2_whitelist_laptop},
Stefan Taunerc2eec2c2014-05-03 21:33:01 +00002385 {0x8086, 0x27A0, 0x8086, 0x7270, 0x8086, 0x27B9, 0x8086, 0x7270, "^MacBook2,1$", NULL, NULL, P2, "Apple", "MacBook2,1", 0, OK, p2_whitelist_laptop},
Joshua Roysea3aed02011-11-16 22:08:11 +00002386 {0x8086, 0x27b8, 0x1849, 0x27b8, 0x8086, 0x27da, 0x1849, 0x27da, "^ConRoeXFire-eSATA2", NULL, NULL, P3, "ASRock", "ConRoeXFire-eSATA2", 0, OK, intel_ich_gpio16_raise},
Stefan Tauner463dd692013-08-08 12:00:19 +00002387 {0x1022, 0x1536, 0x1849, 0x1536, 0x1022, 0x780e, 0x1849, 0x780e, "^Kabini CRB$", NULL, NULL, P2, "ASRock", "IMB-A180(-H)", 0, OK, p2_not_a_laptop},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002388 {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41 $", NULL, NULL, P3, "ASRock", "K7S41", 0, OK, w836xx_memw_enable_2e},
Pawel Rozanski1d233072011-06-19 16:52:48 +00002389 {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41GX$", NULL, NULL, P3, "ASRock", "K7S41GX", 0, OK, w836xx_memw_enable_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002390 {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, P3, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise},
2391 {0x8086, 0x2570, 0x1849, 0x2570, 0x8086, 0x24d3, 0x1849, 0x24d0, NULL, NULL, NULL, P3, "ASRock", "775i65G", 0, OK, intel_ich_gpio23_raise},
Joshua Roys8ca42552011-11-19 19:31:17 +00002392 {0x10DE, 0x0060, 0x1043, 0x80AD, 0x10DE, 0x01E0, 0x1043, 0x80C0, NULL, NULL, NULL, P3, "ASUS", "A7N8X-VM/400", 0, OK, it8712f_gpio12_raise},
Joshua Roysa2f37222011-11-14 13:00:12 +00002393 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, P3, "ASUS", "A7V600-X", 0, OK, it8712f_gpio31_raise},
François Revol495fc2c2014-03-14 08:10:02 +00002394 {0x1106, 0x3177, 0x1043, 0x80F9, 0x1106, 0x3205, 0x1043, 0x80F9, NULL, NULL, NULL, P3, "ASUS", "A7V8X-MX", 0, OK, w836xx_memw_enable_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002395 {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, P3, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e},
2396 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V8X", 0, OK, it8703f_gpio51_raise},
2397 {0x1106, 0x3099, 0x1043, 0x807F, 0x1106, 0x3147, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V333", 0, OK, it8703f_gpio51_raise},
Joshua Roysa2f37222011-11-14 13:00:12 +00002398 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, P3, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio31_raise},
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00002399 {0x1002, 0x4372, 0x103c, 0x2a26, 0x1002, 0x4377, 0x103c, 0x2a26, NULL, NULL, NULL, P3, "ASUS", "A8AE-LE", 0, OK, amd_sbxxx_gpio9_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002400 {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, P3, "ASUS", "A8Jm", 0, NT, intel_ich_gpio34_raise},
Stefan Taunera9cbbac2011-08-07 13:17:20 +00002401 {0x10DE, 0x0260, 0x103C, 0x2A34, 0x10DE, 0x0264, 0x103C, 0x2A34, "NODUSM3", NULL, NULL, P3, "ASUS", "A8M2N-LA (NodusM3-GL8E)", 0, OK, nvidia_mcp_gpio0_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002402 {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI2L", NULL, NULL, P3, "ASUS", "A8N-LA (Nagami-GL8E)", 0, OK, nvidia_mcp_gpio0_raise},
Stefan Taunerff80e682011-07-20 16:34:18 +00002403 {0x10de, 0x0264, 0x1043, 0x81bc, 0x10de, 0x02f0, 0x1043, 0x81cd, NULL, NULL, NULL, P3, "ASUS", "A8N-VM CSM", 0, OK, w83627ehf_gpio22_raise_2e},
Stefan Tauner98546c92012-11-05 12:20:29 +00002404 {0x8086, 0x65c0, 0x1043, 0x8301, 0x8086, 0x2916, 0x1043, 0x82a6, "^DSAN-DX$", NULL, NULL, P3, "ASUS", "DSAN-DX", 0, NT, intel_ich_gpio32_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002405 {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, P3, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise},
2406 {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, P3, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise},
Joshua Roysc73e2812011-07-09 19:46:53 +00002407 {0x8086, 0x24cc, 0, 0, 0x8086, 0x24c3, 0x1043, 0x1869, "^M6Ne$", NULL, NULL, P3, "ASUS", "M6Ne", 0, NT, intel_ich_gpio43_raise},
Joshua Roysd708fad2012-02-17 14:51:15 +00002408 {0x8086, 0x7180, 0, 0, 0x8086, 0x7110, 0, 0, "^OPLX-M$", NULL, NULL, P3, "ASUS", "OPLX-M", 0, NT, intel_piix4_gpo18_lower},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002409 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^P2B-N$", NULL, NULL, P3, "ASUS", "P2B-N", 0, OK, intel_piix4_gpo18_lower},
Keith Hui91486202020-05-12 21:43:58 -04002410 {0x8086, 0x7190, 0x1043, 0x8024, 0x8086, 0x7110, 0, 0, "P3B-F", "asus", "p3b-f", P3, "ASUS", "P3B-F", 0, OK, board_asus_p3b_f},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002411 {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, P3, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise},
2412 {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, P3, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise},
2413 {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, P3, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise},
Joshua Roysa5f5a152011-11-15 08:08:15 +00002414 {0x8086, 0x2560, 0x103C, 0x2A00, 0x8086, 0x24C3, 0x103C, 0x2A01, "^Guppy", NULL, NULL, P3, "ASUS", "P4GV-LA (Guppy)", 0, OK, intel_ich_gpio21_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002415 {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, P3, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
2416 {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D5, 0x1043, 0x80F3, NULL, NULL, NULL, P3, "ASUS", "P4P800", 0, NT, intel_ich_gpio21_raise},
Stefan Taunereb582572012-09-21 12:52:50 +00002417 {0x8086, 0x2570, 0x1043, 0x80f2, 0x8086, 0x24d3, 0x1043, 0x80a6, "^P4P800-E$", NULL, NULL, P3, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
2418 {0x8086, 0x2570, 0x1043, 0x80a5, 0x8086, 0x24d3, 0x1043, 0x80a6, "^P4P800-VM$", NULL, NULL, P3, "ASUS", "P4P800-VM", 0, OK, intel_ich_gpio21_raise},
2419 {0x8086, 0x2570, 0x1043, 0x80f2, 0x8086, 0x24d3, 0x1043, 0x80a6, "^P4P800-X$", NULL, NULL, P3, "ASUS", "P4P800-X", 0, OK, intel_ich_gpio21_raise},
Miklós Mártonde77ad42019-08-06 22:43:19 +02002420 {0x8086, 0x2570, 0x1043, 0x80f2, 0x8086, 0x24d3, 0, 0, "^P4P800SE$", NULL, NULL, P3, "ASUS", "P4P800SE", 0, OK, intel_ich_gpio21_raise},
Stefan Taunerd3b98fb2013-03-04 01:41:56 +00002421 {0x8086, 0x2570, 0x1043, 0x80b2, 0x8086, 0x24c3, 0x1043, 0x8089, "^P4PE-X/TE$",NULL, NULL, P3, "ASUS", "P4PE-X/TE", 0, NT, intel_ich_gpio21_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002422 {0x1039, 0x0651, 0x1043, 0x8081, 0x1039, 0x0962, 0, 0, NULL, NULL, NULL, P3, "ASUS", "P4SC-E", 0, OK, it8707f_write_enable_2e},
2423 {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, P3, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise},
2424 {0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x5513, 0x1043, 0x8087, NULL, NULL, NULL, P3, "ASUS", "P4S800-MX", 512, OK, w836xx_memw_enable_2e},
2425 {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", P3, "ASUS", "P5A", 0, OK, board_asus_p5a},
Stefan Tauner027e0182012-05-02 19:48:21 +00002426 {0x8086, 0x27b8, 0x1043, 0x819e, 0x8086, 0x29f0, 0x1043, 0x82a5, "^P5BV-R$", NULL, NULL, P3, "ASUS", "P5BV-R", 0, OK, intel_ich_gpio20_raise},
Stefan Taunera4f14472011-10-22 22:01:09 +00002427 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, "^P5GD1 PRO$", NULL, NULL, P3, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise},
2428 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, "^P5GD1-VM$", NULL, NULL, P3, "ASUS", "P5GD1-VM/S", 0, OK, intel_ich_gpio21_raise},
2429 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, P3, "ASUS", "P5GD1(-VM)", 0, NT, intel_ich_gpio21_raise},
Joshua Roys1fd4f9e2011-08-11 05:47:32 +00002430 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GD2-Premium$", NULL, NULL, P3, "ASUS", "P5GD2 Premium", 0, OK, intel_ich_gpio21_raise},
Stefan Taunerd94d25d2012-07-28 03:17:15 +00002431 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x81a6, "^P5GD2-X$", NULL, NULL, P3, "ASUS", "P5GD2-X", 0, OK, intel_ich_gpio21_raise},
Stefan Taunera4f14472011-10-22 22:01:09 +00002432 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GDC-V$", NULL, NULL, P3, "ASUS", "P5GDC-V Deluxe", 0, OK, intel_ich_gpio21_raise},
2433 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GDC$", NULL, NULL, P3, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise},
2434 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, P3, "ASUS", "P5GD2/C variants", 0, NT, intel_ich_gpio21_raise},
Michael Karcher14ab8d42011-08-25 14:06:50 +00002435 {0x8086, 0x27b8, 0x103c, 0x2a22, 0x8086, 0x2770, 0x103c, 0x2a22, "^LITHIUM$", NULL, NULL, P3, "ASUS", "P5LP-LE (Lithium-UL8E)",0, OK, intel_ich_gpio34_raise},
2436 {0x8086, 0x27b8, 0x1043, 0x2a22, 0x8086, 0x2770, 0x1043, 0x2a22, "^P5LP-LE$", NULL, NULL, P3, "ASUS", "P5LP-LE (Epson OEM)", 0, OK, intel_ich_gpio34_raise},
Stefan Tauner6697f712014-08-06 15:09:15 +00002437 {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, OK, intel_ich_gpio16_raise},
Dima Veselov9d8f53d2014-07-14 18:04:15 +00002438 {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b0, 0x1043, 0x8179, "^P5LD2-MQ$", NULL, NULL, P3, "ASUS", "P5LD2-MQ", 0, OK, intel_ich_gpio16_raise},
Stefan Tauner5c316f92015-02-08 21:57:52 +00002439 {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2-VM$", NULL, NULL, P3, "ASUS", "P5LD2-VM", 0, OK, intel_ich_gpio16_raise},
Stefan Tauner309dd2c2013-11-21 15:59:52 +00002440 {0x8086, 0x27b0, 0x1043, 0x8179, 0x8086, 0x2770, 0x1043, 0x817a, "^P5LD2-VM DH$", NULL, NULL, P3, "ASUS", "P5LD2-VM DH", 0, OK, intel_ich_gpio16_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002441 {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, P3, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise},
Joshua Roysa2f37222011-11-14 13:00:12 +00002442 {0x10DE, 0x0260, 0x1043, 0x81BC, 0x10DE, 0x026C, 0x1043, 0x829E, "^P5N-D$", NULL, NULL, P3, "ASUS", "P5N-D", 0, OK, it8718f_gpio63_raise},
2443 {0x10DE, 0x0260, 0x1043, 0x81BC, 0x10DE, 0x026C, 0x1043, 0x8249, "^P5N-E SLI$",NULL, NULL, P3, "ASUS", "P5N-E SLI", 0, NT, it8718f_gpio63_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002444 {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, P3, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise},
Tasos Sahanidis58cf5192022-04-20 09:30:42 +03002445 {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5W DH Deluxe$", NULL, NULL, P3, "ASUS", "P5W DH Deluxe", 0, OK, intel_ich_gpio16_raise},
Stefan Taunereb582572012-09-21 12:52:50 +00002446 {0x8086, 0x2443, 0x1043, 0x8027, 0x8086, 0x1130, 0x1043, 0x8027, "^CUSL2-C", NULL, NULL, P3, "ASUS", "CUSL2-C", 0, OK, intel_ich_gpio21_raise},
2447 {0x8086, 0x2443, 0x1043, 0x8027, 0x8086, 0x1130, 0x1043, 0x8027, "^TUSL2-C", NULL, NULL, P3, "ASUS", "TUSL2-C", 0, NT, intel_ich_gpio21_raise},
Stefan Tauner23e10b82016-01-23 16:16:49 +00002448 {0x1022, 0x780E, 0x1043, 0x1437, 0x1022, 0x780B, 0x1043, 0x1437, "^U38N$", NULL, NULL, P2, "ASUS", "U38N", 0, OK, p2_whitelist_laptop},
Corey Osgoodcbd56652013-09-10 10:42:48 +00002449 {0x1106, 0x3059, 0x1106, 0x4161, 0x1106, 0x3065, 0x1106, 0x0102, NULL, NULL, NULL, P3, "Bcom/Clientron", "WinNET P680", 0, OK, w836xx_memw_enable_2e},
Stefan Taunereb582572012-09-21 12:52:50 +00002450 {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3116, 0x1106, 0x3116, "^KM266-8235$", "biostar", "m7viq", P3, "Biostar", "M7VIQ", 0, NT, w83697xx_memw_enable_2e},
Stefan Tauner23e10b82016-01-23 16:16:49 +00002451 {0x8086, 0x283e, 0x1028, 0x01f9, 0x8086, 0x2a01, 0, 0, "^Latitude D630", NULL, NULL, P2, "Dell", "Latitude D630", 0, OK, p2_whitelist_laptop},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002452 {0x10b7, 0x9055, 0x1028, 0x0082, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Dell", "OptiPlex GX1", 0, OK, intel_piix4_gpo30_lower},
2453 {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, P3, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise},
Tadas Slotkus3dcdc032012-08-25 03:53:12 +00002454 {0x1106, 0x3189, 0x1106, 0x3189, 0x1106, 0x3177, 0x1106, 0x3177, "^AD77", "dfi", "ad77", P3, "DFI", "AD77", 0, NT, w836xx_memw_enable_2e},
Stefan Taunere34e3e82013-01-01 00:06:51 +00002455 {0x1039, 0x6325, 0x1019, 0x0f05, 0x1039, 0x0016, 0, 0, NULL, NULL, NULL, P2, "Elitegroup", "A928", 0, OK, p2_whitelist_laptop},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002456 {0x10de, 0x03ea, 0x1019, 0x2602, 0x10de, 0x03e0, 0x1019, 0x2602, NULL, NULL, NULL, P3, "Elitegroup", "GeForce6100SM-M", 0, OK, board_ecs_geforce6100sm_m},
2457 {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, P3, "Elitegroup", "K7VTA3", 256, OK, NULL},
2458 {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, P3, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e},
Stefan Tauneraf4b1582011-08-06 16:16:33 +00002459 {0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, "8NPA7I", NULL, NULL, P3, "EPoX", "EP-8NPA7I", 0, OK, nvidia_mcp_gpio4_raise},
2460 {0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, "9NPA7I", NULL, NULL, P3, "EPoX", "EP-9NPA7I", 0, OK, nvidia_mcp_gpio4_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002461 {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, P3, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise},
2462 {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", P3, "EPoX", "EP-BX3", 0, NT, intel_piix4_gpo22_raise},
2463 {0x10de, 0x02f0, 0x105b, 0x0d01, 0x10de, 0x0264, 0x105b, 0x0d01, NULL, NULL, NULL, P3, "Foxconn", "6150K8MD-8EKRSH", 0, NT, nvidia_mcp_gpio2_raise},
Stefan Tauner23e10b82016-01-23 16:16:49 +00002464 {0x8086, 0x2A40, 0x1734, 0x1148, 0x8086, 0x2930, 0x1734, 0x1148, "^XY680", NULL, NULL, P2, "Fujitsu", "Amilo Xi 3650", 0, OK, p2_whitelist_laptop},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002465 {0x8086, 0x2443, 0x8086, 0x2442, 0x8086, 0x1130, 0x8086, 0x1130, "^6IEM ", NULL, NULL, P3, "GIGABYTE", "GA-6IEM", 0, NT, intel_ich_gpio25_raise},
2466 {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-7ZM", 512, OK, NULL},
Joshua Roys9d9a1042011-06-13 16:59:01 +00002467 {0x8086, 0x2570, 0x1458, 0x2570, 0x8086, 0x24d0, 0, 0, "^8IP775/-G$",NULL, NULL, P3, "GIGABYTE", "GA-8IP775", 0, OK, intel_ich_gpio32_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002468 {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise},
2469 {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise},
Stefan Tauner7fbbbb82014-11-30 22:31:12 +00002470 {0x1039, 0x0650, 0x1039, 0x0650, 0x1039, 0x7012, 0x1458, 0xA002, "^GA-8SIMLFS20$", NULL, NULL, P3, "GIGABYTE", "GA-8SIMLFS 2.0", 0, OK, sis_gpio0_raise_and_w836xx_memw},
Stefan Tauner716e0982011-07-25 20:38:52 +00002471 {0x1039, 0x0651, 0x1039, 0x0651, 0x1039, 0x7002, 0x1458, 0x5004, "^GA-8SIMLH$",NULL, NULL, P3, "GIGABYTE", "GA-8SIMLH", 0, OK, sis_gpio0_raise_and_w836xx_memw},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002472 {0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise},
2473 {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise},
Stefan Tauner23e10b82016-01-23 16:16:49 +00002474 {0x10DE, 0x00E4, 0x1458, 0x0C11, 0x10DE, 0x00E0, 0x1458, 0x0C11, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8NS", 0, OK, nvidia_mcp_gpio0a_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002475 {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise},
Idwer Volleringd8a00a02011-06-13 16:58:54 +00002476 {0x8086, 0x2415, 0x103c, 0x1250, 0x10b7, 0x9200, 0x103c, 0x1247, NULL, NULL, NULL, P3, "HP", "e-Vectra P2706T", 0, OK, board_hp_p2706t},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002477 {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", P3, "HP", "ProLiant DL145 G3", 0, OK, board_hp_dl145_g3_enable},
2478 {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", P3, "HP", "ProLiant DL165 G6", 0, OK, board_hp_dl165_g6_enable},
2479 {0x8086, 0x2580, 0x103c, 0x2a08, 0x8086, 0x2640, 0x103c, 0x2a0a, NULL, NULL, NULL, P3, "HP", "Puffer2-UL8E", 0, OK, intel_ich_gpio18_raise},
Idwer Volleringd8a00a02011-06-13 16:58:54 +00002480 {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, P3, "HP", "Vectra VL400", 0, OK, board_hp_vl400},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002481 {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, P3, "HP", "Vectra VL420 SFF", 0, OK, intel_ich_gpio22_raise},
2482 {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, "hp", "xw9400", P3, "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise},
2483 {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", P3, "IBASE", "MB899", 0, OK, intel_ich_gpio26_raise},
2484 {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, P3, "IBM", "x3455", 0, OK, board_ibm_x3455},
2485 {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, P3, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi},
Stefan Taunere34e3e82013-01-01 00:06:51 +00002486 {0x8086, 0x27b8, 0x8086, 0xd606, 0x8086, 0x2770, 0x8086, 0xd606, "^D945GCNL$", NULL, NULL, P2, "Intel", "D945GCNL", 0, OK, p2_not_a_laptop},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002487 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, P3, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower},
Stefan Tauner24c38df2012-08-11 02:33:20 +00002488 {0x1022, 0x7468, 0, 0, 0x1022, 0x7460, 0, 0, NULL, "iwill", "dk8_htx", P3, "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e},
direstraits96494fa832022-02-16 02:26:51 +00002489 {0x5333, 0x8d04, 0x1106, 0x3065, 0x1106, 0x3059, 0x1106, 0x0571, "P4M266-8235", NULL, NULL, P3, "Jetway", "P4MDPT", 0, OK, w836xx_memw_enable_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002490 {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", P3, "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m},
Leah Rowe8c7e78b2018-01-26 00:57:10 +00002491 {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad R400", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad R400", 0, OK, p2_whitelist_laptop},
Stefan Tauner23e10b82016-01-23 16:16:49 +00002492 {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad T400", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T400", 0, OK, p2_whitelist_laptop},
Leah Rowe8c7e78b2018-01-26 00:57:10 +00002493 {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad T500", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T500", 0, OK, p2_whitelist_laptop},
Stefan Tauner6697f712014-08-06 15:09:15 +00002494 {0x8086, 0x1E22, 0x17AA, 0x21F6, 0x8086, 0x1E55, 0x17AA, 0x21F6, "^ThinkPad T530", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T530", 0, OK, p2_whitelist_laptop},
2495 {0x8086, 0x27a0, 0x17aa, 0x2015, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T60", 0, OK, p2_whitelist_laptop},
2496 {0x8086, 0x27a0, 0x17aa, 0x2017, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T60(s)", 0, OK, p2_whitelist_laptop},
Leah Rowe8c7e78b2018-01-26 00:57:10 +00002497 {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad W500", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad W500", 0, OK, p2_whitelist_laptop},
Stefan Tauner23e10b82016-01-23 16:16:49 +00002498 {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad X200", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X200", 0, OK, p2_whitelist_laptop},
Arthur Heymans9891b752018-07-17 02:44:41 +02002499 {0x8086, 0x3B07, 0x17AA, 0x2166, 0x8086, 0x3B30, 0x17AA, 0x2167, "^ThinkPad X201", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X201", 0, OK, p2_whitelist_laptop},
Arthur Heymans1d50abc2017-06-03 21:29:55 +02002500 {0x8086, 0x1C22, 0x17AA, 0x21DB, 0x8086, 0x1C4F, 0x17AA, 0x21DB, NULL, "lenovo", "x220", P2, "IBM/Lenovo", "ThinkPad X220", 0, OK, p2_whitelist_laptop},
Stefan Tauner6697f712014-08-06 15:09:15 +00002501 {0x8086, 0x1E22, 0x17AA, 0x21FA, 0x8086, 0x1E55, 0x17AA, 0x21FA, "^ThinkPad X230", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X230", 0, OK, p2_whitelist_laptop},
2502 {0x8086, 0x27A0, 0x17AA, 0x2017, 0x8086, 0x27B9, 0x17AA, 0x2009, "^ThinkPad X60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X60(s)", 0, OK, p2_whitelist_laptop},
Leah Rowe8c7e78b2018-01-26 00:57:10 +00002503 {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^Taurinus X200", "Libiquity", "Taurinus X200", P2, "Libiquity", "ThinkPad X200", 0, OK, p2_whitelist_laptop},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002504 {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, P3, "Mitac", "6513WU", 0, OK, board_mitac_6513wu},
Stefan Taunerd7d423b2012-10-20 09:13:16 +00002505 {0x8086, 0x8186, 0x8086, 0x8186, 0x8086, 0x8800, 0, 0, "^MSC Vertriebs GmbH$", NULL, NULL, P2, "MSC", "Q7-TCTC", 0, OK, p2_not_a_laptop},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002506 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^MS-6163 (i440BX)$", NULL, NULL, P3, "MSI", "MS-6163 (MS-6163 Pro)", 0, OK, intel_piix4_gpo14_raise},
Stefan Taunerc2eec2c2014-05-03 21:33:01 +00002507 {0x8086, 0x244b, 0x1462, 0x3910, 0x8086, 0x2442, 0x1462, 0x3910, NULL, NULL, NULL, P3, "MSI", "MS-6391 (845 Pro4)", 0, OK, intel_ich_gpio23_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002508 {0x1039, 0x0745, 0, 0, 0x1039, 0x0018, 0, 0, "^MS-6561", NULL, NULL, P3, "MSI", "MS-6561 (745 Ultra)", 0, OK, w836xx_memw_enable_2e},
Stefan Tauner0be072c2016-03-13 15:16:30 +00002509 {0x8086, 0x2560, 0x1462, 0x5770, 0x8086, 0x24C3, 0x1462, 0x5770, NULL, NULL, NULL, P3, "MSI", "MS-6577 (Xenon)", 0, OK, w83627hf_gpio25_raise_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002510 {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, P3, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v},
Stefan Tauner0be072c2016-03-13 15:16:30 +00002511 {0x1106, 0x0282, 0x1106, 0x0282, 0x1106, 0x3227, 0x1106, 0x3227, "^MS-7094$", NULL, NULL, P3, "MSI", "MS-7094 (K8T Neo2-F V2.0)", 0, OK, w83627thf_gpio44_raise_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002512 {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, P3, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v},
2513 {0x1106, 0x3148, 0 , 0 , 0x1106, 0x3177, 0 , 0 , NULL, "msi", "ms6787", P3, "MSI", "MS-6787 (P4MAM-V/P4MAM-L)", 0, OK, w836xx_memw_enable_2e},
Maciej Pijanka6add0942011-06-09 20:59:30 +00002514 {0x8086, 0x24d3, 0x1462, 0x7880, 0x8086, 0x2570, 0, 0, NULL, NULL, NULL, P3, "MSI", "MS-6788-040 (848P NeoV)", 0, OK, intel_ich_gpio32_raise},
Michael Karchera08d0f22011-07-25 17:25:24 +00002515 {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, P3, "MSI", "MS-7005 (651M-L)", 0, OK, sis_gpio0_raise_and_w836xx_memw},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002516 {0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, P3, "MSI", "MS-7025 (K8N Neo2 Platinum)", 0, OK, nvidia_mcp_gpio0c_raise},
Stefan Tauner33366a02012-09-15 15:51:09 +00002517 {0x10DE, 0x00E0, 0x1462, 0x0300, 0x10DE, 0x00E1, 0x1462, 0x0300, NULL, NULL, NULL, P3, "MSI", "MS-7030 (K8N Neo Platinum)", 0, OK, nvidia_mcp_gpio0c_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002518 {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, P3, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002519 {0x1106, 0x3149, 0x1462, 0x7061, 0x1106, 0x3227, 0, 0, NULL, NULL, NULL, P3, "MSI", "MS-7061 (KM4M-V/KM4AM-V)", 0, OK, w836xx_memw_enable_2e},
Stefan Taunerc2eec2c2014-05-03 21:33:01 +00002520 {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, P3, "MSI", "MS-7125 (K8N Neo4(-F/-FI/-FX/Platinum))", 0, OK, nvidia_mcp_gpio2_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002521 {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", P3, "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio44_raise_4e},
2522 {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, P3, "MSI", "MS-7207 (K8NGM2-L)", 0, NT, nvidia_mcp_gpio2_raise},
Joshua Roys6e48a022012-06-29 23:07:14 +00002523 {0x10DE, 0x0360, 0x1462, 0x7250, 0x10DE, 0x0368, 0x1462, 0x7250, NULL, NULL, NULL, P3, "MSI", "MS-7250 (K9N SLI)", 0, OK, nvidia_mcp_gpio2_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002524 {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0},
Stefan Taunerc2eec2c2014-05-03 21:33:01 +00002525 {0x8086, 0x3B30, 0x1025, 0x0379, 0x8086, 0x3B09, 0x1025, 0x0379, "^EasyNote LM85$", NULL, NULL, P2, "Packard Bell","EasyNote LM85", 0, OK, p2_whitelist_laptop},
Nico Huber31454232016-05-03 11:43:17 +02002526 {0x8086, 0x0154, 0x8086, 0x0154, 0x8086, 0x1e55, 0x8086, 0x1e55, "RV11$", "Roda", "Lizard RV11", P2, "Roda", "RV11", 0, OK, p2_whitelist_laptop},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002527 {0x8086, 0x24d3, 0x144d, 0xb025, 0x8086, 0x1050, 0x144d, 0xb025, NULL, NULL, NULL, P3, "Samsung", "Polaris 32", 0, OK, intel_ich_gpio21_raise},
2528 {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", P3, "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e},
2529 {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, P3, "Shuttle", "AK38N", 256, OK, NULL},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002530 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, P3, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower},
Joshua Roysb992d342011-11-02 14:31:18 +00002531 {0x10de, 0x0364, 0x108e, 0x6676, 0x10de, 0x0369, 0x108e, 0x6676, "^Sun Ultra 40 M2", NULL, NULL, P3, "Sun", "Ultra 40 M2", 0, OK, board_sun_ultra_40_m2},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002532 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, P3, "Tekram", "P6Pro-A5", 256, OK, NULL},
2533 {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, P3, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e},
Michael Karcherbfd89a52012-02-12 00:13:14 +00002534 {0x8086, 0x7120, 0x109f, 0x3157, 0x8086, 0x2410, 0, 0, NULL, NULL, NULL, P3, "TriGem", "Anaheim-3", 0, OK, intel_ich_gpio22_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002535 {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, P3, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e},
2536 {0x1106, 0x0259, 0x1106, 0xAA07, 0x1106, 0x3227, 0x1106, 0xAA07, NULL, NULL, NULL, P3, "VIA", "EPIA EK", 0, NT, via_vt823x_gpio9_raise},
2537 {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, P3, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise},
2538 {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, P3, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise},
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00002539#endif
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002540 { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, P3, NULL, NULL, 0, NT, NULL}, /* end marker */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002541};
2542
Stefan Tauner600576b2014-06-12 22:57:36 +00002543int selfcheck_board_enables(void)
2544{
2545 if (board_matches[ARRAY_SIZE(board_matches) - 1].vendor_name != NULL) {
2546 msg_gerr("Board enables table miscompilation!\n");
2547 return 1;
2548 }
2549
2550 int ret = 0;
2551 unsigned int i;
Nico Huber92b17a52019-10-04 18:47:24 +02002552 for (i = 0; i + 1 < ARRAY_SIZE(board_matches); i++) {
Stefan Tauner600576b2014-06-12 22:57:36 +00002553 const struct board_match *b = &board_matches[i];
2554 if (b->vendor_name == NULL || b->board_name == NULL) {
2555 msg_gerr("ERROR: Board enable #%d does not define a vendor and board name.\n"
Nico Huberac90af62022-12-18 00:22:47 +00002556 "Please report a bug at flashrom-stable@flashrom.org\n", i);
Stefan Tauner600576b2014-06-12 22:57:36 +00002557 ret = 1;
2558 continue;
2559 }
2560 if ((b->first_vendor == 0 || b->first_device == 0 ||
2561 b->second_vendor == 0 || b->second_device == 0) ||
2562 ((b->lb_vendor == NULL) ^ (b->lb_part == NULL)) ||
2563 (b->max_rom_decode_parallel == 0 && b->enable == NULL)) {
2564 msg_gerr("ERROR: Board enable for %s %s is misdefined.\n"
Nico Huberac90af62022-12-18 00:22:47 +00002565 "Please report a bug at flashrom-stable@flashrom.org\n",
Stefan Tauner600576b2014-06-12 22:57:36 +00002566 b->vendor_name, b->board_name);
2567 ret = 1;
2568 }
2569 }
2570 return ret;
2571}
2572
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002573/* Parse the <vendor>:<board> string specified by the user as part of -p internal:mainboard=<vendor>:<board>.
2574 * Parameters vendor and model will be overwritten. Returns 0 on success.
2575 * Note: strtok modifies the original string, so we work on a copy and allocate memory for the results.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002576 */
Jacob Garber1c091d12019-08-12 11:14:14 -06002577int board_parse_parameter(const char *boardstring, char **vendor, char **model)
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002578{
2579 /* strtok may modify the original string. */
2580 char *tempstr = strdup(boardstring);
2581 char *tempstr2 = NULL;
2582 strtok(tempstr, ":");
2583 tempstr2 = strtok(NULL, ":");
2584 if (tempstr == NULL || tempstr2 == NULL) {
2585 free(tempstr);
2586 msg_pinfo("Please supply the board vendor and model name with the "
2587 "-p internal:mainboard=<vendor>:<model> option.\n");
2588 return 1;
2589 }
2590 *vendor = strdup(tempstr);
2591 *model = strdup(tempstr2);
2592 msg_pspew("-p internal:mainboard: vendor=\"%s\", model=\"%s\"\n", tempstr, tempstr2);
2593 free(tempstr);
2594 return 0;
2595}
2596
2597/*
2598 * Match boards on vendor and model name.
Stefan Tauner57f276f2015-01-24 15:16:14 +00002599 * The string parameters can come either from the coreboot table or the command line (i.e. the user).
2600 * The boolean needs to be set accordingly to compare them to the right entries of the board enables table.
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002601 * Require main PCI IDs to match too as extra safety.
Stefan Tauner57f276f2015-01-24 15:16:14 +00002602 * Parameters vendor and model must be non-NULL!
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002603 */
Stefan Tauner57f276f2015-01-24 15:16:14 +00002604static const struct board_match *board_match_name(const char *vendor, const char *model, bool cb)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002605{
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002606 const struct board_match *board = board_matches;
2607 const struct board_match *partmatch = NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002608
Uwe Hermanna93045c2009-05-09 00:47:04 +00002609 for (; board->vendor_name; board++) {
Stefan Tauner57f276f2015-01-24 15:16:14 +00002610 const char *cur_vendor = cb ? board->lb_vendor : board->vendor_name;
2611 const char *cur_model = cb ? board->lb_part : board->board_name;
2612
2613 if (!cur_vendor || strcasecmp(cur_vendor, vendor))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002614 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002615
Stefan Tauner57f276f2015-01-24 15:16:14 +00002616 if (!cur_model || strcasecmp(cur_model, model))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002617 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002618
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002619 if (!pci_dev_find(board->first_vendor, board->first_device)) {
2620 msg_pdbg("Odd. Board name \"%s\":\"%s\" matches, but first PCI device %04x:%04x "
2621 "doesn't.\n", vendor, model, board->first_vendor, board->first_device);
Uwe Hermanna7e05482007-05-09 10:17:44 +00002622 continue;
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002623 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002624
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002625 if (!pci_dev_find(board->second_vendor, board->second_device)) {
2626 msg_pdbg("Odd. Board name \"%s\":\"%s\" matches, but second PCI device %04x:%04x "
2627 "doesn't.\n", vendor, model, board->second_vendor, board->second_device);
Uwe Hermanna7e05482007-05-09 10:17:44 +00002628 continue;
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002629 }
Peter Stuge6b53fed2008-01-27 16:21:21 +00002630
2631 if (partmatch) {
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002632 /* More than one entry has a matching name. */
Nico Huberac90af62022-12-18 00:22:47 +00002633 msg_perr("Board name \"%s\":\"%s\" and PCI IDs matched more than one board enable\n"
2634 "entry. Please report a bug at flashrom-stable@flashrom.org\n", vendor, model);
Peter Stuge6b53fed2008-01-27 16:21:21 +00002635 return NULL;
2636 }
2637 partmatch = board;
Uwe Hermanna7e05482007-05-09 10:17:44 +00002638 }
Uwe Hermann372eeb52007-12-04 21:49:06 +00002639
Peter Stuge6b53fed2008-01-27 16:21:21 +00002640 if (partmatch)
2641 return partmatch;
2642
Uwe Hermanna7e05482007-05-09 10:17:44 +00002643 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002644}
2645
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002646/*
Uwe Hermannffec5f32007-08-23 16:08:21 +00002647 * Match boards on PCI IDs and subsystem IDs.
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002648 * Second set of IDs can be either main+subsystem IDs, main IDs or no IDs.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002649 */
Richard Hughes93e16252018-12-19 11:54:47 +00002650static const struct board_match *board_match_pci_ids(enum board_match_phase phase)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002651{
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002652 const struct board_match *board = board_matches;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002653
Uwe Hermanna93045c2009-05-09 00:47:04 +00002654 for (; board->vendor_name; board++) {
Michael Karcher2eab70d2010-02-04 10:58:50 +00002655 if ((!board->first_card_vendor || !board->first_card_device) &&
2656 !board->dmi_pattern)
Uwe Hermanna7e05482007-05-09 10:17:44 +00002657 continue;
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002658 if (board->phase != phase)
2659 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002660
Uwe Hermanna7e05482007-05-09 10:17:44 +00002661 if (!pci_card_find(board->first_vendor, board->first_device,
Uwe Hermann394131e2008-10-18 21:14:13 +00002662 board->first_card_vendor,
2663 board->first_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002664 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002665
Uwe Hermanna7e05482007-05-09 10:17:44 +00002666 if (board->second_vendor) {
2667 if (board->second_card_vendor) {
2668 if (!pci_card_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00002669 board->second_device,
2670 board->second_card_vendor,
2671 board->second_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002672 continue;
2673 } else {
2674 if (!pci_dev_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00002675 board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002676 continue;
2677 }
2678 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002679
Sean Nelson4c6d3a42013-09-11 23:35:03 +00002680#if defined(__i386__) || defined(__x86_64__)
Michael Karcher6701ee82010-01-20 14:14:11 +00002681 if (board->dmi_pattern) {
2682 if (!has_dmi_support) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00002683 msg_pwarn("Warning: Can't autodetect %s %s, DMI info unavailable.\n",
2684 board->vendor_name, board->board_name);
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002685 msg_pinfo("Please supply the board vendor and model name with the "
2686 "-p internal:mainboard=<vendor>:<model> option.\n");
Michael Karcher6701ee82010-01-20 14:14:11 +00002687 continue;
2688 } else {
2689 if (!dmi_match(board->dmi_pattern))
2690 continue;
2691 }
2692 }
Sean Nelson4c6d3a42013-09-11 23:35:03 +00002693#endif // defined(__i386__) || defined(__x86_64__)
Uwe Hermanna7e05482007-05-09 10:17:44 +00002694 return board;
2695 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002696
Uwe Hermanna7e05482007-05-09 10:17:44 +00002697 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002698}
2699
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002700static int board_enable_safetycheck(const struct board_match *board)
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002701{
2702 if (!board)
2703 return 1;
2704
2705 if (board->status == OK)
2706 return 0;
2707
2708 if (!force_boardenable) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00002709 msg_pwarn("Warning: The mainboard-specific code for %s %s has not been tested,\n"
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002710 "and thus will not be executed by default. Depending on your hardware,\n"
2711 "erasing, writing or even probing can fail without running this code.\n\n"
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002712 "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n"
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002713 "\"internal programmer\") for details.\n", board->vendor_name, board->board_name);
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002714 return 1;
2715 }
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00002716 msg_pwarn("NOTE: Running an untested board enable procedure.\n"
Nico Huberac90af62022-12-18 00:22:47 +00002717 "Please report success/failure to flashrom-stable@flashrom.org.\n");
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002718 return 0;
2719}
2720
2721/* FIXME: Should this be identical to board_flash_enable? */
2722static int board_handle_phase(enum board_match_phase phase)
2723{
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002724 const struct board_match *board = NULL;
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002725
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002726 board = board_match_pci_ids(phase);
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002727
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002728 if (!board)
2729 return 0;
2730
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002731 if (board_enable_safetycheck(board))
2732 return 0;
2733
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002734 if (!board->enable) {
2735 /* Not sure if there is a valid case for this. */
2736 msg_perr("Board match found, but nothing to do?\n");
2737 return 0;
2738 }
2739
2740 return board->enable();
2741}
2742
2743void board_handle_before_superio(void)
2744{
2745 board_handle_phase(P1);
2746}
2747
2748void board_handle_before_laptop(void)
2749{
2750 board_handle_phase(P2);
2751}
2752
Stefan Taunerfa9fa712012-09-24 21:29:29 +00002753int board_flash_enable(const char *vendor, const char *model, const char *cb_vendor, const char *cb_model)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002754{
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002755 const struct board_match *board = NULL;
Uwe Hermanna7e05482007-05-09 10:17:44 +00002756 int ret = 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002757
Stefan Taunerfa9fa712012-09-24 21:29:29 +00002758 if (vendor != NULL && model != NULL) {
Stefan Tauner57f276f2015-01-24 15:16:14 +00002759 board = board_match_name(vendor, model, false);
Stefan Taunerfa9fa712012-09-24 21:29:29 +00002760 if (!board) { /* If a board was given by the user it has to match, else we abort here. */
2761 msg_perr("No suitable board enable found for vendor=\"%s\", model=\"%s\".\n",
2762 vendor, model);
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002763 return 1;
Stefan Taunerfa9fa712012-09-24 21:29:29 +00002764 }
2765 }
2766 if (board == NULL && cb_vendor != NULL && cb_model != NULL) {
Stefan Tauner57f276f2015-01-24 15:16:14 +00002767 board = board_match_name(cb_vendor, cb_model, true);
Stefan Taunerfa9fa712012-09-24 21:29:29 +00002768 if (!board) { /* Failure is an option here, because many cb boards don't require an enable. */
2769 msg_pdbg2("No board enable found matching coreboot IDs vendor=\"%s\", model=\"%s\".\n",
2770 cb_vendor, cb_model);
2771 }
2772 }
2773 if (board == NULL) {
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002774 board = board_match_pci_ids(P3);
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002775 if (!board) /* i.e. there is just no board enable available for this board */
2776 return 0;
2777 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002778
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002779 if (board_enable_safetycheck(board))
2780 return 1;
Michael Karcher7f0c3ec2010-03-07 22:29:28 +00002781
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002782 /* limit the maximum size of the parallel bus */
2783 if (board->max_rom_decode_parallel)
2784 max_rom_decode.parallel = board->max_rom_decode_parallel * 1024;
Luc Verhaegen93938c32010-01-20 14:45:03 +00002785
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002786 if (board->enable != NULL) {
2787 msg_pinfo("Enabling full flash access for board \"%s %s\"... ",
2788 board->vendor_name, board->board_name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002789
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002790 ret = board->enable();
2791 if (ret)
2792 msg_pinfo("FAILED!\n");
2793 else
2794 msg_pinfo("OK.\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +00002795 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002796
Uwe Hermanna7e05482007-05-09 10:17:44 +00002797 return ret;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002798}