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Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
5 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +00006 * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
Carl-Daniel Hailfinger92242622007-09-27 14:29:57 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00008 *
Uwe Hermannd1107642007-08-29 17:52:32 +00009 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000012 *
Uwe Hermannd1107642007-08-29 17:52:32 +000013 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000021 */
22
23/*
24 * Contains the board specific flash enables.
25 */
26
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000027#include <string.h>
Mart Raudseppfaa62fb2008-02-20 11:11:18 +000028#include <fcntl.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000029#include "flash.h"
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000030
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000031/*
Uwe Hermannffec5f32007-08-23 16:08:21 +000032 * Helper functions for many Winbond Super I/Os of the W836xx range.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000033 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000034/* Enter extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000035void w836xx_ext_enter(uint16_t port)
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000036{
Andriy Gapon65c1b862008-05-22 13:22:45 +000037 OUTB(0x87, port);
38 OUTB(0x87, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000039}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000040
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000041/* Leave extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000042void w836xx_ext_leave(uint16_t port)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000043{
Andriy Gapon65c1b862008-05-22 13:22:45 +000044 OUTB(0xAA, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000045}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000046
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000047/* Generic Super I/O helper functions */
48uint8_t sio_read(uint16_t port, uint8_t reg)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000049{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000050 OUTB(reg, port);
51 return INB(port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000052}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000053
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000054void sio_write(uint16_t port, uint8_t reg, uint8_t data)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000055{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000056 OUTB(reg, port);
57 OUTB(data, port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000058}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000059
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000060void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000061{
Ronald G. Minnichfa496922007-10-12 21:22:40 +000062 uint8_t tmp;
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000063
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000064 OUTB(reg, port);
65 tmp = INB(port + 1) & ~mask;
66 OUTB(tmp | (data & mask), port + 1);
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000067}
68
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000069/* Not used yet. */
70#if 0
71static int enable_flash_decode_superio(void)
72{
73 int ret;
74 uint8_t tmp;
75
76 switch (superio.vendor) {
77 case SUPERIO_VENDOR_NONE:
78 ret = -1;
79 break;
80 case SUPERIO_VENDOR_ITE:
81 enter_conf_mode_ite(superio.port);
Uwe Hermann43959702010-03-13 17:28:29 +000082 /* Enable flash mapping. Works for most old ITE style Super I/O. */
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000083 tmp = sio_read(superio.port, 0x24);
84 tmp |= 0xfc;
85 sio_write(superio.port, 0x24, tmp);
86 exit_conf_mode_ite(superio.port);
87 ret = 0;
88 break;
89 default:
Sean Nelson316a29f2010-05-07 20:09:04 +000090 msg_pdbg("Unhandled Super I/O type!\n");
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000091 ret = -1;
92 break;
93 }
94 return ret;
95}
96#endif
97
Uwe Hermannffec5f32007-08-23 16:08:21 +000098/**
99 * Winbond W83627HF: Raise GPIO24.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000100 *
101 * Suited for:
Uwe Hermannffec5f32007-08-23 16:08:21 +0000102 * - Agami Aruma
103 * - IWILL DK8-HTX
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000104 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000105static int w83627hf_gpio24_raise(uint16_t port, const char *name)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000106{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000107 w836xx_ext_enter(port);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000108
Uwe Hermann372eeb52007-12-04 21:49:06 +0000109 /* Is this the W83627HF? */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000110 if (sio_read(port, 0x20) != 0x52) { /* Super I/O device ID reg. */
Sean Nelson316a29f2010-05-07 20:09:04 +0000111 msg_perr("\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n",
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000112 name, sio_read(port, 0x20));
113 w836xx_ext_leave(port);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000114 return -1;
115 }
116
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000117 /* PIN89S: WDTO/GP24 multiplex -> GPIO24 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000118 sio_mask(port, 0x2B, 0x10, 0x10);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000119
Uwe Hermann372eeb52007-12-04 21:49:06 +0000120 /* Select logical device 8: GPIO port 2 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000121 sio_write(port, 0x07, 0x08);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000122
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000123 sio_mask(port, 0x30, 0x01, 0x01); /* Activate logical device. */
124 sio_mask(port, 0xF0, 0x00, 0x10); /* GPIO24 -> output */
125 sio_mask(port, 0xF2, 0x00, 0x10); /* Clear GPIO24 inversion */
126 sio_mask(port, 0xF1, 0x10, 0x10); /* Raise GPIO24 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000127
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000128 w836xx_ext_leave(port);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000129
130 return 0;
131}
132
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000133static int w83627hf_gpio24_raise_2e(const char *name)
134{
Mondrian nuessle197d6cd2009-04-09 14:28:36 +0000135 return w83627hf_gpio24_raise(0x2e, name);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000136}
137
138/**
139 * Winbond W83627THF: GPIO 4, bit 4
140 *
141 * Suited for:
Peter Stugecce26822008-07-21 17:48:40 +0000142 * - MSI K8T Neo2-F
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000143 * - MSI K8N-NEO3
144 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000145static int w83627thf_gpio4_4_raise(uint16_t port, const char *name)
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000146{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000147 w836xx_ext_enter(port);
Uwe Hermann372eeb52007-12-04 21:49:06 +0000148
149 /* Is this the W83627THF? */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000150 if (sio_read(port, 0x20) != 0x82) { /* Super I/O device ID reg. */
Sean Nelson316a29f2010-05-07 20:09:04 +0000151 msg_perr("\nERROR: %s: W83627THF: Wrong ID: 0x%02X.\n",
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000152 name, sio_read(port, 0x20));
153 w836xx_ext_leave(port);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000154 return -1;
155 }
156
157 /* PINxxxxS: GPIO4/bit 4 multiplex -> GPIOXXX */
158
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000159 sio_write(port, 0x07, 0x09); /* Select LDN 9: GPIO port 4 */
160 sio_mask(port, 0x30, 0x02, 0x02); /* Activate logical device. */
161 sio_mask(port, 0xF4, 0x00, 0x10); /* GPIO4 bit 4 -> output */
162 sio_mask(port, 0xF6, 0x00, 0x10); /* Clear GPIO4 bit 4 inversion */
163 sio_mask(port, 0xF5, 0x10, 0x10); /* Raise GPIO4 bit 4 */
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000164
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000165 w836xx_ext_leave(port);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000166
167 return 0;
168}
169
Peter Stugecce26822008-07-21 17:48:40 +0000170static int w83627thf_gpio4_4_raise_2e(const char *name)
171{
172 return w83627thf_gpio4_4_raise(0x2e, name);
173}
174
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000175static int w83627thf_gpio4_4_raise_4e(const char *name)
176{
Uwe Hermann372eeb52007-12-04 21:49:06 +0000177 return w83627thf_gpio4_4_raise(0x4e, name);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000178}
Uwe Hermann372eeb52007-12-04 21:49:06 +0000179
Uwe Hermannffec5f32007-08-23 16:08:21 +0000180/**
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000181 * w83627: Enable MEMW# and set ROM size to max.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000182 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000183static void w836xx_memw_enable(uint16_t port)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000184{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000185 w836xx_ext_enter(port);
186 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000187 /* Enable MEMW# and set ROM size select to max. (4M). */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000188 sio_mask(port, 0x24, 0x28, 0x28);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000189 }
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000190 w836xx_ext_leave(port);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000191}
192
193/**
Luc Verhaegen73d21192009-12-23 00:54:26 +0000194 * Suited for:
195 * - EPoX EP-8K5A2: VIA KT333 + VT8235.
196 * - Albatron PM266A Pro: VIA P4M266A + VT8235.
197 * - Shuttle AK31 (all versions): VIA KT266 + VT8233.
198 * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
199 * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000200 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000201static int w836xx_memw_enable_2e(const char *name)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000202{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000203 w836xx_memw_enable(0x2E);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000204
Luc Verhaegen73d21192009-12-23 00:54:26 +0000205 return 0;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000206}
207
Luc Verhaegen21f54962010-01-20 14:45:07 +0000208/**
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000209 * Suited for:
210 * - Termtek TK-3370 (rev. 2.5b)
211 */
212static int w836xx_memw_enable_4e(const char *name)
213{
214 w836xx_memw_enable(0x4E);
215
216 return 0;
217}
218
219/**
Luc Verhaegen21f54962010-01-20 14:45:07 +0000220 *
221 */
222static int it8705f_write_enable(uint8_t port, const char *name)
223{
224 enter_conf_mode_ite(port);
225 sio_mask(port, 0x24, 0x04, 0x04); /* Flash ROM I/F Writes Enable */
226 exit_conf_mode_ite(port);
227
228 return 0;
229}
230
231/**
232 * Suited for:
233 * - AOpen vKM400Am-S: VIA KM400 + VT8237 + IT8705F.
234 * - Biostar P4M80-M4: VIA P4M800 + VT8237 + IT8705AF
235 * - Elitegroup K7S6A: SiS745 + ITE IT8705F
236 * - Elitegroup K7VTA3: VIA Apollo KT266/A/333 + VIA VT8235 + ITE IT8705F
237 * - GIGABYTE GA-7VT600: VIA KT600 + VT8237 + IT8705
238 * - Shuttle AK38N: VIA KT333CF + VIA VT8235 + ITE IT8705F
239 *
Uwe Hermann43959702010-03-13 17:28:29 +0000240 * The SIS950 Super I/O probably requires the same flash write enable.
Luc Verhaegen21f54962010-01-20 14:45:07 +0000241 */
242static int it8705f_write_enable_2e(const char *name)
243{
244 return it8705f_write_enable(0x2e, name);
245}
Luc Verhaegen73d21192009-12-23 00:54:26 +0000246
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000247static int pc87360_gpio_set(uint8_t gpio, int raise)
248{
249 static const int bankbase[] = {0, 4, 8, 10, 12};
250 int gpio_bank = gpio / 8;
251 int gpio_pin = gpio % 8;
252 uint16_t baseport;
Uwe Hermann43959702010-03-13 17:28:29 +0000253 uint8_t id, val;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000254
Uwe Hermann43959702010-03-13 17:28:29 +0000255 if (gpio_bank > 4) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000256 msg_perr("PC87360: Invalid GPIO %d\n", gpio);
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000257 return -1;
258 }
259
260 id = sio_read(0x2E, 0x20);
Uwe Hermann43959702010-03-13 17:28:29 +0000261 if (id != 0xE1) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000262 msg_perr("PC87360: unexpected ID %02x\n", id);
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000263 return -1;
264 }
265
Uwe Hermann43959702010-03-13 17:28:29 +0000266 sio_write(0x2E, 0x07, 0x07); /* Select GPIO device */
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000267 baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
Uwe Hermann43959702010-03-13 17:28:29 +0000268 if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000269 msg_perr("PC87360: invalid GPIO base address %04x\n",
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000270 baseport);
271 return -1;
272 }
273 sio_mask (0x2E, 0x30, 0x01, 0x01); /* Enable logical device */
Uwe Hermann43959702010-03-13 17:28:29 +0000274 sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin);
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000275 sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output */
276
277 val = INB(baseport + bankbase[gpio_bank]);
Uwe Hermann43959702010-03-13 17:28:29 +0000278 if (raise)
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000279 val |= 1 << gpio_pin;
280 else
281 val &= ~(1 << gpio_pin);
282 OUTB(val, baseport + bankbase[gpio_bank]);
283
284 return 0;
285}
286
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000287/**
288 * VT823x: Set one of the GPIO pins.
289 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000290static int via_vt823x_gpio_set(uint8_t gpio, int raise)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000291{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000292 struct pci_dev *dev;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000293 uint16_t base;
David Bartleyf58d3642009-12-09 07:53:01 +0000294 uint8_t val, bit, offset;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000295
Luc Verhaegen73d21192009-12-23 00:54:26 +0000296 dev = pci_dev_find_vendorclass(0x1106, 0x0601);
297 switch (dev->device_id) {
298 case 0x3177: /* VT8235 */
299 case 0x3227: /* VT8237R */
300 case 0x3337: /* VT8237A */
301 break;
302 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000303 msg_perr("\nERROR: VT823x ISA bridge not found.\n");
Luc Verhaegen73d21192009-12-23 00:54:26 +0000304 return -1;
305 }
306
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000307 if ((gpio >= 12) && (gpio <= 15)) {
308 /* GPIO12-15 -> output */
309 val = pci_read_byte(dev, 0xE4);
310 val |= 0x10;
311 pci_write_byte(dev, 0xE4, val);
312 } else if (gpio == 9) {
313 /* GPIO9 -> Output */
314 val = pci_read_byte(dev, 0xE4);
315 val |= 0x20;
316 pci_write_byte(dev, 0xE4, val);
David Bartleyf58d3642009-12-09 07:53:01 +0000317 } else if (gpio == 5) {
318 val = pci_read_byte(dev, 0xE4);
319 val |= 0x01;
320 pci_write_byte(dev, 0xE4, val);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000321 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000322 msg_perr("\nERROR: "
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000323 "VT823x GPIO%02d is not implemented.\n", gpio);
Luc Verhaegen73d21192009-12-23 00:54:26 +0000324 return -1;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000325 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000326
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000327 /* We need the I/O Base Address for this board's flash enable. */
328 base = pci_read_word(dev, 0x88) & 0xff80;
329
David Bartleyf58d3642009-12-09 07:53:01 +0000330 offset = 0x4C + gpio / 8;
331 bit = 0x01 << (gpio % 8);
332
333 val = INB(base + offset);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000334 if (raise)
335 val |= bit;
336 else
337 val &= ~bit;
David Bartleyf58d3642009-12-09 07:53:01 +0000338 OUTB(val, base + offset);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000339
Uwe Hermanna7e05482007-05-09 10:17:44 +0000340 return 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000341}
342
Uwe Hermannffec5f32007-08-23 16:08:21 +0000343/**
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000344 * Suited for ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000345 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000346static int via_vt823x_gpio5_raise(const char *name)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000347{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000348 /* On M2V-MX: GPO5 is connected to WP# and TBL#. */
349 return via_vt823x_gpio_set(5, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000350}
351
352/**
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000353 * Suited for VIA EPIA N & NL.
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000354 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000355static int via_vt823x_gpio9_raise(const char *name)
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000356{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000357 return via_vt823x_gpio_set(9, 1);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000358}
359
360/**
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000361 * Suited for VIA EPIA M and MII, and maybe other CLE266 based EPIAs.
Luc Verhaegen73d21192009-12-23 00:54:26 +0000362 *
363 * We don't need to do this for EPIA M when using coreboot, GPIO15 is never
364 * lowered there.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000365 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000366static int via_vt823x_gpio15_raise(const char *name)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000367{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000368 return via_vt823x_gpio_set(15, 1);
369}
370
371/**
372 * Winbond W83697HF Super I/O + VIA VT8235 southbridge
373 *
374 * Suited for:
375 * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
376 * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
377 */
378static int board_msi_kt4v(const char *name)
379{
380 int ret;
381
382 ret = via_vt823x_gpio_set(12, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000383 w836xx_memw_enable(0x2E);
Luc Verhaegen97866082008-02-09 02:03:06 +0000384
Luc Verhaegen73d21192009-12-23 00:54:26 +0000385 return ret;
Luc Verhaegen97866082008-02-09 02:03:06 +0000386}
387
388/**
Luc Verhaegen6b141752007-05-20 16:16:13 +0000389 * Suited for ASUS P5A.
390 *
391 * This is rather nasty code, but there's no way to do this cleanly.
392 * We're basically talking to some unknown device on SMBus, my guess
393 * is that it is the Winbond W83781D that lives near the DIP BIOS.
394 */
Luc Verhaegen6b141752007-05-20 16:16:13 +0000395static int board_asus_p5a(const char *name)
396{
397 uint8_t tmp;
398 int i;
399
400#define ASUSP5A_LOOP 5000
401
Andriy Gapon65c1b862008-05-22 13:22:45 +0000402 OUTB(0x00, 0xE807);
403 OUTB(0xEF, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000404
Andriy Gapon65c1b862008-05-22 13:22:45 +0000405 OUTB(0xFF, 0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000406
407 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000408 OUTB(0xE1, 0xFF);
409 if (INB(0xE800) & 0x04)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000410 break;
411 }
412
413 if (i == ASUSP5A_LOOP) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000414 msg_perr("%s: Unable to contact device.\n", name);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000415 return -1;
416 }
417
Andriy Gapon65c1b862008-05-22 13:22:45 +0000418 OUTB(0x20, 0xE801);
419 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000420
Andriy Gapon65c1b862008-05-22 13:22:45 +0000421 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000422
423 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000424 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000425 if (tmp & 0x70)
426 break;
427 }
428
429 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000430 msg_perr("%s: failed to read device.\n", name);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000431 return -1;
432 }
433
Andriy Gapon65c1b862008-05-22 13:22:45 +0000434 tmp = INB(0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000435 tmp &= ~0x02;
436
Andriy Gapon65c1b862008-05-22 13:22:45 +0000437 OUTB(0x00, 0xE807);
438 OUTB(0xEE, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000439
Andriy Gapon65c1b862008-05-22 13:22:45 +0000440 OUTB(tmp, 0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000441
Andriy Gapon65c1b862008-05-22 13:22:45 +0000442 OUTB(0xFF, 0xE800);
443 OUTB(0xE1, 0xFF);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000444
Andriy Gapon65c1b862008-05-22 13:22:45 +0000445 OUTB(0x20, 0xE801);
446 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000447
Andriy Gapon65c1b862008-05-22 13:22:45 +0000448 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000449
450 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000451 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000452 if (tmp & 0x70)
453 break;
454 }
455
456 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000457 msg_perr("%s: failed to write to device.\n", name);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000458 return -1;
459 }
460
461 return 0;
462}
463
Luc Verhaegena7e30502009-12-09 11:39:02 +0000464/*
465 * Set GPIO lines in the Broadcom HT-1000 southbridge.
466 *
467 * It's not a Super I/O but it uses the same index/data port method.
468 */
469static int board_hp_dl145_g3_enable(const char *name)
470{
471 /* GPIO 0 reg from PM regs */
472 /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
473 sio_mask(0xcd6, 0x44, 0x24, 0x24);
474
475 return 0;
476}
477
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000478static int board_ibm_x3455(const char *name)
479{
Luc Verhaegena7e30502009-12-09 11:39:02 +0000480 /* raise gpio13 */
Carl-Daniel Hailfinger500b4232009-06-01 21:30:42 +0000481 sio_mask(0xcd6, 0x45, 0x20, 0x20);
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000482
483 return 0;
484}
485
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000486/**
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000487 * Suited for Shuttle FN25 (SN25P): AMD S939 + NVIDIA CK804 (nForce4).
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000488 */
489static int board_shuttle_fn25(const char *name)
490{
491 struct pci_dev *dev;
492
493 dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA Bridge. */
494 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000495 msg_perr("\nERROR: NVIDIA nForce4 ISA bridge not found.\n");
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000496 return -1;
497 }
498
499 /* one of those bits seems to be connected to TBL#, but -ENOINFO. */
500 pci_write_byte(dev, 0x92, 0);
501
502 return 0;
503}
504
505/**
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000506 * Very similar to AMD 8111 IO Hub.
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000507 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000508static int nvidia_mcp_gpio_set(int gpio, int raise)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000509{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000510 struct pci_dev *dev;
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000511 uint16_t base;
512 uint8_t tmp;
513
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000514 if ((gpio < 0) || (gpio >= 0x40)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000515 msg_perr("\nERROR: unsupported GPIO: %d.\n", gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000516 return -1;
517 }
518
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000519 /* First, check the ISA Bridge */
520 dev = pci_dev_find_vendorclass(0x10DE, 0x0601);
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000521 switch (dev->device_id) {
522 case 0x0030: /* CK804 */
523 case 0x0050: /* MCP04 */
524 case 0x0060: /* MCP2 */
525 break;
526 default:
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000527 /* Newer MCPs use the SMBus Controller */
528 dev = pci_dev_find_vendorclass(0x10DE, 0x0C05);
529 switch (dev->device_id) {
530 case 0x0264: /* MCP51 */
531 break;
532 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000533 msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n");
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000534 return -1;
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000535 }
536 break;
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000537 }
538
539 base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */
540 base += 0xC0;
541
542 tmp = INB(base + gpio);
543 tmp &= ~0x0F; /* null lower nibble */
544 tmp |= 0x04; /* gpio -> output. */
545 if (raise)
546 tmp |= 0x01;
547 OUTB(tmp, base + gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000548
549 return 0;
550}
551
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000552/**
Sean Nelson392e05a2010-03-19 22:58:15 +0000553 * Suited for ASUS A8N-LA: nVidia MCP51.
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000554 * Suited for ASUS M2NBP-VM CSM: NVIDIA MCP51.
Michael Karcherb2184c12010-03-07 16:42:55 +0000555 */
556static int nvidia_mcp_gpio0_raise(const char *name)
557{
558 return nvidia_mcp_gpio_set(0x00, 1);
559}
560
561/**
Sean Nelson92bc6bd2010-03-19 22:37:29 +0000562 * Suited for Abit KN8 Ultra: nVidia CK804.
563 */
564static int nvidia_mcp_gpio2_lower(const char *name)
565{
566 return nvidia_mcp_gpio_set(0x02, 0);
567}
568
569/**
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000570 * Suited for MSI K8N Neo4: NVIDIA CK804.
571 * Suited for MSI K8N GM2-L: NVIDIA MCP51.
Luc Verhaegen6c5f7332009-12-23 03:01:36 +0000572 */
573static int nvidia_mcp_gpio2_raise(const char *name)
574{
575 return nvidia_mcp_gpio_set(0x02, 1);
576}
577
578/**
Michael Karcher8f10d242010-04-11 21:01:06 +0000579 * Suited for Abit NF7-S: NVIDIA CK804.
580 */
581static int nvidia_mcp_gpio8_raise(const char *name)
582{
583 return nvidia_mcp_gpio_set(0x08, 1);
584}
585
586/**
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000587 * Suited for ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04.
588 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000589static int nvidia_mcp_gpio10_raise(const char *name)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000590{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000591 return nvidia_mcp_gpio_set(0x10, 1);
592}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000593
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000594/**
595 * Suited for the Gigabyte GA-K8N-SLI: CK804 southbridge.
596 */
597static int nvidia_mcp_gpio21_raise(const char *name)
598{
599 return nvidia_mcp_gpio_set(0x21, 0x01);
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000600}
601
Luc Verhaegen2c04fab2009-10-05 18:46:35 +0000602/**
603 * Suited for EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2.
604 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000605static int nvidia_mcp_gpio31_raise(const char *name)
Luc Verhaegen2c04fab2009-10-05 18:46:35 +0000606{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000607 return nvidia_mcp_gpio_set(0x31, 0x01);
Luc Verhaegen2c04fab2009-10-05 18:46:35 +0000608}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000609
Luc Verhaegenfdd0c582007-08-11 16:59:11 +0000610/**
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000611 * Suited for Artec Group DBE61 and DBE62.
612 */
613static int board_artecgroup_dbe6x(const char *name)
614{
615#define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015
616#define DBE6x_PRI_BOOT_LOC_SHIFT (2)
617#define DBE6x_BOOT_OP_LATCHED_SHIFT (8)
618#define DBE6x_SEC_BOOT_LOC_SHIFT (10)
619#define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT)
620#define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT)
621#define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT)
622#define DBE6x_BOOT_LOC_FLASH (2)
623#define DBE6x_BOOT_LOC_FWHUB (3)
624
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000625 msr_t msr;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000626 unsigned long boot_loc;
627
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000628 /* Geode only has a single core */
629 if (setup_cpu_msr(0))
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000630 return -1;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000631
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000632 msr = rdmsr(DBE6x_MSR_DIVIL_BALL_OPTS);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000633
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000634 if ((msr.lo & (DBE6x_BOOT_OP_LATCHED)) ==
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000635 (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT))
636 boot_loc = DBE6x_BOOT_LOC_FWHUB;
637 else
638 boot_loc = DBE6x_BOOT_LOC_FLASH;
639
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000640 msr.lo &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC);
641 msr.lo |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) |
Uwe Hermann394131e2008-10-18 21:14:13 +0000642 (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000643
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000644 wrmsr(DBE6x_MSR_DIVIL_BALL_OPTS, msr);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000645
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000646 cleanup_cpu_msr();
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000647
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000648 return 0;
649}
650
Uwe Hermann93f66db2008-05-22 21:19:38 +0000651/**
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000652 * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}.
Luc Verhaegenf5226912009-12-14 10:41:58 +0000653 */
654static int intel_piix4_gpo_set(unsigned int gpo, int raise)
655{
Michael Karcher01f6d7d2010-02-24 00:00:21 +0000656 unsigned int gpo_byte, gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +0000657 struct pci_dev *dev;
658 uint32_t tmp, base;
659
660 dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */
661 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000662 msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +0000663 return -1;
664 }
665
666 /* sanity check */
667 if (gpo > 30) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000668 msg_perr("\nERROR: Intel PIIX4 has no GPO%d.\n", gpo);
Luc Verhaegenf5226912009-12-14 10:41:58 +0000669 return -1;
670 }
671
672 /* these are dual function pins which are most likely in use already */
673 if (((gpo >= 1) && (gpo <= 7)) ||
674 ((gpo >= 9) && (gpo <= 21)) || (gpo == 29)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000675 msg_perr("\nERROR: Unsupported PIIX4 GPO%d.\n", gpo);
Luc Verhaegenf5226912009-12-14 10:41:58 +0000676 return -1;
677 }
678
679 /* dual function that need special enable. */
680 if ((gpo >= 22) && (gpo <= 26)) {
681 tmp = pci_read_long(dev, 0xB0); /* GENCFG */
682 switch (gpo) {
683 case 22: /* XBUS: XDIR#/GPO22 */
684 case 23: /* XBUS: XOE#/GPO23 */
685 tmp |= 1 << 28;
686 break;
687 case 24: /* RTCSS#/GPO24 */
688 tmp |= 1 << 29;
689 break;
690 case 25: /* RTCALE/GPO25 */
691 tmp |= 1 << 30;
692 break;
693 case 26: /* KBCSS#/GPO26 */
694 tmp |= 1 << 31;
695 break;
696 }
697 pci_write_long(dev, 0xB0, tmp);
698 }
699
700 /* GPO {0,8,27,28,30} are always available. */
701
702 dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */
703 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000704 msg_perr("\nERROR: Intel PIIX4 PM not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +0000705 return -1;
706 }
707
708 /* PM IO base */
709 base = pci_read_long(dev, 0x40) & 0x0000FFC0;
710
Michael Karcher01f6d7d2010-02-24 00:00:21 +0000711 gpo_byte = gpo >> 3;
712 gpo_bit = gpo & 7;
713 tmp = INB(base + 0x34 + gpo_byte); /* GPO register */
Luc Verhaegenf5226912009-12-14 10:41:58 +0000714 if (raise)
Michael Karcher01f6d7d2010-02-24 00:00:21 +0000715 tmp |= 0x01 << gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +0000716 else
Michael Karcher01f6d7d2010-02-24 00:00:21 +0000717 tmp &= ~(0x01 << gpo_bit);
718 OUTB(tmp, base + 0x34 + gpo_byte);
Luc Verhaegenf5226912009-12-14 10:41:58 +0000719
720 return 0;
721}
722
723/**
724 * Suited for EPoX EP-BX3, and maybe some other Intel 440BX based boards.
725 */
726static int board_epox_ep_bx3(const char *name)
727{
728 return intel_piix4_gpo_set(22, 1);
729}
730
731/**
Michael Karcher51cd0c92010-03-19 22:35:21 +0000732 * Suited for Intel SE440BX-2
733 */
734static int intel_piix4_gpo27_lower(const char *name)
735{
736 return intel_piix4_gpo_set(27, 0);
737}
738
739/**
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000740 * Set a GPIO line on a given Intel ICH LPC controller.
Uwe Hermann93f66db2008-05-22 21:19:38 +0000741 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000742static int intel_ich_gpio_set(int gpio, int raise)
Uwe Hermann93f66db2008-05-22 21:19:38 +0000743{
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000744 /* Table mapping the different Intel ICH LPC chipsets. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000745 static struct {
746 uint16_t id;
747 uint8_t base_reg;
748 uint32_t bank0;
749 uint32_t bank1;
750 uint32_t bank2;
751 } intel_ich_gpio_table[] = {
752 {0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */
753 {0x2420, 0x58, 0x0FE30000, 0, 0}, /* 82801AB (ICH0) */
754 {0x2440, 0x58, 0x1BFF391B, 0, 0}, /* 82801BA (ICH2) */
755 {0x244C, 0x58, 0x1A23399B, 0, 0}, /* 82801BAM (ICH2M) */
756 {0x2450, 0x58, 0x1BFF0000, 0, 0}, /* 82801E (C-ICH) */
757 {0x2480, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801CA (ICH3-S) */
758 {0x248C, 0x58, 0x1A230000, 0x00000FFF, 0}, /* 82801CAM (ICH3-M) */
759 {0x24C0, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801DB/DBL (ICH4/ICH4-L) */
760 {0x24CC, 0x58, 0x1A030000, 0x00000FFF, 0}, /* 82801DBM (ICH4-M) */
761 {0x24D0, 0x58, 0x1BFF0000, 0x00030305, 0}, /* 82801EB/ER (ICH5/ICH5R) */
762 {0x2640, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FB/FR (ICH6/ICH6R) */
763 {0x2641, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FBM (ICH6M) */
764 {0x27B8, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GB/GR (ICH7 Family) */
765 {0x27B9, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GBM (ICH7-M) */
766 {0x27BD, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GHM (ICH7-M DH) */
767 {0x2810, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HB/HR (ICH8/R) */
768 {0x2811, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HBM (ICH8M-E) */
769 {0x2812, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HH (ICH8DH) */
770 {0x2814, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HO (ICH8DO) */
771 {0x2815, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HEM (ICH8M) */
772 {0x2912, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IH (ICH9DH) */
773 {0x2914, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IO (ICH9DO) */
774 {0x2916, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IR (ICH9R) */
775 {0x2917, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IEM (ICH9M-E) */
776 {0x2918, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IB (ICH9) */
777 {0x2919, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IBM (ICH9M) */
778 {0x3A14, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JDO (ICH10DO) */
779 {0x3A16, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIR (ICH10R) */
780 {0x3A18, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIB (ICH10) */
781 {0x3A1A, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JD (ICH10D) */
782 {0, 0, 0, 0, 0} /* end marker */
783 };
Uwe Hermann93f66db2008-05-22 21:19:38 +0000784
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000785 struct pci_dev *dev;
786 uint16_t base;
787 uint32_t tmp;
788 int i, allowed;
789
790 /* First, look for a known LPC bridge */
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +0000791 for (dev = pacc->devices; dev; dev = dev->next) {
792 pci_fill_info(dev, PCI_FILL_CLASS);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000793 if ((dev->vendor_id == 0x8086) &&
794 (dev->device_class == 0x0601)) { /* ISA Bridge */
795 /* Is this device in our list? */
796 for (i = 0; intel_ich_gpio_table[i].id; i++)
797 if (dev->device_id == intel_ich_gpio_table[i].id)
798 break;
799
800 if (intel_ich_gpio_table[i].id)
801 break;
802 }
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +0000803 }
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000804
Uwe Hermann93f66db2008-05-22 21:19:38 +0000805 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000806 msg_perr("\nERROR: No Known Intel LPC Bridge found.\n");
Uwe Hermann93f66db2008-05-22 21:19:38 +0000807 return -1;
808 }
809
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000810 /* According to the datasheets, all Intel ICHs have the GPIO bar 5:1
811 strapped to zero. From some mobile ICH9 version on, this becomes
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000812 6:1. The mask below catches all. */
813 base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0;
Uwe Hermann93f66db2008-05-22 21:19:38 +0000814
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000815 /* check whether the line is allowed */
816 if (gpio < 32)
817 allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01;
818 else if (gpio < 64)
819 allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01;
820 else
821 allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01;
822
823 if (!allowed) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000824 msg_perr("\nERROR: This Intel LPC Bridge does not allow"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000825 " setting GPIO%02d\n", gpio);
826 return -1;
827 }
828
Sean Nelson316a29f2010-05-07 20:09:04 +0000829 msg_pdbg("\nIntel ICH LPC Bridge: %sing GPIO%02d.\n",
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000830 raise ? "Rais" : "Dropp", gpio);
831
832 if (gpio < 32) {
833 /* Set line to GPIO */
834 tmp = INL(base);
835 /* ICH/ICH0 multiplexes 27/28 on the line set. */
836 if ((gpio == 28) &&
837 ((dev->device_id == 0x2410) || (dev->device_id == 0x2420)))
838 tmp |= 1 << 27;
839 else
840 tmp |= 1 << gpio;
841 OUTL(tmp, base);
842
843 /* As soon as we are talking to ICH8 and above, this register
844 decides whether we can set the gpio or not. */
845 if (dev->device_id > 0x2800) {
846 tmp = INL(base);
847 if (!(tmp & (1 << gpio))) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000848 msg_perr("\nERROR: This Intel LPC Bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000849 " does not allow setting GPIO%02d\n",
850 gpio);
851 return -1;
852 }
853 }
854
855 /* Set GPIO to OUTPUT */
856 tmp = INL(base + 0x04);
857 tmp &= ~(1 << gpio);
858 OUTL(tmp, base + 0x04);
859
860 /* Raise GPIO line */
861 tmp = INL(base + 0x0C);
862 if (raise)
863 tmp |= 1 << gpio;
864 else
865 tmp &= ~(1 << gpio);
866 OUTL(tmp, base + 0x0C);
867 } else if (gpio < 64) {
868 gpio -= 32;
869
870 /* Set line to GPIO */
871 tmp = INL(base + 0x30);
872 tmp |= 1 << gpio;
873 OUTL(tmp, base + 0x30);
874
875 /* As soon as we are talking to ICH8 and above, this register
876 decides whether we can set the gpio or not. */
877 if (dev->device_id > 0x2800) {
878 tmp = INL(base + 30);
879 if (!(tmp & (1 << gpio))) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000880 msg_perr("\nERROR: This Intel LPC Bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000881 " does not allow setting GPIO%02d\n",
882 gpio + 32);
883 return -1;
884 }
885 }
886
887 /* Set GPIO to OUTPUT */
888 tmp = INL(base + 0x34);
889 tmp &= ~(1 << gpio);
890 OUTL(tmp, base + 0x34);
891
892 /* Raise GPIO line */
893 tmp = INL(base + 0x38);
894 if (raise)
895 tmp |= 1 << gpio;
896 else
897 tmp &= ~(1 << gpio);
898 OUTL(tmp, base + 0x38);
899 } else {
900 gpio -= 64;
901
902 /* Set line to GPIO */
903 tmp = INL(base + 0x40);
904 tmp |= 1 << gpio;
905 OUTL(tmp, base + 0x40);
906
907 tmp = INL(base + 40);
908 if (!(tmp & (1 << gpio))) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000909 msg_perr("\nERROR: This Intel LPC Bridge does "
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000910 "not allow setting GPIO%02d\n", gpio + 64);
911 return -1;
912 }
913
914 /* Set GPIO to OUTPUT */
915 tmp = INL(base + 0x44);
916 tmp &= ~(1 << gpio);
917 OUTL(tmp, base + 0x44);
918
919 /* Raise GPIO line */
920 tmp = INL(base + 0x48);
921 if (raise)
922 tmp |= 1 << gpio;
923 else
924 tmp &= ~(1 << gpio);
925 OUTL(tmp, base + 0x48);
926 }
Uwe Hermann93f66db2008-05-22 21:19:38 +0000927
928 return 0;
929}
930
931/**
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000932 * Suited for Abit IP35: Intel P35 + ICH9R.
Michael Karcherb4a3d1c2010-03-03 16:15:12 +0000933 * Suited for Abit IP35 Pro: Intel P35 + ICH9R.
Uwe Hermann93f66db2008-05-22 21:19:38 +0000934 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000935static int intel_ich_gpio16_raise(const char *name)
Uwe Hermann93f66db2008-05-22 21:19:38 +0000936{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000937 return intel_ich_gpio_set(16, 1);
Uwe Hermann93f66db2008-05-22 21:19:38 +0000938}
939
Peter Stuge09c13332009-02-02 22:55:26 +0000940/**
James Lancaster998c9dc2010-03-19 22:39:24 +0000941 * Suited for ASUS A8JM: Intel 945 + ICH7
942 */
943static int intel_ich_gpio34_raise(const char *name)
944{
945 return intel_ich_gpio_set(34, 1);
946}
947
948/**
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000949 * Suited for MSI MS-7046: LGA775 + 915P + ICH6.
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +0000950 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000951static int intel_ich_gpio19_raise(const char *name)
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +0000952{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000953 return intel_ich_gpio_set(19, 1);
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +0000954}
955
956/**
Luc Verhaegen6c5d4cc2009-11-28 18:26:21 +0000957 * Suited for:
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000958 * - ASUS P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2.
959 * - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5.
960 * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R.
Peter Stuge09c13332009-02-02 22:55:26 +0000961 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000962static int intel_ich_gpio21_raise(const char *name)
Peter Stuge09c13332009-02-02 22:55:26 +0000963{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000964 return intel_ich_gpio_set(21, 1);
Peter Stuge09c13332009-02-02 22:55:26 +0000965}
966
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000967/**
Michael Karcher03b80e92010-03-07 16:32:32 +0000968 * Suited for:
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000969 * - ASUS P4B266: socket478 + Intel 845D + ICH2.
970 * - ASUS P4B533-E: socket478 + 845E + ICH4
971 * - ASUS P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000972 */
973static int intel_ich_gpio22_raise(const char *name)
974{
975 return intel_ich_gpio_set(22, 1);
976}
977
978/**
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000979 * Suited for HP Vectra VL400: 815 + ICH + PC87360.
980 */
981
982static int board_hp_vl400(const char *name)
983{
984 int ret;
985 ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */
986 if (!ret)
987 ret = pc87360_gpio_set(0x09, 1); /* #WP ? */
988 if (!ret)
989 ret = pc87360_gpio_set(0x27, 1); /* #TBL */
990 return ret;
991}
992
993/**
Luc Verhaegen1265d8d2009-11-28 18:16:31 +0000994 * Suited for:
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000995 * - Dell PowerEdge 1850: Intel PPGA604 + E7520 + ICH5R.
Luc Verhaegen1265d8d2009-11-28 18:16:31 +0000996 * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R.
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000997 */
998static int intel_ich_gpio23_raise(const char *name)
999{
1000 return intel_ich_gpio_set(23, 1);
1001}
1002
1003/**
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001004 * Suited for IBase MB899: i945GM + ICH7.
1005 */
1006static int intel_ich_gpio26_raise(const char *name)
1007{
1008 return intel_ich_gpio_set(26, 1);
1009}
1010
1011/**
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001012 * Suited for Acorp 6A815EPD: socket 370 + intel 815 + ICH2.
1013 */
1014static int board_acorp_6a815epd(const char *name)
1015{
1016 int ret;
1017
1018 /* Lower Blocks Lock -- pin 7 of PLCC32 */
1019 ret = intel_ich_gpio_set(22, 1);
1020 if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */
1021 ret = intel_ich_gpio_set(23, 1);
1022
1023 return ret;
1024}
1025
1026/**
1027 * Suited for Kontron 986LCD-M: socket478 + 915GM + ICH7R.
1028 */
Stefan Reinauerac378972008-03-17 22:59:40 +00001029static int board_kontron_986lcd_m(const char *name)
1030{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001031 int ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001032
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001033 ret = intel_ich_gpio_set(34, 1); /* #TBL */
1034 if (!ret)
1035 ret = intel_ich_gpio_set(35, 1); /* #WP */
Stefan Reinauerac378972008-03-17 22:59:40 +00001036
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001037 return ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001038}
1039
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001040/**
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001041 * Suited for Soyo SY-7VCA: Pro133A + VT82C686.
1042 */
Michael Karcher06477332010-03-19 22:49:09 +00001043static int via_apollo_gpo_set(int gpio, int raise)
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001044{
Michael Karcher06477332010-03-19 22:49:09 +00001045 struct pci_dev *dev;
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001046 uint32_t base;
Michael Karcher06477332010-03-19 22:49:09 +00001047 uint32_t tmp;
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001048
1049 /* VT82C686 Power management */
1050 dev = pci_dev_find(0x1106, 0x3057);
1051 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001052 msg_perr("\nERROR: VT82C686 PM device not found.\n");
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001053 return -1;
1054 }
1055
Sean Nelson316a29f2010-05-07 20:09:04 +00001056 msg_pdbg("\nVIA Apollo ACPI: %sing GPIO%02d.\n",
Michael Karcher06477332010-03-19 22:49:09 +00001057 raise ? "Rais" : "Dropp", gpio);
1058
1059 /* select GPO function on multiplexed pins */
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001060 tmp = pci_read_byte(dev, 0x54);
Michael Karcher06477332010-03-19 22:49:09 +00001061 switch(gpio)
1062 {
1063 case 0:
1064 tmp &= ~0x03;
1065 break;
1066 case 1:
1067 tmp |= 0x04;
1068 break;
1069 case 2:
1070 tmp |= 0x08;
1071 break;
1072 case 3:
1073 tmp |= 0x10;
1074 break;
1075 }
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001076 pci_write_byte(dev, 0x54, tmp);
1077
1078 /* PM IO base */
1079 base = pci_read_long(dev, 0x48) & 0x0000FF00;
1080
1081 /* Drop GPO0 */
Michael Karcher06477332010-03-19 22:49:09 +00001082 tmp = INL(base + 0x4C);
1083 if (raise)
1084 tmp |= 1U << gpio;
1085 else
1086 tmp &= ~(1U << gpio);
1087 OUTL(tmp, base + 0x4C);
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001088
1089 return 0;
1090}
1091
Michael Karcher9f9e6132010-01-09 17:36:06 +00001092/**
Michael Karcher98eff462010-03-24 22:55:56 +00001093 * Suited for Abit VT6X4: Pro133x + VT82C686A
Michael Karcher187a46a2010-03-19 22:30:49 +00001094 */
1095static int via_apollo_gpo4_lower(const char *name)
1096{
1097 return via_apollo_gpo_set(4, 0);
1098}
1099
1100/**
Michael Karcher06477332010-03-19 22:49:09 +00001101 * Suited for Soyo SY-7VCA: Pro133A + VT82C686.
1102 */
1103static int via_apollo_gpo0_lower(const char *name)
1104{
1105 return via_apollo_gpo_set(0, 0);
1106}
1107
1108/**
Michael Karcher9f9e6132010-01-09 17:36:06 +00001109 * Enable some GPIO pin on SiS southbridge.
1110 * Suited for MSI 651M-L: SiS651 / SiS962
1111 */
1112static int board_msi_651ml(const char *name)
1113{
1114 struct pci_dev *dev;
Uwe Hermann43959702010-03-13 17:28:29 +00001115 uint16_t base, temp;
Michael Karcher9f9e6132010-01-09 17:36:06 +00001116
1117 dev = pci_dev_find(0x1039, 0x0962);
1118 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001119 msg_perr("Expected south bridge not found\n");
Michael Karcher9f9e6132010-01-09 17:36:06 +00001120 return 1;
1121 }
1122
1123 /* Registers 68 and 64 seem like bitmaps */
1124 base = pci_read_word(dev, 0x74);
1125 temp = INW(base + 0x68);
1126 temp &= ~(1 << 0); /* Make pin output? */
Michael Karcher0435dfd2010-01-09 23:31:13 +00001127 OUTW(temp, base + 0x68);
Michael Karcher9f9e6132010-01-09 17:36:06 +00001128
1129 temp = INW(base + 0x64);
1130 temp |= (1 << 0); /* Raise output? */
1131 OUTW(temp, base + 0x64);
1132
1133 w836xx_memw_enable(0x2E);
1134
1135 return 0;
1136}
1137
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001138/**
Michael Gold6d52e472009-06-19 13:00:24 +00001139 * Find the runtime registers of an SMSC Super I/O, after verifying its
1140 * chip ID.
1141 *
1142 * Returns the base port of the runtime register block, or 0 on error.
1143 */
1144static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id,
1145 uint8_t logical_device)
1146{
1147 uint16_t rt_port = 0;
1148
1149 /* Verify the chip ID. */
Uwe Hermann1432a602009-06-28 23:26:37 +00001150 OUTB(0x55, sio_port); /* Enable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00001151 if (sio_read(sio_port, 0x20) != chip_id) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001152 msg_perr("\nERROR: SMSC Super I/O not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +00001153 goto out;
1154 }
1155
1156 /* If the runtime block is active, get its address. */
1157 sio_write(sio_port, 0x07, logical_device);
1158 if (sio_read(sio_port, 0x30) & 1) {
1159 rt_port = (sio_read(sio_port, 0x60) << 8)
1160 | sio_read(sio_port, 0x61);
1161 }
1162
1163 if (rt_port == 0) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001164 msg_perr("\nERROR: "
Michael Gold6d52e472009-06-19 13:00:24 +00001165 "Super I/O runtime interface not available.\n");
1166 }
1167out:
Uwe Hermann1432a602009-06-28 23:26:37 +00001168 OUTB(0xaa, sio_port); /* Disable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00001169 return rt_port;
1170}
1171
1172/**
1173 * Disable write protection on the Mitac 6513WU. WP# on the FWH is
1174 * connected to GP30 on the Super I/O, and TBL# is always high.
1175 */
1176static int board_mitac_6513wu(const char *name)
1177{
1178 struct pci_dev *dev;
1179 uint16_t rt_port;
1180 uint8_t val;
1181
1182 dev = pci_dev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */
1183 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001184 msg_perr("\nERROR: Intel 82801AA ISA bridge not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +00001185 return -1;
1186 }
1187
Uwe Hermann1432a602009-06-28 23:26:37 +00001188 rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa);
Michael Gold6d52e472009-06-19 13:00:24 +00001189 if (rt_port == 0)
1190 return -1;
1191
1192 /* Configure the GPIO pin. */
1193 val = INB(rt_port + 0x33); /* GP30 config */
Uwe Hermann1432a602009-06-28 23:26:37 +00001194 val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */
Michael Gold6d52e472009-06-19 13:00:24 +00001195 OUTB(val, rt_port + 0x33);
1196
1197 /* Disable write protection. */
1198 val = INB(rt_port + 0x4d); /* GP3 values */
Uwe Hermann1432a602009-06-28 23:26:37 +00001199 val |= 0x01; /* Set GP30 high. */
Michael Gold6d52e472009-06-19 13:00:24 +00001200 OUTB(val, rt_port + 0x4d);
1201
1202 return 0;
1203}
1204
1205/**
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001206 * Suited for ASUS A7V8X: VIA KT400 + VT8235 + IT8703F-A
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001207 */
1208static int board_asus_a7v8x(const char *name)
1209{
1210 uint16_t id, base;
1211 uint8_t tmp;
1212
1213 /* find the IT8703F */
1214 w836xx_ext_enter(0x2E);
1215 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
1216 w836xx_ext_leave(0x2E);
1217
1218 if (id != 0x8701) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001219 msg_perr("\nERROR: IT8703F Super I/O not found.\n");
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001220 return -1;
1221 }
1222
1223 /* Get the GP567 IO base */
1224 w836xx_ext_enter(0x2E);
1225 sio_write(0x2E, 0x07, 0x0C);
1226 base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
1227 w836xx_ext_leave(0x2E);
1228
1229 if (!base) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001230 msg_perr("\nERROR: Failed to read IT8703F Super I/O GPIO"
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001231 " Base.\n");
1232 return -1;
1233 }
1234
1235 /* Raise GP51. */
1236 tmp = INB(base);
1237 tmp |= 0x02;
1238 OUTB(tmp, base);
1239
1240 return 0;
1241}
1242
Luc Verhaegen72272912009-09-01 21:22:23 +00001243/*
1244 * General routine for raising/dropping GPIO lines on the ITE IT8712F.
1245 * There is only some limited checking on the port numbers.
1246 */
Uwe Hermann43959702010-03-13 17:28:29 +00001247static int it8712f_gpio_set(unsigned int line, int raise)
Luc Verhaegen72272912009-09-01 21:22:23 +00001248{
1249 unsigned int port;
1250 uint16_t id, base;
1251 uint8_t tmp;
1252
1253 port = line / 10;
1254 port--;
1255 line %= 10;
1256
1257 /* Check line */
1258 if ((port > 4) || /* also catches unsigned -1 */
1259 ((port < 4) && (line > 7)) || ((port == 4) && (line > 5))) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001260 msg_perr("\nERROR: Unsupported IT8712F GPIO Line %02d.\n", line);
Luc Verhaegen72272912009-09-01 21:22:23 +00001261 return -1;
1262 }
1263
1264 /* find the IT8712F */
1265 enter_conf_mode_ite(0x2E);
1266 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
1267 exit_conf_mode_ite(0x2E);
1268
1269 if (id != 0x8712) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001270 msg_perr("\nERROR: IT8712F Super I/O not found.\n");
Luc Verhaegen72272912009-09-01 21:22:23 +00001271 return -1;
1272 }
1273
1274 /* Get the GPIO base */
1275 enter_conf_mode_ite(0x2E);
1276 sio_write(0x2E, 0x07, 0x07);
1277 base = (sio_read(0x2E, 0x62) << 8) | sio_read(0x2E, 0x63);
1278 exit_conf_mode_ite(0x2E);
1279
1280 if (!base) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001281 msg_perr("\nERROR: Failed to read IT8712F Super I/O GPIO"
Luc Verhaegen72272912009-09-01 21:22:23 +00001282 " Base.\n");
1283 return -1;
1284 }
1285
1286 /* set GPIO. */
1287 tmp = INB(base + port);
1288 if (raise)
1289 tmp |= 1 << line;
1290 else
1291 tmp &= ~(1 << line);
1292 OUTB(tmp, base + port);
1293
1294 return 0;
1295}
1296
1297/**
Russ Dillbd622d12010-03-09 16:57:06 +00001298 * Suited for:
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001299 * - ASUS A7V600-X: VIA KT600 + VT8237 + IT8712F
1300 * - ASUS A7V8X-X: VIA KT400 + VT8235 + IT8712F
Luc Verhaegen72272912009-09-01 21:22:23 +00001301 */
Russ Dillbd622d12010-03-09 16:57:06 +00001302static int it8712f_gpio3_1_raise(const char *name)
Luc Verhaegen72272912009-09-01 21:22:23 +00001303{
1304 return it8712f_gpio_set(32, 1);
1305}
1306
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001307/**
Uwe Hermannd0e347d2009-10-06 13:00:00 +00001308 * Below is the list of boards which need a special "board enable" code in
1309 * flashrom before their ROM chip can be accessed/written to.
1310 *
1311 * NOTE: Please add boards that _don't_ need such enables or don't work yet
1312 * to the respective tables in print.c. Thanks!
1313 *
Uwe Hermannffec5f32007-08-23 16:08:21 +00001314 * We use 2 sets of IDs here, you're free to choose which is which. This
1315 * is to provide a very high degree of certainty when matching a board on
1316 * the basis of subsystem/card IDs. As not every vendor handles
1317 * subsystem/card IDs in a sane manner.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001318 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00001319 * Keep the second set NULLed if it should be ignored. Keep the subsystem IDs
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00001320 * NULLed if they don't identify the board fully and if you can't use DMI.
1321 * But please take care to provide an as complete set of pci ids as possible;
1322 * autodetection is the preferred behaviour and we would like to make sure that
1323 * matches are unique.
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001324 *
Michael Karcher6701ee82010-01-20 14:14:11 +00001325 * If PCI IDs are not sufficient for board matching, the match can be further
1326 * constrained by a string that has to be present in the DMI database for
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001327 * the baseboard or the system entry. The pattern is matched by case sensitive
Michael Karcher6701ee82010-01-20 14:14:11 +00001328 * substring match, unless it is anchored to the beginning (with a ^ in front)
1329 * or the end (with a $ at the end). Both anchors may be specified at the
1330 * same time to match the full field.
1331 *
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00001332 * When a board is matched through DMI, the first and second main PCI IDs
1333 * and the first subsystem PCI ID have to match as well. If you specify the
1334 * first subsystem ID as 0x0:0x0, the DMI matching code expects that the
1335 * subsystem ID of that device is indeed zero.
1336 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00001337 * The coreboot ids are used two fold. When running with a coreboot firmware,
1338 * the ids uniquely matches the coreboot board identification string. When a
1339 * legacy bios is installed and when autodetection is not possible, these ids
1340 * can be used to identify the board through the -m command line argument.
1341 *
1342 * When a board is identified through its coreboot ids (in both cases), the
1343 * main pci ids are still required to match, as a safeguard.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001344 */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001345
Uwe Hermanndeeebe22009-05-08 16:23:34 +00001346/* Please keep this list alphabetically ordered by vendor/board name. */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001347struct board_pciid_enable board_pciid_enables[] = {
Uwe Hermann5ab88892009-06-21 20:50:22 +00001348
Michael Karcher0bdc0922010-02-28 01:33:48 +00001349 /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */
Sean Nelsonc94746d2010-03-19 23:00:07 +00001350 {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "Abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001351 {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise},
Michael Karcherb4a3d1c2010-03-03 16:15:12 +00001352 {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise},
Sean Nelson92bc6bd2010-03-19 22:37:29 +00001353 {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, "Abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower},
Michael Karcher8f10d242010-04-11 21:01:06 +00001354 {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, "Abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise},
Michael Karcher98eff462010-03-24 22:55:56 +00001355 {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "Abit", "VT6X4", 0, OK, via_apollo_gpo4_lower},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001356 {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd},
1357 {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise},
1358 {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e},
1359 {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A", 0, OK, w836xx_memw_enable_2e},
1360 {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, NULL, "AOpen", "vKM400Am-S", 0, OK, it8705f_write_enable_2e},
1361 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x},
1362 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x},
Russ Dillbd622d12010-03-09 16:57:06 +00001363 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001364 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V8X", 0, OK, board_asus_a7v8x},
Russ Dillbd622d12010-03-09 16:57:06 +00001365 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001366 {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e},
James Lancaster998c9dc2010-03-19 22:39:24 +00001367 {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, "ASUS", "A8JM", 0, NT, intel_ich_gpio34_raise},
Luc Verhaegen49146c12010-03-19 22:26:44 +00001368 {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, NULL, "ASUS", "A8N", 0, NT, board_shuttle_fn25},
Sean Nelson392e05a2010-03-19 22:58:15 +00001369 {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI", NULL, NULL, "ASUS", "A8N-LA", 0, NT, nvidia_mcp_gpio0_raise},
Michael Karcherb2184c12010-03-07 16:42:55 +00001370 {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001371 {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise},
1372 {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise},
1373 {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise},
Michael Karcher255a9e02010-03-19 22:52:00 +00001374 {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise},
Michael Karcher6499d5a2010-03-17 06:19:23 +00001375 {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001376 {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
1377 {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", "ASUS", "P5A", 0, OK, board_asus_p5a},
1378 {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise},
1379 {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, NULL, "Biostar", "P4M80-M4", 0, OK, it8705f_write_enable_2e},
1380 {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise},
1381 {0x1039, 0x5513, 0x1019, 0x0A41, 0x1039, 0x0018, 0, 0, NULL, NULL, NULL, "Elitegroup", "K7S6A", 0, OK, it8705f_write_enable_2e},
1382 {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, "Elitegroup", "K7VTA3", 256, OK, it8705f_write_enable_2e},
1383 {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e},
1384 {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise},
1385 {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", "EPoX", "EP-BX3", 0, OK, board_epox_ep_bx3},
1386 {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001387 {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, NULL, "GIGABYTE", "GA-7VT600", 0, OK, it8705f_write_enable_2e},
1388 {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001389 {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable},
1390 {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400},
Michael Karcher03b80e92010-03-07 16:32:32 +00001391 {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "VL420 SFF", 0, OK, intel_ich_gpio22_raise},
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001392 {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", "iBASE", "MB899", 0, NT, intel_ich_gpio26_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001393 {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455},
1394 {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi},
Michael Karcher51cd0c92010-03-19 22:35:21 +00001395 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001396 {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, NULL, "iwill", "dk8_htx", "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e},
James Lancaster998c9dc2010-03-19 22:39:24 +00001397 {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001398 {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, "Mitac", "6513WU", 0, OK, board_mitac_6513wu},
1399 {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v},
1400 {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio4_4_raise_2e},
1401 {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v},
1402 {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, "MSI", "MS-7005 (651M-L)", 0, OK, board_msi_651ml},
1403 {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise},
1404 {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio4_4_raise_4e},
Michael Karcher5fdf2702010-03-07 16:52:59 +00001405 {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8N GM2-L)", 0, NT, nvidia_mcp_gpio2_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001406 {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise},
1407 {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e},
1408 {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, it8705f_write_enable_2e},
1409 {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, OK, board_shuttle_fn25},
Michael Karcher06477332010-03-19 22:49:09 +00001410 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001411 {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e},
1412 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, "Tekram", "P6Pro-A5", 256, OK, NULL},
Daniel Brandt4ad4c742010-03-21 13:36:20 +00001413 {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001414 {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise},
1415 {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise},
Luc Verhaegen93938c32010-01-20 14:45:03 +00001416
Michael Karcher0bdc0922010-02-28 01:33:48 +00001417 { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, NT, NULL}, /* end marker */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001418};
1419
Uwe Hermannffec5f32007-08-23 16:08:21 +00001420/**
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +00001421 * Match boards on coreboot table gathered vendor and part name.
Uwe Hermannffec5f32007-08-23 16:08:21 +00001422 * Require main PCI IDs to match too as extra safety.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001423 */
Uwe Hermann394131e2008-10-18 21:14:13 +00001424static struct board_pciid_enable *board_match_coreboot_name(const char *vendor,
1425 const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001426{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001427 struct board_pciid_enable *board = board_pciid_enables;
Peter Stuge6b53fed2008-01-27 16:21:21 +00001428 struct board_pciid_enable *partmatch = NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001429
Uwe Hermanna93045c2009-05-09 00:47:04 +00001430 for (; board->vendor_name; board++) {
Uwe Hermann394131e2008-10-18 21:14:13 +00001431 if (vendor && (!board->lb_vendor
1432 || strcasecmp(board->lb_vendor, vendor)))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001433 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001434
Peter Stuge0b9c5f32008-07-02 00:47:30 +00001435 if (!board->lb_part || strcasecmp(board->lb_part, part))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001436 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001437
Uwe Hermanna7e05482007-05-09 10:17:44 +00001438 if (!pci_dev_find(board->first_vendor, board->first_device))
1439 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001440
Uwe Hermanna7e05482007-05-09 10:17:44 +00001441 if (board->second_vendor &&
Uwe Hermann394131e2008-10-18 21:14:13 +00001442 !pci_dev_find(board->second_vendor, board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001443 continue;
Peter Stuge6b53fed2008-01-27 16:21:21 +00001444
1445 if (vendor)
1446 return board;
1447
1448 if (partmatch) {
1449 /* a second entry has a matching part name */
Sean Nelson316a29f2010-05-07 20:09:04 +00001450 msg_pinfo("AMBIGUOUS BOARD NAME: %s\n", part);
1451 msg_pinfo("At least vendors '%s' and '%s' match.\n",
Uwe Hermann394131e2008-10-18 21:14:13 +00001452 partmatch->lb_vendor, board->lb_vendor);
Sean Nelson316a29f2010-05-07 20:09:04 +00001453 msg_perr("Please use the full -m vendor:part syntax.\n");
Peter Stuge6b53fed2008-01-27 16:21:21 +00001454 return NULL;
1455 }
1456 partmatch = board;
Uwe Hermanna7e05482007-05-09 10:17:44 +00001457 }
Uwe Hermann372eeb52007-12-04 21:49:06 +00001458
Peter Stuge6b53fed2008-01-27 16:21:21 +00001459 if (partmatch)
1460 return partmatch;
1461
Carl-Daniel Hailfingerbc25f942009-07-30 13:30:17 +00001462 if (!partvendor_from_cbtable) {
1463 /* Only warn if the mainboard type was not gathered from the
1464 * coreboot table. If it was, the coreboot implementor is
1465 * expected to fix flashrom, too.
1466 */
Sean Nelson316a29f2010-05-07 20:09:04 +00001467 msg_perr("\nUnknown vendor:board from -m option: %s:%s\n\n",
Carl-Daniel Hailfingerbc25f942009-07-30 13:30:17 +00001468 vendor, part);
1469 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00001470 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001471}
1472
Uwe Hermannffec5f32007-08-23 16:08:21 +00001473/**
1474 * Match boards on PCI IDs and subsystem IDs.
1475 * Second set of IDs can be main only or missing completely.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001476 */
1477static struct board_pciid_enable *board_match_pci_card_ids(void)
1478{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001479 struct board_pciid_enable *board = board_pciid_enables;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001480
Uwe Hermanna93045c2009-05-09 00:47:04 +00001481 for (; board->vendor_name; board++) {
Michael Karcher2eab70d2010-02-04 10:58:50 +00001482 if ((!board->first_card_vendor || !board->first_card_device) &&
1483 !board->dmi_pattern)
Uwe Hermanna7e05482007-05-09 10:17:44 +00001484 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001485
Uwe Hermanna7e05482007-05-09 10:17:44 +00001486 if (!pci_card_find(board->first_vendor, board->first_device,
Uwe Hermann394131e2008-10-18 21:14:13 +00001487 board->first_card_vendor,
1488 board->first_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001489 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001490
Uwe Hermanna7e05482007-05-09 10:17:44 +00001491 if (board->second_vendor) {
1492 if (board->second_card_vendor) {
1493 if (!pci_card_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00001494 board->second_device,
1495 board->second_card_vendor,
1496 board->second_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001497 continue;
1498 } else {
1499 if (!pci_dev_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00001500 board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001501 continue;
1502 }
1503 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001504
Michael Karcher6701ee82010-01-20 14:14:11 +00001505 if (board->dmi_pattern) {
1506 if (!has_dmi_support) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001507 msg_perr("WARNING: Can't autodetect %s %s,"
Michael Karcher6701ee82010-01-20 14:14:11 +00001508 " DMI info unavailable.\n",
1509 board->vendor_name, board->board_name);
1510 continue;
1511 } else {
1512 if (!dmi_match(board->dmi_pattern))
1513 continue;
1514 }
1515 }
1516
Uwe Hermanna7e05482007-05-09 10:17:44 +00001517 return board;
1518 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001519
Uwe Hermanna7e05482007-05-09 10:17:44 +00001520 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001521}
1522
Uwe Hermann372eeb52007-12-04 21:49:06 +00001523int board_flash_enable(const char *vendor, const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001524{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001525 struct board_pciid_enable *board = NULL;
1526 int ret = 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001527
Peter Stuge6b53fed2008-01-27 16:21:21 +00001528 if (part)
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +00001529 board = board_match_coreboot_name(vendor, part);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001530
Uwe Hermanna7e05482007-05-09 10:17:44 +00001531 if (!board)
1532 board = board_match_pci_card_ids();
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001533
Michael Karcher0b9e2a72010-03-11 23:04:16 +00001534 if (board && board->status == NT) {
Uwe Hermann43959702010-03-13 17:28:29 +00001535 if (!force_boardenable) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001536 msg_pinfo("WARNING: Your mainboard is %s %s, but the mainboard-specific\n"
Michael Karcher7f0c3ec2010-03-07 22:29:28 +00001537 "code has not been tested, and thus will not not be executed by default.\n"
1538 "Depending on your hardware environment, erasing, writing or even probing\n"
1539 "can fail without running the board specific code.\n\n"
1540 "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n"
Uwe Hermann43959702010-03-13 17:28:29 +00001541 "\"internal programmer\") for details.\n",
Michael Karcher7f0c3ec2010-03-07 22:29:28 +00001542 board->vendor_name, board->board_name);
1543 board = NULL;
Uwe Hermann43959702010-03-13 17:28:29 +00001544 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +00001545 msg_pinfo("NOTE: Running an untested board enable procedure.\n"
Uwe Hermann43959702010-03-13 17:28:29 +00001546 "Please report success/failure to flashrom@flashrom.org.\n");
1547 }
Michael Karcher7f0c3ec2010-03-07 22:29:28 +00001548 }
1549
Uwe Hermanna7e05482007-05-09 10:17:44 +00001550 if (board) {
Luc Verhaegen93938c32010-01-20 14:45:03 +00001551 if (board->max_rom_decode_parallel)
1552 max_rom_decode.parallel =
1553 board->max_rom_decode_parallel * 1024;
1554
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00001555 if (board->enable != NULL) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001556 msg_pinfo("Disabling flash write protection for "
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00001557 "board \"%s %s\"... ", board->vendor_name,
1558 board->board_name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001559
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00001560 ret = board->enable(board->vendor_name);
1561 if (ret)
Sean Nelson316a29f2010-05-07 20:09:04 +00001562 msg_pinfo("FAILED!\n");
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00001563 else
Sean Nelson316a29f2010-05-07 20:09:04 +00001564 msg_pinfo("OK.\n");
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00001565 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00001566 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001567
Uwe Hermanna7e05482007-05-09 10:17:44 +00001568 return ret;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001569}