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Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
5 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +00006 * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
Carl-Daniel Hailfinger92242622007-09-27 14:29:57 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00008 *
Uwe Hermannd1107642007-08-29 17:52:32 +00009 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000012 *
Uwe Hermannd1107642007-08-29 17:52:32 +000013 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000021 */
22
23/*
24 * Contains the board specific flash enables.
25 */
26
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000027#include <string.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000028#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000029#include "programmer.h"
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000030
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000031#if defined(__i386__) || defined(__x86_64__)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000032/*
Uwe Hermannffec5f32007-08-23 16:08:21 +000033 * Helper functions for many Winbond Super I/Os of the W836xx range.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000034 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000035/* Enter extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000036void w836xx_ext_enter(uint16_t port)
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000037{
Andriy Gapon65c1b862008-05-22 13:22:45 +000038 OUTB(0x87, port);
39 OUTB(0x87, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000040}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000041
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000042/* Leave extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000043void w836xx_ext_leave(uint16_t port)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000044{
Andriy Gapon65c1b862008-05-22 13:22:45 +000045 OUTB(0xAA, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000046}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000047
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000048/* Generic Super I/O helper functions */
49uint8_t sio_read(uint16_t port, uint8_t reg)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000050{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000051 OUTB(reg, port);
52 return INB(port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000053}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000054
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000055void sio_write(uint16_t port, uint8_t reg, uint8_t data)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000056{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000057 OUTB(reg, port);
58 OUTB(data, port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000059}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000060
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000061void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000062{
Ronald G. Minnichfa496922007-10-12 21:22:40 +000063 uint8_t tmp;
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000064
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000065 OUTB(reg, port);
66 tmp = INB(port + 1) & ~mask;
67 OUTB(tmp | (data & mask), port + 1);
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000068}
69
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000070/* Not used yet. */
71#if 0
72static int enable_flash_decode_superio(void)
73{
74 int ret;
75 uint8_t tmp;
76
77 switch (superio.vendor) {
78 case SUPERIO_VENDOR_NONE:
79 ret = -1;
80 break;
81 case SUPERIO_VENDOR_ITE:
82 enter_conf_mode_ite(superio.port);
Uwe Hermann43959702010-03-13 17:28:29 +000083 /* Enable flash mapping. Works for most old ITE style Super I/O. */
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000084 tmp = sio_read(superio.port, 0x24);
85 tmp |= 0xfc;
86 sio_write(superio.port, 0x24, tmp);
87 exit_conf_mode_ite(superio.port);
88 ret = 0;
89 break;
90 default:
Sean Nelson316a29f2010-05-07 20:09:04 +000091 msg_pdbg("Unhandled Super I/O type!\n");
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000092 ret = -1;
93 break;
94 }
95 return ret;
96}
97#endif
98
Uwe Hermann48ec1b12010-08-08 17:01:18 +000099/*
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000100 * SMSC FDC37B787: Raise GPIO50
101 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000102static int fdc37b787_gpio50_raise(uint16_t port)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000103{
104 uint8_t id, val;
105
106 OUTB(0x55, port); /* enter conf mode */
107 id = sio_read(port, 0x20);
108 if (id != 0x44) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000109 msg_perr("\nERROR: FDC37B787: Wrong ID 0x%02X.\n", id);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000110 OUTB(0xAA, port); /* leave conf mode */
111 return -1;
112 }
113
114 sio_write(port, 0x07, 0x08); /* Select Aux I/O subdevice */
115
116 val = sio_read(port, 0xC8); /* GP50 */
117 if ((val & 0x1B) != 0x10) /* output, no invert, GPIO */
118 {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000119 msg_perr("\nERROR: GPIO50 mode 0x%02X unexpected.\n", val);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000120 OUTB(0xAA, port);
121 return -1;
122 }
123
124 sio_mask(port, 0xF9, 0x01, 0x01);
125
126 OUTB(0xAA, port); /* Leave conf mode */
127 return 0;
128}
129
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000130/*
131 * Suited for:
132 * - Nokia IP530: Intel 440BX + PIIX4 + FDC37B787
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000133 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000134static int fdc37b787_gpio50_raise_3f0(void)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000135{
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000136 return fdc37b787_gpio50_raise(0x3f0);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000137}
138
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000139struct winbond_mux {
140 uint8_t reg; /* 0 if the corresponding pin is not muxed */
141 uint8_t data; /* reg/data/mask may be directly ... */
142 uint8_t mask; /* ... passed to sio_mask */
143};
144
145struct winbond_port {
146 const struct winbond_mux *mux; /* NULL or pointer to mux info for the 8 bits */
147 uint8_t ldn; /* LDN this GPIO register is located in */
148 uint8_t enable_bit; /* bit in 0x30 of that LDN to enable
149 the GPIO port */
150 uint8_t base; /* base register in that LDN for the port */
151};
152
153struct winbond_chip {
154 uint8_t device_id; /* reg 0x20 of the expected w83626x */
155 uint8_t gpio_port_count;
156 const struct winbond_port *port;
157};
158
159
160#define UNIMPLEMENTED_PORT {NULL, 0, 0, 0}
161
162enum winbond_id {
163 WINBOND_W83627HF_ID = 0x52,
Michael Karcherea36c9c2010-06-27 15:07:52 +0000164 WINBOND_W83627EHF_ID = 0x88,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000165 WINBOND_W83627THF_ID = 0x82,
166};
167
168static const struct winbond_mux w83627hf_port2_mux[8] = {
169 {0x2A, 0x01, 0x01}, /* or MIDI */
170 {0x2B, 0x80, 0x80}, /* or SPI */
171 {0x2B, 0x40, 0x40}, /* or SPI */
172 {0x2B, 0x20, 0x20}, /* or power LED */
173 {0x2B, 0x10, 0x10}, /* or watchdog */
174 {0x2B, 0x08, 0x08}, /* or infra red */
175 {0x2B, 0x04, 0x04}, /* or infra red */
176 {0x2B, 0x03, 0x03} /* or IRQ1 input */
177};
178
179static const struct winbond_port w83627hf[3] = {
180 UNIMPLEMENTED_PORT,
181 {w83627hf_port2_mux, 0x08, 0, 0xF0},
182 UNIMPLEMENTED_PORT
183};
184
Michael Karcherea36c9c2010-06-27 15:07:52 +0000185static const struct winbond_mux w83627ehf_port2_mux[8] = {
186 {0x29, 0x06, 0x02}, /* or MIDI */
187 {0x29, 0x06, 0x02},
188 {0x24, 0x02, 0x00}, /* or SPI ROM interface */
189 {0x24, 0x02, 0x00},
190 {0x2A, 0x01, 0x01}, /* or keyboard/mouse interface */
191 {0x2A, 0x01, 0x01},
192 {0x2A, 0x01, 0x01},
193 {0x2A, 0x01, 0x01}
194};
195
196static const struct winbond_port w83627ehf[6] = {
197 UNIMPLEMENTED_PORT,
198 {w83627ehf_port2_mux, 0x09, 0, 0xE3},
199 UNIMPLEMENTED_PORT,
200 UNIMPLEMENTED_PORT,
201 UNIMPLEMENTED_PORT,
202 UNIMPLEMENTED_PORT
203};
204
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000205static const struct winbond_mux w83627thf_port4_mux[8] = {
206 {0x2D, 0x01, 0x01}, /* or watchdog or VID level strap */
207 {0x2D, 0x02, 0x02}, /* or resume reset */
208 {0x2D, 0x04, 0x04}, /* or S3 input */
209 {0x2D, 0x08, 0x08}, /* or PSON# */
210 {0x2D, 0x10, 0x10}, /* or PWROK */
211 {0x2D, 0x20, 0x20}, /* or suspend LED */
212 {0x2D, 0x40, 0x40}, /* or panel switch input */
213 {0x2D, 0x80, 0x80} /* or panel switch output */
214};
215
216static const struct winbond_port w83627thf[5] = {
217 UNIMPLEMENTED_PORT, /* GPIO1 */
218 UNIMPLEMENTED_PORT, /* GPIO2 */
219 UNIMPLEMENTED_PORT, /* GPIO3 */
220 {w83627thf_port4_mux, 0x09, 1, 0xF4},
221 UNIMPLEMENTED_PORT /* GPIO5 */
222};
223
224static const struct winbond_chip winbond_chips[] = {
225 {WINBOND_W83627HF_ID, ARRAY_SIZE(w83627hf), w83627hf },
Michael Karcherea36c9c2010-06-27 15:07:52 +0000226 {WINBOND_W83627EHF_ID, ARRAY_SIZE(w83627ehf), w83627ehf},
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000227 {WINBOND_W83627THF_ID, ARRAY_SIZE(w83627thf), w83627thf},
228};
229
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000230/*
231 * Detects which Winbond Super I/O is responding at the given base address,
232 * but takes no effort to make sure the chip is really a Winbond Super I/O.
233 */
234static const struct winbond_chip *winbond_superio_detect(uint16_t base)
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000235{
236 uint8_t chipid;
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000237 const struct winbond_chip *chip = NULL;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000238 int i;
239
240 w836xx_ext_enter(base);
241 chipid = sio_read(base, 0x20);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000242
243 for (i = 0; i < ARRAY_SIZE(winbond_chips); i++) {
244 if (winbond_chips[i].device_id == chipid) {
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000245 chip = &winbond_chips[i];
246 break;
247 }
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000248 }
249
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000250 w836xx_ext_leave(base);
251 return chip;
252}
253
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000254/*
255 * The chipid parameter goes away as soon as we have Super I/O matching in the
256 * board enable table. The call to winbond_superio_detect() goes away as
257 * soon as we have generic Super I/O detection code.
258 */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000259static int winbond_gpio_set(uint16_t base, enum winbond_id chipid,
260 int pin, int raise)
261{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000262 const struct winbond_chip *chip = NULL;
263 const struct winbond_port *gpio;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000264 int port = pin / 10;
265 int bit = pin % 10;
266
267 chip = winbond_superio_detect(base);
268 if (!chip) {
269 msg_perr("\nERROR: No supported Winbond Super I/O found\n");
270 return -1;
271 }
Michael Karcher979d9252010-06-29 14:44:40 +0000272 if (chip->device_id != chipid) {
273 msg_perr("\nERROR: Found Winbond chip with ID 0x%x, "
274 "expected %x\n", chip->device_id, chipid);
275 return -1;
276 }
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000277 if (bit >= 8 || port == 0 || port > chip->gpio_port_count) {
278 msg_perr("\nERROR: winbond_gpio_set: Invalid GPIO number %d\n",
279 pin);
280 return -1;
281 }
282
283 gpio = &chip->port[port - 1];
284
285 if (gpio->ldn == 0) {
286 msg_perr("\nERROR: GPIO%d is not supported yet on this"
287 " winbond chip\n", port);
288 return -1;
289 }
290
291 w836xx_ext_enter(base);
292
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000293 /* Select logical device. */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000294 sio_write(base, 0x07, gpio->ldn);
295
296 /* Activate logical device. */
297 sio_mask(base, 0x30, 1 << gpio->enable_bit, 1 << gpio->enable_bit);
298
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000299 /* Select GPIO function of that pin. */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000300 if (gpio->mux && gpio->mux[bit].reg)
301 sio_mask(base, gpio->mux[bit].reg,
302 gpio->mux[bit].data, gpio->mux[bit].mask);
303
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000304 sio_mask(base, gpio->base + 0, 0, 1 << bit); /* Make pin output */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000305 sio_mask(base, gpio->base + 2, 0, 1 << bit); /* Clear inversion */
306 sio_mask(base, gpio->base + 1, raise << bit, 1 << bit);
307
308 w836xx_ext_leave(base);
309
310 return 0;
311}
312
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000313/*
Uwe Hermannffec5f32007-08-23 16:08:21 +0000314 * Winbond W83627HF: Raise GPIO24.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000315 *
316 * Suited for:
Uwe Hermannffec5f32007-08-23 16:08:21 +0000317 * - Agami Aruma
318 * - IWILL DK8-HTX
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000319 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000320static int w83627hf_gpio24_raise_2e(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000321{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000322 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 24, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000323}
324
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000325/*
Joshua Roysf280a382010-08-07 21:49:11 +0000326 * Winbond W83627HF: Raise GPIO25.
327 *
328 * Suited for:
329 * - MSI MS-6577
330 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000331static int w83627hf_gpio25_raise_2e(void)
Joshua Roysf280a382010-08-07 21:49:11 +0000332{
333 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 25, 1);
334}
335
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000336/*
Stefan Taunerff80e682011-07-20 16:34:18 +0000337 * Winbond W83627EHF: Raise GPIO22.
Michael Karcherea36c9c2010-06-27 15:07:52 +0000338 *
339 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000340 * - ASUS A8N-VM CSM: AMD Socket 939 + GeForce 6150 (C51) + MCP51
Michael Karcherea36c9c2010-06-27 15:07:52 +0000341 */
Stefan Taunerff80e682011-07-20 16:34:18 +0000342static int w83627ehf_gpio22_raise_2e(void)
Michael Karcherea36c9c2010-06-27 15:07:52 +0000343{
Stefan Taunerff80e682011-07-20 16:34:18 +0000344 return winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, 22, 1);
Michael Karcherea36c9c2010-06-27 15:07:52 +0000345}
346
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000347/*
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000348 * Winbond W83627THF: Raise GPIO 44.
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000349 *
350 * Suited for:
Peter Stugecce26822008-07-21 17:48:40 +0000351 * - MSI K8T Neo2-F
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000352 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000353static int w83627thf_gpio44_raise_2e(void)
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000354{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000355 return winbond_gpio_set(0x2e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000356}
357
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000358/*
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000359 * Winbond W83627THF: Raise GPIO 44.
360 *
361 * Suited for:
362 * - MSI K8N Neo3
363 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000364static int w83627thf_gpio44_raise_4e(void)
Peter Stugecce26822008-07-21 17:48:40 +0000365{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000366 return winbond_gpio_set(0x4e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000367}
Uwe Hermann372eeb52007-12-04 21:49:06 +0000368
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000369/*
David Borgb6417a62010-08-02 08:29:34 +0000370 * Enable MEMW# and set ROM size to max.
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000371 * Supported chips: W83L517D, W83697HF/F/HG, W83697SF/UF/UG
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000372 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000373static void w836xx_memw_enable(uint16_t port)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000374{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000375 w836xx_ext_enter(port);
376 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000377 /* Enable MEMW# and set ROM size select to max. (4M). */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000378 sio_mask(port, 0x24, 0x28, 0x28);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000379 }
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000380 w836xx_ext_leave(port);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000381}
382
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000383/*
Luc Verhaegen73d21192009-12-23 00:54:26 +0000384 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000385 * - EPoX EP-8K5A2: VIA KT333 + VT8235
386 * - Albatron PM266A Pro: VIA P4M266A + VT8235
387 * - Shuttle AK31 (all versions): VIA KT266 + VT8233
388 * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
389 * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237
Mattias Mattssone295eee2010-08-15 10:21:29 +0000390 * - MSI KM4M-V and KM4AM-V: VIA KM400/KM400A + VT8237
Mattias Mattssone8388242010-09-11 15:25:48 +0000391 * - MSI MS-6561 (745 Ultra): SiS 745 + W83697HF
Sergey A Lichackf3a4bff2010-09-07 18:14:53 +0000392 * - MSI MS-6787 (P4MAM-V/P4MAM-L): VIA P4M266 + VT8235
Uwe Hermann17da61e2010-10-05 21:48:43 +0000393 * - ASRock K7S41: SiS 741 + SiS 963 + W83697HF
Pawel Rozanski1d233072011-06-19 16:52:48 +0000394 * - ASRock K7S41GX: SiS 741GX + SiS 963L + W83697HF
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000395 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000396static int w836xx_memw_enable_2e(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000397{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000398 w836xx_memw_enable(0x2E);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000399
Luc Verhaegen73d21192009-12-23 00:54:26 +0000400 return 0;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000401}
402
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000403/*
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000404 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000405 * - Termtek TK-3370 (rev. 2.5b)
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000406 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000407static int w836xx_memw_enable_4e(void)
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000408{
409 w836xx_memw_enable(0x4E);
410
411 return 0;
412}
413
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000414/*
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000415 * Suited for all boards with ITE IT8705F.
416 * The SIS950 Super I/O probably requires a similar flash write enable.
Luc Verhaegen21f54962010-01-20 14:45:07 +0000417 */
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000418int it8705f_write_enable(uint8_t port)
Luc Verhaegen21f54962010-01-20 14:45:07 +0000419{
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000420 uint8_t tmp;
421 int ret = 0;
422
Luc Verhaegen21f54962010-01-20 14:45:07 +0000423 enter_conf_mode_ite(port);
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000424 tmp = sio_read(port, 0x24);
425 /* Check if at least one flash segment is enabled. */
426 if (tmp & 0xf0) {
427 /* The IT8705F will respond to LPC cycles and translate them. */
428 buses_supported = CHIP_BUSTYPE_PARALLEL;
429 /* Flash ROM I/F Writes Enable */
430 tmp |= 0x04;
431 msg_pdbg("Enabling IT8705F flash ROM interface write.\n");
432 if (tmp & 0x02) {
433 /* The data sheet contradicts itself about max size. */
434 max_rom_decode.parallel = 1024 * 1024;
435 msg_pinfo("IT8705F with very unusual settings. Please "
436 "send the output of \"flashrom -V\" to \n"
Paul Menzelab6328f2010-10-08 11:03:02 +0000437 "flashrom@flashrom.org with "
438 "IT8705: your board name: flashrom -V\n"
439 "as the subject to help us finish "
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000440 "support for your Super I/O. Thanks.\n");
441 ret = 1;
442 } else if (tmp & 0x08) {
443 max_rom_decode.parallel = 512 * 1024;
444 } else {
445 max_rom_decode.parallel = 256 * 1024;
446 }
447 /* Safety checks. The data sheet is unclear here: Segments 1+3
448 * overlap, no segment seems to cover top - 1MB to top - 512kB.
449 * We assume that certain combinations make no sense.
450 */
451 if (((tmp & 0x02) && !(tmp & 0x08)) || /* 1 MB en, 512 kB dis */
452 (!(tmp & 0x10)) || /* 128 kB dis */
453 (!(tmp & 0x40))) { /* 256/512 kB dis */
454 msg_perr("Inconsistent IT8705F decode size!\n");
455 ret = 1;
456 }
457 if (sio_read(port, 0x25) != 0) {
458 msg_perr("IT8705F flash data pins disabled!\n");
459 ret = 1;
460 }
461 if (sio_read(port, 0x26) != 0) {
462 msg_perr("IT8705F flash address pins 0-7 disabled!\n");
463 ret = 1;
464 }
465 if (sio_read(port, 0x27) != 0) {
466 msg_perr("IT8705F flash address pins 8-15 disabled!\n");
467 ret = 1;
468 }
469 if ((sio_read(port, 0x29) & 0x10) != 0) {
470 msg_perr("IT8705F flash write enable pin disabled!\n");
471 ret = 1;
472 }
473 if ((sio_read(port, 0x29) & 0x08) != 0) {
474 msg_perr("IT8705F flash chip select pin disabled!\n");
475 ret = 1;
476 }
477 if ((sio_read(port, 0x29) & 0x04) != 0) {
478 msg_perr("IT8705F flash read strobe pin disabled!\n");
479 ret = 1;
480 }
481 if ((sio_read(port, 0x29) & 0x03) != 0) {
482 msg_perr("IT8705F flash address pins 16-17 disabled!\n");
483 /* Not really an error if you use flash chips smaller
484 * than 256 kByte, but such a configuration is unlikely.
485 */
486 ret = 1;
487 }
488 msg_pdbg("Maximum IT8705F parallel flash decode size is %u.\n",
489 max_rom_decode.parallel);
490 if (ret) {
491 msg_pinfo("Not enabling IT8705F flash write.\n");
492 } else {
493 sio_write(port, 0x24, tmp);
494 }
495 } else {
496 msg_pdbg("No IT8705F flash segment enabled.\n");
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000497 ret = 0;
498 }
Luc Verhaegen21f54962010-01-20 14:45:07 +0000499 exit_conf_mode_ite(port);
500
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000501 return ret;
Luc Verhaegen21f54962010-01-20 14:45:07 +0000502}
Luc Verhaegen73d21192009-12-23 00:54:26 +0000503
Mattias Mattssonfb60cec2010-09-13 19:39:25 +0000504/*
505 * The ITE IT8707F is a custom chip made by ITE exclusively for ASUS.
506 * It uses the Winbond command sequence to enter extended configuration
507 * mode and the ITE sequence to exit.
508 *
509 * Registers seems similar to the ones on ITE IT8710F.
510 */
511static int it8707f_write_enable(uint8_t port)
512{
513 uint8_t tmp;
514
515 w836xx_ext_enter(port);
516
517 /* Set bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A rw */
518 tmp = sio_read(port, 0x23);
519 tmp |= (1 << 3);
520 sio_write(port, 0x23, tmp);
521
522 /* Set bit 2 (FLASH_WE) and bit 3 (FLASH_IF_EN) of reg 0x24 */
523 tmp = sio_read(port, 0x24);
524 tmp |= (1 << 2) | (1 << 3);
525 sio_write(port, 0x24, tmp);
526
527 /* Clear bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A ro */
528 tmp = sio_read(port, 0x23);
529 tmp &= ~(1 << 3);
530 sio_write(port, 0x23, tmp);
531
532 exit_conf_mode_ite(port);
533
534 return 0;
535}
536
537/*
538 * Suited for:
539 * - ASUS P4SC-E: SiS 651 + 962 + ITE IT8707F
540 */
541static int it8707f_write_enable_2e(void)
542{
543 return it8707f_write_enable(0x2e);
544}
545
Michael Karchercba52de2011-03-06 12:07:19 +0000546#define PC87360_ID 0xE1
547#define PC87364_ID 0xE4
548
549static int pc8736x_gpio_set(uint8_t chipid, uint8_t gpio, int raise)
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000550{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000551 static const int bankbase[] = {0, 4, 8, 10, 12};
552 int gpio_bank = gpio / 8;
553 int gpio_pin = gpio % 8;
554 uint16_t baseport;
555 uint8_t id, val;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000556
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000557 if (gpio_bank > 4) {
Michael Karchercba52de2011-03-06 12:07:19 +0000558 msg_perr("PC8736x: Invalid GPIO %d\n", gpio);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000559 return -1;
560 }
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000561
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000562 id = sio_read(0x2E, 0x20);
Michael Karchercba52de2011-03-06 12:07:19 +0000563 if (id != chipid) {
564 msg_perr("PC8736x: unexpected ID %02x (expected %02x)\n", id, chipid);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000565 return -1;
566 }
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000567
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000568 sio_write(0x2E, 0x07, 0x07); /* Select GPIO device. */
569 baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
570 if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) {
571 msg_perr("PC87360: invalid GPIO base address %04x\n",
572 baseport);
573 return -1;
574 }
575 sio_mask (0x2E, 0x30, 0x01, 0x01); /* Enable logical device. */
576 sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin);
577 sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output. */
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000578
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000579 val = INB(baseport + bankbase[gpio_bank]);
580 if (raise)
581 val |= 1 << gpio_pin;
582 else
583 val &= ~(1 << gpio_pin);
584 OUTB(val, baseport + bankbase[gpio_bank]);
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000585
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000586 return 0;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000587}
588
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000589/*
590 * VIA VT823x: Set one of the GPIO pins.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000591 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000592static int via_vt823x_gpio_set(uint8_t gpio, int raise)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000593{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000594 struct pci_dev *dev;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000595 uint16_t base;
David Bartleyf58d3642009-12-09 07:53:01 +0000596 uint8_t val, bit, offset;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000597
Luc Verhaegen73d21192009-12-23 00:54:26 +0000598 dev = pci_dev_find_vendorclass(0x1106, 0x0601);
599 switch (dev->device_id) {
600 case 0x3177: /* VT8235 */
601 case 0x3227: /* VT8237R */
602 case 0x3337: /* VT8237A */
603 break;
604 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000605 msg_perr("\nERROR: VT823x ISA bridge not found.\n");
Luc Verhaegen73d21192009-12-23 00:54:26 +0000606 return -1;
607 }
608
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000609 if ((gpio >= 12) && (gpio <= 15)) {
610 /* GPIO12-15 -> output */
611 val = pci_read_byte(dev, 0xE4);
612 val |= 0x10;
613 pci_write_byte(dev, 0xE4, val);
614 } else if (gpio == 9) {
615 /* GPIO9 -> Output */
616 val = pci_read_byte(dev, 0xE4);
617 val |= 0x20;
618 pci_write_byte(dev, 0xE4, val);
David Bartleyf58d3642009-12-09 07:53:01 +0000619 } else if (gpio == 5) {
620 val = pci_read_byte(dev, 0xE4);
621 val |= 0x01;
622 pci_write_byte(dev, 0xE4, val);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000623 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000624 msg_perr("\nERROR: "
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000625 "VT823x GPIO%02d is not implemented.\n", gpio);
Luc Verhaegen73d21192009-12-23 00:54:26 +0000626 return -1;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000627 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000628
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000629 /* We need the I/O Base Address for this board's flash enable. */
630 base = pci_read_word(dev, 0x88) & 0xff80;
631
David Bartleyf58d3642009-12-09 07:53:01 +0000632 offset = 0x4C + gpio / 8;
633 bit = 0x01 << (gpio % 8);
634
635 val = INB(base + offset);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000636 if (raise)
637 val |= bit;
638 else
639 val &= ~bit;
David Bartleyf58d3642009-12-09 07:53:01 +0000640 OUTB(val, base + offset);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000641
Uwe Hermanna7e05482007-05-09 10:17:44 +0000642 return 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000643}
644
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000645/*
646 * Suited for:
647 * - ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000648 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000649static int via_vt823x_gpio5_raise(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000650{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000651 /* On M2V-MX: GPO5 is connected to WP# and TBL#. */
652 return via_vt823x_gpio_set(5, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000653}
654
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000655/*
656 * Suited for:
657 * - VIA EPIA EK & N & NL
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000658 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000659static int via_vt823x_gpio9_raise(void)
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000660{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000661 return via_vt823x_gpio_set(9, 1);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000662}
663
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000664/*
665 * Suited for:
666 * - VIA EPIA M and MII (and maybe other CLE266 based EPIAs)
Luc Verhaegen73d21192009-12-23 00:54:26 +0000667 *
668 * We don't need to do this for EPIA M when using coreboot, GPIO15 is never
669 * lowered there.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000670 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000671static int via_vt823x_gpio15_raise(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000672{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000673 return via_vt823x_gpio_set(15, 1);
674}
675
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000676/*
Luc Verhaegen73d21192009-12-23 00:54:26 +0000677 * Winbond W83697HF Super I/O + VIA VT8235 southbridge
678 *
679 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000680 * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
681 * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
Luc Verhaegen73d21192009-12-23 00:54:26 +0000682 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000683static int board_msi_kt4v(void)
Luc Verhaegen73d21192009-12-23 00:54:26 +0000684{
685 int ret;
686
687 ret = via_vt823x_gpio_set(12, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000688 w836xx_memw_enable(0x2E);
Luc Verhaegen97866082008-02-09 02:03:06 +0000689
Luc Verhaegen73d21192009-12-23 00:54:26 +0000690 return ret;
Luc Verhaegen97866082008-02-09 02:03:06 +0000691}
692
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000693/*
694 * Suited for:
695 * - ASUS P5A
Luc Verhaegen6b141752007-05-20 16:16:13 +0000696 *
697 * This is rather nasty code, but there's no way to do this cleanly.
698 * We're basically talking to some unknown device on SMBus, my guess
699 * is that it is the Winbond W83781D that lives near the DIP BIOS.
700 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000701static int board_asus_p5a(void)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000702{
703 uint8_t tmp;
704 int i;
705
706#define ASUSP5A_LOOP 5000
707
Andriy Gapon65c1b862008-05-22 13:22:45 +0000708 OUTB(0x00, 0xE807);
709 OUTB(0xEF, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000710
Andriy Gapon65c1b862008-05-22 13:22:45 +0000711 OUTB(0xFF, 0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000712
713 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000714 OUTB(0xE1, 0xFF);
715 if (INB(0xE800) & 0x04)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000716 break;
717 }
718
719 if (i == ASUSP5A_LOOP) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000720 msg_perr("Unable to contact device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000721 return -1;
722 }
723
Andriy Gapon65c1b862008-05-22 13:22:45 +0000724 OUTB(0x20, 0xE801);
725 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000726
Andriy Gapon65c1b862008-05-22 13:22:45 +0000727 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000728
729 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000730 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000731 if (tmp & 0x70)
732 break;
733 }
734
735 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000736 msg_perr("Failed to read device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000737 return -1;
738 }
739
Andriy Gapon65c1b862008-05-22 13:22:45 +0000740 tmp = INB(0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000741 tmp &= ~0x02;
742
Andriy Gapon65c1b862008-05-22 13:22:45 +0000743 OUTB(0x00, 0xE807);
744 OUTB(0xEE, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000745
Andriy Gapon65c1b862008-05-22 13:22:45 +0000746 OUTB(tmp, 0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000747
Andriy Gapon65c1b862008-05-22 13:22:45 +0000748 OUTB(0xFF, 0xE800);
749 OUTB(0xE1, 0xFF);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000750
Andriy Gapon65c1b862008-05-22 13:22:45 +0000751 OUTB(0x20, 0xE801);
752 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000753
Andriy Gapon65c1b862008-05-22 13:22:45 +0000754 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000755
756 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000757 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000758 if (tmp & 0x70)
759 break;
760 }
761
762 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000763 msg_perr("Failed to write to device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000764 return -1;
765 }
766
767 return 0;
768}
769
Luc Verhaegena7e30502009-12-09 11:39:02 +0000770/*
771 * Set GPIO lines in the Broadcom HT-1000 southbridge.
772 *
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000773 * It's not a Super I/O but it uses the same index/data port method.
Luc Verhaegena7e30502009-12-09 11:39:02 +0000774 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000775static int board_hp_dl145_g3_enable(void)
Luc Verhaegena7e30502009-12-09 11:39:02 +0000776{
777 /* GPIO 0 reg from PM regs */
778 /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
779 sio_mask(0xcd6, 0x44, 0x24, 0x24);
780
781 return 0;
782}
783
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +0000784/*
785 * Set GPIO lines in the Broadcom HT-1000 southbridge.
786 *
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000787 * It's not a Super I/O but it uses the same index/data port method.
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +0000788 */
789static int board_hp_dl165_g6_enable(void)
790{
791 /* Variant of DL145, with slightly different pin placement. */
792 sio_mask(0xcd6, 0x44, 0x80, 0x80); /* TBL# */
793 sio_mask(0xcd6, 0x46, 0x04, 0x04); /* WP# */
794
795 return 0;
796}
797
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000798static int board_ibm_x3455(void)
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000799{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000800 /* Raise GPIO13. */
Carl-Daniel Hailfinger500b4232009-06-01 21:30:42 +0000801 sio_mask(0xcd6, 0x45, 0x20, 0x20);
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000802
803 return 0;
804}
805
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000806/*
807 * Suited for:
808 * - Shuttle FN25 (SN25P): AMD S939 + NVIDIA CK804 (nForce4)
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000809 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000810static int board_shuttle_fn25(void)
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000811{
812 struct pci_dev *dev;
813
814 dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA Bridge. */
815 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000816 msg_perr("\nERROR: NVIDIA nForce4 ISA bridge not found.\n");
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000817 return -1;
818 }
819
820 /* one of those bits seems to be connected to TBL#, but -ENOINFO. */
821 pci_write_byte(dev, 0x92, 0);
822
823 return 0;
824}
825
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000826/*
Mattias Mattssonf4925162010-09-16 22:09:18 +0000827 * Suited for:
828 * - Elitegroup GeForce6100SM-M: NVIDIA MCP61 + ITE IT8726F
829 */
Mattias Mattssonf4925162010-09-16 22:09:18 +0000830static int board_ecs_geforce6100sm_m(void)
831{
832 struct pci_dev *dev;
833 uint32_t tmp;
834
835 dev = pci_dev_find(0x10DE, 0x03EB); /* NVIDIA MCP61 SMBus. */
836 if (!dev) {
837 msg_perr("\nERROR: NVIDIA MCP61 SMBus not found.\n");
838 return -1;
839 }
840
841 tmp = pci_read_byte(dev, 0xE0);
842 tmp &= ~(1 << 3);
843 pci_write_byte(dev, 0xE0, tmp);
844
845 return 0;
846}
847
848/*
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000849 * Very similar to AMD 8111 IO Hub.
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000850 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000851static int nvidia_mcp_gpio_set(int gpio, int raise)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000852{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000853 struct pci_dev *dev;
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000854 uint16_t base;
Michael Karcher2ead2e22010-06-01 16:09:06 +0000855 uint16_t devclass;
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000856 uint8_t tmp;
857
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000858 if ((gpio < 0) || (gpio >= 0x40)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000859 msg_perr("\nERROR: unsupported GPIO: %d.\n", gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000860 return -1;
861 }
862
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000863 /* First, check the ISA Bridge */
864 dev = pci_dev_find_vendorclass(0x10DE, 0x0601);
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000865 switch (dev->device_id) {
866 case 0x0030: /* CK804 */
867 case 0x0050: /* MCP04 */
868 case 0x0060: /* MCP2 */
Michael Karcher5f31ebe2010-06-12 23:07:26 +0000869 case 0x00E0: /* CK8 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000870 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +0000871 case 0x0260: /* MCP51 */
Michael Karcher242efd42011-03-06 12:09:05 +0000872 case 0x0261: /* MCP51 */
Michael Karcher2ead2e22010-06-01 16:09:06 +0000873 case 0x0364: /* MCP55 */
874 /* find SMBus controller on *this* southbridge */
875 /* The infamous Tyan S2915-E has two south bridges; they are
876 easily told apart from each other by the class of the
877 LPC bridge, but have the same SMBus bridge IDs */
878 if (dev->func != 0) {
879 msg_perr("MCP LPC bridge at unexpected function"
880 " number %d\n", dev->func);
881 return -1;
882 }
883
Carl-Daniel Hailfinger44cd9ab2010-07-17 22:28:05 +0000884#if PCI_LIB_VERSION >= 0x020200
Michael Karcher2ead2e22010-06-01 16:09:06 +0000885 dev = pci_get_dev(pacc, dev->domain, dev->bus, dev->dev, 1);
Carl-Daniel Hailfinger44cd9ab2010-07-17 22:28:05 +0000886#else
887 /* pciutils/libpci before version 2.2 is too old to support
888 * PCI domains. Such old machines usually don't have domains
889 * besides domain 0, so this is not a problem.
890 */
891 dev = pci_get_dev(pacc, dev->bus, dev->dev, 1);
892#endif
Michael Karcher2ead2e22010-06-01 16:09:06 +0000893 if (!dev) {
894 msg_perr("MCP SMBus controller could not be found\n");
895 return -1;
896 }
897 devclass = pci_read_word(dev, PCI_CLASS_DEVICE);
898 if (devclass != 0x0C05) {
899 msg_perr("Unexpected device class %04x for SMBus"
900 " controller\n", devclass);
901 return -1;
902 }
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000903 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +0000904 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000905 msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n");
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000906 return -1;
907 }
908
909 base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */
910 base += 0xC0;
911
912 tmp = INB(base + gpio);
913 tmp &= ~0x0F; /* null lower nibble */
914 tmp |= 0x04; /* gpio -> output. */
915 if (raise)
916 tmp |= 0x01;
917 OUTB(tmp, base + gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000918
919 return 0;
920}
921
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000922/*
923 * Suited for:
Sean Nelson0a247512010-08-15 14:36:18 +0000924 * - ASUS A8N-LA (HP OEM "Nagami-GL8E"): NVIDIA MCP51
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000925 * - ASUS M2NBP-VM CSM: NVIDIA MCP51
Michael Karcherb2184c12010-03-07 16:42:55 +0000926 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000927static int nvidia_mcp_gpio0_raise(void)
Michael Karcherb2184c12010-03-07 16:42:55 +0000928{
929 return nvidia_mcp_gpio_set(0x00, 1);
930}
931
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000932/*
933 * Suited for:
934 * - abit KN8 Ultra: NVIDIA CK804
Sean Nelson92bc6bd2010-03-19 22:37:29 +0000935 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000936static int nvidia_mcp_gpio2_lower(void)
Sean Nelson92bc6bd2010-03-19 22:37:29 +0000937{
938 return nvidia_mcp_gpio_set(0x02, 0);
939}
940
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000941/*
942 * Suited for:
Michael Karcher2842db32011-04-14 23:14:27 +0000943 * - Foxconn 6150K8MD-8EKRSH: Socket 939 + NVIDIA MCP51
Uwe Hermannead705f2010-08-15 15:26:30 +0000944 * - MSI K8N Neo4: NVIDIA CK804. TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html.
945 * - MSI K8NGM2-L: NVIDIA MCP51
Luc Verhaegen6c5f7332009-12-23 03:01:36 +0000946 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000947static int nvidia_mcp_gpio2_raise(void)
Luc Verhaegen6c5f7332009-12-23 03:01:36 +0000948{
949 return nvidia_mcp_gpio_set(0x02, 1);
950}
951
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000952/*
953 * Suited for:
Uwe Hermann83d349a2010-10-18 22:32:03 +0000954 * - EPoX EP-8NPA7I: Socket 754 + NVIDIA nForce4 4X
Jonathan Kollaschf8db9592010-10-15 23:02:15 +0000955 */
956static int nvidia_mcp_gpio4_raise(void)
957{
958 return nvidia_mcp_gpio_set(0x04, 1);
959}
960
961/*
962 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000963 * - HP xw9400 (Tyan S2915-E OEM): Dual(!) NVIDIA MCP55
964 *
965 * Notes: a) There are two MCP55 chips, so also two SMBus bridges on that
966 * board. We can't tell the SMBus logical devices apart, but we
967 * can tell the LPC bridge functions apart.
968 * We need to choose the SMBus bridge next to the LPC bridge with
969 * ID 0x364 and the "LPC bridge" class.
970 * b) #TBL is hardwired on that board to a pull-down. It can be
971 * overridden by connecting the two solder points next to F2.
Michael Karcher2ead2e22010-06-01 16:09:06 +0000972 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000973static int nvidia_mcp_gpio5_raise(void)
Michael Karcher2ead2e22010-06-01 16:09:06 +0000974{
975 return nvidia_mcp_gpio_set(0x05, 1);
976}
977
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000978/*
979 * Suited for:
980 * - abit NF7-S: NVIDIA CK804
Michael Karcher8f10d242010-04-11 21:01:06 +0000981 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000982static int nvidia_mcp_gpio8_raise(void)
Michael Karcher8f10d242010-04-11 21:01:06 +0000983{
984 return nvidia_mcp_gpio_set(0x08, 1);
985}
986
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000987/*
988 * Suited for:
Cristian Măgherușan-Stanciu9932c7b2011-07-07 19:56:58 +0000989 * - GIGABYTE GA-K8NS Pro-939: Socket 939 + NVIDIA nForce3 + CK8
Idwer Volleringd8a00a02011-06-13 16:58:54 +0000990 */
991static int nvidia_mcp_gpio0a_raise(void)
992{
993 return nvidia_mcp_gpio_set(0x0a, 1);
994}
995
996/*
997 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000998 * - MSI K8N Neo2 Platinum: Socket 939 + nForce3 Ultra + CK8
Michael Karcher5f31ebe2010-06-12 23:07:26 +0000999 */
Michael Karcher51825082010-06-12 23:14:03 +00001000static int nvidia_mcp_gpio0c_raise(void)
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001001{
1002 return nvidia_mcp_gpio_set(0x0c, 1);
1003}
1004
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001005/*
1006 * Suited for:
1007 * - abit NF-M2 nView: Socket AM2 + NVIDIA MCP51
Michael Karcherefd8af32010-07-24 22:50:54 +00001008 */
1009static int nvidia_mcp_gpio4_lower(void)
1010{
1011 return nvidia_mcp_gpio_set(0x04, 0);
1012}
1013
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001014/*
1015 * Suited for:
1016 * - ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001017 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001018static int nvidia_mcp_gpio10_raise(void)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001019{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001020 return nvidia_mcp_gpio_set(0x10, 1);
1021}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001022
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001023/*
1024 * Suited for:
1025 * - GIGABYTE GA-K8N-SLI: AMD socket 939 + NVIDIA CK804 + ITE IT8712F
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001026 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001027static int nvidia_mcp_gpio21_raise(void)
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001028{
1029 return nvidia_mcp_gpio_set(0x21, 0x01);
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001030}
1031
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001032/*
1033 * Suited for:
1034 * - EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001035 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001036static int nvidia_mcp_gpio31_raise(void)
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001037{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001038 return nvidia_mcp_gpio_set(0x31, 0x01);
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001039}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001040
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001041/*
1042 * Suited for:
Michael Karcher242efd42011-03-06 12:09:05 +00001043 * - GIGABYTE GA-K8N51GMF: Socket 754 + Geforce 6100 + MCP51
1044 * - GIGABYTE GA-K8N51GMF-9: Socket 939 + Geforce 6100 + MCP51
Joshua Roys2ee137f2010-09-07 17:52:09 +00001045 */
1046static int nvidia_mcp_gpio3b_raise(void)
1047{
1048 return nvidia_mcp_gpio_set(0x3b, 1);
1049}
1050
1051/*
1052 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001053 * - Artec Group DBE61 and DBE62
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001054 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001055static int board_artecgroup_dbe6x(void)
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001056{
1057#define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001058#define DBE6x_PRI_BOOT_LOC_SHIFT 2
1059#define DBE6x_BOOT_OP_LATCHED_SHIFT 8
1060#define DBE6x_SEC_BOOT_LOC_SHIFT 10
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001061#define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT)
1062#define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT)
1063#define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT)
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001064#define DBE6x_BOOT_LOC_FLASH 2
1065#define DBE6x_BOOT_LOC_FWHUB 3
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001066
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001067 msr_t msr;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001068 unsigned long boot_loc;
1069
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001070 /* Geode only has a single core */
1071 if (setup_cpu_msr(0))
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001072 return -1;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001073
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001074 msr = rdmsr(DBE6x_MSR_DIVIL_BALL_OPTS);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001075
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001076 if ((msr.lo & (DBE6x_BOOT_OP_LATCHED)) ==
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001077 (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT))
1078 boot_loc = DBE6x_BOOT_LOC_FWHUB;
1079 else
1080 boot_loc = DBE6x_BOOT_LOC_FLASH;
1081
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001082 msr.lo &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC);
1083 msr.lo |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) |
Uwe Hermann394131e2008-10-18 21:14:13 +00001084 (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001085
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001086 wrmsr(DBE6x_MSR_DIVIL_BALL_OPTS, msr);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001087
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001088 cleanup_cpu_msr();
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001089
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001090 return 0;
1091}
1092
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001093/*
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001094 * Suited for:
1095 * - Asus A8AE-LE (Codename AmberineM; used in Compaq Presario 061)
1096 * Datasheet(s) used:
1097 * - AMD document 43009 "AMD SB700/710/750 Register Reference Guide" rev. 1.00
1098 */
1099static int amd_sbxxx_gpio9_raise(void)
1100{
1101 struct pci_dev *dev;
1102 uint32_t reg;
1103
1104 dev = pci_dev_find(0x1002, 0x4372); /* AMD SMBus Controller */
1105 if (!dev) {
1106 msg_perr("\nERROR: AMD SMBus Controller (0x4372) not found.\n");
1107 return -1;
1108 }
1109
1110 reg = pci_read_long(dev, 0xA8); /* GPIO_12_to_4_Cntrl CI_Reg: A8h-ABh */
1111 /* enable output (0: enable, 1: tristate):
1112 GPIO9 output enable is at bit 5 in 0xA9 */
1113 reg &= ~((uint32_t)1<<(8+5));
1114 /* raise:
1115 GPIO9 output register is at bit 5 in 0xA8 */
1116 reg |= (1<<5);
1117 pci_write_long(dev, 0xA8, reg);
1118
1119 return 0;
1120}
1121
1122/*
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001123 * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}.
Luc Verhaegenf5226912009-12-14 10:41:58 +00001124 */
1125static int intel_piix4_gpo_set(unsigned int gpo, int raise)
1126{
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001127 unsigned int gpo_byte, gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001128 struct pci_dev *dev;
1129 uint32_t tmp, base;
1130
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001131 static const uint32_t nonmuxed_gpos = 0x58000101; /* GPPO {0,8,27,28,30} are always available */
1132
1133 static const struct {unsigned int reg, mask, value; } piix4_gpo[] = {
1134 {0},
1135 {0xB0, 0x0001, 0x0000}, /* GPO1... */
1136 {0xB0, 0x0001, 0x0000},
1137 {0xB0, 0x0001, 0x0000},
1138 {0xB0, 0x0001, 0x0000},
1139 {0xB0, 0x0001, 0x0000},
1140 {0xB0, 0x0001, 0x0000},
1141 {0xB0, 0x0001, 0x0000}, /* ...GPO7: GENCFG bit 0 */
1142 {0},
1143 {0xB0, 0x0100, 0x0000}, /* GPO9: GENCFG bit 8 */
1144 {0xB0, 0x0200, 0x0000}, /* GPO10: GENCFG bit 9 */
1145 {0xB0, 0x0400, 0x0000}, /* GPO11: GENCFG bit 10 */
1146 {0x4E, 0x0100, 0x0000}, /* GPO12... */
1147 {0x4E, 0x0100, 0x0000},
1148 {0x4E, 0x0100, 0x0000}, /* ...GPO14: XBCS bit 8 */
1149 {0xB2, 0x0002, 0x0002}, /* GPO15... */
1150 {0xB2, 0x0002, 0x0002}, /* ...GPO16: GENCFG bit 17 */
1151 {0xB2, 0x0004, 0x0004}, /* GPO17: GENCFG bit 18 */
1152 {0xB2, 0x0008, 0x0008}, /* GPO18: GENCFG bit 19 */
1153 {0xB2, 0x0010, 0x0010}, /* GPO19: GENCFG bit 20 */
1154 {0xB2, 0x0020, 0x0020}, /* GPO20: GENCFG bit 21 */
1155 {0xB2, 0x0040, 0x0040}, /* GPO21: GENCFG bit 22 */
1156 {0xB2, 0x1000, 0x1000}, /* GPO22... */
1157 {0xB2, 0x1000, 0x1000}, /* ...GPO23: GENCFG bit 28 */
1158 {0xB2, 0x2000, 0x2000}, /* GPO24: GENCFG bit 29 */
1159 {0xB2, 0x4000, 0x4000}, /* GPO25: GENCFG bit 30 */
1160 {0xB2, 0x8000, 0x8000}, /* GPO26: GENCFG bit 31 */
1161 {0},
1162 {0},
1163 {0x4E, 0x0100, 0x0000}, /* ...GPO29: XBCS bit 8 */
1164 {0}
1165 };
1166
1167
Luc Verhaegenf5226912009-12-14 10:41:58 +00001168 dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */
1169 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001170 msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +00001171 return -1;
1172 }
1173
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001174 /* Sanity check. */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001175 if (gpo > 30) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001176 msg_perr("\nERROR: Intel PIIX4 has no GPO%d.\n", gpo);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001177 return -1;
1178 }
1179
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001180 if ( (((1 << gpo) & nonmuxed_gpos) == 0) &&
1181 (pci_read_word(dev, piix4_gpo[gpo].reg) & piix4_gpo[gpo].mask) != piix4_gpo[gpo].value ) {
Peter Huewe3d3fd6a2011-01-25 00:23:32 +00001182 msg_perr("\nERROR: PIIX4 GPO%d not programmed for output.\n", gpo);
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001183 return -1;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001184 }
1185
Luc Verhaegenf5226912009-12-14 10:41:58 +00001186 dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */
1187 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001188 msg_perr("\nERROR: Intel PIIX4 PM not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +00001189 return -1;
1190 }
1191
1192 /* PM IO base */
1193 base = pci_read_long(dev, 0x40) & 0x0000FFC0;
1194
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001195 gpo_byte = gpo >> 3;
1196 gpo_bit = gpo & 7;
1197 tmp = INB(base + 0x34 + gpo_byte); /* GPO register */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001198 if (raise)
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001199 tmp |= 0x01 << gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001200 else
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001201 tmp &= ~(0x01 << gpo_bit);
1202 OUTB(tmp, base + 0x34 + gpo_byte);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001203
1204 return 0;
1205}
1206
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001207/*
1208 * Suited for:
Mattias Mattsson85016b92010-09-01 01:21:34 +00001209 * - ASUS P2B-N
1210 */
1211static int intel_piix4_gpo18_lower(void)
1212{
1213 return intel_piix4_gpo_set(18, 0);
1214}
1215
1216/*
1217 * Suited for:
Mattias Mattssonc8ca3de2010-09-13 18:22:36 +00001218 * - MSI MS-6163 v2 (MS-6163 Pro): Intel 440BX + PIIX4E + Winbond W83977EF
1219 */
1220static int intel_piix4_gpo14_raise(void)
1221{
1222 return intel_piix4_gpo_set(14, 1);
1223}
1224
1225/*
1226 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001227 * - EPoX EP-BX3
Luc Verhaegenf5226912009-12-14 10:41:58 +00001228 */
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001229static int intel_piix4_gpo22_raise(void)
Luc Verhaegenf5226912009-12-14 10:41:58 +00001230{
1231 return intel_piix4_gpo_set(22, 1);
1232}
1233
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001234/*
1235 * Suited for:
Tim ter Laak4b933f02010-09-13 23:00:57 +00001236 * - abit BM6
1237 */
1238static int intel_piix4_gpo26_lower(void)
1239{
1240 return intel_piix4_gpo_set(26, 0);
1241}
1242
1243/*
1244 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001245 * - Intel SE440BX-2
Michael Karcher51cd0c92010-03-19 22:35:21 +00001246 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001247static int intel_piix4_gpo27_lower(void)
Michael Karcher51cd0c92010-03-19 22:35:21 +00001248{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001249 return intel_piix4_gpo_set(27, 0);
Michael Karcher51cd0c92010-03-19 22:35:21 +00001250}
1251
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001252/*
Mattias Mattsson2eaad632010-10-05 21:32:29 +00001253 * Suited for:
1254 * - Dell OptiPlex GX1
1255 */
1256static int intel_piix4_gpo30_lower(void)
1257{
1258 return intel_piix4_gpo_set(30, 0);
1259}
1260
1261/*
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001262 * Set a GPIO line on a given Intel ICH LPC controller.
Uwe Hermann93f66db2008-05-22 21:19:38 +00001263 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001264static int intel_ich_gpio_set(int gpio, int raise)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001265{
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001266 /* Table mapping the different Intel ICH LPC chipsets. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001267 static struct {
1268 uint16_t id;
1269 uint8_t base_reg;
1270 uint32_t bank0;
1271 uint32_t bank1;
1272 uint32_t bank2;
1273 } intel_ich_gpio_table[] = {
1274 {0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */
1275 {0x2420, 0x58, 0x0FE30000, 0, 0}, /* 82801AB (ICH0) */
1276 {0x2440, 0x58, 0x1BFF391B, 0, 0}, /* 82801BA (ICH2) */
1277 {0x244C, 0x58, 0x1A23399B, 0, 0}, /* 82801BAM (ICH2M) */
1278 {0x2450, 0x58, 0x1BFF0000, 0, 0}, /* 82801E (C-ICH) */
1279 {0x2480, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801CA (ICH3-S) */
1280 {0x248C, 0x58, 0x1A230000, 0x00000FFF, 0}, /* 82801CAM (ICH3-M) */
1281 {0x24C0, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801DB/DBL (ICH4/ICH4-L) */
1282 {0x24CC, 0x58, 0x1A030000, 0x00000FFF, 0}, /* 82801DBM (ICH4-M) */
1283 {0x24D0, 0x58, 0x1BFF0000, 0x00030305, 0}, /* 82801EB/ER (ICH5/ICH5R) */
1284 {0x2640, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FB/FR (ICH6/ICH6R) */
1285 {0x2641, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FBM (ICH6M) */
1286 {0x27B8, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GB/GR (ICH7 Family) */
1287 {0x27B9, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GBM (ICH7-M) */
1288 {0x27BD, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GHM (ICH7-M DH) */
1289 {0x2810, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HB/HR (ICH8/R) */
1290 {0x2811, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HBM (ICH8M-E) */
1291 {0x2812, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HH (ICH8DH) */
1292 {0x2814, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HO (ICH8DO) */
1293 {0x2815, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HEM (ICH8M) */
1294 {0x2912, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IH (ICH9DH) */
1295 {0x2914, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IO (ICH9DO) */
1296 {0x2916, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IR (ICH9R) */
1297 {0x2917, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IEM (ICH9M-E) */
1298 {0x2918, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IB (ICH9) */
1299 {0x2919, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IBM (ICH9M) */
1300 {0x3A14, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JDO (ICH10DO) */
1301 {0x3A16, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIR (ICH10R) */
1302 {0x3A18, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIB (ICH10) */
1303 {0x3A1A, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JD (ICH10D) */
1304 {0, 0, 0, 0, 0} /* end marker */
1305 };
Uwe Hermann93f66db2008-05-22 21:19:38 +00001306
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001307 struct pci_dev *dev;
1308 uint16_t base;
1309 uint32_t tmp;
1310 int i, allowed;
1311
1312 /* First, look for a known LPC bridge */
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001313 for (dev = pacc->devices; dev; dev = dev->next) {
Carl-Daniel Hailfingerd175e062010-05-21 23:00:56 +00001314 uint16_t device_class;
1315 /* libpci before version 2.2.4 does not store class info. */
1316 device_class = pci_read_word(dev, PCI_CLASS_DEVICE);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001317 if ((dev->vendor_id == 0x8086) &&
Carl-Daniel Hailfingerd175e062010-05-21 23:00:56 +00001318 (device_class == 0x0601)) { /* ISA Bridge */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001319 /* Is this device in our list? */
1320 for (i = 0; intel_ich_gpio_table[i].id; i++)
1321 if (dev->device_id == intel_ich_gpio_table[i].id)
1322 break;
1323
1324 if (intel_ich_gpio_table[i].id)
1325 break;
1326 }
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001327 }
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001328
Uwe Hermann93f66db2008-05-22 21:19:38 +00001329 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001330 msg_perr("\nERROR: No Known Intel LPC Bridge found.\n");
Uwe Hermann93f66db2008-05-22 21:19:38 +00001331 return -1;
1332 }
1333
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001334 /*
1335 * According to the datasheets, all Intel ICHs have the GPIO bar 5:1
1336 * strapped to zero. From some mobile ICH9 version on, this becomes
1337 * 6:1. The mask below catches all.
1338 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001339 base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0;
Uwe Hermann93f66db2008-05-22 21:19:38 +00001340
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001341 /* Check whether the line is allowed. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001342 if (gpio < 32)
1343 allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01;
1344 else if (gpio < 64)
1345 allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01;
1346 else
1347 allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01;
1348
1349 if (!allowed) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001350 msg_perr("\nERROR: This Intel LPC Bridge does not allow"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001351 " setting GPIO%02d\n", gpio);
1352 return -1;
1353 }
1354
Sean Nelson316a29f2010-05-07 20:09:04 +00001355 msg_pdbg("\nIntel ICH LPC Bridge: %sing GPIO%02d.\n",
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001356 raise ? "Rais" : "Dropp", gpio);
1357
1358 if (gpio < 32) {
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001359 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001360 tmp = INL(base);
1361 /* ICH/ICH0 multiplexes 27/28 on the line set. */
1362 if ((gpio == 28) &&
1363 ((dev->device_id == 0x2410) || (dev->device_id == 0x2420)))
1364 tmp |= 1 << 27;
1365 else
1366 tmp |= 1 << gpio;
1367 OUTL(tmp, base);
1368
1369 /* As soon as we are talking to ICH8 and above, this register
1370 decides whether we can set the gpio or not. */
1371 if (dev->device_id > 0x2800) {
1372 tmp = INL(base);
1373 if (!(tmp & (1 << gpio))) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001374 msg_perr("\nERROR: This Intel LPC Bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001375 " does not allow setting GPIO%02d\n",
1376 gpio);
1377 return -1;
1378 }
1379 }
1380
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001381 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001382 tmp = INL(base + 0x04);
1383 tmp &= ~(1 << gpio);
1384 OUTL(tmp, base + 0x04);
1385
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001386 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001387 tmp = INL(base + 0x0C);
1388 if (raise)
1389 tmp |= 1 << gpio;
1390 else
1391 tmp &= ~(1 << gpio);
1392 OUTL(tmp, base + 0x0C);
1393 } else if (gpio < 64) {
1394 gpio -= 32;
1395
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001396 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001397 tmp = INL(base + 0x30);
1398 tmp |= 1 << gpio;
1399 OUTL(tmp, base + 0x30);
1400
1401 /* As soon as we are talking to ICH8 and above, this register
1402 decides whether we can set the gpio or not. */
1403 if (dev->device_id > 0x2800) {
1404 tmp = INL(base + 30);
1405 if (!(tmp & (1 << gpio))) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001406 msg_perr("\nERROR: This Intel LPC Bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001407 " does not allow setting GPIO%02d\n",
1408 gpio + 32);
1409 return -1;
1410 }
1411 }
1412
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001413 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001414 tmp = INL(base + 0x34);
1415 tmp &= ~(1 << gpio);
1416 OUTL(tmp, base + 0x34);
1417
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001418 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001419 tmp = INL(base + 0x38);
1420 if (raise)
1421 tmp |= 1 << gpio;
1422 else
1423 tmp &= ~(1 << gpio);
1424 OUTL(tmp, base + 0x38);
1425 } else {
1426 gpio -= 64;
1427
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001428 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001429 tmp = INL(base + 0x40);
1430 tmp |= 1 << gpio;
1431 OUTL(tmp, base + 0x40);
1432
1433 tmp = INL(base + 40);
1434 if (!(tmp & (1 << gpio))) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001435 msg_perr("\nERROR: This Intel LPC Bridge does "
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001436 "not allow setting GPIO%02d\n", gpio + 64);
1437 return -1;
1438 }
1439
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001440 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001441 tmp = INL(base + 0x44);
1442 tmp &= ~(1 << gpio);
1443 OUTL(tmp, base + 0x44);
1444
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001445 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001446 tmp = INL(base + 0x48);
1447 if (raise)
1448 tmp |= 1 << gpio;
1449 else
1450 tmp &= ~(1 << gpio);
1451 OUTL(tmp, base + 0x48);
1452 }
Uwe Hermann93f66db2008-05-22 21:19:38 +00001453
1454 return 0;
1455}
1456
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001457/*
1458 * Suited for:
1459 * - abit IP35: Intel P35 + ICH9R
1460 * - abit IP35 Pro: Intel P35 + ICH9R
Uwe Hermann93f66db2008-05-22 21:19:38 +00001461 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001462static int intel_ich_gpio16_raise(void)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001463{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001464 return intel_ich_gpio_set(16, 1);
Uwe Hermann93f66db2008-05-22 21:19:38 +00001465}
1466
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001467/*
1468 * Suited for:
1469 * - HP Puffer2-UL8E (ASUS PTGD-LA OEM): LGA775 + 915 + ICH6
Michael Karchere57957c2010-07-24 11:14:37 +00001470 */
1471static int intel_ich_gpio18_raise(void)
1472{
1473 return intel_ich_gpio_set(18, 1);
1474}
1475
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001476/*
1477 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001478 * - MSI MS-7046: LGA775 + 915P + ICH6
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001479 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001480static int intel_ich_gpio19_raise(void)
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001481{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001482 return intel_ich_gpio_set(19, 1);
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001483}
1484
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001485/*
Luc Verhaegen6c5d4cc2009-11-28 18:26:21 +00001486 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001487 * - ASUS P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2
1488 * - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5
Michael Karcherf4b58792010-09-10 14:54:18 +00001489 * - ASUS P4P800: Intel socket478 + 865PE + ICH5R
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001490 * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R
Diego Elio Pettenòc6f71462011-03-06 22:52:55 +00001491 * - ASUS P4P800-VM: Intel socket478 + 865PE + ICH5R
Michael Karcher4a23e442010-09-10 14:46:46 +00001492 * - ASUS P5GD1 Pro: Intel LGA 775 + 915P + ICH6R
Joshua Roysb1d980f2010-09-13 14:02:22 +00001493 * - ASUS P5GDC Deluxe: Intel socket775 + 915P + ICH6R
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001494 * - ASUS P5PE-VM: Intel LGA775 + 865G + ICH5
1495 * - Samsung Polaris 32: socket478 + 865P + ICH5
Peter Stuge09c13332009-02-02 22:55:26 +00001496 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001497static int intel_ich_gpio21_raise(void)
Peter Stuge09c13332009-02-02 22:55:26 +00001498{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001499 return intel_ich_gpio_set(21, 1);
Peter Stuge09c13332009-02-02 22:55:26 +00001500}
1501
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001502/*
Michael Karcher03b80e92010-03-07 16:32:32 +00001503 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001504 * - ASUS P4B266: socket478 + Intel 845D + ICH2
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001505 * - ASUS P4B533-E: socket478 + 845E + ICH4
1506 * - ASUS P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001507 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001508static int intel_ich_gpio22_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001509{
1510 return intel_ich_gpio_set(22, 1);
1511}
1512
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001513/*
1514 * Suited for:
Stefan Tauner716e0982011-07-25 20:38:52 +00001515 * - ASUS A8Jm (laptop): Intel 945 + ICH7
1516 */
1517static int intel_ich_gpio34_raise(void)
1518{
1519 return intel_ich_gpio_set(34, 1);
1520}
1521
1522/*
1523 * Suited for:
Joshua Roysc73e2812011-07-09 19:46:53 +00001524 * - ASUS M6Ne (laptop): socket 479M (guessed) + Intel 855PM + ICH4-M
1525 */
1526static int intel_ich_gpio43_raise(void)
1527{
1528 return intel_ich_gpio_set(43, 1);
1529}
1530
1531/*
1532 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001533 * - HP Vectra VL400: 815 + ICH + PC87360
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001534 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001535static int board_hp_vl400(void)
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001536{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001537 int ret;
1538 ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */
1539 if (!ret)
Michael Karchercba52de2011-03-06 12:07:19 +00001540 ret = pc8736x_gpio_set(PC87360_ID, 0x09, 1); /* #WP ? */
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001541 if (!ret)
Michael Karchercba52de2011-03-06 12:07:19 +00001542 ret = pc8736x_gpio_set(PC87360_ID, 0x27, 1); /* #TBL */
1543 return ret;
1544}
1545
1546/*
1547 * Suited for:
1548 * - HP e-Vectra P2706T: 810E + ICH + PC87364
1549 */
1550static int board_hp_p2706t(void)
1551{
1552 int ret;
1553 ret = pc8736x_gpio_set(PC87364_ID, 0x25, 1);
1554 if (!ret)
1555 ret = pc8736x_gpio_set(PC87364_ID, 0x26, 1);
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001556 return ret;
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001557}
1558
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001559/*
Luc Verhaegen1265d8d2009-11-28 18:16:31 +00001560 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001561 * - Dell PowerEdge 1850: Intel PPGA604 + E7520 + ICH5R
1562 * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R
1563 * - ASRock 775i65G: Intel LGA 775 + 865G + ICH5
Uwe Hermann742999c2010-12-02 21:57:42 +00001564 * - MSI MS-6391 (845 Pro4): Intel Socket478 + 845 + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001565 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001566static int intel_ich_gpio23_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001567{
1568 return intel_ich_gpio_set(23, 1);
1569}
1570
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001571/*
1572 * Suited for:
Michael Karcher39dcdec2010-10-05 17:29:35 +00001573 * - GIGABYTE GA-6IEM: Intel Socket370 + i815 + ICH2
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001574 * - GIGABYTE GA-8IRML: Intel Socket478 + i845 + ICH2
Michael Karcherc7a1ffb2010-07-24 22:27:29 +00001575 */
1576static int intel_ich_gpio25_raise(void)
1577{
1578 return intel_ich_gpio_set(25, 1);
1579}
1580
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001581/*
1582 * Suited for:
1583 * - IBASE MB899: i945GM + ICH7
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001584 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001585static int intel_ich_gpio26_raise(void)
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001586{
1587 return intel_ich_gpio_set(26, 1);
1588}
1589
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001590/*
1591 * Suited for:
1592 * - P4SD-LA (HP OEM): i865 + ICH5
Joshua Roys9d9a1042011-06-13 16:59:01 +00001593 * - GIGABYTE GA-8IP775: 865P + ICH5
Michael Karcherc8613242010-08-13 12:49:01 +00001594 * - GIGABYTE GA-8PE667 Ultra 2: socket 478 + i845PE + ICH4
Maciej Pijanka6add0942011-06-09 20:59:30 +00001595 * - MSI MS-6788-40 (aka 848P Neo-V)
Michael Karcher87c90992010-07-24 11:03:48 +00001596 */
Idwer Vollering19dceac2010-07-24 18:47:45 +00001597static int intel_ich_gpio32_raise(void)
Michael Karcher87c90992010-07-24 11:03:48 +00001598{
1599 return intel_ich_gpio_set(32, 1);
1600}
1601
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001602/*
1603 * Suited for:
Joshua Roys7225ccd2011-05-18 01:32:16 +00001604 * - AOpen i975Xa-YDG: i975X + ICH7 + W83627EHF
1605 */
1606static int board_aopen_i975xa_ydg(void)
1607{
1608 int ret;
1609
1610 /* vendor BIOS ends up in LDN6... maybe the board enable is wrong,
1611 * or perhaps it's not needed at all?
1612 * the regs it tries to touch are 0xF0, 0xF1, 0xF2 which means if it
1613 * were in the right LDN, it would have to be GPIO1 or GPIO3
1614 */
1615/*
1616 ret = winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, x, 0)
1617 if (!ret)
1618*/
1619 ret = intel_ich_gpio_set(33, 1);
1620
1621 return ret;
1622}
1623
1624/*
1625 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001626 * - Acorp 6A815EPD: socket 370 + intel 815 + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001627 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001628static int board_acorp_6a815epd(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001629{
1630 int ret;
1631
1632 /* Lower Blocks Lock -- pin 7 of PLCC32 */
1633 ret = intel_ich_gpio_set(22, 1);
1634 if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */
1635 ret = intel_ich_gpio_set(23, 1);
1636
1637 return ret;
1638}
1639
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001640/*
1641 * Suited for:
1642 * - Kontron 986LCD-M: Socket478 + 915GM + ICH7R
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001643 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001644static int board_kontron_986lcd_m(void)
Stefan Reinauerac378972008-03-17 22:59:40 +00001645{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001646 int ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001647
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001648 ret = intel_ich_gpio_set(34, 1); /* #TBL */
1649 if (!ret)
1650 ret = intel_ich_gpio_set(35, 1); /* #WP */
Stefan Reinauerac378972008-03-17 22:59:40 +00001651
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001652 return ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001653}
1654
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001655/*
1656 * Suited for:
1657 * - Soyo SY-7VCA: Pro133A + VT82C686
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001658 */
Michael Karcher06477332010-03-19 22:49:09 +00001659static int via_apollo_gpo_set(int gpio, int raise)
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001660{
Michael Karcher06477332010-03-19 22:49:09 +00001661 struct pci_dev *dev;
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001662 uint32_t base;
Michael Karcher06477332010-03-19 22:49:09 +00001663 uint32_t tmp;
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001664
1665 /* VT82C686 Power management */
1666 dev = pci_dev_find(0x1106, 0x3057);
1667 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001668 msg_perr("\nERROR: VT82C686 PM device not found.\n");
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001669 return -1;
1670 }
1671
Sean Nelson316a29f2010-05-07 20:09:04 +00001672 msg_pdbg("\nVIA Apollo ACPI: %sing GPIO%02d.\n",
Michael Karcher06477332010-03-19 22:49:09 +00001673 raise ? "Rais" : "Dropp", gpio);
1674
1675 /* select GPO function on multiplexed pins */
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001676 tmp = pci_read_byte(dev, 0x54);
Michael Karcher06477332010-03-19 22:49:09 +00001677 switch(gpio)
1678 {
1679 case 0:
1680 tmp &= ~0x03;
1681 break;
1682 case 1:
1683 tmp |= 0x04;
1684 break;
1685 case 2:
1686 tmp |= 0x08;
1687 break;
1688 case 3:
1689 tmp |= 0x10;
1690 break;
1691 }
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001692 pci_write_byte(dev, 0x54, tmp);
1693
1694 /* PM IO base */
1695 base = pci_read_long(dev, 0x48) & 0x0000FF00;
1696
1697 /* Drop GPO0 */
Michael Karcher06477332010-03-19 22:49:09 +00001698 tmp = INL(base + 0x4C);
1699 if (raise)
1700 tmp |= 1U << gpio;
1701 else
1702 tmp &= ~(1U << gpio);
1703 OUTL(tmp, base + 0x4C);
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001704
1705 return 0;
1706}
1707
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001708/*
1709 * Suited for:
1710 * - abit VT6X4: Pro133x + VT82C686A
Mattias Mattssone3df96e2010-08-15 22:43:23 +00001711 * - abit VA6: Pro133x + VT82C686A
Michael Karcher187a46a2010-03-19 22:30:49 +00001712 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001713static int via_apollo_gpo4_lower(void)
Michael Karcher187a46a2010-03-19 22:30:49 +00001714{
1715 return via_apollo_gpo_set(4, 0);
1716}
1717
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001718/*
1719 * Suited for:
1720 * - Soyo SY-7VCA: Pro133A + VT82C686
Michael Karcher06477332010-03-19 22:49:09 +00001721 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001722static int via_apollo_gpo0_lower(void)
Michael Karcher06477332010-03-19 22:49:09 +00001723{
1724 return via_apollo_gpo_set(0, 0);
1725}
1726
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001727/*
Michael Karchera08d0f22011-07-25 17:25:24 +00001728 * Enable some GPIO pin on SiS southbridge and enables SIO flash writes.
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001729 *
1730 * Suited for:
1731 * - MSI 651M-L: SiS651 / SiS962
Michael Karchera08d0f22011-07-25 17:25:24 +00001732 * - GIGABYTE GA-8SIMLH
Michael Karcher9f9e6132010-01-09 17:36:06 +00001733 */
Michael Karchera08d0f22011-07-25 17:25:24 +00001734static int sis_gpio0_raise_and_w836xx_memw(void)
Michael Karcher9f9e6132010-01-09 17:36:06 +00001735{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001736 struct pci_dev *dev;
Uwe Hermann43959702010-03-13 17:28:29 +00001737 uint16_t base, temp;
Michael Karcher9f9e6132010-01-09 17:36:06 +00001738
1739 dev = pci_dev_find(0x1039, 0x0962);
1740 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001741 msg_perr("Expected south bridge not found\n");
Michael Karcher9f9e6132010-01-09 17:36:06 +00001742 return 1;
1743 }
1744
Michael Karcher9f9e6132010-01-09 17:36:06 +00001745 base = pci_read_word(dev, 0x74);
1746 temp = INW(base + 0x68);
1747 temp &= ~(1 << 0); /* Make pin output? */
Michael Karcher0435dfd2010-01-09 23:31:13 +00001748 OUTW(temp, base + 0x68);
Michael Karcher9f9e6132010-01-09 17:36:06 +00001749
1750 temp = INW(base + 0x64);
1751 temp |= (1 << 0); /* Raise output? */
1752 OUTW(temp, base + 0x64);
1753
1754 w836xx_memw_enable(0x2E);
1755
1756 return 0;
1757}
1758
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001759/*
Michael Gold6d52e472009-06-19 13:00:24 +00001760 * Find the runtime registers of an SMSC Super I/O, after verifying its
1761 * chip ID.
1762 *
1763 * Returns the base port of the runtime register block, or 0 on error.
1764 */
1765static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id,
1766 uint8_t logical_device)
1767{
1768 uint16_t rt_port = 0;
1769
1770 /* Verify the chip ID. */
Uwe Hermann1432a602009-06-28 23:26:37 +00001771 OUTB(0x55, sio_port); /* Enable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00001772 if (sio_read(sio_port, 0x20) != chip_id) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001773 msg_perr("\nERROR: SMSC Super I/O not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +00001774 goto out;
1775 }
1776
1777 /* If the runtime block is active, get its address. */
1778 sio_write(sio_port, 0x07, logical_device);
1779 if (sio_read(sio_port, 0x30) & 1) {
1780 rt_port = (sio_read(sio_port, 0x60) << 8)
1781 | sio_read(sio_port, 0x61);
1782 }
1783
1784 if (rt_port == 0) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001785 msg_perr("\nERROR: "
Michael Gold6d52e472009-06-19 13:00:24 +00001786 "Super I/O runtime interface not available.\n");
1787 }
1788out:
Uwe Hermann1432a602009-06-28 23:26:37 +00001789 OUTB(0xaa, sio_port); /* Disable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00001790 return rt_port;
1791}
1792
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001793/*
1794 * Disable write protection on the Mitac 6513WU. WP# on the FWH is
Michael Gold6d52e472009-06-19 13:00:24 +00001795 * connected to GP30 on the Super I/O, and TBL# is always high.
1796 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001797static int board_mitac_6513wu(void)
Michael Gold6d52e472009-06-19 13:00:24 +00001798{
1799 struct pci_dev *dev;
1800 uint16_t rt_port;
1801 uint8_t val;
1802
1803 dev = pci_dev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */
1804 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001805 msg_perr("\nERROR: Intel 82801AA ISA bridge not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +00001806 return -1;
1807 }
1808
Uwe Hermann1432a602009-06-28 23:26:37 +00001809 rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa);
Michael Gold6d52e472009-06-19 13:00:24 +00001810 if (rt_port == 0)
1811 return -1;
1812
1813 /* Configure the GPIO pin. */
1814 val = INB(rt_port + 0x33); /* GP30 config */
Uwe Hermann1432a602009-06-28 23:26:37 +00001815 val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */
Michael Gold6d52e472009-06-19 13:00:24 +00001816 OUTB(val, rt_port + 0x33);
1817
1818 /* Disable write protection. */
1819 val = INB(rt_port + 0x4d); /* GP3 values */
Uwe Hermann1432a602009-06-28 23:26:37 +00001820 val |= 0x01; /* Set GP30 high. */
Michael Gold6d52e472009-06-19 13:00:24 +00001821 OUTB(val, rt_port + 0x4d);
1822
1823 return 0;
1824}
1825
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001826/*
1827 * Suited for:
Uwe Hermann45bd1442010-09-14 23:20:35 +00001828 * - ASUS A7V333: VIA KT333 + VT8233A + IT8703F
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001829 * - ASUS A7V8X: VIA KT400 + VT8235 + IT8703F
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001830 */
Uwe Hermann45bd1442010-09-14 23:20:35 +00001831static int it8703f_gpio51_raise(void)
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001832{
1833 uint16_t id, base;
1834 uint8_t tmp;
1835
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001836 /* Find the IT8703F. */
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001837 w836xx_ext_enter(0x2E);
1838 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
1839 w836xx_ext_leave(0x2E);
1840
1841 if (id != 0x8701) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001842 msg_perr("\nERROR: IT8703F Super I/O not found.\n");
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001843 return -1;
1844 }
1845
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001846 /* Get the GP567 I/O base. */
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001847 w836xx_ext_enter(0x2E);
1848 sio_write(0x2E, 0x07, 0x0C);
1849 base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
1850 w836xx_ext_leave(0x2E);
1851
1852 if (!base) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001853 msg_perr("\nERROR: Failed to read IT8703F Super I/O GPIO"
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001854 " Base.\n");
1855 return -1;
1856 }
1857
1858 /* Raise GP51. */
1859 tmp = INB(base);
1860 tmp |= 0x02;
1861 OUTB(tmp, base);
1862
1863 return 0;
1864}
1865
Luc Verhaegen72272912009-09-01 21:22:23 +00001866/*
1867 * General routine for raising/dropping GPIO lines on the ITE IT8712F.
1868 * There is only some limited checking on the port numbers.
1869 */
Uwe Hermann43959702010-03-13 17:28:29 +00001870static int it8712f_gpio_set(unsigned int line, int raise)
Luc Verhaegen72272912009-09-01 21:22:23 +00001871{
1872 unsigned int port;
1873 uint16_t id, base;
1874 uint8_t tmp;
1875
1876 port = line / 10;
1877 port--;
1878 line %= 10;
1879
1880 /* Check line */
1881 if ((port > 4) || /* also catches unsigned -1 */
1882 ((port < 4) && (line > 7)) || ((port == 4) && (line > 5))) {
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001883 msg_perr("\nERROR: Unsupported IT8712F GPIO line %02d.\n", line);
Luc Verhaegen72272912009-09-01 21:22:23 +00001884 return -1;
1885 }
1886
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001887 /* Find the IT8712F. */
Luc Verhaegen72272912009-09-01 21:22:23 +00001888 enter_conf_mode_ite(0x2E);
1889 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
1890 exit_conf_mode_ite(0x2E);
1891
1892 if (id != 0x8712) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001893 msg_perr("\nERROR: IT8712F Super I/O not found.\n");
Luc Verhaegen72272912009-09-01 21:22:23 +00001894 return -1;
1895 }
1896
1897 /* Get the GPIO base */
1898 enter_conf_mode_ite(0x2E);
1899 sio_write(0x2E, 0x07, 0x07);
1900 base = (sio_read(0x2E, 0x62) << 8) | sio_read(0x2E, 0x63);
1901 exit_conf_mode_ite(0x2E);
1902
1903 if (!base) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001904 msg_perr("\nERROR: Failed to read IT8712F Super I/O GPIO"
Luc Verhaegen72272912009-09-01 21:22:23 +00001905 " Base.\n");
1906 return -1;
1907 }
1908
1909 /* set GPIO. */
1910 tmp = INB(base + port);
1911 if (raise)
1912 tmp |= 1 << line;
1913 else
1914 tmp &= ~(1 << line);
1915 OUTB(tmp, base + port);
1916
1917 return 0;
1918}
1919
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001920/*
Russ Dillbd622d12010-03-09 16:57:06 +00001921 * Suited for:
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001922 * - ASUS A7V600-X: VIA KT600 + VT8237 + IT8712F
1923 * - ASUS A7V8X-X: VIA KT400 + VT8235 + IT8712F
Luc Verhaegen72272912009-09-01 21:22:23 +00001924 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001925static int it8712f_gpio3_1_raise(void)
Luc Verhaegen72272912009-09-01 21:22:23 +00001926{
1927 return it8712f_gpio_set(32, 1);
1928}
1929
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001930#endif
1931
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001932/*
Uwe Hermannd0e347d2009-10-06 13:00:00 +00001933 * Below is the list of boards which need a special "board enable" code in
1934 * flashrom before their ROM chip can be accessed/written to.
1935 *
1936 * NOTE: Please add boards that _don't_ need such enables or don't work yet
1937 * to the respective tables in print.c. Thanks!
1938 *
Uwe Hermannffec5f32007-08-23 16:08:21 +00001939 * We use 2 sets of IDs here, you're free to choose which is which. This
1940 * is to provide a very high degree of certainty when matching a board on
1941 * the basis of subsystem/card IDs. As not every vendor handles
1942 * subsystem/card IDs in a sane manner.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001943 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00001944 * Keep the second set NULLed if it should be ignored. Keep the subsystem IDs
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00001945 * NULLed if they don't identify the board fully and if you can't use DMI.
1946 * But please take care to provide an as complete set of pci ids as possible;
1947 * autodetection is the preferred behaviour and we would like to make sure that
1948 * matches are unique.
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001949 *
Michael Karcher6701ee82010-01-20 14:14:11 +00001950 * If PCI IDs are not sufficient for board matching, the match can be further
1951 * constrained by a string that has to be present in the DMI database for
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001952 * the baseboard or the system entry. The pattern is matched by case sensitive
Michael Karcher6701ee82010-01-20 14:14:11 +00001953 * substring match, unless it is anchored to the beginning (with a ^ in front)
1954 * or the end (with a $ at the end). Both anchors may be specified at the
1955 * same time to match the full field.
1956 *
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00001957 * When a board is matched through DMI, the first and second main PCI IDs
1958 * and the first subsystem PCI ID have to match as well. If you specify the
1959 * first subsystem ID as 0x0:0x0, the DMI matching code expects that the
1960 * subsystem ID of that device is indeed zero.
1961 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00001962 * The coreboot ids are used two fold. When running with a coreboot firmware,
1963 * the ids uniquely matches the coreboot board identification string. When a
1964 * legacy bios is installed and when autodetection is not possible, these ids
1965 * can be used to identify the board through the -m command line argument.
1966 *
1967 * When a board is identified through its coreboot ids (in both cases), the
1968 * main pci ids are still required to match, as a safeguard.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001969 */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001970
Uwe Hermanndeeebe22009-05-08 16:23:34 +00001971/* Please keep this list alphabetically ordered by vendor/board name. */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +00001972const struct board_pciid_enable board_pciid_enables[] = {
Uwe Hermann5ab88892009-06-21 20:50:22 +00001973
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00001974 /* first pci-id set [4], second pci-id set [4], dmi identifier, coreboot id [2], phase, vendor name, board name max_rom_... OK? flash enable */
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001975#if defined(__i386__) || defined(__x86_64__)
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00001976 {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, P3, "abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise},
1977 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^i440BX-W977 (BM6)$", NULL, NULL, P3, "abit", "BM6", 0, OK, intel_piix4_gpo26_lower},
1978 {0x8086, 0x24d3, 0x147b, 0x1014, 0x8086, 0x2578, 0x147b, 0x1014, NULL, NULL, NULL, P3, "abit", "IC7", 0, NT, intel_ich_gpio23_raise},
1979 {0x8086, 0x2930, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, P3, "abit", "IP35", 0, OK, intel_ich_gpio16_raise},
1980 {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, P3, "abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise},
1981 {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, P3, "abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower},
1982 {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, P3, "abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise},
Antony Rheneus0fbba982011-05-26 14:28:51 +00001983 {0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0240, 0x10de, 0x0222, NULL, NULL, NULL, P3, "abit", "NF-M2 nView", 0, OK, nvidia_mcp_gpio4_lower},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00001984 {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, "(VA6)$", NULL, NULL, P3, "abit", "VA6", 0, OK, via_apollo_gpo4_lower},
1985 {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", P3, "abit", "VT6X4", 0, OK, via_apollo_gpo4_lower},
1986 {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, P3, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd},
1987 {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", P3, "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e},
1988 {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, P3, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e},
1989 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", P3, "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x},
1990 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", P3, "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x},
Joshua Roys7225ccd2011-05-18 01:32:16 +00001991 {0x8086, 0x277c, 0xa0a0, 0x060b, 0x8086, 0x27da, 0xa0a0, 0x060b, NULL, NULL, NULL, P3, "AOpen", "i975Xa-YDG", 0, OK, board_aopen_i975xa_ydg},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00001992 {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41 $", NULL, NULL, P3, "ASRock", "K7S41", 0, OK, w836xx_memw_enable_2e},
Pawel Rozanski1d233072011-06-19 16:52:48 +00001993 {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41GX$", NULL, NULL, P3, "ASRock", "K7S41GX", 0, OK, w836xx_memw_enable_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00001994 {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, P3, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise},
1995 {0x8086, 0x2570, 0x1849, 0x2570, 0x8086, 0x24d3, 0x1849, 0x24d0, NULL, NULL, NULL, P3, "ASRock", "775i65G", 0, OK, intel_ich_gpio23_raise},
1996 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, P3, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise},
1997 {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, P3, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e},
1998 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V8X", 0, OK, it8703f_gpio51_raise},
1999 {0x1106, 0x3099, 0x1043, 0x807F, 0x1106, 0x3147, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V333", 0, OK, it8703f_gpio51_raise},
2000 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, P3, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise},
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00002001 {0x1002, 0x4372, 0x103c, 0x2a26, 0x1002, 0x4377, 0x103c, 0x2a26, NULL, NULL, NULL, P3, "ASUS", "A8AE-LE", 0, OK, amd_sbxxx_gpio9_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002002 {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, P3, "ASUS", "A8Jm", 0, NT, intel_ich_gpio34_raise},
2003 {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI2L", NULL, NULL, P3, "ASUS", "A8N-LA (Nagami-GL8E)", 0, OK, nvidia_mcp_gpio0_raise},
Stefan Taunerd06d9412011-06-12 19:47:55 +00002004 {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, "^A8N-SLI", NULL, NULL, P3, "ASUS", "A8N-SLI Deluxe", 0, NT, board_shuttle_fn25},
Stefan Taunerff80e682011-07-20 16:34:18 +00002005 {0x10de, 0x0264, 0x1043, 0x81bc, 0x10de, 0x02f0, 0x1043, 0x81cd, NULL, NULL, NULL, P3, "ASUS", "A8N-VM CSM", 0, OK, w83627ehf_gpio22_raise_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002006 {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, P3, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise},
2007 {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, P3, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise},
Joshua Roysc73e2812011-07-09 19:46:53 +00002008 {0x8086, 0x24cc, 0, 0, 0x8086, 0x24c3, 0x1043, 0x1869, "^M6Ne$", NULL, NULL, P3, "ASUS", "M6Ne", 0, NT, intel_ich_gpio43_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002009 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^P2B-N$", NULL, NULL, P3, "ASUS", "P2B-N", 0, OK, intel_piix4_gpo18_lower},
2010 {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, P3, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise},
2011 {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, P3, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise},
2012 {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, P3, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise},
2013 {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, P3, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
2014 {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D5, 0x1043, 0x80F3, NULL, NULL, NULL, P3, "ASUS", "P4P800", 0, NT, intel_ich_gpio21_raise},
2015 {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, P3, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
2016 {0x8086, 0x2570, 0x1043, 0x80A5, 0x8086, 0x24d0, 0, 0, NULL, NULL, NULL, P3, "ASUS", "P4P800-VM", 0, OK, intel_ich_gpio21_raise},
2017 {0x1039, 0x0651, 0x1043, 0x8081, 0x1039, 0x0962, 0, 0, NULL, NULL, NULL, P3, "ASUS", "P4SC-E", 0, OK, it8707f_write_enable_2e},
2018 {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, P3, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise},
2019 {0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x5513, 0x1043, 0x8087, NULL, NULL, NULL, P3, "ASUS", "P4S800-MX", 512, OK, w836xx_memw_enable_2e},
2020 {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", P3, "ASUS", "P5A", 0, OK, board_asus_p5a},
2021 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, P3, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise},
2022 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, P3, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise},
2023 {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, P3, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise},
2024 {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, P3, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise},
2025 {0x10b7, 0x9055, 0x1028, 0x0082, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Dell", "OptiPlex GX1", 0, OK, intel_piix4_gpo30_lower},
2026 {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, P3, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise},
2027 {0x10de, 0x03ea, 0x1019, 0x2602, 0x10de, 0x03e0, 0x1019, 0x2602, NULL, NULL, NULL, P3, "Elitegroup", "GeForce6100SM-M", 0, OK, board_ecs_geforce6100sm_m},
2028 {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, P3, "Elitegroup", "K7VTA3", 256, OK, NULL},
2029 {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, P3, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e},
Stefan Taunerb86e1182011-07-24 16:30:31 +00002030 {0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, "8NPA7I", NULL, NULL, P3, "EPoX", "EP-8NPA7I", 0, NT, nvidia_mcp_gpio4_raise}, /* needs http://patchwork.coreboot.org/patch/2125/ */
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002031 {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, P3, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise},
2032 {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", P3, "EPoX", "EP-BX3", 0, NT, intel_piix4_gpo22_raise},
2033 {0x10de, 0x02f0, 0x105b, 0x0d01, 0x10de, 0x0264, 0x105b, 0x0d01, NULL, NULL, NULL, P3, "Foxconn", "6150K8MD-8EKRSH", 0, NT, nvidia_mcp_gpio2_raise},
2034 {0x8086, 0x2443, 0x8086, 0x2442, 0x8086, 0x1130, 0x8086, 0x1130, "^6IEM ", NULL, NULL, P3, "GIGABYTE", "GA-6IEM", 0, NT, intel_ich_gpio25_raise},
2035 {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-7ZM", 512, OK, NULL},
Joshua Roys9d9a1042011-06-13 16:59:01 +00002036 {0x8086, 0x2570, 0x1458, 0x2570, 0x8086, 0x24d0, 0, 0, "^8IP775/-G$",NULL, NULL, P3, "GIGABYTE", "GA-8IP775", 0, OK, intel_ich_gpio32_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002037 {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise},
2038 {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise},
Stefan Tauner716e0982011-07-25 20:38:52 +00002039 {0x1039, 0x0651, 0x1039, 0x0651, 0x1039, 0x7002, 0x1458, 0x5004, "^GA-8SIMLH$",NULL, NULL, P3, "GIGABYTE", "GA-8SIMLH", 0, OK, sis_gpio0_raise_and_w836xx_memw},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002040 {0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise},
2041 {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise},
Idwer Volleringd8a00a02011-06-13 16:58:54 +00002042 {0x10de, 0x00e4, 0x1458, 0x0c11, 0x10de, 0x00e0, 0x1458, 0x0c11, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8NS Pro-939", 0, NT, nvidia_mcp_gpio0a_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002043 {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise},
Idwer Volleringd8a00a02011-06-13 16:58:54 +00002044 {0x8086, 0x2415, 0x103c, 0x1250, 0x10b7, 0x9200, 0x103c, 0x1247, NULL, NULL, NULL, P3, "HP", "e-Vectra P2706T", 0, OK, board_hp_p2706t},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002045 {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", P3, "HP", "ProLiant DL145 G3", 0, OK, board_hp_dl145_g3_enable},
2046 {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", P3, "HP", "ProLiant DL165 G6", 0, OK, board_hp_dl165_g6_enable},
2047 {0x8086, 0x2580, 0x103c, 0x2a08, 0x8086, 0x2640, 0x103c, 0x2a0a, NULL, NULL, NULL, P3, "HP", "Puffer2-UL8E", 0, OK, intel_ich_gpio18_raise},
Idwer Volleringd8a00a02011-06-13 16:58:54 +00002048 {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, P3, "HP", "Vectra VL400", 0, OK, board_hp_vl400},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002049 {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, P3, "HP", "Vectra VL420 SFF", 0, OK, intel_ich_gpio22_raise},
2050 {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, "hp", "xw9400", P3, "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise},
2051 {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", P3, "IBASE", "MB899", 0, OK, intel_ich_gpio26_raise},
2052 {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, P3, "IBM", "x3455", 0, OK, board_ibm_x3455},
2053 {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, P3, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi},
2054 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, P3, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower},
2055 {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, NULL, "iwill", "dk8_htx", P3, "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e},
2056 {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", P3, "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m},
2057 {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, P3, "Mitac", "6513WU", 0, OK, board_mitac_6513wu},
2058 {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, P3, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, /* TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html. */
2059 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^MS-6163 (i440BX)$", NULL, NULL, P3, "MSI", "MS-6163 (MS-6163 Pro)", 0, OK, intel_piix4_gpo14_raise},
2060 {0x1039, 0x0745, 0, 0, 0x1039, 0x0018, 0, 0, "^MS-6561", NULL, NULL, P3, "MSI", "MS-6561 (745 Ultra)", 0, OK, w836xx_memw_enable_2e},
2061 {0x8086, 0x2560, 0x1462, 0x5770, 0x8086, 0x2562, 0x1462, 0x5778, NULL, NULL, NULL, P3, "MSI", "MS-6577 (Xenon)", 0, OK, w83627hf_gpio25_raise_2e},
2062 {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, P3, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v},
2063 {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, P3, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio44_raise_2e},
2064 {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, P3, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v},
2065 {0x1106, 0x3148, 0 , 0 , 0x1106, 0x3177, 0 , 0 , NULL, "msi", "ms6787", P3, "MSI", "MS-6787 (P4MAM-V/P4MAM-L)", 0, OK, w836xx_memw_enable_2e},
Maciej Pijanka6add0942011-06-09 20:59:30 +00002066 {0x8086, 0x24d3, 0x1462, 0x7880, 0x8086, 0x2570, 0, 0, NULL, NULL, NULL, P3, "MSI", "MS-6788-040 (848P NeoV)", 0, OK, intel_ich_gpio32_raise},
Michael Karchera08d0f22011-07-25 17:25:24 +00002067 {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, P3, "MSI", "MS-7005 (651M-L)", 0, OK, sis_gpio0_raise_and_w836xx_memw},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002068 {0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, P3, "MSI", "MS-7025 (K8N Neo2 Platinum)", 0, OK, nvidia_mcp_gpio0c_raise},
2069 {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, P3, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise},
2070 {0x8086, 0x244b, 0x1462, 0x3910, 0x8086, 0x2442, 0x1462, 0x3910, NULL, NULL, NULL, P3, "MSI", "MS-6391 (845 Pro4)", 0, OK, intel_ich_gpio23_raise},
2071 {0x1106, 0x3149, 0x1462, 0x7061, 0x1106, 0x3227, 0, 0, NULL, NULL, NULL, P3, "MSI", "MS-7061 (KM4M-V/KM4AM-V)", 0, OK, w836xx_memw_enable_2e},
2072 {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", P3, "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio44_raise_4e},
2073 {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, P3, "MSI", "MS-7207 (K8NGM2-L)", 0, NT, nvidia_mcp_gpio2_raise},
2074 {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0},
2075 {0x8086, 0x24d3, 0x144d, 0xb025, 0x8086, 0x1050, 0x144d, 0xb025, NULL, NULL, NULL, P3, "Samsung", "Polaris 32", 0, OK, intel_ich_gpio21_raise},
2076 {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", P3, "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e},
2077 {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, P3, "Shuttle", "AK38N", 256, OK, NULL},
2078 {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, P3, "Shuttle", "FN25", 0, OK, board_shuttle_fn25},
2079 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, P3, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower},
2080 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, P3, "Tekram", "P6Pro-A5", 256, OK, NULL},
2081 {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, P3, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e},
2082 {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, P3, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e},
2083 {0x1106, 0x0259, 0x1106, 0xAA07, 0x1106, 0x3227, 0x1106, 0xAA07, NULL, NULL, NULL, P3, "VIA", "EPIA EK", 0, NT, via_vt823x_gpio9_raise},
2084 {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, P3, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise},
2085 {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, P3, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise},
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00002086#endif
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002087 { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, P3, NULL, NULL, 0, NT, NULL}, /* end marker */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002088};
2089
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002090/*
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +00002091 * Match boards on coreboot table gathered vendor and part name.
Uwe Hermannffec5f32007-08-23 16:08:21 +00002092 * Require main PCI IDs to match too as extra safety.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002093 */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +00002094static const struct board_pciid_enable *board_match_coreboot_name(const char *vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00002095 const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002096{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +00002097 const struct board_pciid_enable *board = board_pciid_enables;
2098 const struct board_pciid_enable *partmatch = NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002099
Uwe Hermanna93045c2009-05-09 00:47:04 +00002100 for (; board->vendor_name; board++) {
Uwe Hermann394131e2008-10-18 21:14:13 +00002101 if (vendor && (!board->lb_vendor
2102 || strcasecmp(board->lb_vendor, vendor)))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002103 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002104
Peter Stuge0b9c5f32008-07-02 00:47:30 +00002105 if (!board->lb_part || strcasecmp(board->lb_part, part))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002106 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002107
Uwe Hermanna7e05482007-05-09 10:17:44 +00002108 if (!pci_dev_find(board->first_vendor, board->first_device))
2109 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002110
Uwe Hermanna7e05482007-05-09 10:17:44 +00002111 if (board->second_vendor &&
Uwe Hermann394131e2008-10-18 21:14:13 +00002112 !pci_dev_find(board->second_vendor, board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002113 continue;
Peter Stuge6b53fed2008-01-27 16:21:21 +00002114
2115 if (vendor)
2116 return board;
2117
2118 if (partmatch) {
2119 /* a second entry has a matching part name */
Sean Nelson316a29f2010-05-07 20:09:04 +00002120 msg_pinfo("AMBIGUOUS BOARD NAME: %s\n", part);
2121 msg_pinfo("At least vendors '%s' and '%s' match.\n",
Uwe Hermann394131e2008-10-18 21:14:13 +00002122 partmatch->lb_vendor, board->lb_vendor);
Sean Nelson316a29f2010-05-07 20:09:04 +00002123 msg_perr("Please use the full -m vendor:part syntax.\n");
Peter Stuge6b53fed2008-01-27 16:21:21 +00002124 return NULL;
2125 }
2126 partmatch = board;
Uwe Hermanna7e05482007-05-09 10:17:44 +00002127 }
Uwe Hermann372eeb52007-12-04 21:49:06 +00002128
Peter Stuge6b53fed2008-01-27 16:21:21 +00002129 if (partmatch)
2130 return partmatch;
2131
Carl-Daniel Hailfingerbc25f942009-07-30 13:30:17 +00002132 if (!partvendor_from_cbtable) {
2133 /* Only warn if the mainboard type was not gathered from the
2134 * coreboot table. If it was, the coreboot implementor is
2135 * expected to fix flashrom, too.
2136 */
Sean Nelson316a29f2010-05-07 20:09:04 +00002137 msg_perr("\nUnknown vendor:board from -m option: %s:%s\n\n",
Carl-Daniel Hailfingerbc25f942009-07-30 13:30:17 +00002138 vendor, part);
2139 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00002140 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002141}
2142
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002143/*
Uwe Hermannffec5f32007-08-23 16:08:21 +00002144 * Match boards on PCI IDs and subsystem IDs.
2145 * Second set of IDs can be main only or missing completely.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002146 */
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002147const static struct board_pciid_enable *board_match_pci_card_ids(enum board_match_phase phase)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002148{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +00002149 const struct board_pciid_enable *board = board_pciid_enables;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002150
Uwe Hermanna93045c2009-05-09 00:47:04 +00002151 for (; board->vendor_name; board++) {
Michael Karcher2eab70d2010-02-04 10:58:50 +00002152 if ((!board->first_card_vendor || !board->first_card_device) &&
2153 !board->dmi_pattern)
Uwe Hermanna7e05482007-05-09 10:17:44 +00002154 continue;
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002155 if (board->phase != phase)
2156 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002157
Uwe Hermanna7e05482007-05-09 10:17:44 +00002158 if (!pci_card_find(board->first_vendor, board->first_device,
Uwe Hermann394131e2008-10-18 21:14:13 +00002159 board->first_card_vendor,
2160 board->first_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002161 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002162
Uwe Hermanna7e05482007-05-09 10:17:44 +00002163 if (board->second_vendor) {
2164 if (board->second_card_vendor) {
2165 if (!pci_card_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00002166 board->second_device,
2167 board->second_card_vendor,
2168 board->second_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002169 continue;
2170 } else {
2171 if (!pci_dev_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00002172 board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002173 continue;
2174 }
2175 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002176
Michael Karcher6701ee82010-01-20 14:14:11 +00002177 if (board->dmi_pattern) {
2178 if (!has_dmi_support) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002179 msg_perr("WARNING: Can't autodetect %s %s,"
Michael Karcher6701ee82010-01-20 14:14:11 +00002180 " DMI info unavailable.\n",
2181 board->vendor_name, board->board_name);
2182 continue;
2183 } else {
2184 if (!dmi_match(board->dmi_pattern))
2185 continue;
2186 }
2187 }
2188
Uwe Hermanna7e05482007-05-09 10:17:44 +00002189 return board;
2190 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002191
Uwe Hermanna7e05482007-05-09 10:17:44 +00002192 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002193}
2194
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002195static int unsafe_board_handler(const struct board_pciid_enable *board)
2196{
2197 if (!board)
2198 return 1;
2199
2200 if (board->status == OK)
2201 return 0;
2202
2203 if (!force_boardenable) {
2204 msg_pinfo("WARNING: Your mainboard is %s %s, but the mainboard-specific\n"
Stefan Tauner9df880f2011-05-17 23:30:13 +00002205 "code has not been tested, and thus will not be executed by default.\n"
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002206 "Depending on your hardware environment, erasing, writing or even probing\n"
2207 "can fail without running the board specific code.\n\n"
2208 "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n"
2209 "\"internal programmer\") for details.\n",
2210 board->vendor_name, board->board_name);
2211 return 1;
2212 }
2213 msg_pinfo("NOTE: Running an untested board enable procedure.\n"
2214 "Please report success/failure to flashrom@flashrom.org\n"
2215 "with your board name and SUCCESS or FAILURE in the subject.\n");
2216 return 0;
2217}
2218
2219/* FIXME: Should this be identical to board_flash_enable? */
2220static int board_handle_phase(enum board_match_phase phase)
2221{
2222 const struct board_pciid_enable *board = NULL;
2223
2224 board = board_match_pci_card_ids(phase);
2225
2226 if (unsafe_board_handler(board))
2227 board = NULL;
2228
2229 if (!board)
2230 return 0;
2231
2232 if (!board->enable) {
2233 /* Not sure if there is a valid case for this. */
2234 msg_perr("Board match found, but nothing to do?\n");
2235 return 0;
2236 }
2237
2238 return board->enable();
2239}
2240
2241void board_handle_before_superio(void)
2242{
2243 board_handle_phase(P1);
2244}
2245
2246void board_handle_before_laptop(void)
2247{
2248 board_handle_phase(P2);
2249}
2250
Uwe Hermann372eeb52007-12-04 21:49:06 +00002251int board_flash_enable(const char *vendor, const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002252{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +00002253 const struct board_pciid_enable *board = NULL;
Uwe Hermanna7e05482007-05-09 10:17:44 +00002254 int ret = 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002255
Peter Stuge6b53fed2008-01-27 16:21:21 +00002256 if (part)
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +00002257 board = board_match_coreboot_name(vendor, part);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002258
Uwe Hermanna7e05482007-05-09 10:17:44 +00002259 if (!board)
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002260 board = board_match_pci_card_ids(P3);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002261
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002262 if (unsafe_board_handler(board))
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002263 board = NULL;
Michael Karcher7f0c3ec2010-03-07 22:29:28 +00002264
Uwe Hermanna7e05482007-05-09 10:17:44 +00002265 if (board) {
Luc Verhaegen93938c32010-01-20 14:45:03 +00002266 if (board->max_rom_decode_parallel)
2267 max_rom_decode.parallel =
2268 board->max_rom_decode_parallel * 1024;
2269
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00002270 if (board->enable != NULL) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002271 msg_pinfo("Disabling flash write protection for "
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002272 "board \"%s %s\"... ", board->vendor_name,
2273 board->board_name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002274
Uwe Hermann36dec8b2010-06-07 19:06:26 +00002275 ret = board->enable();
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00002276 if (ret)
Sean Nelson316a29f2010-05-07 20:09:04 +00002277 msg_pinfo("FAILED!\n");
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00002278 else
Sean Nelson316a29f2010-05-07 20:09:04 +00002279 msg_pinfo("OK.\n");
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00002280 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00002281 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002282
Uwe Hermanna7e05482007-05-09 10:17:44 +00002283 return ret;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002284}