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Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
5 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +00006 * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
Carl-Daniel Hailfinger92242622007-09-27 14:29:57 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00008 *
Uwe Hermannd1107642007-08-29 17:52:32 +00009 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000012 *
Uwe Hermannd1107642007-08-29 17:52:32 +000013 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000021 */
22
23/*
24 * Contains the board specific flash enables.
25 */
26
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000027#include <string.h>
Stefan Taunerb4e06bd2012-08-20 00:24:22 +000028#include <stdlib.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000029#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000030#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000031#include "hwaccess.h"
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000032
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000033#if defined(__i386__) || defined(__x86_64__)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000034/*
Uwe Hermannffec5f32007-08-23 16:08:21 +000035 * Helper functions for many Winbond Super I/Os of the W836xx range.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000036 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000037/* Enter extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000038void w836xx_ext_enter(uint16_t port)
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000039{
Andriy Gapon65c1b862008-05-22 13:22:45 +000040 OUTB(0x87, port);
41 OUTB(0x87, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000042}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000043
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000044/* Leave extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000045void w836xx_ext_leave(uint16_t port)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000046{
Andriy Gapon65c1b862008-05-22 13:22:45 +000047 OUTB(0xAA, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000048}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000049
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000050/* Generic Super I/O helper functions */
51uint8_t sio_read(uint16_t port, uint8_t reg)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000052{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000053 OUTB(reg, port);
54 return INB(port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000055}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000056
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000057void sio_write(uint16_t port, uint8_t reg, uint8_t data)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000058{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000059 OUTB(reg, port);
60 OUTB(data, port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000061}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000062
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000063void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000064{
Ronald G. Minnichfa496922007-10-12 21:22:40 +000065 uint8_t tmp;
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000066
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000067 OUTB(reg, port);
68 tmp = INB(port + 1) & ~mask;
69 OUTB(tmp | (data & mask), port + 1);
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000070}
71
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +000072/* Winbond W83697 documentation indicates that the index register has to be written for each access. */
73void sio_mask_alzheimer(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
74{
75 uint8_t tmp;
76
77 OUTB(reg, port);
78 tmp = INB(port + 1) & ~mask;
79 OUTB(reg, port);
80 OUTB(tmp | (data & mask), port + 1);
81}
82
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000083/* Not used yet. */
84#if 0
85static int enable_flash_decode_superio(void)
86{
87 int ret;
88 uint8_t tmp;
89
90 switch (superio.vendor) {
91 case SUPERIO_VENDOR_NONE:
92 ret = -1;
93 break;
94 case SUPERIO_VENDOR_ITE:
95 enter_conf_mode_ite(superio.port);
Uwe Hermann43959702010-03-13 17:28:29 +000096 /* Enable flash mapping. Works for most old ITE style Super I/O. */
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000097 tmp = sio_read(superio.port, 0x24);
98 tmp |= 0xfc;
99 sio_write(superio.port, 0x24, tmp);
100 exit_conf_mode_ite(superio.port);
101 ret = 0;
102 break;
103 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000104 msg_pdbg("Unhandled Super I/O type!\n");
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +0000105 ret = -1;
106 break;
107 }
108 return ret;
109}
110#endif
111
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000112/*
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000113 * SMSC FDC37B787: Raise GPIO50
114 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000115static int fdc37b787_gpio50_raise(uint16_t port)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000116{
117 uint8_t id, val;
118
119 OUTB(0x55, port); /* enter conf mode */
120 id = sio_read(port, 0x20);
121 if (id != 0x44) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000122 msg_perr("\nERROR: FDC37B787: Wrong ID 0x%02X.\n", id);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000123 OUTB(0xAA, port); /* leave conf mode */
124 return -1;
125 }
126
127 sio_write(port, 0x07, 0x08); /* Select Aux I/O subdevice */
128
129 val = sio_read(port, 0xC8); /* GP50 */
130 if ((val & 0x1B) != 0x10) /* output, no invert, GPIO */
131 {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000132 msg_perr("\nERROR: GPIO50 mode 0x%02X unexpected.\n", val);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000133 OUTB(0xAA, port);
134 return -1;
135 }
136
137 sio_mask(port, 0xF9, 0x01, 0x01);
138
139 OUTB(0xAA, port); /* Leave conf mode */
140 return 0;
141}
142
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000143/*
144 * Suited for:
145 * - Nokia IP530: Intel 440BX + PIIX4 + FDC37B787
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000146 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000147static int fdc37b787_gpio50_raise_3f0(void)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000148{
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000149 return fdc37b787_gpio50_raise(0x3f0);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000150}
151
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000152struct winbond_mux {
153 uint8_t reg; /* 0 if the corresponding pin is not muxed */
154 uint8_t data; /* reg/data/mask may be directly ... */
155 uint8_t mask; /* ... passed to sio_mask */
156};
157
158struct winbond_port {
159 const struct winbond_mux *mux; /* NULL or pointer to mux info for the 8 bits */
160 uint8_t ldn; /* LDN this GPIO register is located in */
161 uint8_t enable_bit; /* bit in 0x30 of that LDN to enable
162 the GPIO port */
163 uint8_t base; /* base register in that LDN for the port */
164};
165
166struct winbond_chip {
167 uint8_t device_id; /* reg 0x20 of the expected w83626x */
168 uint8_t gpio_port_count;
169 const struct winbond_port *port;
170};
171
172
173#define UNIMPLEMENTED_PORT {NULL, 0, 0, 0}
174
175enum winbond_id {
176 WINBOND_W83627HF_ID = 0x52,
Michael Karcherea36c9c2010-06-27 15:07:52 +0000177 WINBOND_W83627EHF_ID = 0x88,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000178 WINBOND_W83627THF_ID = 0x82,
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000179 WINBOND_W83697HF_ID = 0x60,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000180};
181
182static const struct winbond_mux w83627hf_port2_mux[8] = {
183 {0x2A, 0x01, 0x01}, /* or MIDI */
184 {0x2B, 0x80, 0x80}, /* or SPI */
185 {0x2B, 0x40, 0x40}, /* or SPI */
186 {0x2B, 0x20, 0x20}, /* or power LED */
187 {0x2B, 0x10, 0x10}, /* or watchdog */
188 {0x2B, 0x08, 0x08}, /* or infra red */
189 {0x2B, 0x04, 0x04}, /* or infra red */
190 {0x2B, 0x03, 0x03} /* or IRQ1 input */
191};
192
193static const struct winbond_port w83627hf[3] = {
194 UNIMPLEMENTED_PORT,
195 {w83627hf_port2_mux, 0x08, 0, 0xF0},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000196 UNIMPLEMENTED_PORT,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000197};
198
Michael Karcherea36c9c2010-06-27 15:07:52 +0000199static const struct winbond_mux w83627ehf_port2_mux[8] = {
200 {0x29, 0x06, 0x02}, /* or MIDI */
201 {0x29, 0x06, 0x02},
202 {0x24, 0x02, 0x00}, /* or SPI ROM interface */
203 {0x24, 0x02, 0x00},
204 {0x2A, 0x01, 0x01}, /* or keyboard/mouse interface */
205 {0x2A, 0x01, 0x01},
206 {0x2A, 0x01, 0x01},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000207 {0x2A, 0x01, 0x01},
Michael Karcherea36c9c2010-06-27 15:07:52 +0000208};
209
210static const struct winbond_port w83627ehf[6] = {
211 UNIMPLEMENTED_PORT,
212 {w83627ehf_port2_mux, 0x09, 0, 0xE3},
213 UNIMPLEMENTED_PORT,
214 UNIMPLEMENTED_PORT,
215 UNIMPLEMENTED_PORT,
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000216 UNIMPLEMENTED_PORT,
Michael Karcherea36c9c2010-06-27 15:07:52 +0000217};
218
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000219static const struct winbond_mux w83627thf_port4_mux[8] = {
220 {0x2D, 0x01, 0x01}, /* or watchdog or VID level strap */
221 {0x2D, 0x02, 0x02}, /* or resume reset */
222 {0x2D, 0x04, 0x04}, /* or S3 input */
223 {0x2D, 0x08, 0x08}, /* or PSON# */
224 {0x2D, 0x10, 0x10}, /* or PWROK */
225 {0x2D, 0x20, 0x20}, /* or suspend LED */
226 {0x2D, 0x40, 0x40}, /* or panel switch input */
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000227 {0x2D, 0x80, 0x80}, /* or panel switch output */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000228};
229
230static const struct winbond_port w83627thf[5] = {
231 UNIMPLEMENTED_PORT, /* GPIO1 */
232 UNIMPLEMENTED_PORT, /* GPIO2 */
233 UNIMPLEMENTED_PORT, /* GPIO3 */
234 {w83627thf_port4_mux, 0x09, 1, 0xF4},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000235 UNIMPLEMENTED_PORT, /* GPIO5 */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000236};
237
238static const struct winbond_chip winbond_chips[] = {
239 {WINBOND_W83627HF_ID, ARRAY_SIZE(w83627hf), w83627hf },
Michael Karcherea36c9c2010-06-27 15:07:52 +0000240 {WINBOND_W83627EHF_ID, ARRAY_SIZE(w83627ehf), w83627ehf},
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000241 {WINBOND_W83627THF_ID, ARRAY_SIZE(w83627thf), w83627thf},
242};
243
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000244#define WINBOND_SUPERIO_PORT1 0x2e
245#define WINBOND_SUPERIO_PORT2 0x4e
246
247/* We don't really care about the hardware monitor, but it offers better (more specific) device ID info than
248 * the simple device ID in the normal configuration registers.
249 * Note: This function expects to be called while the Super I/O is in config mode.
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000250 */
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000251static uint8_t w836xx_deviceid_hwmon(uint16_t sio_port)
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000252{
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000253 uint16_t hwmport;
254 uint16_t hwm_vendorid;
255 uint8_t hwm_deviceid;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000256
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000257 sio_write(sio_port, 0x07, 0x0b); /* Select LDN 0xb (HWM). */
258 if ((sio_read(sio_port, 0x30) & (1 << 0)) != (1 << 0)) {
259 msg_pinfo("W836xx hardware monitor disabled or does not exist.\n");
260 return 0;
261 }
262 /* Get HWM base address (stored in LDN 0xb, index 0x60/0x61). */
263 hwmport = sio_read(sio_port, 0x60) << 8;
264 hwmport |= sio_read(sio_port, 0x61);
265 /* HWM address register = HWM base address + 5. */
266 hwmport += 5;
267 msg_pdbg2("W836xx Hardware Monitor at port %04x\n", hwmport);
268 /* FIXME: This busy check should happen before each HWM access. */
269 if (INB(hwmport) & 0x80) {
270 msg_pinfo("W836xx hardware monitor busy, ignoring it.\n");
271 return 0;
272 }
273 /* Set HBACS=1. */
274 sio_mask_alzheimer(hwmport, 0x4e, 0x80, 0x80);
275 /* Read upper byte of vendor ID. */
276 hwm_vendorid = sio_read(hwmport, 0x4f) << 8;
277 /* Set HBACS=0. */
278 sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x80);
279 /* Read lower byte of vendor ID. */
280 hwm_vendorid |= sio_read(hwmport, 0x4f);
281 if (hwm_vendorid != 0x5ca3) {
282 msg_pinfo("W836xx hardware monitor vendor ID weirdness: expected 0x5ca3, got %04x\n",
283 hwm_vendorid);
284 return 0;
285 }
286 /* Set Bank=0. */
287 sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x07);
288 /* Read "chip" ID. We call this one the device ID. */
289 hwm_deviceid = sio_read(hwmport, 0x58);
290 return hwm_deviceid;
291}
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000292
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000293void probe_superio_winbond(void)
294{
295 struct superio s = {};
296 uint16_t winbond_ports[] = {WINBOND_SUPERIO_PORT1, WINBOND_SUPERIO_PORT2, 0};
297 uint16_t *i = winbond_ports;
298 uint8_t model;
299 uint8_t tmp;
300
301 s.vendor = SUPERIO_VENDOR_WINBOND;
302 for (; *i; i++) {
303 s.port = *i;
304 /* If we're already in Super I/O config more, the W836xx enter sequence won't hurt. */
305 w836xx_ext_enter(s.port);
306 model = sio_read(s.port, 0x20);
307 /* No response, no point leaving the config mode. */
308 if (model == 0xff)
309 continue;
310 /* Try to leave config mode. If the ID register is still readable, it's not a Winbond chip. */
311 w836xx_ext_leave(s.port);
312 if (model == sio_read(s.port, 0x20)) {
313 msg_pdbg("W836xx enter config mode worked or we were already in config mode. W836xx "
314 "leave config mode had no effect.\n");
315 if (model == 0x87) {
316 /* ITE IT8707F and IT8710F are special: They need the W837xx enter sequence,
317 * but they want the ITE exit sequence. Handle them here.
318 */
319 tmp = sio_read(s.port, 0x21);
320 switch (tmp) {
321 case 0x07:
322 case 0x10:
323 s.vendor = SUPERIO_VENDOR_ITE;
324 s.model = (0x87 << 8) | tmp ;
325 msg_pdbg("Found ITE Super I/O, ID 0x%04hx on port "
326 "0x%x\n", s.model, s.port);
327 register_superio(s);
328 /* Exit ITE config mode. */
329 exit_conf_mode_ite(s.port);
330 /* Restore vendor for next loop iteration. */
331 s.vendor = SUPERIO_VENDOR_WINBOND;
332 continue;
333 }
334 }
335 msg_pinfo("Active config mode, unknown reg 0x20 ID: %02x.\n", model);
336 msg_pinfo("Please send the output of \"flashrom -V\" to \n"
337 "flashrom@flashrom.org with W836xx: your board name: flashrom -V\n"
338 "as the subject to help us finish support for your Super I/O. Thanks.\n");
339 continue;
340 }
341 /* The Super I/O reacts to W836xx enter and exit config mode, it's probably Winbond. */
342 w836xx_ext_enter(s.port);
343 s.model = sio_read(s.port, 0x20);
344 switch (s.model) {
345 case WINBOND_W83627HF_ID:
346 case WINBOND_W83627EHF_ID:
347 case WINBOND_W83627THF_ID:
348 msg_pdbg("Found Winbond Super I/O, id %02hx\n", s.model);
349 register_superio(s);
350 break;
351 case WINBOND_W83697HF_ID:
352 /* This code is extremely paranoid. */
353 tmp = sio_read(s.port, 0x26) & 0x40;
354 if (((tmp == 0x00) && (s.port != WINBOND_SUPERIO_PORT1)) ||
355 ((tmp == 0x40) && (s.port != WINBOND_SUPERIO_PORT2))) {
356 msg_pdbg("Winbond Super I/O probe weirdness: Port mismatch for ID "
357 "%02x at port %04x\n", s.model, s.port);
358 break;
359 }
360 tmp = w836xx_deviceid_hwmon(s.port);
361 /* FIXME: This might be too paranoid... */
362 if (!tmp) {
363 msg_pdbg("Probably not a Winbond Super I/O\n");
364 break;
365 }
366 if (tmp != s.model) {
367 msg_pinfo("W83 series hardware monitor device ID weirdness: expected %02x, "
368 "got %02x\n", WINBOND_W83697HF_ID, tmp);
369 break;
370 }
371 msg_pinfo("Found Winbond Super I/O, id %02hx\n", s.model);
372 register_superio(s);
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000373 break;
374 }
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000375 w836xx_ext_leave(s.port);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000376 }
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000377 return;
378}
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000379
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000380static const struct winbond_chip *winbond_superio_chipdef(void)
381{
382 int i, j;
383
384 for (i = 0; i < superio_count; i++) {
385 if (superios[i].vendor != SUPERIO_VENDOR_WINBOND)
386 continue;
387 for (j = 0; j < ARRAY_SIZE(winbond_chips); j++)
388 if (winbond_chips[j].device_id == superios[i].model)
389 return &winbond_chips[j];
390 }
391 return NULL;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000392}
393
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000394/*
395 * The chipid parameter goes away as soon as we have Super I/O matching in the
396 * board enable table. The call to winbond_superio_detect() goes away as
397 * soon as we have generic Super I/O detection code.
398 */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000399static int winbond_gpio_set(uint16_t base, enum winbond_id chipid,
400 int pin, int raise)
401{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000402 const struct winbond_chip *chip = NULL;
403 const struct winbond_port *gpio;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000404 int port = pin / 10;
405 int bit = pin % 10;
406
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000407 chip = winbond_superio_chipdef();
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000408 if (!chip) {
409 msg_perr("\nERROR: No supported Winbond Super I/O found\n");
410 return -1;
411 }
Michael Karcher979d9252010-06-29 14:44:40 +0000412 if (chip->device_id != chipid) {
413 msg_perr("\nERROR: Found Winbond chip with ID 0x%x, "
414 "expected %x\n", chip->device_id, chipid);
415 return -1;
416 }
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000417 if (bit >= 8 || port == 0 || port > chip->gpio_port_count) {
418 msg_perr("\nERROR: winbond_gpio_set: Invalid GPIO number %d\n",
419 pin);
420 return -1;
421 }
422
423 gpio = &chip->port[port - 1];
424
425 if (gpio->ldn == 0) {
426 msg_perr("\nERROR: GPIO%d is not supported yet on this"
427 " winbond chip\n", port);
428 return -1;
429 }
430
431 w836xx_ext_enter(base);
432
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000433 /* Select logical device. */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000434 sio_write(base, 0x07, gpio->ldn);
435
436 /* Activate logical device. */
437 sio_mask(base, 0x30, 1 << gpio->enable_bit, 1 << gpio->enable_bit);
438
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000439 /* Select GPIO function of that pin. */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000440 if (gpio->mux && gpio->mux[bit].reg)
441 sio_mask(base, gpio->mux[bit].reg,
442 gpio->mux[bit].data, gpio->mux[bit].mask);
443
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000444 sio_mask(base, gpio->base + 0, 0, 1 << bit); /* Make pin output */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000445 sio_mask(base, gpio->base + 2, 0, 1 << bit); /* Clear inversion */
446 sio_mask(base, gpio->base + 1, raise << bit, 1 << bit);
447
448 w836xx_ext_leave(base);
449
450 return 0;
451}
452
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000453/*
Uwe Hermannffec5f32007-08-23 16:08:21 +0000454 * Winbond W83627HF: Raise GPIO24.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000455 *
456 * Suited for:
Uwe Hermannffec5f32007-08-23 16:08:21 +0000457 * - Agami Aruma
458 * - IWILL DK8-HTX
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000459 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000460static int w83627hf_gpio24_raise_2e(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000461{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000462 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 24, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000463}
464
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000465/*
Joshua Roysf280a382010-08-07 21:49:11 +0000466 * Winbond W83627HF: Raise GPIO25.
467 *
468 * Suited for:
469 * - MSI MS-6577
470 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000471static int w83627hf_gpio25_raise_2e(void)
Joshua Roysf280a382010-08-07 21:49:11 +0000472{
473 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 25, 1);
474}
475
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000476/*
Stefan Taunerff80e682011-07-20 16:34:18 +0000477 * Winbond W83627EHF: Raise GPIO22.
Michael Karcherea36c9c2010-06-27 15:07:52 +0000478 *
479 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000480 * - ASUS A8N-VM CSM: AMD Socket 939 + GeForce 6150 (C51) + MCP51
Michael Karcherea36c9c2010-06-27 15:07:52 +0000481 */
Stefan Taunerff80e682011-07-20 16:34:18 +0000482static int w83627ehf_gpio22_raise_2e(void)
Michael Karcherea36c9c2010-06-27 15:07:52 +0000483{
Stefan Taunerff80e682011-07-20 16:34:18 +0000484 return winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, 22, 1);
Michael Karcherea36c9c2010-06-27 15:07:52 +0000485}
486
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000487/*
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000488 * Winbond W83627THF: Raise GPIO 44.
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000489 *
490 * Suited for:
Peter Stugecce26822008-07-21 17:48:40 +0000491 * - MSI K8T Neo2-F
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000492 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000493static int w83627thf_gpio44_raise_2e(void)
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000494{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000495 return winbond_gpio_set(0x2e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000496}
497
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000498/*
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000499 * Winbond W83627THF: Raise GPIO 44.
500 *
501 * Suited for:
502 * - MSI K8N Neo3
503 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000504static int w83627thf_gpio44_raise_4e(void)
Peter Stugecce26822008-07-21 17:48:40 +0000505{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000506 return winbond_gpio_set(0x4e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000507}
Uwe Hermann372eeb52007-12-04 21:49:06 +0000508
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000509/*
David Borgb6417a62010-08-02 08:29:34 +0000510 * Enable MEMW# and set ROM size to max.
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000511 * Supported chips: W83L517D, W83697HF/F/HG, W83697SF/UF/UG
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000512 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000513static void w836xx_memw_enable(uint16_t port)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000514{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000515 w836xx_ext_enter(port);
516 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000517 /* Enable MEMW# and set ROM size select to max. (4M). */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000518 sio_mask(port, 0x24, 0x28, 0x28);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000519 }
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000520 w836xx_ext_leave(port);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000521}
522
David Borgb02c62b2012-05-05 20:43:42 +0000523/**
524 * Enable MEMW# and set ROM size to max.
525 * Supported chips:
526 * W83697HF/F/HG, W83697SF/UF/UG
527 */
528void w83697xx_memw_enable(uint16_t port)
529{
530 w836xx_ext_enter(port);
531 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
532 if((sio_read(port, 0x2A) & 0xF0) == 0xF0) {
533
534 /* CR24 Bits 7 & 2 must be set to 0 enable the flash ROM */
535 /* address segments 000E0000h ~ 000FFFFFh on W83697SF/UF/UG */
536 /* These bits are reserved on W83697HF/F/HG */
537 /* Shouldn't be needed though. */
538
539 /* CR28 Bit3 must be set to 1 to enable flash access to */
540 /* FFE80000h ~ FFEFFFFFh on W83697SF/UF/UG. */
541 /* This bit is reserved on W83697HF/F/HG which default to 0 */
542 sio_mask(port, 0x28, 0x08, 0x08);
543
544 /* Enable MEMW# and set ROM size select to max. (4M)*/
545 sio_mask(port, 0x24, 0x28, 0x38);
546
547 } else {
548 msg_perr("WARNING: Flash interface in use by GPIO!\n");
549 }
550 } else {
551 msg_pinfo("BIOS ROM is disabled\n");
552 }
553 w836xx_ext_leave(port);
554}
555
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000556/*
Luc Verhaegen73d21192009-12-23 00:54:26 +0000557 * Suited for:
Stefan Taunerb6304c12012-08-09 23:25:27 +0000558 * - Biostar M7VIQ: VIA KM266 + VT8235
559 */
560static int w83697xx_memw_enable_2e(void)
561{
562 w83697xx_memw_enable(0x2E);
563
564 return 0;
565}
566
567
568/*
569 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000570 * - EPoX EP-8K5A2: VIA KT333 + VT8235
571 * - Albatron PM266A Pro: VIA P4M266A + VT8235
572 * - Shuttle AK31 (all versions): VIA KT266 + VT8233
573 * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
574 * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237
Mattias Mattssone295eee2010-08-15 10:21:29 +0000575 * - MSI KM4M-V and KM4AM-V: VIA KM400/KM400A + VT8237
Mattias Mattssone8388242010-09-11 15:25:48 +0000576 * - MSI MS-6561 (745 Ultra): SiS 745 + W83697HF
Sergey A Lichackf3a4bff2010-09-07 18:14:53 +0000577 * - MSI MS-6787 (P4MAM-V/P4MAM-L): VIA P4M266 + VT8235
Uwe Hermann17da61e2010-10-05 21:48:43 +0000578 * - ASRock K7S41: SiS 741 + SiS 963 + W83697HF
Pawel Rozanski1d233072011-06-19 16:52:48 +0000579 * - ASRock K7S41GX: SiS 741GX + SiS 963L + W83697HF
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000580 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000581static int w836xx_memw_enable_2e(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000582{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000583 w836xx_memw_enable(0x2E);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000584
Luc Verhaegen73d21192009-12-23 00:54:26 +0000585 return 0;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000586}
587
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000588/*
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000589 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000590 * - Termtek TK-3370 (rev. 2.5b)
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000591 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000592static int w836xx_memw_enable_4e(void)
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000593{
594 w836xx_memw_enable(0x4E);
595
596 return 0;
597}
598
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000599/*
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000600 * Suited for all boards with ITE IT8705F.
601 * The SIS950 Super I/O probably requires a similar flash write enable.
Luc Verhaegen21f54962010-01-20 14:45:07 +0000602 */
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000603int it8705f_write_enable(uint8_t port)
Luc Verhaegen21f54962010-01-20 14:45:07 +0000604{
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000605 uint8_t tmp;
606 int ret = 0;
607
Luc Verhaegen21f54962010-01-20 14:45:07 +0000608 enter_conf_mode_ite(port);
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000609 tmp = sio_read(port, 0x24);
610 /* Check if at least one flash segment is enabled. */
611 if (tmp & 0xf0) {
612 /* The IT8705F will respond to LPC cycles and translate them. */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000613 internal_buses_supported = BUS_PARALLEL;
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000614 /* Flash ROM I/F Writes Enable */
615 tmp |= 0x04;
616 msg_pdbg("Enabling IT8705F flash ROM interface write.\n");
617 if (tmp & 0x02) {
618 /* The data sheet contradicts itself about max size. */
619 max_rom_decode.parallel = 1024 * 1024;
620 msg_pinfo("IT8705F with very unusual settings. Please "
621 "send the output of \"flashrom -V\" to \n"
Paul Menzelab6328f2010-10-08 11:03:02 +0000622 "flashrom@flashrom.org with "
623 "IT8705: your board name: flashrom -V\n"
624 "as the subject to help us finish "
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000625 "support for your Super I/O. Thanks.\n");
626 ret = 1;
627 } else if (tmp & 0x08) {
628 max_rom_decode.parallel = 512 * 1024;
629 } else {
630 max_rom_decode.parallel = 256 * 1024;
631 }
632 /* Safety checks. The data sheet is unclear here: Segments 1+3
633 * overlap, no segment seems to cover top - 1MB to top - 512kB.
634 * We assume that certain combinations make no sense.
635 */
636 if (((tmp & 0x02) && !(tmp & 0x08)) || /* 1 MB en, 512 kB dis */
637 (!(tmp & 0x10)) || /* 128 kB dis */
638 (!(tmp & 0x40))) { /* 256/512 kB dis */
639 msg_perr("Inconsistent IT8705F decode size!\n");
640 ret = 1;
641 }
642 if (sio_read(port, 0x25) != 0) {
643 msg_perr("IT8705F flash data pins disabled!\n");
644 ret = 1;
645 }
646 if (sio_read(port, 0x26) != 0) {
647 msg_perr("IT8705F flash address pins 0-7 disabled!\n");
648 ret = 1;
649 }
650 if (sio_read(port, 0x27) != 0) {
651 msg_perr("IT8705F flash address pins 8-15 disabled!\n");
652 ret = 1;
653 }
654 if ((sio_read(port, 0x29) & 0x10) != 0) {
655 msg_perr("IT8705F flash write enable pin disabled!\n");
656 ret = 1;
657 }
658 if ((sio_read(port, 0x29) & 0x08) != 0) {
659 msg_perr("IT8705F flash chip select pin disabled!\n");
660 ret = 1;
661 }
662 if ((sio_read(port, 0x29) & 0x04) != 0) {
663 msg_perr("IT8705F flash read strobe pin disabled!\n");
664 ret = 1;
665 }
666 if ((sio_read(port, 0x29) & 0x03) != 0) {
667 msg_perr("IT8705F flash address pins 16-17 disabled!\n");
668 /* Not really an error if you use flash chips smaller
669 * than 256 kByte, but such a configuration is unlikely.
670 */
671 ret = 1;
672 }
673 msg_pdbg("Maximum IT8705F parallel flash decode size is %u.\n",
674 max_rom_decode.parallel);
675 if (ret) {
676 msg_pinfo("Not enabling IT8705F flash write.\n");
677 } else {
678 sio_write(port, 0x24, tmp);
679 }
680 } else {
681 msg_pdbg("No IT8705F flash segment enabled.\n");
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000682 ret = 0;
683 }
Luc Verhaegen21f54962010-01-20 14:45:07 +0000684 exit_conf_mode_ite(port);
685
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000686 return ret;
Luc Verhaegen21f54962010-01-20 14:45:07 +0000687}
Luc Verhaegen73d21192009-12-23 00:54:26 +0000688
Mattias Mattssonfb60cec2010-09-13 19:39:25 +0000689/*
690 * The ITE IT8707F is a custom chip made by ITE exclusively for ASUS.
691 * It uses the Winbond command sequence to enter extended configuration
692 * mode and the ITE sequence to exit.
693 *
694 * Registers seems similar to the ones on ITE IT8710F.
695 */
696static int it8707f_write_enable(uint8_t port)
697{
698 uint8_t tmp;
699
700 w836xx_ext_enter(port);
701
702 /* Set bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A rw */
703 tmp = sio_read(port, 0x23);
704 tmp |= (1 << 3);
705 sio_write(port, 0x23, tmp);
706
707 /* Set bit 2 (FLASH_WE) and bit 3 (FLASH_IF_EN) of reg 0x24 */
708 tmp = sio_read(port, 0x24);
709 tmp |= (1 << 2) | (1 << 3);
710 sio_write(port, 0x24, tmp);
711
712 /* Clear bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A ro */
713 tmp = sio_read(port, 0x23);
714 tmp &= ~(1 << 3);
715 sio_write(port, 0x23, tmp);
716
717 exit_conf_mode_ite(port);
718
719 return 0;
720}
721
722/*
723 * Suited for:
724 * - ASUS P4SC-E: SiS 651 + 962 + ITE IT8707F
725 */
726static int it8707f_write_enable_2e(void)
727{
728 return it8707f_write_enable(0x2e);
729}
730
Michael Karchercba52de2011-03-06 12:07:19 +0000731#define PC87360_ID 0xE1
732#define PC87364_ID 0xE4
733
734static int pc8736x_gpio_set(uint8_t chipid, uint8_t gpio, int raise)
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000735{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000736 static const int bankbase[] = {0, 4, 8, 10, 12};
737 int gpio_bank = gpio / 8;
738 int gpio_pin = gpio % 8;
739 uint16_t baseport;
740 uint8_t id, val;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000741
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000742 if (gpio_bank > 4) {
Michael Karchercba52de2011-03-06 12:07:19 +0000743 msg_perr("PC8736x: Invalid GPIO %d\n", gpio);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000744 return -1;
745 }
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000746
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000747 id = sio_read(0x2E, 0x20);
Michael Karchercba52de2011-03-06 12:07:19 +0000748 if (id != chipid) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000749 msg_perr("PC8736x: unexpected ID %02x (expected %02x)\n",
750 id, chipid);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000751 return -1;
752 }
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000753
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000754 sio_write(0x2E, 0x07, 0x07); /* Select GPIO device. */
755 baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
756 if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) {
757 msg_perr("PC87360: invalid GPIO base address %04x\n",
758 baseport);
759 return -1;
760 }
761 sio_mask (0x2E, 0x30, 0x01, 0x01); /* Enable logical device. */
762 sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin);
763 sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output. */
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000764
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000765 val = INB(baseport + bankbase[gpio_bank]);
766 if (raise)
767 val |= 1 << gpio_pin;
768 else
769 val &= ~(1 << gpio_pin);
770 OUTB(val, baseport + bankbase[gpio_bank]);
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000771
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000772 return 0;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000773}
774
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000775/*
776 * VIA VT823x: Set one of the GPIO pins.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000777 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000778static int via_vt823x_gpio_set(uint8_t gpio, int raise)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000779{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000780 struct pci_dev *dev;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000781 uint16_t base;
David Bartleyf58d3642009-12-09 07:53:01 +0000782 uint8_t val, bit, offset;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000783
Luc Verhaegen73d21192009-12-23 00:54:26 +0000784 dev = pci_dev_find_vendorclass(0x1106, 0x0601);
785 switch (dev->device_id) {
786 case 0x3177: /* VT8235 */
787 case 0x3227: /* VT8237R */
788 case 0x3337: /* VT8237A */
789 break;
790 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000791 msg_perr("\nERROR: VT823x ISA bridge not found.\n");
Luc Verhaegen73d21192009-12-23 00:54:26 +0000792 return -1;
793 }
794
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000795 if ((gpio >= 12) && (gpio <= 15)) {
796 /* GPIO12-15 -> output */
797 val = pci_read_byte(dev, 0xE4);
798 val |= 0x10;
799 pci_write_byte(dev, 0xE4, val);
800 } else if (gpio == 9) {
801 /* GPIO9 -> Output */
802 val = pci_read_byte(dev, 0xE4);
803 val |= 0x20;
804 pci_write_byte(dev, 0xE4, val);
David Bartleyf58d3642009-12-09 07:53:01 +0000805 } else if (gpio == 5) {
806 val = pci_read_byte(dev, 0xE4);
807 val |= 0x01;
808 pci_write_byte(dev, 0xE4, val);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000809 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000810 msg_perr("\nERROR: "
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000811 "VT823x GPIO%02d is not implemented.\n", gpio);
Luc Verhaegen73d21192009-12-23 00:54:26 +0000812 return -1;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000813 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000814
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000815 /* We need the I/O Base Address for this board's flash enable. */
816 base = pci_read_word(dev, 0x88) & 0xff80;
817
David Bartleyf58d3642009-12-09 07:53:01 +0000818 offset = 0x4C + gpio / 8;
819 bit = 0x01 << (gpio % 8);
820
821 val = INB(base + offset);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000822 if (raise)
823 val |= bit;
824 else
825 val &= ~bit;
David Bartleyf58d3642009-12-09 07:53:01 +0000826 OUTB(val, base + offset);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000827
Uwe Hermanna7e05482007-05-09 10:17:44 +0000828 return 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000829}
830
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000831/*
832 * Suited for:
833 * - ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000834 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000835static int via_vt823x_gpio5_raise(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000836{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000837 /* On M2V-MX: GPO5 is connected to WP# and TBL#. */
838 return via_vt823x_gpio_set(5, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000839}
840
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000841/*
842 * Suited for:
843 * - VIA EPIA EK & N & NL
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000844 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000845static int via_vt823x_gpio9_raise(void)
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000846{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000847 return via_vt823x_gpio_set(9, 1);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000848}
849
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000850/*
851 * Suited for:
852 * - VIA EPIA M and MII (and maybe other CLE266 based EPIAs)
Luc Verhaegen73d21192009-12-23 00:54:26 +0000853 *
854 * We don't need to do this for EPIA M when using coreboot, GPIO15 is never
855 * lowered there.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000856 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000857static int via_vt823x_gpio15_raise(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000858{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000859 return via_vt823x_gpio_set(15, 1);
860}
861
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000862/*
Luc Verhaegen73d21192009-12-23 00:54:26 +0000863 * Winbond W83697HF Super I/O + VIA VT8235 southbridge
864 *
865 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000866 * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
867 * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
Luc Verhaegen73d21192009-12-23 00:54:26 +0000868 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000869static int board_msi_kt4v(void)
Luc Verhaegen73d21192009-12-23 00:54:26 +0000870{
871 int ret;
872
873 ret = via_vt823x_gpio_set(12, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000874 w836xx_memw_enable(0x2E);
Luc Verhaegen97866082008-02-09 02:03:06 +0000875
Luc Verhaegen73d21192009-12-23 00:54:26 +0000876 return ret;
Luc Verhaegen97866082008-02-09 02:03:06 +0000877}
878
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000879/*
880 * Suited for:
881 * - ASUS P5A
Luc Verhaegen6b141752007-05-20 16:16:13 +0000882 *
883 * This is rather nasty code, but there's no way to do this cleanly.
884 * We're basically talking to some unknown device on SMBus, my guess
885 * is that it is the Winbond W83781D that lives near the DIP BIOS.
886 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000887static int board_asus_p5a(void)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000888{
889 uint8_t tmp;
890 int i;
891
892#define ASUSP5A_LOOP 5000
893
Andriy Gapon65c1b862008-05-22 13:22:45 +0000894 OUTB(0x00, 0xE807);
895 OUTB(0xEF, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000896
Andriy Gapon65c1b862008-05-22 13:22:45 +0000897 OUTB(0xFF, 0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000898
899 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000900 OUTB(0xE1, 0xFF);
901 if (INB(0xE800) & 0x04)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000902 break;
903 }
904
905 if (i == ASUSP5A_LOOP) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000906 msg_perr("Unable to contact device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000907 return -1;
908 }
909
Andriy Gapon65c1b862008-05-22 13:22:45 +0000910 OUTB(0x20, 0xE801);
911 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000912
Andriy Gapon65c1b862008-05-22 13:22:45 +0000913 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000914
915 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000916 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000917 if (tmp & 0x70)
918 break;
919 }
920
921 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000922 msg_perr("Failed to read device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000923 return -1;
924 }
925
Andriy Gapon65c1b862008-05-22 13:22:45 +0000926 tmp = INB(0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000927 tmp &= ~0x02;
928
Andriy Gapon65c1b862008-05-22 13:22:45 +0000929 OUTB(0x00, 0xE807);
930 OUTB(0xEE, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000931
Andriy Gapon65c1b862008-05-22 13:22:45 +0000932 OUTB(tmp, 0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000933
Andriy Gapon65c1b862008-05-22 13:22:45 +0000934 OUTB(0xFF, 0xE800);
935 OUTB(0xE1, 0xFF);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000936
Andriy Gapon65c1b862008-05-22 13:22:45 +0000937 OUTB(0x20, 0xE801);
938 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000939
Andriy Gapon65c1b862008-05-22 13:22:45 +0000940 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000941
942 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000943 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000944 if (tmp & 0x70)
945 break;
946 }
947
948 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000949 msg_perr("Failed to write to device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000950 return -1;
951 }
952
953 return 0;
954}
955
Luc Verhaegena7e30502009-12-09 11:39:02 +0000956/*
957 * Set GPIO lines in the Broadcom HT-1000 southbridge.
958 *
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000959 * It's not a Super I/O but it uses the same index/data port method.
Luc Verhaegena7e30502009-12-09 11:39:02 +0000960 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000961static int board_hp_dl145_g3_enable(void)
Luc Verhaegena7e30502009-12-09 11:39:02 +0000962{
963 /* GPIO 0 reg from PM regs */
964 /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
965 sio_mask(0xcd6, 0x44, 0x24, 0x24);
966
967 return 0;
968}
969
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +0000970/*
971 * Set GPIO lines in the Broadcom HT-1000 southbridge.
972 *
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000973 * It's not a Super I/O but it uses the same index/data port method.
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +0000974 */
975static int board_hp_dl165_g6_enable(void)
976{
977 /* Variant of DL145, with slightly different pin placement. */
978 sio_mask(0xcd6, 0x44, 0x80, 0x80); /* TBL# */
979 sio_mask(0xcd6, 0x46, 0x04, 0x04); /* WP# */
980
981 return 0;
982}
983
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000984static int board_ibm_x3455(void)
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000985{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000986 /* Raise GPIO13. */
Carl-Daniel Hailfinger500b4232009-06-01 21:30:42 +0000987 sio_mask(0xcd6, 0x45, 0x20, 0x20);
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000988
989 return 0;
990}
991
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000992/*
993 * Suited for:
994 * - Shuttle FN25 (SN25P): AMD S939 + NVIDIA CK804 (nForce4)
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000995 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000996static int board_shuttle_fn25(void)
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000997{
998 struct pci_dev *dev;
999
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001000 dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA bridge. */
Luc Verhaegen20fdce12009-10-21 12:05:50 +00001001 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001002 msg_perr("\nERROR: NVIDIA nForce4 ISA bridge not found.\n");
Luc Verhaegen20fdce12009-10-21 12:05:50 +00001003 return -1;
1004 }
1005
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001006 /* One of those bits seems to be connected to TBL#, but -ENOINFO. */
Luc Verhaegen20fdce12009-10-21 12:05:50 +00001007 pci_write_byte(dev, 0x92, 0);
1008
1009 return 0;
1010}
1011
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001012/*
Mattias Mattssonf4925162010-09-16 22:09:18 +00001013 * Suited for:
1014 * - Elitegroup GeForce6100SM-M: NVIDIA MCP61 + ITE IT8726F
1015 */
Mattias Mattssonf4925162010-09-16 22:09:18 +00001016static int board_ecs_geforce6100sm_m(void)
1017{
1018 struct pci_dev *dev;
1019 uint32_t tmp;
1020
1021 dev = pci_dev_find(0x10DE, 0x03EB); /* NVIDIA MCP61 SMBus. */
1022 if (!dev) {
1023 msg_perr("\nERROR: NVIDIA MCP61 SMBus not found.\n");
1024 return -1;
1025 }
1026
1027 tmp = pci_read_byte(dev, 0xE0);
1028 tmp &= ~(1 << 3);
1029 pci_write_byte(dev, 0xE0, tmp);
1030
1031 return 0;
1032}
1033
1034/*
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001035 * Very similar to AMD 8111 IO Hub.
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001036 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001037static int nvidia_mcp_gpio_set(int gpio, int raise)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001038{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001039 struct pci_dev *dev;
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001040 uint16_t base, devclass;
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001041 uint8_t tmp;
1042
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001043 if ((gpio < 0) || (gpio >= 0x40)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001044 msg_perr("\nERROR: unsupported GPIO: %d.\n", gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +00001045 return -1;
1046 }
1047
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001048 /* Check for the ISA bridge first. */
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001049 dev = pci_dev_find_vendorclass(0x10DE, 0x0601);
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001050 switch (dev->device_id) {
1051 case 0x0030: /* CK804 */
1052 case 0x0050: /* MCP04 */
1053 case 0x0060: /* MCP2 */
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001054 case 0x00E0: /* CK8 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001055 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +00001056 case 0x0260: /* MCP51 */
Michael Karcher242efd42011-03-06 12:09:05 +00001057 case 0x0261: /* MCP51 */
Joshua Roys6e48a022012-06-29 23:07:14 +00001058 case 0x0360: /* MCP55 */
Michael Karcher2ead2e22010-06-01 16:09:06 +00001059 case 0x0364: /* MCP55 */
1060 /* find SMBus controller on *this* southbridge */
1061 /* The infamous Tyan S2915-E has two south bridges; they are
1062 easily told apart from each other by the class of the
1063 LPC bridge, but have the same SMBus bridge IDs */
1064 if (dev->func != 0) {
1065 msg_perr("MCP LPC bridge at unexpected function"
1066 " number %d\n", dev->func);
1067 return -1;
1068 }
1069
Carl-Daniel Hailfinger44cd9ab2010-07-17 22:28:05 +00001070#if PCI_LIB_VERSION >= 0x020200
Michael Karcher2ead2e22010-06-01 16:09:06 +00001071 dev = pci_get_dev(pacc, dev->domain, dev->bus, dev->dev, 1);
Carl-Daniel Hailfinger44cd9ab2010-07-17 22:28:05 +00001072#else
1073 /* pciutils/libpci before version 2.2 is too old to support
1074 * PCI domains. Such old machines usually don't have domains
1075 * besides domain 0, so this is not a problem.
1076 */
1077 dev = pci_get_dev(pacc, dev->bus, dev->dev, 1);
1078#endif
Michael Karcher2ead2e22010-06-01 16:09:06 +00001079 if (!dev) {
1080 msg_perr("MCP SMBus controller could not be found\n");
1081 return -1;
1082 }
1083 devclass = pci_read_word(dev, PCI_CLASS_DEVICE);
1084 if (devclass != 0x0C05) {
1085 msg_perr("Unexpected device class %04x for SMBus"
1086 " controller\n", devclass);
1087 return -1;
1088 }
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001089 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +00001090 default:
Sean Nelson316a29f2010-05-07 20:09:04 +00001091 msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n");
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001092 return -1;
1093 }
1094
1095 base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */
1096 base += 0xC0;
1097
1098 tmp = INB(base + gpio);
1099 tmp &= ~0x0F; /* null lower nibble */
1100 tmp |= 0x04; /* gpio -> output. */
1101 if (raise)
1102 tmp |= 0x01;
1103 OUTB(tmp, base + gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +00001104
1105 return 0;
1106}
1107
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001108/*
1109 * Suited for:
Stefan Taunera9cbbac2011-08-07 13:17:20 +00001110 * - ASUS A8M2N-LA (HP OEM "NodusM3-GL8E"): NVIDIA MCP51
Sean Nelson0a247512010-08-15 14:36:18 +00001111 * - ASUS A8N-LA (HP OEM "Nagami-GL8E"): NVIDIA MCP51
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001112 * - ASUS M2NBP-VM CSM: NVIDIA MCP51
Michael Karcherb2184c12010-03-07 16:42:55 +00001113 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001114static int nvidia_mcp_gpio0_raise(void)
Michael Karcherb2184c12010-03-07 16:42:55 +00001115{
1116 return nvidia_mcp_gpio_set(0x00, 1);
1117}
1118
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001119/*
1120 * Suited for:
1121 * - abit KN8 Ultra: NVIDIA CK804
Sean Nelson92bc6bd2010-03-19 22:37:29 +00001122 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001123static int nvidia_mcp_gpio2_lower(void)
Sean Nelson92bc6bd2010-03-19 22:37:29 +00001124{
1125 return nvidia_mcp_gpio_set(0x02, 0);
1126}
1127
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001128/*
1129 * Suited for:
Michael Karcher2842db32011-04-14 23:14:27 +00001130 * - Foxconn 6150K8MD-8EKRSH: Socket 939 + NVIDIA MCP51
Uwe Hermannead705f2010-08-15 15:26:30 +00001131 * - MSI K8N Neo4: NVIDIA CK804. TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html.
1132 * - MSI K8NGM2-L: NVIDIA MCP51
Joshua Roys6e48a022012-06-29 23:07:14 +00001133 * - MSI K9N SLI: NVIDIA MCP55
Luc Verhaegen6c5f7332009-12-23 03:01:36 +00001134 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001135static int nvidia_mcp_gpio2_raise(void)
Luc Verhaegen6c5f7332009-12-23 03:01:36 +00001136{
1137 return nvidia_mcp_gpio_set(0x02, 1);
1138}
1139
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001140/*
1141 * Suited for:
Uwe Hermann83d349a2010-10-18 22:32:03 +00001142 * - EPoX EP-8NPA7I: Socket 754 + NVIDIA nForce4 4X
Jonathan Kollaschf8db9592010-10-15 23:02:15 +00001143 */
1144static int nvidia_mcp_gpio4_raise(void)
1145{
1146 return nvidia_mcp_gpio_set(0x04, 1);
1147}
1148
1149/*
1150 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001151 * - HP xw9400 (Tyan S2915-E OEM): Dual(!) NVIDIA MCP55
1152 *
1153 * Notes: a) There are two MCP55 chips, so also two SMBus bridges on that
1154 * board. We can't tell the SMBus logical devices apart, but we
1155 * can tell the LPC bridge functions apart.
1156 * We need to choose the SMBus bridge next to the LPC bridge with
1157 * ID 0x364 and the "LPC bridge" class.
1158 * b) #TBL is hardwired on that board to a pull-down. It can be
1159 * overridden by connecting the two solder points next to F2.
Michael Karcher2ead2e22010-06-01 16:09:06 +00001160 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001161static int nvidia_mcp_gpio5_raise(void)
Michael Karcher2ead2e22010-06-01 16:09:06 +00001162{
1163 return nvidia_mcp_gpio_set(0x05, 1);
1164}
1165
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001166/*
1167 * Suited for:
1168 * - abit NF7-S: NVIDIA CK804
Michael Karcher8f10d242010-04-11 21:01:06 +00001169 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001170static int nvidia_mcp_gpio8_raise(void)
Michael Karcher8f10d242010-04-11 21:01:06 +00001171{
1172 return nvidia_mcp_gpio_set(0x08, 1);
1173}
1174
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001175/*
1176 * Suited for:
Cristian Măgherușan-Stanciu9932c7b2011-07-07 19:56:58 +00001177 * - GIGABYTE GA-K8NS Pro-939: Socket 939 + NVIDIA nForce3 + CK8
Idwer Volleringd8a00a02011-06-13 16:58:54 +00001178 */
1179static int nvidia_mcp_gpio0a_raise(void)
1180{
1181 return nvidia_mcp_gpio_set(0x0a, 1);
1182}
1183
1184/*
1185 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001186 * - MSI K8N Neo2 Platinum: Socket 939 + nForce3 Ultra + CK8
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001187 */
Michael Karcher51825082010-06-12 23:14:03 +00001188static int nvidia_mcp_gpio0c_raise(void)
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001189{
1190 return nvidia_mcp_gpio_set(0x0c, 1);
1191}
1192
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001193/*
1194 * Suited for:
1195 * - abit NF-M2 nView: Socket AM2 + NVIDIA MCP51
Michael Karcherefd8af32010-07-24 22:50:54 +00001196 */
1197static int nvidia_mcp_gpio4_lower(void)
1198{
1199 return nvidia_mcp_gpio_set(0x04, 0);
1200}
1201
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001202/*
1203 * Suited for:
1204 * - ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001205 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001206static int nvidia_mcp_gpio10_raise(void)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001207{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001208 return nvidia_mcp_gpio_set(0x10, 1);
1209}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001210
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001211/*
1212 * Suited for:
1213 * - GIGABYTE GA-K8N-SLI: AMD socket 939 + NVIDIA CK804 + ITE IT8712F
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001214 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001215static int nvidia_mcp_gpio21_raise(void)
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001216{
1217 return nvidia_mcp_gpio_set(0x21, 0x01);
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001218}
1219
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001220/*
1221 * Suited for:
1222 * - EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001223 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001224static int nvidia_mcp_gpio31_raise(void)
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001225{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001226 return nvidia_mcp_gpio_set(0x31, 0x01);
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001227}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001228
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001229/*
1230 * Suited for:
Michael Karcher242efd42011-03-06 12:09:05 +00001231 * - GIGABYTE GA-K8N51GMF: Socket 754 + Geforce 6100 + MCP51
1232 * - GIGABYTE GA-K8N51GMF-9: Socket 939 + Geforce 6100 + MCP51
Joshua Roys2ee137f2010-09-07 17:52:09 +00001233 */
1234static int nvidia_mcp_gpio3b_raise(void)
1235{
1236 return nvidia_mcp_gpio_set(0x3b, 1);
1237}
1238
1239/*
1240 * Suited for:
Joshua Roysb992d342011-11-02 14:31:18 +00001241 * - Sun Ultra 40 M2: Dual Socket F (1207) + MCP55
1242 */
1243static int board_sun_ultra_40_m2(void)
1244{
1245 int ret;
1246 uint8_t reg;
1247 uint16_t base;
1248 struct pci_dev *dev;
1249
1250 ret = nvidia_mcp_gpio4_lower();
1251 if (ret)
1252 return ret;
1253
1254 dev = pci_dev_find(0x10de, 0x0364); /* NVIDIA MCP55 LPC bridge */
1255 if (!dev) {
1256 msg_perr("\nERROR: NVIDIA MCP55 LPC bridge not found.\n");
1257 return -1;
1258 }
1259
1260 base = pci_read_word(dev, 0xb4); /* some IO BAR? */
1261 if (!base)
1262 return -1;
1263
1264 reg = INB(base + 0x4b);
1265 reg |= 0x10;
1266 OUTB(reg, base + 0x4b);
1267
1268 return 0;
1269}
1270
1271/*
1272 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001273 * - Artec Group DBE61 and DBE62
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001274 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001275static int board_artecgroup_dbe6x(void)
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001276{
1277#define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001278#define DBE6x_PRI_BOOT_LOC_SHIFT 2
1279#define DBE6x_BOOT_OP_LATCHED_SHIFT 8
1280#define DBE6x_SEC_BOOT_LOC_SHIFT 10
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001281#define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT)
1282#define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT)
1283#define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT)
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001284#define DBE6x_BOOT_LOC_FLASH 2
1285#define DBE6x_BOOT_LOC_FWHUB 3
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001286
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001287 msr_t msr;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001288 unsigned long boot_loc;
1289
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001290 /* Geode only has a single core */
1291 if (setup_cpu_msr(0))
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001292 return -1;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001293
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001294 msr = rdmsr(DBE6x_MSR_DIVIL_BALL_OPTS);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001295
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001296 if ((msr.lo & (DBE6x_BOOT_OP_LATCHED)) ==
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001297 (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT))
1298 boot_loc = DBE6x_BOOT_LOC_FWHUB;
1299 else
1300 boot_loc = DBE6x_BOOT_LOC_FLASH;
1301
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001302 msr.lo &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC);
1303 msr.lo |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) |
Uwe Hermann394131e2008-10-18 21:14:13 +00001304 (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001305
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001306 wrmsr(DBE6x_MSR_DIVIL_BALL_OPTS, msr);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001307
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001308 cleanup_cpu_msr();
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001309
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001310 return 0;
1311}
1312
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001313/*
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001314 * Suited for:
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001315 * - ASUS A8AE-LE (Codename AmberineM; used in Compaq Presario 061)
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001316 * Datasheet(s) used:
1317 * - AMD document 43009 "AMD SB700/710/750 Register Reference Guide" rev. 1.00
1318 */
1319static int amd_sbxxx_gpio9_raise(void)
1320{
1321 struct pci_dev *dev;
1322 uint32_t reg;
1323
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001324 dev = pci_dev_find(0x1002, 0x4372); /* AMD SMBus controller */
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001325 if (!dev) {
1326 msg_perr("\nERROR: AMD SMBus Controller (0x4372) not found.\n");
1327 return -1;
1328 }
1329
1330 reg = pci_read_long(dev, 0xA8); /* GPIO_12_to_4_Cntrl CI_Reg: A8h-ABh */
1331 /* enable output (0: enable, 1: tristate):
1332 GPIO9 output enable is at bit 5 in 0xA9 */
1333 reg &= ~((uint32_t)1<<(8+5));
1334 /* raise:
1335 GPIO9 output register is at bit 5 in 0xA8 */
1336 reg |= (1<<5);
1337 pci_write_long(dev, 0xA8, reg);
1338
1339 return 0;
1340}
1341
1342/*
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001343 * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}.
Luc Verhaegenf5226912009-12-14 10:41:58 +00001344 */
1345static int intel_piix4_gpo_set(unsigned int gpo, int raise)
1346{
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001347 unsigned int gpo_byte, gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001348 struct pci_dev *dev;
1349 uint32_t tmp, base;
1350
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001351 /* GPO{0,8,27,28,30} are always available. */
1352 static const uint32_t nonmuxed_gpos = 0x58000101;
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001353
1354 static const struct {unsigned int reg, mask, value; } piix4_gpo[] = {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001355 {0},
1356 {0xB0, 0x0001, 0x0000}, /* GPO1... */
1357 {0xB0, 0x0001, 0x0000},
1358 {0xB0, 0x0001, 0x0000},
1359 {0xB0, 0x0001, 0x0000},
1360 {0xB0, 0x0001, 0x0000},
1361 {0xB0, 0x0001, 0x0000},
1362 {0xB0, 0x0001, 0x0000}, /* ...GPO7: GENCFG bit 0 */
1363 {0},
1364 {0xB0, 0x0100, 0x0000}, /* GPO9: GENCFG bit 8 */
1365 {0xB0, 0x0200, 0x0000}, /* GPO10: GENCFG bit 9 */
1366 {0xB0, 0x0400, 0x0000}, /* GPO11: GENCFG bit 10 */
1367 {0x4E, 0x0100, 0x0000}, /* GPO12... */
1368 {0x4E, 0x0100, 0x0000},
1369 {0x4E, 0x0100, 0x0000}, /* ...GPO14: XBCS bit 8 */
1370 {0xB2, 0x0002, 0x0002}, /* GPO15... */
1371 {0xB2, 0x0002, 0x0002}, /* ...GPO16: GENCFG bit 17 */
1372 {0xB2, 0x0004, 0x0004}, /* GPO17: GENCFG bit 18 */
1373 {0xB2, 0x0008, 0x0008}, /* GPO18: GENCFG bit 19 */
1374 {0xB2, 0x0010, 0x0010}, /* GPO19: GENCFG bit 20 */
1375 {0xB2, 0x0020, 0x0020}, /* GPO20: GENCFG bit 21 */
1376 {0xB2, 0x0040, 0x0040}, /* GPO21: GENCFG bit 22 */
1377 {0xB2, 0x1000, 0x1000}, /* GPO22... */
1378 {0xB2, 0x1000, 0x1000}, /* ...GPO23: GENCFG bit 28 */
1379 {0xB2, 0x2000, 0x2000}, /* GPO24: GENCFG bit 29 */
1380 {0xB2, 0x4000, 0x4000}, /* GPO25: GENCFG bit 30 */
1381 {0xB2, 0x8000, 0x8000}, /* GPO26: GENCFG bit 31 */
1382 {0},
1383 {0},
1384 {0x4E, 0x0100, 0x0000}, /* ...GPO29: XBCS bit 8 */
1385 {0}
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001386 };
1387
Luc Verhaegenf5226912009-12-14 10:41:58 +00001388 dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */
1389 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001390 msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +00001391 return -1;
1392 }
1393
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001394 /* Sanity check. */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001395 if (gpo > 30) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001396 msg_perr("\nERROR: Intel PIIX4 has no GPO%d.\n", gpo);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001397 return -1;
1398 }
1399
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001400 if ((((1 << gpo) & nonmuxed_gpos) == 0) &&
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001401 ((pci_read_word(dev, piix4_gpo[gpo].reg) & piix4_gpo[gpo].mask) !=
1402 piix4_gpo[gpo].value)) {
1403 msg_perr("\nERROR: PIIX4 GPO%d not programmed for output.\n", gpo);
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001404 return -1;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001405 }
1406
Luc Verhaegenf5226912009-12-14 10:41:58 +00001407 dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */
1408 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001409 msg_perr("\nERROR: Intel PIIX4 PM not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +00001410 return -1;
1411 }
1412
1413 /* PM IO base */
1414 base = pci_read_long(dev, 0x40) & 0x0000FFC0;
1415
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001416 gpo_byte = gpo >> 3;
1417 gpo_bit = gpo & 7;
1418 tmp = INB(base + 0x34 + gpo_byte); /* GPO register */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001419 if (raise)
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001420 tmp |= 0x01 << gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001421 else
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001422 tmp &= ~(0x01 << gpo_bit);
1423 OUTB(tmp, base + 0x34 + gpo_byte);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001424
1425 return 0;
1426}
1427
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001428/*
1429 * Suited for:
Joshua Roysd708fad2012-02-17 14:51:15 +00001430 * - ASUS OPLX-M
Mattias Mattsson85016b92010-09-01 01:21:34 +00001431 * - ASUS P2B-N
1432 */
1433static int intel_piix4_gpo18_lower(void)
1434{
1435 return intel_piix4_gpo_set(18, 0);
1436}
1437
1438/*
1439 * Suited for:
Mattias Mattssonc8ca3de2010-09-13 18:22:36 +00001440 * - MSI MS-6163 v2 (MS-6163 Pro): Intel 440BX + PIIX4E + Winbond W83977EF
1441 */
1442static int intel_piix4_gpo14_raise(void)
1443{
1444 return intel_piix4_gpo_set(14, 1);
1445}
1446
1447/*
1448 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001449 * - EPoX EP-BX3
Luc Verhaegenf5226912009-12-14 10:41:58 +00001450 */
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001451static int intel_piix4_gpo22_raise(void)
Luc Verhaegenf5226912009-12-14 10:41:58 +00001452{
1453 return intel_piix4_gpo_set(22, 1);
1454}
1455
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001456/*
1457 * Suited for:
Tim ter Laak4b933f02010-09-13 23:00:57 +00001458 * - abit BM6
1459 */
1460static int intel_piix4_gpo26_lower(void)
1461{
1462 return intel_piix4_gpo_set(26, 0);
1463}
1464
1465/*
1466 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001467 * - Intel SE440BX-2
Michael Karcher51cd0c92010-03-19 22:35:21 +00001468 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001469static int intel_piix4_gpo27_lower(void)
Michael Karcher51cd0c92010-03-19 22:35:21 +00001470{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001471 return intel_piix4_gpo_set(27, 0);
Michael Karcher51cd0c92010-03-19 22:35:21 +00001472}
1473
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001474/*
Mattias Mattsson2eaad632010-10-05 21:32:29 +00001475 * Suited for:
1476 * - Dell OptiPlex GX1
1477 */
1478static int intel_piix4_gpo30_lower(void)
1479{
1480 return intel_piix4_gpo_set(30, 0);
1481}
1482
1483/*
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001484 * Set a GPIO line on a given Intel ICH LPC controller.
Uwe Hermann93f66db2008-05-22 21:19:38 +00001485 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001486static int intel_ich_gpio_set(int gpio, int raise)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001487{
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001488 /* Table mapping the different Intel ICH LPC chipsets. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001489 static struct {
1490 uint16_t id;
1491 uint8_t base_reg;
1492 uint32_t bank0;
1493 uint32_t bank1;
1494 uint32_t bank2;
1495 } intel_ich_gpio_table[] = {
1496 {0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */
1497 {0x2420, 0x58, 0x0FE30000, 0, 0}, /* 82801AB (ICH0) */
1498 {0x2440, 0x58, 0x1BFF391B, 0, 0}, /* 82801BA (ICH2) */
1499 {0x244C, 0x58, 0x1A23399B, 0, 0}, /* 82801BAM (ICH2M) */
1500 {0x2450, 0x58, 0x1BFF0000, 0, 0}, /* 82801E (C-ICH) */
1501 {0x2480, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801CA (ICH3-S) */
1502 {0x248C, 0x58, 0x1A230000, 0x00000FFF, 0}, /* 82801CAM (ICH3-M) */
1503 {0x24C0, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801DB/DBL (ICH4/ICH4-L) */
1504 {0x24CC, 0x58, 0x1A030000, 0x00000FFF, 0}, /* 82801DBM (ICH4-M) */
1505 {0x24D0, 0x58, 0x1BFF0000, 0x00030305, 0}, /* 82801EB/ER (ICH5/ICH5R) */
1506 {0x2640, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FB/FR (ICH6/ICH6R) */
1507 {0x2641, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FBM (ICH6M) */
1508 {0x27B8, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GB/GR (ICH7 Family) */
1509 {0x27B9, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GBM (ICH7-M) */
1510 {0x27BD, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GHM (ICH7-M DH) */
1511 {0x2810, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HB/HR (ICH8/R) */
1512 {0x2811, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HBM (ICH8M-E) */
1513 {0x2812, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HH (ICH8DH) */
1514 {0x2814, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HO (ICH8DO) */
1515 {0x2815, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HEM (ICH8M) */
1516 {0x2912, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IH (ICH9DH) */
1517 {0x2914, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IO (ICH9DO) */
1518 {0x2916, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IR (ICH9R) */
1519 {0x2917, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IEM (ICH9M-E) */
1520 {0x2918, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IB (ICH9) */
1521 {0x2919, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IBM (ICH9M) */
1522 {0x3A14, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JDO (ICH10DO) */
1523 {0x3A16, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIR (ICH10R) */
1524 {0x3A18, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIB (ICH10) */
1525 {0x3A1A, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JD (ICH10D) */
1526 {0, 0, 0, 0, 0} /* end marker */
1527 };
Uwe Hermann93f66db2008-05-22 21:19:38 +00001528
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001529 struct pci_dev *dev;
1530 uint16_t base;
1531 uint32_t tmp;
1532 int i, allowed;
1533
1534 /* First, look for a known LPC bridge */
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001535 for (dev = pacc->devices; dev; dev = dev->next) {
Carl-Daniel Hailfingerd175e062010-05-21 23:00:56 +00001536 uint16_t device_class;
1537 /* libpci before version 2.2.4 does not store class info. */
1538 device_class = pci_read_word(dev, PCI_CLASS_DEVICE);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001539 if ((dev->vendor_id == 0x8086) &&
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001540 (device_class == 0x0601)) { /* ISA bridge */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001541 /* Is this device in our list? */
1542 for (i = 0; intel_ich_gpio_table[i].id; i++)
1543 if (dev->device_id == intel_ich_gpio_table[i].id)
1544 break;
1545
1546 if (intel_ich_gpio_table[i].id)
1547 break;
1548 }
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001549 }
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001550
Uwe Hermann93f66db2008-05-22 21:19:38 +00001551 if (!dev) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001552 msg_perr("\nERROR: No known Intel LPC bridge found.\n");
Uwe Hermann93f66db2008-05-22 21:19:38 +00001553 return -1;
1554 }
1555
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001556 /*
1557 * According to the datasheets, all Intel ICHs have the GPIO bar 5:1
1558 * strapped to zero. From some mobile ICH9 version on, this becomes
1559 * 6:1. The mask below catches all.
1560 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001561 base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0;
Uwe Hermann93f66db2008-05-22 21:19:38 +00001562
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001563 /* Check whether the line is allowed. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001564 if (gpio < 32)
1565 allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01;
1566 else if (gpio < 64)
1567 allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01;
1568 else
1569 allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01;
1570
1571 if (!allowed) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001572 msg_perr("\nERROR: This Intel LPC bridge does not allow"
1573 " setting GPIO%02d\n", gpio);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001574 return -1;
1575 }
1576
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001577 msg_pdbg("\nIntel ICH LPC bridge: %sing GPIO%02d.\n",
1578 raise ? "Rais" : "Dropp", gpio);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001579
1580 if (gpio < 32) {
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001581 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001582 tmp = INL(base);
1583 /* ICH/ICH0 multiplexes 27/28 on the line set. */
1584 if ((gpio == 28) &&
1585 ((dev->device_id == 0x2410) || (dev->device_id == 0x2420)))
1586 tmp |= 1 << 27;
1587 else
1588 tmp |= 1 << gpio;
1589 OUTL(tmp, base);
1590
1591 /* As soon as we are talking to ICH8 and above, this register
1592 decides whether we can set the gpio or not. */
1593 if (dev->device_id > 0x2800) {
1594 tmp = INL(base);
1595 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001596 msg_perr("\nERROR: This Intel LPC bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001597 " does not allow setting GPIO%02d\n",
1598 gpio);
1599 return -1;
1600 }
1601 }
1602
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001603 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001604 tmp = INL(base + 0x04);
1605 tmp &= ~(1 << gpio);
1606 OUTL(tmp, base + 0x04);
1607
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001608 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001609 tmp = INL(base + 0x0C);
1610 if (raise)
1611 tmp |= 1 << gpio;
1612 else
1613 tmp &= ~(1 << gpio);
1614 OUTL(tmp, base + 0x0C);
1615 } else if (gpio < 64) {
1616 gpio -= 32;
1617
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001618 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001619 tmp = INL(base + 0x30);
1620 tmp |= 1 << gpio;
1621 OUTL(tmp, base + 0x30);
1622
1623 /* As soon as we are talking to ICH8 and above, this register
1624 decides whether we can set the gpio or not. */
1625 if (dev->device_id > 0x2800) {
1626 tmp = INL(base + 30);
1627 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001628 msg_perr("\nERROR: This Intel LPC bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001629 " does not allow setting GPIO%02d\n",
1630 gpio + 32);
1631 return -1;
1632 }
1633 }
1634
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001635 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001636 tmp = INL(base + 0x34);
1637 tmp &= ~(1 << gpio);
1638 OUTL(tmp, base + 0x34);
1639
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001640 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001641 tmp = INL(base + 0x38);
1642 if (raise)
1643 tmp |= 1 << gpio;
1644 else
1645 tmp &= ~(1 << gpio);
1646 OUTL(tmp, base + 0x38);
1647 } else {
1648 gpio -= 64;
1649
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001650 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001651 tmp = INL(base + 0x40);
1652 tmp |= 1 << gpio;
1653 OUTL(tmp, base + 0x40);
1654
1655 tmp = INL(base + 40);
1656 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001657 msg_perr("\nERROR: This Intel LPC bridge does "
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001658 "not allow setting GPIO%02d\n", gpio + 64);
1659 return -1;
1660 }
1661
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001662 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001663 tmp = INL(base + 0x44);
1664 tmp &= ~(1 << gpio);
1665 OUTL(tmp, base + 0x44);
1666
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001667 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001668 tmp = INL(base + 0x48);
1669 if (raise)
1670 tmp |= 1 << gpio;
1671 else
1672 tmp &= ~(1 << gpio);
1673 OUTL(tmp, base + 0x48);
1674 }
Uwe Hermann93f66db2008-05-22 21:19:38 +00001675
1676 return 0;
1677}
1678
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001679/*
1680 * Suited for:
1681 * - abit IP35: Intel P35 + ICH9R
1682 * - abit IP35 Pro: Intel P35 + ICH9R
Joshua Roysac8b2a12011-08-11 04:21:34 +00001683 * - ASUS P5LD2
Uwe Hermann93f66db2008-05-22 21:19:38 +00001684 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001685static int intel_ich_gpio16_raise(void)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001686{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001687 return intel_ich_gpio_set(16, 1);
Uwe Hermann93f66db2008-05-22 21:19:38 +00001688}
1689
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001690/*
1691 * Suited for:
1692 * - HP Puffer2-UL8E (ASUS PTGD-LA OEM): LGA775 + 915 + ICH6
Michael Karchere57957c2010-07-24 11:14:37 +00001693 */
1694static int intel_ich_gpio18_raise(void)
1695{
1696 return intel_ich_gpio_set(18, 1);
1697}
1698
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001699/*
1700 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001701 * - MSI MS-7046: LGA775 + 915P + ICH6
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001702 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001703static int intel_ich_gpio19_raise(void)
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001704{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001705 return intel_ich_gpio_set(19, 1);
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001706}
1707
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001708/*
Luc Verhaegen6c5d4cc2009-11-28 18:26:21 +00001709 * Suited for:
Stefan Tauner027e0182012-05-02 19:48:21 +00001710 * - ASUS P5BV-R: LGA775 + 3200 + ICH7
1711 */
1712static int intel_ich_gpio20_raise(void)
1713{
1714 return intel_ich_gpio_set(20, 1);
1715}
1716
1717/*
1718 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001719 * - ASUS P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2
1720 * - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5
Michael Karcherf4b58792010-09-10 14:54:18 +00001721 * - ASUS P4P800: Intel socket478 + 865PE + ICH5R
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001722 * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R
Diego Elio Pettenòc6f71462011-03-06 22:52:55 +00001723 * - ASUS P4P800-VM: Intel socket478 + 865PE + ICH5R
Michael Karcher4a23e442010-09-10 14:46:46 +00001724 * - ASUS P5GD1 Pro: Intel LGA 775 + 915P + ICH6R
Joshua Roys1fd4f9e2011-08-11 05:47:32 +00001725 * - ASUS P5GD2 Premium: Intel LGA775 + 915G + ICH6R
Joshua Roysb1d980f2010-09-13 14:02:22 +00001726 * - ASUS P5GDC Deluxe: Intel socket775 + 915P + ICH6R
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001727 * - ASUS P5PE-VM: Intel LGA775 + 865G + ICH5
Stefan Taunerded71e52012-03-10 19:22:13 +00001728 * - ASUS TUSL2-C: Intel socket370 + 815 + ICH2
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001729 * - Samsung Polaris 32: socket478 + 865P + ICH5
Peter Stuge09c13332009-02-02 22:55:26 +00001730 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001731static int intel_ich_gpio21_raise(void)
Peter Stuge09c13332009-02-02 22:55:26 +00001732{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001733 return intel_ich_gpio_set(21, 1);
Peter Stuge09c13332009-02-02 22:55:26 +00001734}
1735
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001736/*
Michael Karcher03b80e92010-03-07 16:32:32 +00001737 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001738 * - ASUS P4B266: socket478 + Intel 845D + ICH2
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001739 * - ASUS P4B533-E: socket478 + 845E + ICH4
1740 * - ASUS P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2
Michael Karcherbfd89a52012-02-12 00:13:14 +00001741 * - TriGem Anaheim-3: socket370 + Intel 810 + ICH
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001742 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001743static int intel_ich_gpio22_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001744{
1745 return intel_ich_gpio_set(22, 1);
1746}
1747
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001748/*
1749 * Suited for:
Stefan Tauner716e0982011-07-25 20:38:52 +00001750 * - ASUS A8Jm (laptop): Intel 945 + ICH7
Michael Karcher14ab8d42011-08-25 14:06:50 +00001751 * - ASUS P5LP-LE used in ...
1752 * - HP Media Center m7270.fr Desktop PC as "Lithium-UL8E"
1753 * - Epson Endeavor MT7700
Stefan Tauner716e0982011-07-25 20:38:52 +00001754 */
1755static int intel_ich_gpio34_raise(void)
1756{
1757 return intel_ich_gpio_set(34, 1);
1758}
1759
1760/*
1761 * Suited for:
Stefan Taunerc6782182012-01-19 17:50:32 +00001762 * - AOpen i945GMx-VFX: Intel 945GM + ICH7-M used in ...
Paul Menzelac427b22012-02-16 21:07:07 +00001763 * - FSC ESPRIMO Q5010 (SMBIOS: D2544-B1)
Stefan Taunerc6782182012-01-19 17:50:32 +00001764 */
1765static int intel_ich_gpio38_raise(void)
1766{
1767 return intel_ich_gpio_set(38, 1);
1768}
1769
1770/*
1771 * Suited for:
Joshua Roysc73e2812011-07-09 19:46:53 +00001772 * - ASUS M6Ne (laptop): socket 479M (guessed) + Intel 855PM + ICH4-M
1773 */
1774static int intel_ich_gpio43_raise(void)
1775{
1776 return intel_ich_gpio_set(43, 1);
1777}
1778
1779/*
1780 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001781 * - HP Vectra VL400: 815 + ICH + PC87360
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001782 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001783static int board_hp_vl400(void)
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001784{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001785 int ret;
1786 ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */
1787 if (!ret)
Michael Karchercba52de2011-03-06 12:07:19 +00001788 ret = pc8736x_gpio_set(PC87360_ID, 0x09, 1); /* #WP ? */
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001789 if (!ret)
Michael Karchercba52de2011-03-06 12:07:19 +00001790 ret = pc8736x_gpio_set(PC87360_ID, 0x27, 1); /* #TBL */
1791 return ret;
1792}
1793
1794/*
1795 * Suited for:
1796 * - HP e-Vectra P2706T: 810E + ICH + PC87364
1797 */
1798static int board_hp_p2706t(void)
1799{
1800 int ret;
1801 ret = pc8736x_gpio_set(PC87364_ID, 0x25, 1);
1802 if (!ret)
1803 ret = pc8736x_gpio_set(PC87364_ID, 0x26, 1);
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001804 return ret;
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001805}
1806
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001807/*
Luc Verhaegen1265d8d2009-11-28 18:16:31 +00001808 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001809 * - Dell PowerEdge 1850: Intel PPGA604 + E7520 + ICH5R
1810 * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R
1811 * - ASRock 775i65G: Intel LGA 775 + 865G + ICH5
Uwe Hermann742999c2010-12-02 21:57:42 +00001812 * - MSI MS-6391 (845 Pro4): Intel Socket478 + 845 + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001813 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001814static int intel_ich_gpio23_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001815{
1816 return intel_ich_gpio_set(23, 1);
1817}
1818
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001819/*
1820 * Suited for:
Michael Karcher39dcdec2010-10-05 17:29:35 +00001821 * - GIGABYTE GA-6IEM: Intel Socket370 + i815 + ICH2
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001822 * - GIGABYTE GA-8IRML: Intel Socket478 + i845 + ICH2
Michael Karcherc7a1ffb2010-07-24 22:27:29 +00001823 */
1824static int intel_ich_gpio25_raise(void)
1825{
1826 return intel_ich_gpio_set(25, 1);
1827}
1828
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001829/*
1830 * Suited for:
1831 * - IBASE MB899: i945GM + ICH7
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001832 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001833static int intel_ich_gpio26_raise(void)
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001834{
1835 return intel_ich_gpio_set(26, 1);
1836}
1837
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001838/*
1839 * Suited for:
1840 * - P4SD-LA (HP OEM): i865 + ICH5
Joshua Roys9d9a1042011-06-13 16:59:01 +00001841 * - GIGABYTE GA-8IP775: 865P + ICH5
Michael Karcherc8613242010-08-13 12:49:01 +00001842 * - GIGABYTE GA-8PE667 Ultra 2: socket 478 + i845PE + ICH4
Maciej Pijanka6add0942011-06-09 20:59:30 +00001843 * - MSI MS-6788-40 (aka 848P Neo-V)
Michael Karcher87c90992010-07-24 11:03:48 +00001844 */
Idwer Vollering19dceac2010-07-24 18:47:45 +00001845static int intel_ich_gpio32_raise(void)
Michael Karcher87c90992010-07-24 11:03:48 +00001846{
1847 return intel_ich_gpio_set(32, 1);
1848}
1849
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001850/*
1851 * Suited for:
Joshua Roys7225ccd2011-05-18 01:32:16 +00001852 * - AOpen i975Xa-YDG: i975X + ICH7 + W83627EHF
1853 */
1854static int board_aopen_i975xa_ydg(void)
1855{
1856 int ret;
1857
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001858 /* Vendor BIOS ends up in LDN6... maybe the board enable is wrong,
Joshua Roys7225ccd2011-05-18 01:32:16 +00001859 * or perhaps it's not needed at all?
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001860 * The regs it tries to touch are 0xF0, 0xF1, 0xF2 which means if it
1861 * were in the right LDN, it would have to be GPIO1 or GPIO3.
Joshua Roys7225ccd2011-05-18 01:32:16 +00001862 */
1863/*
1864 ret = winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, x, 0)
1865 if (!ret)
1866*/
1867 ret = intel_ich_gpio_set(33, 1);
1868
1869 return ret;
1870}
1871
1872/*
1873 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001874 * - Acorp 6A815EPD: socket 370 + intel 815 + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001875 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001876static int board_acorp_6a815epd(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001877{
1878 int ret;
1879
1880 /* Lower Blocks Lock -- pin 7 of PLCC32 */
1881 ret = intel_ich_gpio_set(22, 1);
1882 if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */
1883 ret = intel_ich_gpio_set(23, 1);
1884
1885 return ret;
1886}
1887
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001888/*
1889 * Suited for:
1890 * - Kontron 986LCD-M: Socket478 + 915GM + ICH7R
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001891 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001892static int board_kontron_986lcd_m(void)
Stefan Reinauerac378972008-03-17 22:59:40 +00001893{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001894 int ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001895
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001896 ret = intel_ich_gpio_set(34, 1); /* #TBL */
1897 if (!ret)
1898 ret = intel_ich_gpio_set(35, 1); /* #WP */
Stefan Reinauerac378972008-03-17 22:59:40 +00001899
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001900 return ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001901}
1902
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001903/*
1904 * Suited for:
1905 * - Soyo SY-7VCA: Pro133A + VT82C686
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001906 */
Michael Karcher06477332010-03-19 22:49:09 +00001907static int via_apollo_gpo_set(int gpio, int raise)
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001908{
Michael Karcher06477332010-03-19 22:49:09 +00001909 struct pci_dev *dev;
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001910 uint32_t base, tmp;
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001911
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001912 /* VT82C686 power management */
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001913 dev = pci_dev_find(0x1106, 0x3057);
1914 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001915 msg_perr("\nERROR: VT82C686 PM device not found.\n");
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001916 return -1;
1917 }
1918
Sean Nelson316a29f2010-05-07 20:09:04 +00001919 msg_pdbg("\nVIA Apollo ACPI: %sing GPIO%02d.\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001920 raise ? "Rais" : "Dropp", gpio);
Michael Karcher06477332010-03-19 22:49:09 +00001921
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001922 /* Select GPO function on multiplexed pins. */
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001923 tmp = pci_read_byte(dev, 0x54);
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001924 switch (gpio) {
1925 case 0:
1926 tmp &= ~0x03;
1927 break;
1928 case 1:
1929 tmp |= 0x04;
1930 break;
1931 case 2:
1932 tmp |= 0x08;
1933 break;
1934 case 3:
1935 tmp |= 0x10;
1936 break;
Michael Karcher06477332010-03-19 22:49:09 +00001937 }
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001938 pci_write_byte(dev, 0x54, tmp);
1939
1940 /* PM IO base */
1941 base = pci_read_long(dev, 0x48) & 0x0000FF00;
1942
1943 /* Drop GPO0 */
Michael Karcher06477332010-03-19 22:49:09 +00001944 tmp = INL(base + 0x4C);
1945 if (raise)
1946 tmp |= 1U << gpio;
1947 else
1948 tmp &= ~(1U << gpio);
1949 OUTL(tmp, base + 0x4C);
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001950
1951 return 0;
1952}
1953
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001954/*
1955 * Suited for:
1956 * - abit VT6X4: Pro133x + VT82C686A
Mattias Mattssone3df96e2010-08-15 22:43:23 +00001957 * - abit VA6: Pro133x + VT82C686A
Michael Karcher187a46a2010-03-19 22:30:49 +00001958 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001959static int via_apollo_gpo4_lower(void)
Michael Karcher187a46a2010-03-19 22:30:49 +00001960{
1961 return via_apollo_gpo_set(4, 0);
1962}
1963
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001964/*
1965 * Suited for:
1966 * - Soyo SY-7VCA: Pro133A + VT82C686
Michael Karcher06477332010-03-19 22:49:09 +00001967 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001968static int via_apollo_gpo0_lower(void)
Michael Karcher06477332010-03-19 22:49:09 +00001969{
1970 return via_apollo_gpo_set(0, 0);
1971}
1972
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001973/*
Michael Karchera08d0f22011-07-25 17:25:24 +00001974 * Enable some GPIO pin on SiS southbridge and enables SIO flash writes.
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001975 *
1976 * Suited for:
1977 * - MSI 651M-L: SiS651 / SiS962
Michael Karchera08d0f22011-07-25 17:25:24 +00001978 * - GIGABYTE GA-8SIMLH
Michael Karcher9f9e6132010-01-09 17:36:06 +00001979 */
Michael Karchera08d0f22011-07-25 17:25:24 +00001980static int sis_gpio0_raise_and_w836xx_memw(void)
Michael Karcher9f9e6132010-01-09 17:36:06 +00001981{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001982 struct pci_dev *dev;
Uwe Hermann43959702010-03-13 17:28:29 +00001983 uint16_t base, temp;
Michael Karcher9f9e6132010-01-09 17:36:06 +00001984
1985 dev = pci_dev_find(0x1039, 0x0962);
1986 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001987 msg_perr("Expected south bridge not found\n");
Michael Karcher9f9e6132010-01-09 17:36:06 +00001988 return 1;
1989 }
1990
Michael Karcher9f9e6132010-01-09 17:36:06 +00001991 base = pci_read_word(dev, 0x74);
1992 temp = INW(base + 0x68);
1993 temp &= ~(1 << 0); /* Make pin output? */
Michael Karcher0435dfd2010-01-09 23:31:13 +00001994 OUTW(temp, base + 0x68);
Michael Karcher9f9e6132010-01-09 17:36:06 +00001995
1996 temp = INW(base + 0x64);
1997 temp |= (1 << 0); /* Raise output? */
1998 OUTW(temp, base + 0x64);
1999
2000 w836xx_memw_enable(0x2E);
2001
2002 return 0;
2003}
2004
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002005/*
Michael Gold6d52e472009-06-19 13:00:24 +00002006 * Find the runtime registers of an SMSC Super I/O, after verifying its
2007 * chip ID.
2008 *
2009 * Returns the base port of the runtime register block, or 0 on error.
2010 */
2011static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id,
2012 uint8_t logical_device)
2013{
2014 uint16_t rt_port = 0;
2015
2016 /* Verify the chip ID. */
Uwe Hermann1432a602009-06-28 23:26:37 +00002017 OUTB(0x55, sio_port); /* Enable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00002018 if (sio_read(sio_port, 0x20) != chip_id) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002019 msg_perr("\nERROR: SMSC Super I/O not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +00002020 goto out;
2021 }
2022
2023 /* If the runtime block is active, get its address. */
2024 sio_write(sio_port, 0x07, logical_device);
2025 if (sio_read(sio_port, 0x30) & 1) {
2026 rt_port = (sio_read(sio_port, 0x60) << 8)
2027 | sio_read(sio_port, 0x61);
2028 }
2029
2030 if (rt_port == 0) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002031 msg_perr("\nERROR: "
Michael Gold6d52e472009-06-19 13:00:24 +00002032 "Super I/O runtime interface not available.\n");
2033 }
2034out:
Uwe Hermann1432a602009-06-28 23:26:37 +00002035 OUTB(0xaa, sio_port); /* Disable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00002036 return rt_port;
2037}
2038
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002039/*
2040 * Disable write protection on the Mitac 6513WU. WP# on the FWH is
Michael Gold6d52e472009-06-19 13:00:24 +00002041 * connected to GP30 on the Super I/O, and TBL# is always high.
2042 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00002043static int board_mitac_6513wu(void)
Michael Gold6d52e472009-06-19 13:00:24 +00002044{
2045 struct pci_dev *dev;
2046 uint16_t rt_port;
2047 uint8_t val;
2048
2049 dev = pci_dev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */
2050 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002051 msg_perr("\nERROR: Intel 82801AA ISA bridge not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +00002052 return -1;
2053 }
2054
Uwe Hermann1432a602009-06-28 23:26:37 +00002055 rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa);
Michael Gold6d52e472009-06-19 13:00:24 +00002056 if (rt_port == 0)
2057 return -1;
2058
2059 /* Configure the GPIO pin. */
2060 val = INB(rt_port + 0x33); /* GP30 config */
Uwe Hermann1432a602009-06-28 23:26:37 +00002061 val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */
Michael Gold6d52e472009-06-19 13:00:24 +00002062 OUTB(val, rt_port + 0x33);
2063
2064 /* Disable write protection. */
2065 val = INB(rt_port + 0x4d); /* GP3 values */
Uwe Hermann1432a602009-06-28 23:26:37 +00002066 val |= 0x01; /* Set GP30 high. */
Michael Gold6d52e472009-06-19 13:00:24 +00002067 OUTB(val, rt_port + 0x4d);
2068
2069 return 0;
2070}
2071
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002072/*
2073 * Suited for:
Christoph Grenzd13a3942011-10-21 13:20:11 +00002074 * - abit AV8: Socket939 + K8T800Pro + VT8237
2075 */
2076static int board_abit_av8(void)
2077{
2078 uint8_t val;
2079
2080 /* Raise GPO pins GP22 & GP23 */
2081 val = INB(0x404E);
2082 val |= 0xC0;
2083 OUTB(val, 0x404E);
2084
2085 return 0;
2086}
2087
2088/*
2089 * Suited for:
Uwe Hermann45bd1442010-09-14 23:20:35 +00002090 * - ASUS A7V333: VIA KT333 + VT8233A + IT8703F
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002091 * - ASUS A7V8X: VIA KT400 + VT8235 + IT8703F
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002092 */
Uwe Hermann45bd1442010-09-14 23:20:35 +00002093static int it8703f_gpio51_raise(void)
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002094{
2095 uint16_t id, base;
2096 uint8_t tmp;
2097
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002098 /* Find the IT8703F. */
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002099 w836xx_ext_enter(0x2E);
2100 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
2101 w836xx_ext_leave(0x2E);
2102
2103 if (id != 0x8701) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002104 msg_perr("\nERROR: IT8703F Super I/O not found.\n");
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002105 return -1;
2106 }
2107
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002108 /* Get the GP567 I/O base. */
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002109 w836xx_ext_enter(0x2E);
2110 sio_write(0x2E, 0x07, 0x0C);
2111 base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
2112 w836xx_ext_leave(0x2E);
2113
2114 if (!base) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002115 msg_perr("\nERROR: Failed to read IT8703F Super I/O GPIO"
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002116 " Base.\n");
2117 return -1;
2118 }
2119
2120 /* Raise GP51. */
2121 tmp = INB(base);
2122 tmp |= 0x02;
2123 OUTB(tmp, base);
2124
2125 return 0;
2126}
2127
Luc Verhaegen72272912009-09-01 21:22:23 +00002128/*
Joshua Roysa2f37222011-11-14 13:00:12 +00002129 * General routine for raising/dropping GPIO lines on the ITE IT87xx.
Luc Verhaegen72272912009-09-01 21:22:23 +00002130 */
Joshua Roysa2f37222011-11-14 13:00:12 +00002131static int it87_gpio_set(unsigned int gpio, int raise)
Luc Verhaegen72272912009-09-01 21:22:23 +00002132{
Joshua Roysa2f37222011-11-14 13:00:12 +00002133 int allowed, sio;
Luc Verhaegen72272912009-09-01 21:22:23 +00002134 unsigned int port;
Joshua Roysa2f37222011-11-14 13:00:12 +00002135 uint16_t base, sioport;
Luc Verhaegen72272912009-09-01 21:22:23 +00002136 uint8_t tmp;
2137
Joshua Roysa2f37222011-11-14 13:00:12 +00002138 /* IT87 GPIO configuration table */
2139 static const struct it87cfg {
2140 uint16_t id;
2141 uint8_t base_reg;
2142 uint32_t bank0;
2143 uint32_t bank1;
2144 uint32_t bank2;
2145 } it87_gpio_table[] = {
2146 {0x8712, 0x62, 0xCFF3FC00, 0x00FCFF3F, 0},
2147 {0x8718, 0x62, 0xCFF37C00, 0xF3FCDF3F, 0x0000000F},
2148 {0, 0, 0, 0, 0} /* end marker */
2149 };
2150 const struct it87cfg *cfg = NULL;
Luc Verhaegen72272912009-09-01 21:22:23 +00002151
Joshua Roysa2f37222011-11-14 13:00:12 +00002152 /* Find the Super I/O in the probed list */
2153 for (sio = 0; sio < superio_count; sio++) {
2154 int i;
2155 if (superios[sio].vendor != SUPERIO_VENDOR_ITE)
2156 continue;
2157
2158 /* Is this device in our list? */
2159 for (i = 0; it87_gpio_table[i].id; i++)
2160 if (superios[sio].model == it87_gpio_table[i].id) {
2161 cfg = &it87_gpio_table[i];
2162 goto found;
2163 }
2164 }
2165
2166 if (cfg == NULL) {
2167 msg_perr("\nERROR: No IT87 Super I/O GPIO configuration "
2168 "found.\n");
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002169 return -1;
Luc Verhaegen72272912009-09-01 21:22:23 +00002170 }
2171
Joshua Roysa2f37222011-11-14 13:00:12 +00002172found:
2173 /* Check whether the gpio is allowed. */
2174 if (gpio < 32)
2175 allowed = (cfg->bank0 >> gpio) & 0x01;
2176 else if (gpio < 64)
2177 allowed = (cfg->bank1 >> (gpio - 32)) & 0x01;
2178 else if (gpio < 96)
2179 allowed = (cfg->bank2 >> (gpio - 64)) & 0x01;
2180 else
2181 allowed = 0;
Luc Verhaegen72272912009-09-01 21:22:23 +00002182
Joshua Roysa2f37222011-11-14 13:00:12 +00002183 if (!allowed) {
2184 msg_perr("\nERROR: IT%02X does not allow setting GPIO%02u.\n",
2185 cfg->id, gpio);
Luc Verhaegen72272912009-09-01 21:22:23 +00002186 return -1;
2187 }
2188
Joshua Roysa2f37222011-11-14 13:00:12 +00002189 /* Read the Simple I/O Base Address Register */
2190 sioport = superios[sio].port;
2191 enter_conf_mode_ite(sioport);
2192 sio_write(sioport, 0x07, 0x07);
2193 base = (sio_read(sioport, cfg->base_reg) << 8) |
2194 sio_read(sioport, cfg->base_reg + 1);
2195 exit_conf_mode_ite(sioport);
Luc Verhaegen72272912009-09-01 21:22:23 +00002196
2197 if (!base) {
Joshua Roysa2f37222011-11-14 13:00:12 +00002198 msg_perr("\nERROR: Failed to read IT87 Super I/O GPIO Base.\n");
Luc Verhaegen72272912009-09-01 21:22:23 +00002199 return -1;
2200 }
2201
Joshua Roysa2f37222011-11-14 13:00:12 +00002202 msg_pdbg("Using IT87 GPIO base 0x%04x\n", base);
2203
2204 port = gpio / 10 - 1;
2205 gpio %= 10;
2206
2207 /* set GPIO. */
Luc Verhaegen72272912009-09-01 21:22:23 +00002208 tmp = INB(base + port);
2209 if (raise)
Joshua Roysa2f37222011-11-14 13:00:12 +00002210 tmp |= 1 << gpio;
Luc Verhaegen72272912009-09-01 21:22:23 +00002211 else
Joshua Roysa2f37222011-11-14 13:00:12 +00002212 tmp &= ~(1 << gpio);
Luc Verhaegen72272912009-09-01 21:22:23 +00002213 OUTB(tmp, base + port);
2214
2215 return 0;
2216}
2217
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002218/*
Russ Dillbd622d12010-03-09 16:57:06 +00002219 * Suited for:
Joshua Roys8ca42552011-11-19 19:31:17 +00002220 * - ASUS A7N8X-VM/400: NVIDIA nForce2 IGP2 + IT8712F
2221 */
2222static int it8712f_gpio12_raise(void)
2223{
2224 return it87_gpio_set(12, 1);
2225}
2226
2227/*
2228 * Suited for:
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00002229 * - ASUS A7V600-X: VIA KT600 + VT8237 + IT8712F
2230 * - ASUS A7V8X-X: VIA KT400 + VT8235 + IT8712F
Luc Verhaegen72272912009-09-01 21:22:23 +00002231 */
Joshua Roysa2f37222011-11-14 13:00:12 +00002232static int it8712f_gpio31_raise(void)
Luc Verhaegen72272912009-09-01 21:22:23 +00002233{
Joshua Roysa2f37222011-11-14 13:00:12 +00002234 return it87_gpio_set(32, 1);
2235}
2236
2237/*
2238 * Suited for:
2239 * - ASUS P5N-D: NVIDIA MCP51 + IT8718F
2240 * - ASUS P5N-E SLI: NVIDIA MCP51 + IT8718F
2241 */
2242static int it8718f_gpio63_raise(void)
2243{
2244 return it87_gpio_set(63, 1);
Luc Verhaegen72272912009-09-01 21:22:23 +00002245}
2246
Ingo Feldschmid8a0f9b02012-01-31 06:51:56 +00002247/*
2248 * Suited for all boards with ambiguous DMI chassis information, which should be
2249 * whitelisted because they are known to work:
2250 * - MSC Q7 Tunnel Creek Module (Q7-TCTC)
2251 */
2252static int p2_not_a_laptop(void)
2253{
2254 /* label this board as not a laptop */
2255 is_laptop = 0;
2256 msg_pdbg("Laptop detection overridden by P2 board enable.\n");
2257 return 0;
2258}
2259
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00002260#endif
2261
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002262/*
Uwe Hermannd0e347d2009-10-06 13:00:00 +00002263 * Below is the list of boards which need a special "board enable" code in
2264 * flashrom before their ROM chip can be accessed/written to.
2265 *
2266 * NOTE: Please add boards that _don't_ need such enables or don't work yet
2267 * to the respective tables in print.c. Thanks!
2268 *
Uwe Hermannffec5f32007-08-23 16:08:21 +00002269 * We use 2 sets of IDs here, you're free to choose which is which. This
2270 * is to provide a very high degree of certainty when matching a board on
2271 * the basis of subsystem/card IDs. As not every vendor handles
2272 * subsystem/card IDs in a sane manner.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002273 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00002274 * Keep the second set NULLed if it should be ignored. Keep the subsystem IDs
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00002275 * NULLed if they don't identify the board fully and if you can't use DMI.
2276 * But please take care to provide an as complete set of pci ids as possible;
2277 * autodetection is the preferred behaviour and we would like to make sure that
2278 * matches are unique.
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00002279 *
Michael Karcher6701ee82010-01-20 14:14:11 +00002280 * If PCI IDs are not sufficient for board matching, the match can be further
2281 * constrained by a string that has to be present in the DMI database for
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00002282 * the baseboard or the system entry. The pattern is matched by case sensitive
Michael Karcher6701ee82010-01-20 14:14:11 +00002283 * substring match, unless it is anchored to the beginning (with a ^ in front)
2284 * or the end (with a $ at the end). Both anchors may be specified at the
2285 * same time to match the full field.
2286 *
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00002287 * When a board is matched through DMI, the first and second main PCI IDs
2288 * and the first subsystem PCI ID have to match as well. If you specify the
2289 * first subsystem ID as 0x0:0x0, the DMI matching code expects that the
2290 * subsystem ID of that device is indeed zero.
2291 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00002292 * The coreboot ids are used two fold. When running with a coreboot firmware,
2293 * the ids uniquely matches the coreboot board identification string. When a
2294 * legacy bios is installed and when autodetection is not possible, these ids
Carl-Daniel Hailfinger2d927fb2012-01-04 00:48:27 +00002295 * can be used to identify the board through the -p internal:mainboard=
2296 * programmer parameter.
Luc Verhaegenc5210162009-04-20 12:38:17 +00002297 *
2298 * When a board is identified through its coreboot ids (in both cases), the
2299 * main pci ids are still required to match, as a safeguard.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002300 */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002301
Uwe Hermanndeeebe22009-05-08 16:23:34 +00002302/* Please keep this list alphabetically ordered by vendor/board name. */
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002303const struct board_match board_matches[] = {
Uwe Hermann5ab88892009-06-21 20:50:22 +00002304
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002305 /* first pci-id set [4], second pci-id set [4], dmi identifier, coreboot id [2], phase, vendor name, board name max_rom_... OK? flash enable */
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00002306#if defined(__i386__) || defined(__x86_64__)
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002307 {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, P3, "abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise},
Christoph Grenzd13a3942011-10-21 13:20:11 +00002308 {0x1106, 0x0282, 0x147B, 0x1415, 0x1106, 0x3227, 0x147B, 0x1415, "^AV8 ", NULL, NULL, P3, "abit", "AV8", 0, OK, board_abit_av8},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002309 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^i440BX-W977 (BM6)$", NULL, NULL, P3, "abit", "BM6", 0, OK, intel_piix4_gpo26_lower},
2310 {0x8086, 0x24d3, 0x147b, 0x1014, 0x8086, 0x2578, 0x147b, 0x1014, NULL, NULL, NULL, P3, "abit", "IC7", 0, NT, intel_ich_gpio23_raise},
2311 {0x8086, 0x2930, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, P3, "abit", "IP35", 0, OK, intel_ich_gpio16_raise},
2312 {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, P3, "abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise},
Stefan Tauner24c38df2012-08-11 02:33:20 +00002313 {0x10de, 0x0050, 0x147b, 0x1c1a, 0x10de, 0x0052, 0x147b, 0x1c1a, NULL, NULL, NULL, P3, "abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002314 {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, P3, "abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise},
Paul Menzelac427b22012-02-16 21:07:07 +00002315 {0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0260, 0x147b, 0x1c26, NULL, NULL, NULL, P3, "abit", "NF-M2 nView", 0, OK, nvidia_mcp_gpio4_lower},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002316 {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, "(VA6)$", NULL, NULL, P3, "abit", "VA6", 0, OK, via_apollo_gpo4_lower},
2317 {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", P3, "abit", "VT6X4", 0, OK, via_apollo_gpo4_lower},
2318 {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, P3, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd},
Stefan Tauner24c38df2012-08-11 02:33:20 +00002319 {0x1022, 0x746B, 0, 0, 0x1022, 0x7460, 0, 0, NULL, "AGAMI", "ARUMA", P3, "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002320 {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, P3, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e},
2321 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", P3, "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x},
2322 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", P3, "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x},
Stefan Taunerc6782182012-01-19 17:50:32 +00002323 {0x8086, 0x27b9, 0xa0a0, 0x0632, 0x8086, 0x27da, 0xa0a0, 0x0632, NULL, NULL, NULL, P3, "AOpen", "i945GMx-VFX", 0, OK, intel_ich_gpio38_raise},
Joshua Roys7225ccd2011-05-18 01:32:16 +00002324 {0x8086, 0x277c, 0xa0a0, 0x060b, 0x8086, 0x27da, 0xa0a0, 0x060b, NULL, NULL, NULL, P3, "AOpen", "i975Xa-YDG", 0, OK, board_aopen_i975xa_ydg},
Joshua Roysea3aed02011-11-16 22:08:11 +00002325 {0x8086, 0x27b8, 0x1849, 0x27b8, 0x8086, 0x27da, 0x1849, 0x27da, "^ConRoeXFire-eSATA2", NULL, NULL, P3, "ASRock", "ConRoeXFire-eSATA2", 0, OK, intel_ich_gpio16_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002326 {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41 $", NULL, NULL, P3, "ASRock", "K7S41", 0, OK, w836xx_memw_enable_2e},
Pawel Rozanski1d233072011-06-19 16:52:48 +00002327 {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41GX$", NULL, NULL, P3, "ASRock", "K7S41GX", 0, OK, w836xx_memw_enable_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002328 {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, P3, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise},
2329 {0x8086, 0x2570, 0x1849, 0x2570, 0x8086, 0x24d3, 0x1849, 0x24d0, NULL, NULL, NULL, P3, "ASRock", "775i65G", 0, OK, intel_ich_gpio23_raise},
Joshua Roys8ca42552011-11-19 19:31:17 +00002330 {0x10DE, 0x0060, 0x1043, 0x80AD, 0x10DE, 0x01E0, 0x1043, 0x80C0, NULL, NULL, NULL, P3, "ASUS", "A7N8X-VM/400", 0, OK, it8712f_gpio12_raise},
Joshua Roysa2f37222011-11-14 13:00:12 +00002331 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, P3, "ASUS", "A7V600-X", 0, OK, it8712f_gpio31_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002332 {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, P3, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e},
2333 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V8X", 0, OK, it8703f_gpio51_raise},
2334 {0x1106, 0x3099, 0x1043, 0x807F, 0x1106, 0x3147, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V333", 0, OK, it8703f_gpio51_raise},
Joshua Roysa2f37222011-11-14 13:00:12 +00002335 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, P3, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio31_raise},
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00002336 {0x1002, 0x4372, 0x103c, 0x2a26, 0x1002, 0x4377, 0x103c, 0x2a26, NULL, NULL, NULL, P3, "ASUS", "A8AE-LE", 0, OK, amd_sbxxx_gpio9_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002337 {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, P3, "ASUS", "A8Jm", 0, NT, intel_ich_gpio34_raise},
Stefan Taunera9cbbac2011-08-07 13:17:20 +00002338 {0x10DE, 0x0260, 0x103C, 0x2A34, 0x10DE, 0x0264, 0x103C, 0x2A34, "NODUSM3", NULL, NULL, P3, "ASUS", "A8M2N-LA (NodusM3-GL8E)", 0, OK, nvidia_mcp_gpio0_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002339 {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI2L", NULL, NULL, P3, "ASUS", "A8N-LA (Nagami-GL8E)", 0, OK, nvidia_mcp_gpio0_raise},
Stefan Tauner2414e092011-08-06 16:16:45 +00002340 {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, "^A8N-SLI DELUXE", NULL, NULL, P3, "ASUS", "A8N-SLI Deluxe", 0, NT, board_shuttle_fn25},
Stefan Taunerff80e682011-07-20 16:34:18 +00002341 {0x10de, 0x0264, 0x1043, 0x81bc, 0x10de, 0x02f0, 0x1043, 0x81cd, NULL, NULL, NULL, P3, "ASUS", "A8N-VM CSM", 0, OK, w83627ehf_gpio22_raise_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002342 {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, P3, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise},
2343 {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, P3, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise},
Joshua Roysc73e2812011-07-09 19:46:53 +00002344 {0x8086, 0x24cc, 0, 0, 0x8086, 0x24c3, 0x1043, 0x1869, "^M6Ne$", NULL, NULL, P3, "ASUS", "M6Ne", 0, NT, intel_ich_gpio43_raise},
Joshua Roysd708fad2012-02-17 14:51:15 +00002345 {0x8086, 0x7180, 0, 0, 0x8086, 0x7110, 0, 0, "^OPLX-M$", NULL, NULL, P3, "ASUS", "OPLX-M", 0, NT, intel_piix4_gpo18_lower},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002346 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^P2B-N$", NULL, NULL, P3, "ASUS", "P2B-N", 0, OK, intel_piix4_gpo18_lower},
2347 {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, P3, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise},
2348 {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, P3, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise},
2349 {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, P3, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise},
Joshua Roysa5f5a152011-11-15 08:08:15 +00002350 {0x8086, 0x2560, 0x103C, 0x2A00, 0x8086, 0x24C3, 0x103C, 0x2A01, "^Guppy", NULL, NULL, P3, "ASUS", "P4GV-LA (Guppy)", 0, OK, intel_ich_gpio21_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002351 {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, P3, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
2352 {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D5, 0x1043, 0x80F3, NULL, NULL, NULL, P3, "ASUS", "P4P800", 0, NT, intel_ich_gpio21_raise},
Sylvain "ythier" Hitier3093f8f2011-09-03 11:22:27 +00002353 {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D3, 0x1043, 0x80A6, "^P4P800-E$", NULL, NULL, P3, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002354 {0x8086, 0x2570, 0x1043, 0x80A5, 0x8086, 0x24d0, 0, 0, NULL, NULL, NULL, P3, "ASUS", "P4P800-VM", 0, OK, intel_ich_gpio21_raise},
2355 {0x1039, 0x0651, 0x1043, 0x8081, 0x1039, 0x0962, 0, 0, NULL, NULL, NULL, P3, "ASUS", "P4SC-E", 0, OK, it8707f_write_enable_2e},
2356 {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, P3, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise},
2357 {0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x5513, 0x1043, 0x8087, NULL, NULL, NULL, P3, "ASUS", "P4S800-MX", 512, OK, w836xx_memw_enable_2e},
2358 {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", P3, "ASUS", "P5A", 0, OK, board_asus_p5a},
Stefan Tauner027e0182012-05-02 19:48:21 +00002359 {0x8086, 0x27b8, 0x1043, 0x819e, 0x8086, 0x29f0, 0x1043, 0x82a5, "^P5BV-R$", NULL, NULL, P3, "ASUS", "P5BV-R", 0, OK, intel_ich_gpio20_raise},
Stefan Taunera4f14472011-10-22 22:01:09 +00002360 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, "^P5GD1 PRO$", NULL, NULL, P3, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise},
2361 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, "^P5GD1-VM$", NULL, NULL, P3, "ASUS", "P5GD1-VM/S", 0, OK, intel_ich_gpio21_raise},
2362 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, P3, "ASUS", "P5GD1(-VM)", 0, NT, intel_ich_gpio21_raise},
Joshua Roys1fd4f9e2011-08-11 05:47:32 +00002363 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GD2-Premium$", NULL, NULL, P3, "ASUS", "P5GD2 Premium", 0, OK, intel_ich_gpio21_raise},
Stefan Taunerd94d25d2012-07-28 03:17:15 +00002364 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x81a6, "^P5GD2-X$", NULL, NULL, P3, "ASUS", "P5GD2-X", 0, OK, intel_ich_gpio21_raise},
Stefan Taunera4f14472011-10-22 22:01:09 +00002365 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GDC-V$", NULL, NULL, P3, "ASUS", "P5GDC-V Deluxe", 0, OK, intel_ich_gpio21_raise},
2366 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GDC$", NULL, NULL, P3, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise},
2367 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, P3, "ASUS", "P5GD2/C variants", 0, NT, intel_ich_gpio21_raise},
Michael Karcher14ab8d42011-08-25 14:06:50 +00002368 {0x8086, 0x27b8, 0x103c, 0x2a22, 0x8086, 0x2770, 0x103c, 0x2a22, "^LITHIUM$", NULL, NULL, P3, "ASUS", "P5LP-LE (Lithium-UL8E)",0, OK, intel_ich_gpio34_raise},
2369 {0x8086, 0x27b8, 0x1043, 0x2a22, 0x8086, 0x2770, 0x1043, 0x2a22, "^P5LP-LE$", NULL, NULL, P3, "ASUS", "P5LP-LE (Epson OEM)", 0, OK, intel_ich_gpio34_raise},
Joshua Roys1fd4f9e2011-08-11 05:47:32 +00002370 {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, NT, intel_ich_gpio16_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002371 {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, P3, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise},
Joshua Roysa2f37222011-11-14 13:00:12 +00002372 {0x10DE, 0x0260, 0x1043, 0x81BC, 0x10DE, 0x026C, 0x1043, 0x829E, "^P5N-D$", NULL, NULL, P3, "ASUS", "P5N-D", 0, OK, it8718f_gpio63_raise},
2373 {0x10DE, 0x0260, 0x1043, 0x81BC, 0x10DE, 0x026C, 0x1043, 0x8249, "^P5N-E SLI$",NULL, NULL, P3, "ASUS", "P5N-E SLI", 0, NT, it8718f_gpio63_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002374 {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, P3, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise},
Stefan Taunerded71e52012-03-10 19:22:13 +00002375 {0x8086, 0x2443, 0x1043, 0x8027, 0x8086, 0x1130, 0x1043, 0x8027, NULL, NULL, NULL, P3, "ASUS", "TUSL2-C", 0, NT, intel_ich_gpio21_raise},
Stefan Taunerb6304c12012-08-09 23:25:27 +00002376 {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3116, 0x1106, 0x3116, "^KM266-8235$", "biostar", "m7viq", P3, "Biostar", "M7VIQ", 0, NT, w83697xx_memw_enable_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002377 {0x10b7, 0x9055, 0x1028, 0x0082, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Dell", "OptiPlex GX1", 0, OK, intel_piix4_gpo30_lower},
2378 {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, P3, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise},
2379 {0x10de, 0x03ea, 0x1019, 0x2602, 0x10de, 0x03e0, 0x1019, 0x2602, NULL, NULL, NULL, P3, "Elitegroup", "GeForce6100SM-M", 0, OK, board_ecs_geforce6100sm_m},
2380 {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, P3, "Elitegroup", "K7VTA3", 256, OK, NULL},
2381 {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, P3, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e},
Stefan Tauneraf4b1582011-08-06 16:16:33 +00002382 {0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, "8NPA7I", NULL, NULL, P3, "EPoX", "EP-8NPA7I", 0, OK, nvidia_mcp_gpio4_raise},
2383 {0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, "9NPA7I", NULL, NULL, P3, "EPoX", "EP-9NPA7I", 0, OK, nvidia_mcp_gpio4_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002384 {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, P3, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise},
2385 {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", P3, "EPoX", "EP-BX3", 0, NT, intel_piix4_gpo22_raise},
2386 {0x10de, 0x02f0, 0x105b, 0x0d01, 0x10de, 0x0264, 0x105b, 0x0d01, NULL, NULL, NULL, P3, "Foxconn", "6150K8MD-8EKRSH", 0, NT, nvidia_mcp_gpio2_raise},
2387 {0x8086, 0x2443, 0x8086, 0x2442, 0x8086, 0x1130, 0x8086, 0x1130, "^6IEM ", NULL, NULL, P3, "GIGABYTE", "GA-6IEM", 0, NT, intel_ich_gpio25_raise},
2388 {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-7ZM", 512, OK, NULL},
Joshua Roys9d9a1042011-06-13 16:59:01 +00002389 {0x8086, 0x2570, 0x1458, 0x2570, 0x8086, 0x24d0, 0, 0, "^8IP775/-G$",NULL, NULL, P3, "GIGABYTE", "GA-8IP775", 0, OK, intel_ich_gpio32_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002390 {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise},
2391 {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise},
Stefan Tauner716e0982011-07-25 20:38:52 +00002392 {0x1039, 0x0651, 0x1039, 0x0651, 0x1039, 0x7002, 0x1458, 0x5004, "^GA-8SIMLH$",NULL, NULL, P3, "GIGABYTE", "GA-8SIMLH", 0, OK, sis_gpio0_raise_and_w836xx_memw},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002393 {0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise},
2394 {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise},
Idwer Volleringd8a00a02011-06-13 16:58:54 +00002395 {0x10de, 0x00e4, 0x1458, 0x0c11, 0x10de, 0x00e0, 0x1458, 0x0c11, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8NS Pro-939", 0, NT, nvidia_mcp_gpio0a_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002396 {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise},
Idwer Volleringd8a00a02011-06-13 16:58:54 +00002397 {0x8086, 0x2415, 0x103c, 0x1250, 0x10b7, 0x9200, 0x103c, 0x1247, NULL, NULL, NULL, P3, "HP", "e-Vectra P2706T", 0, OK, board_hp_p2706t},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002398 {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", P3, "HP", "ProLiant DL145 G3", 0, OK, board_hp_dl145_g3_enable},
2399 {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", P3, "HP", "ProLiant DL165 G6", 0, OK, board_hp_dl165_g6_enable},
2400 {0x8086, 0x2580, 0x103c, 0x2a08, 0x8086, 0x2640, 0x103c, 0x2a0a, NULL, NULL, NULL, P3, "HP", "Puffer2-UL8E", 0, OK, intel_ich_gpio18_raise},
Idwer Volleringd8a00a02011-06-13 16:58:54 +00002401 {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, P3, "HP", "Vectra VL400", 0, OK, board_hp_vl400},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002402 {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, P3, "HP", "Vectra VL420 SFF", 0, OK, intel_ich_gpio22_raise},
2403 {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, "hp", "xw9400", P3, "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise},
2404 {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", P3, "IBASE", "MB899", 0, OK, intel_ich_gpio26_raise},
2405 {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, P3, "IBM", "x3455", 0, OK, board_ibm_x3455},
2406 {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, P3, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi},
2407 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, P3, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower},
Stefan Tauner24c38df2012-08-11 02:33:20 +00002408 {0x1022, 0x7468, 0, 0, 0x1022, 0x7460, 0, 0, NULL, "iwill", "dk8_htx", P3, "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002409 {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", P3, "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m},
2410 {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, P3, "Mitac", "6513WU", 0, OK, board_mitac_6513wu},
Ingo Feldschmid8a0f9b02012-01-31 06:51:56 +00002411 {0x8086, 0x8186, 0x8086, 0x8186, 0x8086, 0x8800, 0x0000, 0x0000, "^MSC Vertriebs GmbH$", NULL, NULL, P2, "MSC", "Q7-TCTC", 0, OK, p2_not_a_laptop},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002412 {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, P3, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, /* TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html. */
2413 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^MS-6163 (i440BX)$", NULL, NULL, P3, "MSI", "MS-6163 (MS-6163 Pro)", 0, OK, intel_piix4_gpo14_raise},
2414 {0x1039, 0x0745, 0, 0, 0x1039, 0x0018, 0, 0, "^MS-6561", NULL, NULL, P3, "MSI", "MS-6561 (745 Ultra)", 0, OK, w836xx_memw_enable_2e},
2415 {0x8086, 0x2560, 0x1462, 0x5770, 0x8086, 0x2562, 0x1462, 0x5778, NULL, NULL, NULL, P3, "MSI", "MS-6577 (Xenon)", 0, OK, w83627hf_gpio25_raise_2e},
2416 {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, P3, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v},
2417 {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, P3, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio44_raise_2e},
2418 {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, P3, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v},
2419 {0x1106, 0x3148, 0 , 0 , 0x1106, 0x3177, 0 , 0 , NULL, "msi", "ms6787", P3, "MSI", "MS-6787 (P4MAM-V/P4MAM-L)", 0, OK, w836xx_memw_enable_2e},
Maciej Pijanka6add0942011-06-09 20:59:30 +00002420 {0x8086, 0x24d3, 0x1462, 0x7880, 0x8086, 0x2570, 0, 0, NULL, NULL, NULL, P3, "MSI", "MS-6788-040 (848P NeoV)", 0, OK, intel_ich_gpio32_raise},
Michael Karchera08d0f22011-07-25 17:25:24 +00002421 {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, P3, "MSI", "MS-7005 (651M-L)", 0, OK, sis_gpio0_raise_and_w836xx_memw},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002422 {0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, P3, "MSI", "MS-7025 (K8N Neo2 Platinum)", 0, OK, nvidia_mcp_gpio0c_raise},
2423 {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, P3, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise},
2424 {0x8086, 0x244b, 0x1462, 0x3910, 0x8086, 0x2442, 0x1462, 0x3910, NULL, NULL, NULL, P3, "MSI", "MS-6391 (845 Pro4)", 0, OK, intel_ich_gpio23_raise},
2425 {0x1106, 0x3149, 0x1462, 0x7061, 0x1106, 0x3227, 0, 0, NULL, NULL, NULL, P3, "MSI", "MS-7061 (KM4M-V/KM4AM-V)", 0, OK, w836xx_memw_enable_2e},
2426 {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", P3, "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio44_raise_4e},
2427 {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, P3, "MSI", "MS-7207 (K8NGM2-L)", 0, NT, nvidia_mcp_gpio2_raise},
Joshua Roys6e48a022012-06-29 23:07:14 +00002428 {0x10DE, 0x0360, 0x1462, 0x7250, 0x10DE, 0x0368, 0x1462, 0x7250, NULL, NULL, NULL, P3, "MSI", "MS-7250 (K9N SLI)", 0, OK, nvidia_mcp_gpio2_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002429 {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0},
2430 {0x8086, 0x24d3, 0x144d, 0xb025, 0x8086, 0x1050, 0x144d, 0xb025, NULL, NULL, NULL, P3, "Samsung", "Polaris 32", 0, OK, intel_ich_gpio21_raise},
2431 {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", P3, "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e},
2432 {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, P3, "Shuttle", "AK38N", 256, OK, NULL},
2433 {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, P3, "Shuttle", "FN25", 0, OK, board_shuttle_fn25},
2434 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, P3, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower},
Joshua Roysb992d342011-11-02 14:31:18 +00002435 {0x10de, 0x0364, 0x108e, 0x6676, 0x10de, 0x0369, 0x108e, 0x6676, "^Sun Ultra 40 M2", NULL, NULL, P3, "Sun", "Ultra 40 M2", 0, OK, board_sun_ultra_40_m2},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002436 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, P3, "Tekram", "P6Pro-A5", 256, OK, NULL},
2437 {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, P3, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e},
Michael Karcherbfd89a52012-02-12 00:13:14 +00002438 {0x8086, 0x7120, 0x109f, 0x3157, 0x8086, 0x2410, 0, 0, NULL, NULL, NULL, P3, "TriGem", "Anaheim-3", 0, OK, intel_ich_gpio22_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002439 {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, P3, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e},
2440 {0x1106, 0x0259, 0x1106, 0xAA07, 0x1106, 0x3227, 0x1106, 0xAA07, NULL, NULL, NULL, P3, "VIA", "EPIA EK", 0, NT, via_vt823x_gpio9_raise},
2441 {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, P3, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise},
2442 {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, P3, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise},
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00002443#endif
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002444 { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, P3, NULL, NULL, 0, NT, NULL}, /* end marker */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002445};
2446
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002447/* Parse the <vendor>:<board> string specified by the user as part of -p internal:mainboard=<vendor>:<board>.
2448 * Parameters vendor and model will be overwritten. Returns 0 on success.
2449 * Note: strtok modifies the original string, so we work on a copy and allocate memory for the results.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002450 */
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002451int board_parse_parameter(const char *boardstring, const char **vendor, const char **model)
2452{
2453 /* strtok may modify the original string. */
2454 char *tempstr = strdup(boardstring);
2455 char *tempstr2 = NULL;
2456 strtok(tempstr, ":");
2457 tempstr2 = strtok(NULL, ":");
2458 if (tempstr == NULL || tempstr2 == NULL) {
2459 free(tempstr);
2460 msg_pinfo("Please supply the board vendor and model name with the "
2461 "-p internal:mainboard=<vendor>:<model> option.\n");
2462 return 1;
2463 }
2464 *vendor = strdup(tempstr);
2465 *model = strdup(tempstr2);
2466 msg_pspew("-p internal:mainboard: vendor=\"%s\", model=\"%s\"\n", tempstr, tempstr2);
2467 free(tempstr);
2468 return 0;
2469}
2470
2471/*
2472 * Match boards on vendor and model name.
2473 * Hint: the parameters can come either from the coreboot table or the command line (i.e. the user).
2474 * Require main PCI IDs to match too as extra safety.
2475 * vendor and model must be non-NULL!
2476 */
2477static const struct board_match *board_match_name(const char *vendor, const char *model)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002478{
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002479 const struct board_match *board = board_matches;
2480 const struct board_match *partmatch = NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002481
Uwe Hermanna93045c2009-05-09 00:47:04 +00002482 for (; board->vendor_name; board++) {
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002483 if (!board->lb_vendor || strcasecmp(board->lb_vendor, vendor))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002484 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002485
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002486 if (!board->lb_part || strcasecmp(board->lb_part, model))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002487 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002488
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002489 if (!pci_dev_find(board->first_vendor, board->first_device)) {
2490 msg_pdbg("Odd. Board name \"%s\":\"%s\" matches, but first PCI device %04x:%04x "
2491 "doesn't.\n", vendor, model, board->first_vendor, board->first_device);
Uwe Hermanna7e05482007-05-09 10:17:44 +00002492 continue;
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002493 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002494
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002495 if (!pci_dev_find(board->second_vendor, board->second_device)) {
2496 msg_pdbg("Odd. Board name \"%s\":\"%s\" matches, but second PCI device %04x:%04x "
2497 "doesn't.\n", vendor, model, board->second_vendor, board->second_device);
Uwe Hermanna7e05482007-05-09 10:17:44 +00002498 continue;
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002499 }
Peter Stuge6b53fed2008-01-27 16:21:21 +00002500
2501 if (partmatch) {
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002502 /* More than one entry has a matching name. */
2503 msg_perr("Board name \"%s\":\"%s\" and PCI IDs matched more than one board enable "
2504 "entry. Please report a bug at flashrom@flashrom.org\n", vendor, model);
Peter Stuge6b53fed2008-01-27 16:21:21 +00002505 return NULL;
2506 }
2507 partmatch = board;
Uwe Hermanna7e05482007-05-09 10:17:44 +00002508 }
Uwe Hermann372eeb52007-12-04 21:49:06 +00002509
Peter Stuge6b53fed2008-01-27 16:21:21 +00002510 if (partmatch)
2511 return partmatch;
2512
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002513 msg_perr("No suitable board enable found for vendor=\"%s\", model=\"%s\".\n", vendor, model);
Uwe Hermanna7e05482007-05-09 10:17:44 +00002514 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002515}
2516
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002517/*
Uwe Hermannffec5f32007-08-23 16:08:21 +00002518 * Match boards on PCI IDs and subsystem IDs.
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002519 * Second set of IDs can be either main+subsystem IDs, main IDs or no IDs.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002520 */
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002521const static struct board_match *board_match_pci_ids(enum board_match_phase phase)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002522{
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002523 const struct board_match *board = board_matches;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002524
Uwe Hermanna93045c2009-05-09 00:47:04 +00002525 for (; board->vendor_name; board++) {
Michael Karcher2eab70d2010-02-04 10:58:50 +00002526 if ((!board->first_card_vendor || !board->first_card_device) &&
2527 !board->dmi_pattern)
Uwe Hermanna7e05482007-05-09 10:17:44 +00002528 continue;
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002529 if (board->phase != phase)
2530 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002531
Uwe Hermanna7e05482007-05-09 10:17:44 +00002532 if (!pci_card_find(board->first_vendor, board->first_device,
Uwe Hermann394131e2008-10-18 21:14:13 +00002533 board->first_card_vendor,
2534 board->first_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002535 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002536
Uwe Hermanna7e05482007-05-09 10:17:44 +00002537 if (board->second_vendor) {
2538 if (board->second_card_vendor) {
2539 if (!pci_card_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00002540 board->second_device,
2541 board->second_card_vendor,
2542 board->second_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002543 continue;
2544 } else {
2545 if (!pci_dev_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00002546 board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002547 continue;
2548 }
2549 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002550
Michael Karcher6701ee82010-01-20 14:14:11 +00002551 if (board->dmi_pattern) {
2552 if (!has_dmi_support) {
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002553 msg_perr("WARNING: Can't autodetect %s %s, DMI info unavailable.\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002554 board->vendor_name, board->board_name);
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002555 msg_pinfo("Please supply the board vendor and model name with the "
2556 "-p internal:mainboard=<vendor>:<model> option.\n");
Michael Karcher6701ee82010-01-20 14:14:11 +00002557 continue;
2558 } else {
2559 if (!dmi_match(board->dmi_pattern))
2560 continue;
2561 }
2562 }
2563
Uwe Hermanna7e05482007-05-09 10:17:44 +00002564 return board;
2565 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002566
Uwe Hermanna7e05482007-05-09 10:17:44 +00002567 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002568}
2569
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002570static int board_enable_safetycheck(const struct board_match *board)
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002571{
2572 if (!board)
2573 return 1;
2574
2575 if (board->status == OK)
2576 return 0;
2577
2578 if (!force_boardenable) {
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002579 msg_pinfo("WARNING: The mainboard-specific code for %s %s has not been tested,\n"
2580 "and thus will not be executed by default. Depending on your hardware,\n"
2581 "erasing, writing or even probing can fail without running this code.\n\n"
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002582 "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n"
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002583 "\"internal programmer\") for details.\n", board->vendor_name, board->board_name);
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002584 return 1;
2585 }
2586 msg_pinfo("NOTE: Running an untested board enable procedure.\n"
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002587 "Please report success/failure to flashrom@flashrom.org.\n");
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002588 return 0;
2589}
2590
2591/* FIXME: Should this be identical to board_flash_enable? */
2592static int board_handle_phase(enum board_match_phase phase)
2593{
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002594 const struct board_match *board = NULL;
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002595
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002596 board = board_match_pci_ids(phase);
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002597
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002598 if (!board)
2599 return 0;
2600
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002601 if (board_enable_safetycheck(board))
2602 return 0;
2603
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002604 if (!board->enable) {
2605 /* Not sure if there is a valid case for this. */
2606 msg_perr("Board match found, but nothing to do?\n");
2607 return 0;
2608 }
2609
2610 return board->enable();
2611}
2612
2613void board_handle_before_superio(void)
2614{
2615 board_handle_phase(P1);
2616}
2617
2618void board_handle_before_laptop(void)
2619{
2620 board_handle_phase(P2);
2621}
2622
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002623int board_flash_enable(const char *vendor, const char *model)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002624{
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002625 const struct board_match *board = NULL;
Uwe Hermanna7e05482007-05-09 10:17:44 +00002626 int ret = 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002627
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002628 if (vendor && model) {
2629 board = board_match_name(vendor, model);
2630 if (!board) /* if a board was given it has to match, else we abort here. */
2631 return 1;
2632 } else {
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002633 board = board_match_pci_ids(P3);
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002634 if (!board) /* i.e. there is just no board enable available for this board */
2635 return 0;
2636 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002637
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002638 if (board_enable_safetycheck(board))
2639 return 1;
Michael Karcher7f0c3ec2010-03-07 22:29:28 +00002640
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002641 /* limit the maximum size of the parallel bus */
2642 if (board->max_rom_decode_parallel)
2643 max_rom_decode.parallel = board->max_rom_decode_parallel * 1024;
Luc Verhaegen93938c32010-01-20 14:45:03 +00002644
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002645 if (board->enable != NULL) {
2646 msg_pinfo("Enabling full flash access for board \"%s %s\"... ",
2647 board->vendor_name, board->board_name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002648
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002649 ret = board->enable();
2650 if (ret)
2651 msg_pinfo("FAILED!\n");
2652 else
2653 msg_pinfo("OK.\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +00002654 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002655
Uwe Hermanna7e05482007-05-09 10:17:44 +00002656 return ret;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002657}