Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1 | /* |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 2 | * This file is part of the flashrom project. |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 3 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 4 | * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de> |
| 5 | * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de> |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 6 | * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be> |
Carl-Daniel Hailfinger | 9224262 | 2007-09-27 14:29:57 +0000 | [diff] [blame] | 7 | * Copyright (C) 2007 Carl-Daniel Hailfinger |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 8 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; version 2 of the License. |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 12 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 21 | */ |
| 22 | |
| 23 | /* |
| 24 | * Contains the board specific flash enables. |
| 25 | */ |
| 26 | |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 27 | #include <string.h> |
Mart Raudsepp | faa62fb | 2008-02-20 11:11:18 +0000 | [diff] [blame] | 28 | #include <fcntl.h> |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 29 | #include "flash.h" |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 30 | |
Luc Verhaegen | 7977f4e | 2007-05-04 04:47:04 +0000 | [diff] [blame] | 31 | /* |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 32 | * Helper functions for many Winbond Super I/Os of the W836xx range. |
Luc Verhaegen | 7977f4e | 2007-05-04 04:47:04 +0000 | [diff] [blame] | 33 | */ |
Luc Verhaegen | 7977f4e | 2007-05-04 04:47:04 +0000 | [diff] [blame] | 34 | /* Enter extended functions */ |
Peter Stuge | 9d9399c | 2009-01-26 02:34:51 +0000 | [diff] [blame] | 35 | void w836xx_ext_enter(uint16_t port) |
Mondrian Nuessle | aef1c7c | 2007-05-03 10:09:23 +0000 | [diff] [blame] | 36 | { |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 37 | OUTB(0x87, port); |
| 38 | OUTB(0x87, port); |
Luc Verhaegen | 7977f4e | 2007-05-04 04:47:04 +0000 | [diff] [blame] | 39 | } |
Mondrian Nuessle | aef1c7c | 2007-05-03 10:09:23 +0000 | [diff] [blame] | 40 | |
Luc Verhaegen | 7977f4e | 2007-05-04 04:47:04 +0000 | [diff] [blame] | 41 | /* Leave extended functions */ |
Peter Stuge | 9d9399c | 2009-01-26 02:34:51 +0000 | [diff] [blame] | 42 | void w836xx_ext_leave(uint16_t port) |
Luc Verhaegen | 7977f4e | 2007-05-04 04:47:04 +0000 | [diff] [blame] | 43 | { |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 44 | OUTB(0xAA, port); |
Luc Verhaegen | 7977f4e | 2007-05-04 04:47:04 +0000 | [diff] [blame] | 45 | } |
Mondrian Nuessle | aef1c7c | 2007-05-03 10:09:23 +0000 | [diff] [blame] | 46 | |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 47 | /* Generic Super I/O helper functions */ |
| 48 | uint8_t sio_read(uint16_t port, uint8_t reg) |
Luc Verhaegen | 7977f4e | 2007-05-04 04:47:04 +0000 | [diff] [blame] | 49 | { |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 50 | OUTB(reg, port); |
| 51 | return INB(port + 1); |
Luc Verhaegen | 7977f4e | 2007-05-04 04:47:04 +0000 | [diff] [blame] | 52 | } |
Mondrian Nuessle | aef1c7c | 2007-05-03 10:09:23 +0000 | [diff] [blame] | 53 | |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 54 | void sio_write(uint16_t port, uint8_t reg, uint8_t data) |
Luc Verhaegen | 7977f4e | 2007-05-04 04:47:04 +0000 | [diff] [blame] | 55 | { |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 56 | OUTB(reg, port); |
| 57 | OUTB(data, port + 1); |
Luc Verhaegen | 7977f4e | 2007-05-04 04:47:04 +0000 | [diff] [blame] | 58 | } |
Mondrian Nuessle | aef1c7c | 2007-05-03 10:09:23 +0000 | [diff] [blame] | 59 | |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 60 | void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask) |
Luc Verhaegen | 7977f4e | 2007-05-04 04:47:04 +0000 | [diff] [blame] | 61 | { |
Ronald G. Minnich | fa49692 | 2007-10-12 21:22:40 +0000 | [diff] [blame] | 62 | uint8_t tmp; |
Mondrian Nuessle | aef1c7c | 2007-05-03 10:09:23 +0000 | [diff] [blame] | 63 | |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 64 | OUTB(reg, port); |
| 65 | tmp = INB(port + 1) & ~mask; |
| 66 | OUTB(tmp | (data & mask), port + 1); |
Mondrian Nuessle | aef1c7c | 2007-05-03 10:09:23 +0000 | [diff] [blame] | 67 | } |
| 68 | |
Carl-Daniel Hailfinger | 14e100c | 2009-12-22 23:42:04 +0000 | [diff] [blame] | 69 | /* Not used yet. */ |
| 70 | #if 0 |
| 71 | static int enable_flash_decode_superio(void) |
| 72 | { |
| 73 | int ret; |
| 74 | uint8_t tmp; |
| 75 | |
| 76 | switch (superio.vendor) { |
| 77 | case SUPERIO_VENDOR_NONE: |
| 78 | ret = -1; |
| 79 | break; |
| 80 | case SUPERIO_VENDOR_ITE: |
| 81 | enter_conf_mode_ite(superio.port); |
| 82 | /* Enable flash mapping. Works for most old ITE style SuperI/O. */ |
| 83 | tmp = sio_read(superio.port, 0x24); |
| 84 | tmp |= 0xfc; |
| 85 | sio_write(superio.port, 0x24, tmp); |
| 86 | exit_conf_mode_ite(superio.port); |
| 87 | ret = 0; |
| 88 | break; |
| 89 | default: |
| 90 | printf_debug("Unhandled SuperI/O type!\n"); |
| 91 | ret = -1; |
| 92 | break; |
| 93 | } |
| 94 | return ret; |
| 95 | } |
| 96 | #endif |
| 97 | |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 98 | /** |
| 99 | * Winbond W83627HF: Raise GPIO24. |
Luc Verhaegen | 7977f4e | 2007-05-04 04:47:04 +0000 | [diff] [blame] | 100 | * |
| 101 | * Suited for: |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 102 | * - Agami Aruma |
| 103 | * - IWILL DK8-HTX |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 104 | */ |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 105 | static int w83627hf_gpio24_raise(uint16_t port, const char *name) |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 106 | { |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 107 | w836xx_ext_enter(port); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 108 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 109 | /* Is this the W83627HF? */ |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 110 | if (sio_read(port, 0x20) != 0x52) { /* Super I/O device ID reg. */ |
Luc Verhaegen | 7977f4e | 2007-05-04 04:47:04 +0000 | [diff] [blame] | 111 | fprintf(stderr, "\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n", |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 112 | name, sio_read(port, 0x20)); |
| 113 | w836xx_ext_leave(port); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 114 | return -1; |
| 115 | } |
| 116 | |
Luc Verhaegen | 7977f4e | 2007-05-04 04:47:04 +0000 | [diff] [blame] | 117 | /* PIN89S: WDTO/GP24 multiplex -> GPIO24 */ |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 118 | sio_mask(port, 0x2B, 0x10, 0x10); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 119 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 120 | /* Select logical device 8: GPIO port 2 */ |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 121 | sio_write(port, 0x07, 0x08); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 122 | |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 123 | sio_mask(port, 0x30, 0x01, 0x01); /* Activate logical device. */ |
| 124 | sio_mask(port, 0xF0, 0x00, 0x10); /* GPIO24 -> output */ |
| 125 | sio_mask(port, 0xF2, 0x00, 0x10); /* Clear GPIO24 inversion */ |
| 126 | sio_mask(port, 0xF1, 0x10, 0x10); /* Raise GPIO24 */ |
Luc Verhaegen | 7977f4e | 2007-05-04 04:47:04 +0000 | [diff] [blame] | 127 | |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 128 | w836xx_ext_leave(port); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 129 | |
| 130 | return 0; |
| 131 | } |
| 132 | |
Ronald G. Minnich | fa49692 | 2007-10-12 21:22:40 +0000 | [diff] [blame] | 133 | static int w83627hf_gpio24_raise_2e(const char *name) |
| 134 | { |
Mondrian nuessle | 197d6cd | 2009-04-09 14:28:36 +0000 | [diff] [blame] | 135 | return w83627hf_gpio24_raise(0x2e, name); |
Ronald G. Minnich | fa49692 | 2007-10-12 21:22:40 +0000 | [diff] [blame] | 136 | } |
| 137 | |
| 138 | /** |
| 139 | * Winbond W83627THF: GPIO 4, bit 4 |
| 140 | * |
| 141 | * Suited for: |
Peter Stuge | cce2682 | 2008-07-21 17:48:40 +0000 | [diff] [blame] | 142 | * - MSI K8T Neo2-F |
Ronald G. Minnich | fa49692 | 2007-10-12 21:22:40 +0000 | [diff] [blame] | 143 | * - MSI K8N-NEO3 |
| 144 | */ |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 145 | static int w83627thf_gpio4_4_raise(uint16_t port, const char *name) |
Ronald G. Minnich | fa49692 | 2007-10-12 21:22:40 +0000 | [diff] [blame] | 146 | { |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 147 | w836xx_ext_enter(port); |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 148 | |
| 149 | /* Is this the W83627THF? */ |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 150 | if (sio_read(port, 0x20) != 0x82) { /* Super I/O device ID reg. */ |
Ronald G. Minnich | fa49692 | 2007-10-12 21:22:40 +0000 | [diff] [blame] | 151 | fprintf(stderr, "\nERROR: %s: W83627THF: Wrong ID: 0x%02X.\n", |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 152 | name, sio_read(port, 0x20)); |
| 153 | w836xx_ext_leave(port); |
Ronald G. Minnich | fa49692 | 2007-10-12 21:22:40 +0000 | [diff] [blame] | 154 | return -1; |
| 155 | } |
| 156 | |
| 157 | /* PINxxxxS: GPIO4/bit 4 multiplex -> GPIOXXX */ |
| 158 | |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 159 | sio_write(port, 0x07, 0x09); /* Select LDN 9: GPIO port 4 */ |
| 160 | sio_mask(port, 0x30, 0x02, 0x02); /* Activate logical device. */ |
| 161 | sio_mask(port, 0xF4, 0x00, 0x10); /* GPIO4 bit 4 -> output */ |
| 162 | sio_mask(port, 0xF6, 0x00, 0x10); /* Clear GPIO4 bit 4 inversion */ |
| 163 | sio_mask(port, 0xF5, 0x10, 0x10); /* Raise GPIO4 bit 4 */ |
Ronald G. Minnich | fa49692 | 2007-10-12 21:22:40 +0000 | [diff] [blame] | 164 | |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 165 | w836xx_ext_leave(port); |
Ronald G. Minnich | fa49692 | 2007-10-12 21:22:40 +0000 | [diff] [blame] | 166 | |
| 167 | return 0; |
| 168 | } |
| 169 | |
Peter Stuge | cce2682 | 2008-07-21 17:48:40 +0000 | [diff] [blame] | 170 | static int w83627thf_gpio4_4_raise_2e(const char *name) |
| 171 | { |
| 172 | return w83627thf_gpio4_4_raise(0x2e, name); |
| 173 | } |
| 174 | |
Ronald G. Minnich | fa49692 | 2007-10-12 21:22:40 +0000 | [diff] [blame] | 175 | static int w83627thf_gpio4_4_raise_4e(const char *name) |
| 176 | { |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 177 | return w83627thf_gpio4_4_raise(0x4e, name); |
Ronald G. Minnich | fa49692 | 2007-10-12 21:22:40 +0000 | [diff] [blame] | 178 | } |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 179 | |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 180 | /** |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 181 | * w83627: Enable MEMW# and set ROM size to max. |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 182 | */ |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 183 | static void w836xx_memw_enable(uint16_t port) |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 184 | { |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 185 | w836xx_ext_enter(port); |
| 186 | if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */ |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 187 | /* Enable MEMW# and set ROM size select to max. (4M). */ |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 188 | sio_mask(port, 0x24, 0x28, 0x28); |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 189 | } |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 190 | w836xx_ext_leave(port); |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 191 | } |
| 192 | |
| 193 | /** |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 194 | * Suited for: |
| 195 | * - EPoX EP-8K5A2: VIA KT333 + VT8235. |
| 196 | * - Albatron PM266A Pro: VIA P4M266A + VT8235. |
| 197 | * - Shuttle AK31 (all versions): VIA KT266 + VT8233. |
| 198 | * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235 |
| 199 | * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237. |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 200 | */ |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 201 | static int w836xx_memw_enable_2e(const char *name) |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 202 | { |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 203 | w836xx_memw_enable(0x2E); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 204 | |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 205 | return 0; |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 206 | } |
| 207 | |
Luc Verhaegen | 21f5496 | 2010-01-20 14:45:07 +0000 | [diff] [blame] | 208 | /** |
| 209 | * |
| 210 | */ |
| 211 | static int it8705f_write_enable(uint8_t port, const char *name) |
| 212 | { |
| 213 | enter_conf_mode_ite(port); |
| 214 | sio_mask(port, 0x24, 0x04, 0x04); /* Flash ROM I/F Writes Enable */ |
| 215 | exit_conf_mode_ite(port); |
| 216 | |
| 217 | return 0; |
| 218 | } |
| 219 | |
| 220 | /** |
| 221 | * Suited for: |
| 222 | * - AOpen vKM400Am-S: VIA KM400 + VT8237 + IT8705F. |
| 223 | * - Biostar P4M80-M4: VIA P4M800 + VT8237 + IT8705AF |
| 224 | * - Elitegroup K7S6A: SiS745 + ITE IT8705F |
| 225 | * - Elitegroup K7VTA3: VIA Apollo KT266/A/333 + VIA VT8235 + ITE IT8705F |
| 226 | * - GIGABYTE GA-7VT600: VIA KT600 + VT8237 + IT8705 |
| 227 | * - Shuttle AK38N: VIA KT333CF + VIA VT8235 + ITE IT8705F |
| 228 | * |
| 229 | * SIS950 superio probably requires the same flash write enable. |
| 230 | */ |
| 231 | static int it8705f_write_enable_2e(const char *name) |
| 232 | { |
| 233 | return it8705f_write_enable(0x2e, name); |
| 234 | } |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 235 | |
Michael Karcher | 5fbd18d | 2010-02-27 18:35:54 +0000 | [diff] [blame] | 236 | static int pc87360_gpio_set(uint8_t gpio, int raise) |
| 237 | { |
| 238 | static const int bankbase[] = {0, 4, 8, 10, 12}; |
| 239 | int gpio_bank = gpio / 8; |
| 240 | int gpio_pin = gpio % 8; |
| 241 | uint16_t baseport; |
| 242 | uint8_t id; |
| 243 | uint8_t val; |
| 244 | |
| 245 | if (gpio_bank > 4) |
| 246 | { |
| 247 | fprintf(stderr, "PC87360: Invalid GPIO %d\n", gpio); |
| 248 | return -1; |
| 249 | } |
| 250 | |
| 251 | id = sio_read(0x2E, 0x20); |
| 252 | if (id != 0xE1) |
| 253 | { |
| 254 | fprintf(stderr, "PC87360: unexpected ID %02x\n", id); |
| 255 | return -1; |
| 256 | } |
| 257 | |
| 258 | sio_write(0x2E, 0x07, 0x07); /* select GPIO device */ |
| 259 | baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61); |
| 260 | if((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) |
| 261 | { |
| 262 | fprintf (stderr, "PC87360: invalid GPIO base address %04x\n", |
| 263 | baseport); |
| 264 | return -1; |
| 265 | } |
| 266 | sio_mask (0x2E, 0x30, 0x01, 0x01); /* Enable logical device */ |
| 267 | sio_write(0x2E, 0xF0, gpio_bank*16 + gpio_pin); |
| 268 | sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output */ |
| 269 | |
| 270 | val = INB(baseport + bankbase[gpio_bank]); |
| 271 | if(raise) |
| 272 | val |= 1 << gpio_pin; |
| 273 | else |
| 274 | val &= ~(1 << gpio_pin); |
| 275 | OUTB(val, baseport + bankbase[gpio_bank]); |
| 276 | |
| 277 | return 0; |
| 278 | } |
| 279 | |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 280 | /** |
| 281 | * VT823x: Set one of the GPIO pins. |
| 282 | */ |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 283 | static int via_vt823x_gpio_set(uint8_t gpio, int raise) |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 284 | { |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 285 | struct pci_dev *dev; |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 286 | uint16_t base; |
David Bartley | f58d364 | 2009-12-09 07:53:01 +0000 | [diff] [blame] | 287 | uint8_t val, bit, offset; |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 288 | |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 289 | dev = pci_dev_find_vendorclass(0x1106, 0x0601); |
| 290 | switch (dev->device_id) { |
| 291 | case 0x3177: /* VT8235 */ |
| 292 | case 0x3227: /* VT8237R */ |
| 293 | case 0x3337: /* VT8237A */ |
| 294 | break; |
| 295 | default: |
| 296 | fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n"); |
| 297 | return -1; |
| 298 | } |
| 299 | |
Jon Harrison | 2eeff4e | 2009-06-19 13:53:59 +0000 | [diff] [blame] | 300 | if ((gpio >= 12) && (gpio <= 15)) { |
| 301 | /* GPIO12-15 -> output */ |
| 302 | val = pci_read_byte(dev, 0xE4); |
| 303 | val |= 0x10; |
| 304 | pci_write_byte(dev, 0xE4, val); |
| 305 | } else if (gpio == 9) { |
| 306 | /* GPIO9 -> Output */ |
| 307 | val = pci_read_byte(dev, 0xE4); |
| 308 | val |= 0x20; |
| 309 | pci_write_byte(dev, 0xE4, val); |
David Bartley | f58d364 | 2009-12-09 07:53:01 +0000 | [diff] [blame] | 310 | } else if (gpio == 5) { |
| 311 | val = pci_read_byte(dev, 0xE4); |
| 312 | val |= 0x01; |
| 313 | pci_write_byte(dev, 0xE4, val); |
Jon Harrison | 2eeff4e | 2009-06-19 13:53:59 +0000 | [diff] [blame] | 314 | } else { |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 315 | fprintf(stderr, "\nERROR: " |
| 316 | "VT823x GPIO%02d is not implemented.\n", gpio); |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 317 | return -1; |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 318 | } |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 319 | |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 320 | /* We need the I/O Base Address for this board's flash enable. */ |
| 321 | base = pci_read_word(dev, 0x88) & 0xff80; |
| 322 | |
David Bartley | f58d364 | 2009-12-09 07:53:01 +0000 | [diff] [blame] | 323 | offset = 0x4C + gpio / 8; |
| 324 | bit = 0x01 << (gpio % 8); |
| 325 | |
| 326 | val = INB(base + offset); |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 327 | if (raise) |
| 328 | val |= bit; |
| 329 | else |
| 330 | val &= ~bit; |
David Bartley | f58d364 | 2009-12-09 07:53:01 +0000 | [diff] [blame] | 331 | OUTB(val, base + offset); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 332 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 333 | return 0; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 334 | } |
| 335 | |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 336 | /** |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 337 | * Suited for Asus M2V-MX: VIA K8M890 + VT8237A + IT8716F |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 338 | */ |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 339 | static int via_vt823x_gpio5_raise(const char *name) |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 340 | { |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 341 | /* On M2V-MX: GPO5 is connected to WP# and TBL#. */ |
| 342 | return via_vt823x_gpio_set(5, 1); |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 343 | } |
| 344 | |
| 345 | /** |
Jon Harrison | 2eeff4e | 2009-06-19 13:53:59 +0000 | [diff] [blame] | 346 | * Suited for VIAs EPIA N & NL. |
| 347 | */ |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 348 | static int via_vt823x_gpio9_raise(const char *name) |
Jon Harrison | 2eeff4e | 2009-06-19 13:53:59 +0000 | [diff] [blame] | 349 | { |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 350 | return via_vt823x_gpio_set(9, 1); |
Jon Harrison | 2eeff4e | 2009-06-19 13:53:59 +0000 | [diff] [blame] | 351 | } |
| 352 | |
| 353 | /** |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 354 | * Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs. |
| 355 | * |
| 356 | * We don't need to do this for EPIA M when using coreboot, GPIO15 is never |
| 357 | * lowered there. |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 358 | */ |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 359 | static int via_vt823x_gpio15_raise(const char *name) |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 360 | { |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 361 | return via_vt823x_gpio_set(15, 1); |
| 362 | } |
| 363 | |
| 364 | /** |
| 365 | * Winbond W83697HF Super I/O + VIA VT8235 southbridge |
| 366 | * |
| 367 | * Suited for: |
| 368 | * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235 |
| 369 | * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235 |
| 370 | */ |
| 371 | static int board_msi_kt4v(const char *name) |
| 372 | { |
| 373 | int ret; |
| 374 | |
| 375 | ret = via_vt823x_gpio_set(12, 1); |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 376 | w836xx_memw_enable(0x2E); |
Luc Verhaegen | 9786608 | 2008-02-09 02:03:06 +0000 | [diff] [blame] | 377 | |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 378 | return ret; |
Luc Verhaegen | 9786608 | 2008-02-09 02:03:06 +0000 | [diff] [blame] | 379 | } |
| 380 | |
| 381 | /** |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 382 | * Suited for ASUS P5A. |
| 383 | * |
| 384 | * This is rather nasty code, but there's no way to do this cleanly. |
| 385 | * We're basically talking to some unknown device on SMBus, my guess |
| 386 | * is that it is the Winbond W83781D that lives near the DIP BIOS. |
| 387 | */ |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 388 | static int board_asus_p5a(const char *name) |
| 389 | { |
| 390 | uint8_t tmp; |
| 391 | int i; |
| 392 | |
| 393 | #define ASUSP5A_LOOP 5000 |
| 394 | |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 395 | OUTB(0x00, 0xE807); |
| 396 | OUTB(0xEF, 0xE803); |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 397 | |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 398 | OUTB(0xFF, 0xE800); |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 399 | |
| 400 | for (i = 0; i < ASUSP5A_LOOP; i++) { |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 401 | OUTB(0xE1, 0xFF); |
| 402 | if (INB(0xE800) & 0x04) |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 403 | break; |
| 404 | } |
| 405 | |
| 406 | if (i == ASUSP5A_LOOP) { |
| 407 | printf("%s: Unable to contact device.\n", name); |
| 408 | return -1; |
| 409 | } |
| 410 | |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 411 | OUTB(0x20, 0xE801); |
| 412 | OUTB(0x20, 0xE1); |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 413 | |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 414 | OUTB(0xFF, 0xE802); |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 415 | |
| 416 | for (i = 0; i < ASUSP5A_LOOP; i++) { |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 417 | tmp = INB(0xE800); |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 418 | if (tmp & 0x70) |
| 419 | break; |
| 420 | } |
| 421 | |
| 422 | if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) { |
| 423 | printf("%s: failed to read device.\n", name); |
| 424 | return -1; |
| 425 | } |
| 426 | |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 427 | tmp = INB(0xE804); |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 428 | tmp &= ~0x02; |
| 429 | |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 430 | OUTB(0x00, 0xE807); |
| 431 | OUTB(0xEE, 0xE803); |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 432 | |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 433 | OUTB(tmp, 0xE804); |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 434 | |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 435 | OUTB(0xFF, 0xE800); |
| 436 | OUTB(0xE1, 0xFF); |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 437 | |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 438 | OUTB(0x20, 0xE801); |
| 439 | OUTB(0x20, 0xE1); |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 440 | |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 441 | OUTB(0xFF, 0xE802); |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 442 | |
| 443 | for (i = 0; i < ASUSP5A_LOOP; i++) { |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 444 | tmp = INB(0xE800); |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 445 | if (tmp & 0x70) |
| 446 | break; |
| 447 | } |
| 448 | |
| 449 | if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) { |
| 450 | printf("%s: failed to write to device.\n", name); |
| 451 | return -1; |
| 452 | } |
| 453 | |
| 454 | return 0; |
| 455 | } |
| 456 | |
Luc Verhaegen | a7e3050 | 2009-12-09 11:39:02 +0000 | [diff] [blame] | 457 | /* |
| 458 | * Set GPIO lines in the Broadcom HT-1000 southbridge. |
| 459 | * |
| 460 | * It's not a Super I/O but it uses the same index/data port method. |
| 461 | */ |
| 462 | static int board_hp_dl145_g3_enable(const char *name) |
| 463 | { |
| 464 | /* GPIO 0 reg from PM regs */ |
| 465 | /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */ |
| 466 | sio_mask(0xcd6, 0x44, 0x24, 0x24); |
| 467 | |
| 468 | return 0; |
| 469 | } |
| 470 | |
Stefan Reinauer | 1c283f4 | 2007-06-05 12:51:52 +0000 | [diff] [blame] | 471 | static int board_ibm_x3455(const char *name) |
| 472 | { |
Luc Verhaegen | a7e3050 | 2009-12-09 11:39:02 +0000 | [diff] [blame] | 473 | /* raise gpio13 */ |
Carl-Daniel Hailfinger | 500b423 | 2009-06-01 21:30:42 +0000 | [diff] [blame] | 474 | sio_mask(0xcd6, 0x45, 0x20, 0x20); |
Stefan Reinauer | 1c283f4 | 2007-06-05 12:51:52 +0000 | [diff] [blame] | 475 | |
| 476 | return 0; |
| 477 | } |
| 478 | |
Luc Verhaegen | 48f34c6 | 2009-06-03 07:50:39 +0000 | [diff] [blame] | 479 | /** |
Luc Verhaegen | 20fdce1 | 2009-10-21 12:05:50 +0000 | [diff] [blame] | 480 | * Suited for Shuttle FN25 (SN25P): AMD S939 + Nvidia CK804 (nForce4). |
| 481 | */ |
| 482 | static int board_shuttle_fn25(const char *name) |
| 483 | { |
| 484 | struct pci_dev *dev; |
| 485 | |
| 486 | dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA Bridge. */ |
| 487 | if (!dev) { |
| 488 | fprintf(stderr, |
| 489 | "\nERROR: NVIDIA nForce4 ISA bridge not found.\n"); |
| 490 | return -1; |
| 491 | } |
| 492 | |
| 493 | /* one of those bits seems to be connected to TBL#, but -ENOINFO. */ |
| 494 | pci_write_byte(dev, 0x92, 0); |
| 495 | |
| 496 | return 0; |
| 497 | } |
| 498 | |
| 499 | /** |
Luc Verhaegen | 96f88fb | 2009-12-03 12:25:34 +0000 | [diff] [blame] | 500 | * Very similar to AMD 8111 IO Hub. |
Luc Verhaegen | 8ff741e | 2009-10-05 16:07:00 +0000 | [diff] [blame] | 501 | */ |
Luc Verhaegen | 96f88fb | 2009-12-03 12:25:34 +0000 | [diff] [blame] | 502 | static int nvidia_mcp_gpio_set(int gpio, int raise) |
Luc Verhaegen | 8ff741e | 2009-10-05 16:07:00 +0000 | [diff] [blame] | 503 | { |
Luc Verhaegen | 96f88fb | 2009-12-03 12:25:34 +0000 | [diff] [blame] | 504 | struct pci_dev *dev; |
Luc Verhaegen | 8ff741e | 2009-10-05 16:07:00 +0000 | [diff] [blame] | 505 | uint16_t base; |
| 506 | uint8_t tmp; |
| 507 | |
Luc Verhaegen | 23ebd75 | 2009-12-22 13:04:13 +0000 | [diff] [blame] | 508 | if ((gpio < 0) || (gpio >= 0x40)) { |
Luc Verhaegen | 96f88fb | 2009-12-03 12:25:34 +0000 | [diff] [blame] | 509 | fprintf(stderr, "\nERROR: unsupported GPIO: %d.\n", gpio); |
Luc Verhaegen | 48f34c6 | 2009-06-03 07:50:39 +0000 | [diff] [blame] | 510 | return -1; |
| 511 | } |
| 512 | |
Luc Verhaegen | 23ebd75 | 2009-12-22 13:04:13 +0000 | [diff] [blame] | 513 | /* First, check the ISA Bridge */ |
| 514 | dev = pci_dev_find_vendorclass(0x10DE, 0x0601); |
Luc Verhaegen | 96f88fb | 2009-12-03 12:25:34 +0000 | [diff] [blame] | 515 | switch (dev->device_id) { |
| 516 | case 0x0030: /* CK804 */ |
| 517 | case 0x0050: /* MCP04 */ |
| 518 | case 0x0060: /* MCP2 */ |
| 519 | break; |
| 520 | default: |
Luc Verhaegen | 23ebd75 | 2009-12-22 13:04:13 +0000 | [diff] [blame] | 521 | /* Newer MCPs use the SMBus Controller */ |
| 522 | dev = pci_dev_find_vendorclass(0x10DE, 0x0C05); |
| 523 | switch (dev->device_id) { |
| 524 | case 0x0264: /* MCP51 */ |
| 525 | break; |
| 526 | default: |
| 527 | fprintf(stderr, |
| 528 | "\nERROR: no nVidia LPC/SMBus controller found.\n"); |
Luc Verhaegen | 96f88fb | 2009-12-03 12:25:34 +0000 | [diff] [blame] | 529 | return -1; |
Luc Verhaegen | 23ebd75 | 2009-12-22 13:04:13 +0000 | [diff] [blame] | 530 | } |
| 531 | break; |
Luc Verhaegen | 96f88fb | 2009-12-03 12:25:34 +0000 | [diff] [blame] | 532 | } |
| 533 | |
| 534 | base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */ |
| 535 | base += 0xC0; |
| 536 | |
| 537 | tmp = INB(base + gpio); |
| 538 | tmp &= ~0x0F; /* null lower nibble */ |
| 539 | tmp |= 0x04; /* gpio -> output. */ |
| 540 | if (raise) |
| 541 | tmp |= 0x01; |
| 542 | OUTB(tmp, base + gpio); |
Luc Verhaegen | 48f34c6 | 2009-06-03 07:50:39 +0000 | [diff] [blame] | 543 | |
| 544 | return 0; |
| 545 | } |
| 546 | |
Luc Verhaegen | 8ff741e | 2009-10-05 16:07:00 +0000 | [diff] [blame] | 547 | /** |
Michael Karcher | b2184c1 | 2010-03-07 16:42:55 +0000 | [diff] [blame] | 548 | * Suited for ASUS M2NBP-VM CSM: nVidia MCP51. |
| 549 | */ |
| 550 | static int nvidia_mcp_gpio0_raise(const char *name) |
| 551 | { |
| 552 | return nvidia_mcp_gpio_set(0x00, 1); |
| 553 | } |
| 554 | |
| 555 | /** |
Luc Verhaegen | 6c5f733 | 2009-12-23 03:01:36 +0000 | [diff] [blame] | 556 | * Suited for MSI K8N Neo4: nVidia CK804. |
Michael Karcher | 5fdf270 | 2010-03-07 16:52:59 +0000 | [diff] [blame] | 557 | * Suited for MSI K8N GM2-L: nVidia MCP51. |
Luc Verhaegen | 6c5f733 | 2009-12-23 03:01:36 +0000 | [diff] [blame] | 558 | */ |
| 559 | static int nvidia_mcp_gpio2_raise(const char *name) |
| 560 | { |
| 561 | return nvidia_mcp_gpio_set(0x02, 1); |
| 562 | } |
| 563 | |
| 564 | /** |
Luc Verhaegen | 8ff741e | 2009-10-05 16:07:00 +0000 | [diff] [blame] | 565 | * Suited for ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04. |
| 566 | */ |
Luc Verhaegen | 96f88fb | 2009-12-03 12:25:34 +0000 | [diff] [blame] | 567 | static int nvidia_mcp_gpio10_raise(const char *name) |
Luc Verhaegen | 8ff741e | 2009-10-05 16:07:00 +0000 | [diff] [blame] | 568 | { |
Luc Verhaegen | 96f88fb | 2009-12-03 12:25:34 +0000 | [diff] [blame] | 569 | return nvidia_mcp_gpio_set(0x10, 1); |
| 570 | } |
Luc Verhaegen | 8ff741e | 2009-10-05 16:07:00 +0000 | [diff] [blame] | 571 | |
Luc Verhaegen | 96f88fb | 2009-12-03 12:25:34 +0000 | [diff] [blame] | 572 | /** |
| 573 | * Suited for the Gigabyte GA-K8N-SLI: CK804 southbridge. |
| 574 | */ |
| 575 | static int nvidia_mcp_gpio21_raise(const char *name) |
| 576 | { |
| 577 | return nvidia_mcp_gpio_set(0x21, 0x01); |
Luc Verhaegen | 8ff741e | 2009-10-05 16:07:00 +0000 | [diff] [blame] | 578 | } |
| 579 | |
Luc Verhaegen | 2c04fab | 2009-10-05 18:46:35 +0000 | [diff] [blame] | 580 | /** |
| 581 | * Suited for EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2. |
| 582 | */ |
Luc Verhaegen | 96f88fb | 2009-12-03 12:25:34 +0000 | [diff] [blame] | 583 | static int nvidia_mcp_gpio31_raise(const char *name) |
Luc Verhaegen | 2c04fab | 2009-10-05 18:46:35 +0000 | [diff] [blame] | 584 | { |
Luc Verhaegen | 96f88fb | 2009-12-03 12:25:34 +0000 | [diff] [blame] | 585 | return nvidia_mcp_gpio_set(0x31, 0x01); |
Luc Verhaegen | 2c04fab | 2009-10-05 18:46:35 +0000 | [diff] [blame] | 586 | } |
Luc Verhaegen | 8ff741e | 2009-10-05 16:07:00 +0000 | [diff] [blame] | 587 | |
Luc Verhaegen | fdd0c58 | 2007-08-11 16:59:11 +0000 | [diff] [blame] | 588 | /** |
Mart Raudsepp | faa62fb | 2008-02-20 11:11:18 +0000 | [diff] [blame] | 589 | * Suited for Artec Group DBE61 and DBE62. |
| 590 | */ |
| 591 | static int board_artecgroup_dbe6x(const char *name) |
| 592 | { |
| 593 | #define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015 |
| 594 | #define DBE6x_PRI_BOOT_LOC_SHIFT (2) |
| 595 | #define DBE6x_BOOT_OP_LATCHED_SHIFT (8) |
| 596 | #define DBE6x_SEC_BOOT_LOC_SHIFT (10) |
| 597 | #define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT) |
| 598 | #define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT) |
| 599 | #define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT) |
| 600 | #define DBE6x_BOOT_LOC_FLASH (2) |
| 601 | #define DBE6x_BOOT_LOC_FWHUB (3) |
| 602 | |
Stefan Reinauer | b4fe664 | 2009-08-12 18:25:24 +0000 | [diff] [blame] | 603 | msr_t msr; |
Mart Raudsepp | faa62fb | 2008-02-20 11:11:18 +0000 | [diff] [blame] | 604 | unsigned long boot_loc; |
| 605 | |
Stefan Reinauer | b4fe664 | 2009-08-12 18:25:24 +0000 | [diff] [blame] | 606 | /* Geode only has a single core */ |
| 607 | if (setup_cpu_msr(0)) |
Mart Raudsepp | faa62fb | 2008-02-20 11:11:18 +0000 | [diff] [blame] | 608 | return -1; |
Mart Raudsepp | faa62fb | 2008-02-20 11:11:18 +0000 | [diff] [blame] | 609 | |
Stefan Reinauer | b4fe664 | 2009-08-12 18:25:24 +0000 | [diff] [blame] | 610 | msr = rdmsr(DBE6x_MSR_DIVIL_BALL_OPTS); |
Mart Raudsepp | faa62fb | 2008-02-20 11:11:18 +0000 | [diff] [blame] | 611 | |
Stefan Reinauer | b4fe664 | 2009-08-12 18:25:24 +0000 | [diff] [blame] | 612 | if ((msr.lo & (DBE6x_BOOT_OP_LATCHED)) == |
Mart Raudsepp | faa62fb | 2008-02-20 11:11:18 +0000 | [diff] [blame] | 613 | (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT)) |
| 614 | boot_loc = DBE6x_BOOT_LOC_FWHUB; |
| 615 | else |
| 616 | boot_loc = DBE6x_BOOT_LOC_FLASH; |
| 617 | |
Stefan Reinauer | b4fe664 | 2009-08-12 18:25:24 +0000 | [diff] [blame] | 618 | msr.lo &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC); |
| 619 | msr.lo |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) | |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 620 | (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT)); |
Mart Raudsepp | faa62fb | 2008-02-20 11:11:18 +0000 | [diff] [blame] | 621 | |
Stefan Reinauer | b4fe664 | 2009-08-12 18:25:24 +0000 | [diff] [blame] | 622 | wrmsr(DBE6x_MSR_DIVIL_BALL_OPTS, msr); |
Mart Raudsepp | faa62fb | 2008-02-20 11:11:18 +0000 | [diff] [blame] | 623 | |
Stefan Reinauer | b4fe664 | 2009-08-12 18:25:24 +0000 | [diff] [blame] | 624 | cleanup_cpu_msr(); |
Mart Raudsepp | faa62fb | 2008-02-20 11:11:18 +0000 | [diff] [blame] | 625 | |
Mart Raudsepp | faa62fb | 2008-02-20 11:11:18 +0000 | [diff] [blame] | 626 | return 0; |
| 627 | } |
| 628 | |
Uwe Hermann | 93f66db | 2008-05-22 21:19:38 +0000 | [diff] [blame] | 629 | /** |
Luc Verhaegen | f522691 | 2009-12-14 10:41:58 +0000 | [diff] [blame] | 630 | * Helper function to raise/drop a given gpo line on intel PIIX4{,E,M} |
| 631 | */ |
| 632 | static int intel_piix4_gpo_set(unsigned int gpo, int raise) |
| 633 | { |
Michael Karcher | 01f6d7d | 2010-02-24 00:00:21 +0000 | [diff] [blame] | 634 | unsigned int gpo_byte, gpo_bit; |
Luc Verhaegen | f522691 | 2009-12-14 10:41:58 +0000 | [diff] [blame] | 635 | struct pci_dev *dev; |
| 636 | uint32_t tmp, base; |
| 637 | |
| 638 | dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */ |
| 639 | if (!dev) { |
| 640 | fprintf(stderr, "\nERROR: Intel PIIX4 ISA bridge not found.\n"); |
| 641 | return -1; |
| 642 | } |
| 643 | |
| 644 | /* sanity check */ |
| 645 | if (gpo > 30) { |
| 646 | fprintf(stderr, "\nERROR: Intel PIIX4 has no GPO%d.\n", gpo); |
| 647 | return -1; |
| 648 | } |
| 649 | |
| 650 | /* these are dual function pins which are most likely in use already */ |
| 651 | if (((gpo >= 1) && (gpo <= 7)) || |
| 652 | ((gpo >= 9) && (gpo <= 21)) || (gpo == 29)) { |
| 653 | fprintf(stderr, "\nERROR: Unsupported PIIX4 GPO%d.\n", gpo); |
| 654 | return -1; |
| 655 | } |
| 656 | |
| 657 | /* dual function that need special enable. */ |
| 658 | if ((gpo >= 22) && (gpo <= 26)) { |
| 659 | tmp = pci_read_long(dev, 0xB0); /* GENCFG */ |
| 660 | switch (gpo) { |
| 661 | case 22: /* XBUS: XDIR#/GPO22 */ |
| 662 | case 23: /* XBUS: XOE#/GPO23 */ |
| 663 | tmp |= 1 << 28; |
| 664 | break; |
| 665 | case 24: /* RTCSS#/GPO24 */ |
| 666 | tmp |= 1 << 29; |
| 667 | break; |
| 668 | case 25: /* RTCALE/GPO25 */ |
| 669 | tmp |= 1 << 30; |
| 670 | break; |
| 671 | case 26: /* KBCSS#/GPO26 */ |
| 672 | tmp |= 1 << 31; |
| 673 | break; |
| 674 | } |
| 675 | pci_write_long(dev, 0xB0, tmp); |
| 676 | } |
| 677 | |
| 678 | /* GPO {0,8,27,28,30} are always available. */ |
| 679 | |
| 680 | dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */ |
| 681 | if (!dev) { |
| 682 | fprintf(stderr, "\nERROR: Intel PIIX4 PM not found.\n"); |
| 683 | return -1; |
| 684 | } |
| 685 | |
| 686 | /* PM IO base */ |
| 687 | base = pci_read_long(dev, 0x40) & 0x0000FFC0; |
| 688 | |
Michael Karcher | 01f6d7d | 2010-02-24 00:00:21 +0000 | [diff] [blame] | 689 | gpo_byte = gpo >> 3; |
| 690 | gpo_bit = gpo & 7; |
| 691 | tmp = INB(base + 0x34 + gpo_byte); /* GPO register */ |
Luc Verhaegen | f522691 | 2009-12-14 10:41:58 +0000 | [diff] [blame] | 692 | if (raise) |
Michael Karcher | 01f6d7d | 2010-02-24 00:00:21 +0000 | [diff] [blame] | 693 | tmp |= 0x01 << gpo_bit; |
Luc Verhaegen | f522691 | 2009-12-14 10:41:58 +0000 | [diff] [blame] | 694 | else |
Michael Karcher | 01f6d7d | 2010-02-24 00:00:21 +0000 | [diff] [blame] | 695 | tmp &= ~(0x01 << gpo_bit); |
| 696 | OUTB(tmp, base + 0x34 + gpo_byte); |
Luc Verhaegen | f522691 | 2009-12-14 10:41:58 +0000 | [diff] [blame] | 697 | |
| 698 | return 0; |
| 699 | } |
| 700 | |
| 701 | /** |
| 702 | * Suited for EPoX EP-BX3, and maybe some other Intel 440BX based boards. |
| 703 | */ |
| 704 | static int board_epox_ep_bx3(const char *name) |
| 705 | { |
| 706 | return intel_piix4_gpo_set(22, 1); |
| 707 | } |
| 708 | |
| 709 | /** |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 710 | * Set a GPIO line on a given intel ICH LPC controller. |
Uwe Hermann | 93f66db | 2008-05-22 21:19:38 +0000 | [diff] [blame] | 711 | */ |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 712 | static int intel_ich_gpio_set(int gpio, int raise) |
Uwe Hermann | 93f66db | 2008-05-22 21:19:38 +0000 | [diff] [blame] | 713 | { |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 714 | /* table mapping the different intel ICH LPC chipsets. */ |
| 715 | static struct { |
| 716 | uint16_t id; |
| 717 | uint8_t base_reg; |
| 718 | uint32_t bank0; |
| 719 | uint32_t bank1; |
| 720 | uint32_t bank2; |
| 721 | } intel_ich_gpio_table[] = { |
| 722 | {0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */ |
| 723 | {0x2420, 0x58, 0x0FE30000, 0, 0}, /* 82801AB (ICH0) */ |
| 724 | {0x2440, 0x58, 0x1BFF391B, 0, 0}, /* 82801BA (ICH2) */ |
| 725 | {0x244C, 0x58, 0x1A23399B, 0, 0}, /* 82801BAM (ICH2M) */ |
| 726 | {0x2450, 0x58, 0x1BFF0000, 0, 0}, /* 82801E (C-ICH) */ |
| 727 | {0x2480, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801CA (ICH3-S) */ |
| 728 | {0x248C, 0x58, 0x1A230000, 0x00000FFF, 0}, /* 82801CAM (ICH3-M) */ |
| 729 | {0x24C0, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801DB/DBL (ICH4/ICH4-L) */ |
| 730 | {0x24CC, 0x58, 0x1A030000, 0x00000FFF, 0}, /* 82801DBM (ICH4-M) */ |
| 731 | {0x24D0, 0x58, 0x1BFF0000, 0x00030305, 0}, /* 82801EB/ER (ICH5/ICH5R) */ |
| 732 | {0x2640, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FB/FR (ICH6/ICH6R) */ |
| 733 | {0x2641, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FBM (ICH6M) */ |
| 734 | {0x27B8, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GB/GR (ICH7 Family) */ |
| 735 | {0x27B9, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GBM (ICH7-M) */ |
| 736 | {0x27BD, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GHM (ICH7-M DH) */ |
| 737 | {0x2810, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HB/HR (ICH8/R) */ |
| 738 | {0x2811, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HBM (ICH8M-E) */ |
| 739 | {0x2812, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HH (ICH8DH) */ |
| 740 | {0x2814, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HO (ICH8DO) */ |
| 741 | {0x2815, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HEM (ICH8M) */ |
| 742 | {0x2912, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IH (ICH9DH) */ |
| 743 | {0x2914, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IO (ICH9DO) */ |
| 744 | {0x2916, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IR (ICH9R) */ |
| 745 | {0x2917, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IEM (ICH9M-E) */ |
| 746 | {0x2918, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IB (ICH9) */ |
| 747 | {0x2919, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IBM (ICH9M) */ |
| 748 | {0x3A14, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JDO (ICH10DO) */ |
| 749 | {0x3A16, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIR (ICH10R) */ |
| 750 | {0x3A18, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIB (ICH10) */ |
| 751 | {0x3A1A, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JD (ICH10D) */ |
| 752 | {0, 0, 0, 0, 0} /* end marker */ |
| 753 | }; |
Uwe Hermann | 93f66db | 2008-05-22 21:19:38 +0000 | [diff] [blame] | 754 | |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 755 | struct pci_dev *dev; |
| 756 | uint16_t base; |
| 757 | uint32_t tmp; |
| 758 | int i, allowed; |
| 759 | |
| 760 | /* First, look for a known LPC bridge */ |
Jonathan A. Kollasch | b87f23b | 2009-12-14 04:24:42 +0000 | [diff] [blame] | 761 | for (dev = pacc->devices; dev; dev = dev->next) { |
| 762 | pci_fill_info(dev, PCI_FILL_CLASS); |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 763 | if ((dev->vendor_id == 0x8086) && |
| 764 | (dev->device_class == 0x0601)) { /* ISA Bridge */ |
| 765 | /* Is this device in our list? */ |
| 766 | for (i = 0; intel_ich_gpio_table[i].id; i++) |
| 767 | if (dev->device_id == intel_ich_gpio_table[i].id) |
| 768 | break; |
| 769 | |
| 770 | if (intel_ich_gpio_table[i].id) |
| 771 | break; |
| 772 | } |
Jonathan A. Kollasch | b87f23b | 2009-12-14 04:24:42 +0000 | [diff] [blame] | 773 | } |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 774 | |
Uwe Hermann | 93f66db | 2008-05-22 21:19:38 +0000 | [diff] [blame] | 775 | if (!dev) { |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 776 | fprintf(stderr, "\nERROR: No Known Intel LPC Bridge found.\n"); |
Uwe Hermann | 93f66db | 2008-05-22 21:19:38 +0000 | [diff] [blame] | 777 | return -1; |
| 778 | } |
| 779 | |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 780 | /* According to the datasheets, all intel ICHs have the gpio bar 5:1 |
| 781 | strapped to zero. From some mobile ich9 version on, this becomes |
| 782 | 6:1. The mask below catches all. */ |
| 783 | base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0; |
Uwe Hermann | 93f66db | 2008-05-22 21:19:38 +0000 | [diff] [blame] | 784 | |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 785 | /* check whether the line is allowed */ |
| 786 | if (gpio < 32) |
| 787 | allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01; |
| 788 | else if (gpio < 64) |
| 789 | allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01; |
| 790 | else |
| 791 | allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01; |
| 792 | |
| 793 | if (!allowed) { |
| 794 | fprintf(stderr, "\nERROR: This Intel LPC Bridge does not allow" |
| 795 | " setting GPIO%02d\n", gpio); |
| 796 | return -1; |
| 797 | } |
| 798 | |
| 799 | printf("\nIntel ICH LPC Bridge: %sing GPIO%02d.\n", |
| 800 | raise ? "Rais" : "Dropp", gpio); |
| 801 | |
| 802 | if (gpio < 32) { |
| 803 | /* Set line to GPIO */ |
| 804 | tmp = INL(base); |
| 805 | /* ICH/ICH0 multiplexes 27/28 on the line set. */ |
| 806 | if ((gpio == 28) && |
| 807 | ((dev->device_id == 0x2410) || (dev->device_id == 0x2420))) |
| 808 | tmp |= 1 << 27; |
| 809 | else |
| 810 | tmp |= 1 << gpio; |
| 811 | OUTL(tmp, base); |
| 812 | |
| 813 | /* As soon as we are talking to ICH8 and above, this register |
| 814 | decides whether we can set the gpio or not. */ |
| 815 | if (dev->device_id > 0x2800) { |
| 816 | tmp = INL(base); |
| 817 | if (!(tmp & (1 << gpio))) { |
| 818 | fprintf(stderr, "\nERROR: This Intel LPC Bridge" |
| 819 | " does not allow setting GPIO%02d\n", |
| 820 | gpio); |
| 821 | return -1; |
| 822 | } |
| 823 | } |
| 824 | |
| 825 | /* Set GPIO to OUTPUT */ |
| 826 | tmp = INL(base + 0x04); |
| 827 | tmp &= ~(1 << gpio); |
| 828 | OUTL(tmp, base + 0x04); |
| 829 | |
| 830 | /* Raise GPIO line */ |
| 831 | tmp = INL(base + 0x0C); |
| 832 | if (raise) |
| 833 | tmp |= 1 << gpio; |
| 834 | else |
| 835 | tmp &= ~(1 << gpio); |
| 836 | OUTL(tmp, base + 0x0C); |
| 837 | } else if (gpio < 64) { |
| 838 | gpio -= 32; |
| 839 | |
| 840 | /* Set line to GPIO */ |
| 841 | tmp = INL(base + 0x30); |
| 842 | tmp |= 1 << gpio; |
| 843 | OUTL(tmp, base + 0x30); |
| 844 | |
| 845 | /* As soon as we are talking to ICH8 and above, this register |
| 846 | decides whether we can set the gpio or not. */ |
| 847 | if (dev->device_id > 0x2800) { |
| 848 | tmp = INL(base + 30); |
| 849 | if (!(tmp & (1 << gpio))) { |
| 850 | fprintf(stderr, "\nERROR: This Intel LPC Bridge" |
| 851 | " does not allow setting GPIO%02d\n", |
| 852 | gpio + 32); |
| 853 | return -1; |
| 854 | } |
| 855 | } |
| 856 | |
| 857 | /* Set GPIO to OUTPUT */ |
| 858 | tmp = INL(base + 0x34); |
| 859 | tmp &= ~(1 << gpio); |
| 860 | OUTL(tmp, base + 0x34); |
| 861 | |
| 862 | /* Raise GPIO line */ |
| 863 | tmp = INL(base + 0x38); |
| 864 | if (raise) |
| 865 | tmp |= 1 << gpio; |
| 866 | else |
| 867 | tmp &= ~(1 << gpio); |
| 868 | OUTL(tmp, base + 0x38); |
| 869 | } else { |
| 870 | gpio -= 64; |
| 871 | |
| 872 | /* Set line to GPIO */ |
| 873 | tmp = INL(base + 0x40); |
| 874 | tmp |= 1 << gpio; |
| 875 | OUTL(tmp, base + 0x40); |
| 876 | |
| 877 | tmp = INL(base + 40); |
| 878 | if (!(tmp & (1 << gpio))) { |
| 879 | fprintf(stderr, "\nERROR: This Intel LPC Bridge does " |
| 880 | "not allow setting GPIO%02d\n", gpio + 64); |
| 881 | return -1; |
| 882 | } |
| 883 | |
| 884 | /* Set GPIO to OUTPUT */ |
| 885 | tmp = INL(base + 0x44); |
| 886 | tmp &= ~(1 << gpio); |
| 887 | OUTL(tmp, base + 0x44); |
| 888 | |
| 889 | /* Raise GPIO line */ |
| 890 | tmp = INL(base + 0x48); |
| 891 | if (raise) |
| 892 | tmp |= 1 << gpio; |
| 893 | else |
| 894 | tmp &= ~(1 << gpio); |
| 895 | OUTL(tmp, base + 0x48); |
| 896 | } |
Uwe Hermann | 93f66db | 2008-05-22 21:19:38 +0000 | [diff] [blame] | 897 | |
| 898 | return 0; |
| 899 | } |
| 900 | |
| 901 | /** |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 902 | * Suited for Abit IP35: Intel P35 + ICH9R. |
Michael Karcher | b4a3d1c | 2010-03-03 16:15:12 +0000 | [diff] [blame] | 903 | * Suited for Abit IP35 Pro: Intel P35 + ICH9R. |
Uwe Hermann | 93f66db | 2008-05-22 21:19:38 +0000 | [diff] [blame] | 904 | */ |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 905 | static int intel_ich_gpio16_raise(const char *name) |
Uwe Hermann | 93f66db | 2008-05-22 21:19:38 +0000 | [diff] [blame] | 906 | { |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 907 | return intel_ich_gpio_set(16, 1); |
Uwe Hermann | 93f66db | 2008-05-22 21:19:38 +0000 | [diff] [blame] | 908 | } |
| 909 | |
Peter Stuge | 09c1333 | 2009-02-02 22:55:26 +0000 | [diff] [blame] | 910 | /** |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 911 | * Suited for MSI MS-7046: LGA775 + 915P + ICH6. |
Carl-Daniel Hailfinger | 2912426 | 2009-09-23 02:05:12 +0000 | [diff] [blame] | 912 | */ |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 913 | static int intel_ich_gpio19_raise(const char *name) |
Carl-Daniel Hailfinger | 2912426 | 2009-09-23 02:05:12 +0000 | [diff] [blame] | 914 | { |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 915 | return intel_ich_gpio_set(19, 1); |
Carl-Daniel Hailfinger | 2912426 | 2009-09-23 02:05:12 +0000 | [diff] [blame] | 916 | } |
| 917 | |
| 918 | /** |
Luc Verhaegen | 6c5d4cc | 2009-11-28 18:26:21 +0000 | [diff] [blame] | 919 | * Suited for: |
| 920 | * - Asus P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2. |
| 921 | * - Asus P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R. |
Peter Stuge | 09c1333 | 2009-02-02 22:55:26 +0000 | [diff] [blame] | 922 | */ |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 923 | static int intel_ich_gpio21_raise(const char *name) |
Peter Stuge | 09c1333 | 2009-02-02 22:55:26 +0000 | [diff] [blame] | 924 | { |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 925 | return intel_ich_gpio_set(21, 1); |
Peter Stuge | 09c1333 | 2009-02-02 22:55:26 +0000 | [diff] [blame] | 926 | } |
| 927 | |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 928 | /** |
Michael Karcher | 03b80e9 | 2010-03-07 16:32:32 +0000 | [diff] [blame] | 929 | * Suited for: |
| 930 | * - Asus P4B266: socket478 + intel 845D + ICH2. |
| 931 | * - Asus P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2 |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 932 | */ |
| 933 | static int intel_ich_gpio22_raise(const char *name) |
| 934 | { |
| 935 | return intel_ich_gpio_set(22, 1); |
| 936 | } |
| 937 | |
| 938 | /** |
Michael Karcher | 5fbd18d | 2010-02-27 18:35:54 +0000 | [diff] [blame] | 939 | * Suited for HP Vectra VL400: 815 + ICH + PC87360. |
| 940 | */ |
| 941 | |
| 942 | static int board_hp_vl400(const char *name) |
| 943 | { |
| 944 | int ret; |
| 945 | ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */ |
| 946 | if (!ret) |
| 947 | ret = pc87360_gpio_set(0x09, 1); /* #WP ? */ |
| 948 | if (!ret) |
| 949 | ret = pc87360_gpio_set(0x27, 1); /* #TBL */ |
| 950 | return ret; |
| 951 | } |
| 952 | |
| 953 | /** |
Luc Verhaegen | 1265d8d | 2009-11-28 18:16:31 +0000 | [diff] [blame] | 954 | * Suited for: |
| 955 | * - Dell Poweredge 1850: Intel PPGA604 + E7520 + ICH5R. |
| 956 | * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R. |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 957 | */ |
| 958 | static int intel_ich_gpio23_raise(const char *name) |
| 959 | { |
| 960 | return intel_ich_gpio_set(23, 1); |
| 961 | } |
| 962 | |
| 963 | /** |
| 964 | * Suited for Acorp 6A815EPD: socket 370 + intel 815 + ICH2. |
| 965 | */ |
| 966 | static int board_acorp_6a815epd(const char *name) |
| 967 | { |
| 968 | int ret; |
| 969 | |
| 970 | /* Lower Blocks Lock -- pin 7 of PLCC32 */ |
| 971 | ret = intel_ich_gpio_set(22, 1); |
| 972 | if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */ |
| 973 | ret = intel_ich_gpio_set(23, 1); |
| 974 | |
| 975 | return ret; |
| 976 | } |
| 977 | |
| 978 | /** |
| 979 | * Suited for Kontron 986LCD-M: socket478 + 915GM + ICH7R. |
| 980 | */ |
Stefan Reinauer | ac37897 | 2008-03-17 22:59:40 +0000 | [diff] [blame] | 981 | static int board_kontron_986lcd_m(const char *name) |
| 982 | { |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 983 | int ret; |
Stefan Reinauer | ac37897 | 2008-03-17 22:59:40 +0000 | [diff] [blame] | 984 | |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 985 | ret = intel_ich_gpio_set(34, 1); /* #TBL */ |
| 986 | if (!ret) |
| 987 | ret = intel_ich_gpio_set(35, 1); /* #WP */ |
Stefan Reinauer | ac37897 | 2008-03-17 22:59:40 +0000 | [diff] [blame] | 988 | |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 989 | return ret; |
Stefan Reinauer | ac37897 | 2008-03-17 22:59:40 +0000 | [diff] [blame] | 990 | } |
| 991 | |
Mart Raudsepp | faa62fb | 2008-02-20 11:11:18 +0000 | [diff] [blame] | 992 | /** |
Luc Verhaegen | 3920eda | 2009-06-17 14:43:24 +0000 | [diff] [blame] | 993 | * Suited for Soyo SY-7VCA: Pro133A + VT82C686. |
| 994 | */ |
| 995 | static int board_soyo_sy_7vca(const char *name) |
| 996 | { |
| 997 | struct pci_dev *dev; |
| 998 | uint32_t base; |
| 999 | uint8_t tmp; |
| 1000 | |
| 1001 | /* VT82C686 Power management */ |
| 1002 | dev = pci_dev_find(0x1106, 0x3057); |
| 1003 | if (!dev) { |
| 1004 | fprintf(stderr, "\nERROR: VT82C686 PM device not found.\n"); |
| 1005 | return -1; |
| 1006 | } |
| 1007 | |
| 1008 | /* GPO0 output from PM IO base + 0x4C */ |
| 1009 | tmp = pci_read_byte(dev, 0x54); |
| 1010 | tmp &= ~0x03; |
| 1011 | pci_write_byte(dev, 0x54, tmp); |
| 1012 | |
| 1013 | /* PM IO base */ |
| 1014 | base = pci_read_long(dev, 0x48) & 0x0000FF00; |
| 1015 | |
| 1016 | /* Drop GPO0 */ |
| 1017 | tmp = INB(base + 0x4C); |
| 1018 | tmp &= ~0x01; |
| 1019 | OUTB(tmp, base + 0x4C); |
| 1020 | |
| 1021 | return 0; |
| 1022 | } |
| 1023 | |
Michael Karcher | 9f9e613 | 2010-01-09 17:36:06 +0000 | [diff] [blame] | 1024 | /** |
| 1025 | * Enable some GPIO pin on SiS southbridge. |
| 1026 | * Suited for MSI 651M-L: SiS651 / SiS962 |
| 1027 | */ |
| 1028 | static int board_msi_651ml(const char *name) |
| 1029 | { |
| 1030 | struct pci_dev *dev; |
| 1031 | uint16_t base; |
| 1032 | uint16_t temp; |
| 1033 | |
| 1034 | dev = pci_dev_find(0x1039, 0x0962); |
| 1035 | if (!dev) { |
| 1036 | fprintf(stderr, "Expected south bridge not found\n"); |
| 1037 | return 1; |
| 1038 | } |
| 1039 | |
| 1040 | /* Registers 68 and 64 seem like bitmaps */ |
| 1041 | base = pci_read_word(dev, 0x74); |
| 1042 | temp = INW(base + 0x68); |
| 1043 | temp &= ~(1 << 0); /* Make pin output? */ |
Michael Karcher | 0435dfd | 2010-01-09 23:31:13 +0000 | [diff] [blame] | 1044 | OUTW(temp, base + 0x68); |
Michael Karcher | 9f9e613 | 2010-01-09 17:36:06 +0000 | [diff] [blame] | 1045 | |
| 1046 | temp = INW(base + 0x64); |
| 1047 | temp |= (1 << 0); /* Raise output? */ |
| 1048 | OUTW(temp, base + 0x64); |
| 1049 | |
| 1050 | w836xx_memw_enable(0x2E); |
| 1051 | |
| 1052 | return 0; |
| 1053 | } |
| 1054 | |
Luc Verhaegen | 3920eda | 2009-06-17 14:43:24 +0000 | [diff] [blame] | 1055 | /** |
Michael Gold | 6d52e47 | 2009-06-19 13:00:24 +0000 | [diff] [blame] | 1056 | * Find the runtime registers of an SMSC Super I/O, after verifying its |
| 1057 | * chip ID. |
| 1058 | * |
| 1059 | * Returns the base port of the runtime register block, or 0 on error. |
| 1060 | */ |
| 1061 | static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id, |
| 1062 | uint8_t logical_device) |
| 1063 | { |
| 1064 | uint16_t rt_port = 0; |
| 1065 | |
| 1066 | /* Verify the chip ID. */ |
Uwe Hermann | 1432a60 | 2009-06-28 23:26:37 +0000 | [diff] [blame] | 1067 | OUTB(0x55, sio_port); /* Enable configuration. */ |
Michael Gold | 6d52e47 | 2009-06-19 13:00:24 +0000 | [diff] [blame] | 1068 | if (sio_read(sio_port, 0x20) != chip_id) { |
Uwe Hermann | 1432a60 | 2009-06-28 23:26:37 +0000 | [diff] [blame] | 1069 | fprintf(stderr, "\nERROR: SMSC Super I/O not found.\n"); |
Michael Gold | 6d52e47 | 2009-06-19 13:00:24 +0000 | [diff] [blame] | 1070 | goto out; |
| 1071 | } |
| 1072 | |
| 1073 | /* If the runtime block is active, get its address. */ |
| 1074 | sio_write(sio_port, 0x07, logical_device); |
| 1075 | if (sio_read(sio_port, 0x30) & 1) { |
| 1076 | rt_port = (sio_read(sio_port, 0x60) << 8) |
| 1077 | | sio_read(sio_port, 0x61); |
| 1078 | } |
| 1079 | |
| 1080 | if (rt_port == 0) { |
| 1081 | fprintf(stderr, "\nERROR: " |
| 1082 | "Super I/O runtime interface not available.\n"); |
| 1083 | } |
| 1084 | out: |
Uwe Hermann | 1432a60 | 2009-06-28 23:26:37 +0000 | [diff] [blame] | 1085 | OUTB(0xaa, sio_port); /* Disable configuration. */ |
Michael Gold | 6d52e47 | 2009-06-19 13:00:24 +0000 | [diff] [blame] | 1086 | return rt_port; |
| 1087 | } |
| 1088 | |
| 1089 | /** |
| 1090 | * Disable write protection on the Mitac 6513WU. WP# on the FWH is |
| 1091 | * connected to GP30 on the Super I/O, and TBL# is always high. |
| 1092 | */ |
| 1093 | static int board_mitac_6513wu(const char *name) |
| 1094 | { |
| 1095 | struct pci_dev *dev; |
| 1096 | uint16_t rt_port; |
| 1097 | uint8_t val; |
| 1098 | |
| 1099 | dev = pci_dev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */ |
| 1100 | if (!dev) { |
| 1101 | fprintf(stderr, "\nERROR: Intel 82801AA ISA bridge not found.\n"); |
| 1102 | return -1; |
| 1103 | } |
| 1104 | |
Uwe Hermann | 1432a60 | 2009-06-28 23:26:37 +0000 | [diff] [blame] | 1105 | rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa); |
Michael Gold | 6d52e47 | 2009-06-19 13:00:24 +0000 | [diff] [blame] | 1106 | if (rt_port == 0) |
| 1107 | return -1; |
| 1108 | |
| 1109 | /* Configure the GPIO pin. */ |
| 1110 | val = INB(rt_port + 0x33); /* GP30 config */ |
Uwe Hermann | 1432a60 | 2009-06-28 23:26:37 +0000 | [diff] [blame] | 1111 | val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */ |
Michael Gold | 6d52e47 | 2009-06-19 13:00:24 +0000 | [diff] [blame] | 1112 | OUTB(val, rt_port + 0x33); |
| 1113 | |
| 1114 | /* Disable write protection. */ |
| 1115 | val = INB(rt_port + 0x4d); /* GP3 values */ |
Uwe Hermann | 1432a60 | 2009-06-28 23:26:37 +0000 | [diff] [blame] | 1116 | val |= 0x01; /* Set GP30 high. */ |
Michael Gold | 6d52e47 | 2009-06-19 13:00:24 +0000 | [diff] [blame] | 1117 | OUTB(val, rt_port + 0x4d); |
| 1118 | |
| 1119 | return 0; |
| 1120 | } |
| 1121 | |
| 1122 | /** |
Luc Verhaegen | 78e4e12 | 2009-07-13 12:40:17 +0000 | [diff] [blame] | 1123 | * Suited for Asus A7V8X: VIA KT400 + VT8235 + IT8703F-A |
| 1124 | */ |
| 1125 | static int board_asus_a7v8x(const char *name) |
| 1126 | { |
| 1127 | uint16_t id, base; |
| 1128 | uint8_t tmp; |
| 1129 | |
| 1130 | /* find the IT8703F */ |
| 1131 | w836xx_ext_enter(0x2E); |
| 1132 | id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21); |
| 1133 | w836xx_ext_leave(0x2E); |
| 1134 | |
| 1135 | if (id != 0x8701) { |
| 1136 | fprintf(stderr, "\nERROR: IT8703F SuperIO not found.\n"); |
| 1137 | return -1; |
| 1138 | } |
| 1139 | |
| 1140 | /* Get the GP567 IO base */ |
| 1141 | w836xx_ext_enter(0x2E); |
| 1142 | sio_write(0x2E, 0x07, 0x0C); |
| 1143 | base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61); |
| 1144 | w836xx_ext_leave(0x2E); |
| 1145 | |
| 1146 | if (!base) { |
| 1147 | fprintf(stderr, "\nERROR: Failed to read IT8703F SuperIO GPIO" |
| 1148 | " Base.\n"); |
| 1149 | return -1; |
| 1150 | } |
| 1151 | |
| 1152 | /* Raise GP51. */ |
| 1153 | tmp = INB(base); |
| 1154 | tmp |= 0x02; |
| 1155 | OUTB(tmp, base); |
| 1156 | |
| 1157 | return 0; |
| 1158 | } |
| 1159 | |
Luc Verhaegen | 7227291 | 2009-09-01 21:22:23 +0000 | [diff] [blame] | 1160 | /* |
| 1161 | * General routine for raising/dropping GPIO lines on the ITE IT8712F. |
| 1162 | * There is only some limited checking on the port numbers. |
| 1163 | */ |
| 1164 | static int |
| 1165 | it8712f_gpio_set(unsigned int line, int raise) |
| 1166 | { |
| 1167 | unsigned int port; |
| 1168 | uint16_t id, base; |
| 1169 | uint8_t tmp; |
| 1170 | |
| 1171 | port = line / 10; |
| 1172 | port--; |
| 1173 | line %= 10; |
| 1174 | |
| 1175 | /* Check line */ |
| 1176 | if ((port > 4) || /* also catches unsigned -1 */ |
| 1177 | ((port < 4) && (line > 7)) || ((port == 4) && (line > 5))) { |
| 1178 | fprintf(stderr, |
| 1179 | "\nERROR: Unsupported IT8712F GPIO Line %02d.\n", line); |
| 1180 | return -1; |
| 1181 | } |
| 1182 | |
| 1183 | /* find the IT8712F */ |
| 1184 | enter_conf_mode_ite(0x2E); |
| 1185 | id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21); |
| 1186 | exit_conf_mode_ite(0x2E); |
| 1187 | |
| 1188 | if (id != 0x8712) { |
| 1189 | fprintf(stderr, "\nERROR: IT8712F SuperIO not found.\n"); |
| 1190 | return -1; |
| 1191 | } |
| 1192 | |
| 1193 | /* Get the GPIO base */ |
| 1194 | enter_conf_mode_ite(0x2E); |
| 1195 | sio_write(0x2E, 0x07, 0x07); |
| 1196 | base = (sio_read(0x2E, 0x62) << 8) | sio_read(0x2E, 0x63); |
| 1197 | exit_conf_mode_ite(0x2E); |
| 1198 | |
| 1199 | if (!base) { |
| 1200 | fprintf(stderr, "\nERROR: Failed to read IT8712F SuperIO GPIO" |
| 1201 | " Base.\n"); |
| 1202 | return -1; |
| 1203 | } |
| 1204 | |
| 1205 | /* set GPIO. */ |
| 1206 | tmp = INB(base + port); |
| 1207 | if (raise) |
| 1208 | tmp |= 1 << line; |
| 1209 | else |
| 1210 | tmp &= ~(1 << line); |
| 1211 | OUTB(tmp, base + port); |
| 1212 | |
| 1213 | return 0; |
| 1214 | } |
| 1215 | |
| 1216 | /** |
Russ Dill | bd622d1 | 2010-03-09 16:57:06 +0000 | [diff] [blame^] | 1217 | * Suited for: |
| 1218 | * - Asus A7V600-X: VIA KT600 + VT8237 + IT8712F |
| 1219 | * - Asus A7V8X-X: VIA KT400 + VT8235 + IT8712F |
Luc Verhaegen | 7227291 | 2009-09-01 21:22:23 +0000 | [diff] [blame] | 1220 | */ |
Russ Dill | bd622d1 | 2010-03-09 16:57:06 +0000 | [diff] [blame^] | 1221 | static int it8712f_gpio3_1_raise(const char *name) |
Luc Verhaegen | 7227291 | 2009-09-01 21:22:23 +0000 | [diff] [blame] | 1222 | { |
| 1223 | return it8712f_gpio_set(32, 1); |
| 1224 | } |
| 1225 | |
Luc Verhaegen | 78e4e12 | 2009-07-13 12:40:17 +0000 | [diff] [blame] | 1226 | /** |
Uwe Hermann | d0e347d | 2009-10-06 13:00:00 +0000 | [diff] [blame] | 1227 | * Below is the list of boards which need a special "board enable" code in |
| 1228 | * flashrom before their ROM chip can be accessed/written to. |
| 1229 | * |
| 1230 | * NOTE: Please add boards that _don't_ need such enables or don't work yet |
| 1231 | * to the respective tables in print.c. Thanks! |
| 1232 | * |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 1233 | * We use 2 sets of IDs here, you're free to choose which is which. This |
| 1234 | * is to provide a very high degree of certainty when matching a board on |
| 1235 | * the basis of subsystem/card IDs. As not every vendor handles |
| 1236 | * subsystem/card IDs in a sane manner. |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1237 | * |
Luc Verhaegen | c521016 | 2009-04-20 12:38:17 +0000 | [diff] [blame] | 1238 | * Keep the second set NULLed if it should be ignored. Keep the subsystem IDs |
Carl-Daniel Hailfinger | 7a788f5 | 2010-02-04 11:12:04 +0000 | [diff] [blame] | 1239 | * NULLed if they don't identify the board fully and if you can't use DMI. |
| 1240 | * But please take care to provide an as complete set of pci ids as possible; |
| 1241 | * autodetection is the preferred behaviour and we would like to make sure that |
| 1242 | * matches are unique. |
Mart Raudsepp | faa62fb | 2008-02-20 11:11:18 +0000 | [diff] [blame] | 1243 | * |
Michael Karcher | 6701ee8 | 2010-01-20 14:14:11 +0000 | [diff] [blame] | 1244 | * If PCI IDs are not sufficient for board matching, the match can be further |
| 1245 | * constrained by a string that has to be present in the DMI database for |
| 1246 | * the baseboard or the system entry. The pattern is matched by case sensitve |
| 1247 | * substring match, unless it is anchored to the beginning (with a ^ in front) |
| 1248 | * or the end (with a $ at the end). Both anchors may be specified at the |
| 1249 | * same time to match the full field. |
| 1250 | * |
Carl-Daniel Hailfinger | 7a788f5 | 2010-02-04 11:12:04 +0000 | [diff] [blame] | 1251 | * When a board is matched through DMI, the first and second main PCI IDs |
| 1252 | * and the first subsystem PCI ID have to match as well. If you specify the |
| 1253 | * first subsystem ID as 0x0:0x0, the DMI matching code expects that the |
| 1254 | * subsystem ID of that device is indeed zero. |
| 1255 | * |
Luc Verhaegen | c521016 | 2009-04-20 12:38:17 +0000 | [diff] [blame] | 1256 | * The coreboot ids are used two fold. When running with a coreboot firmware, |
| 1257 | * the ids uniquely matches the coreboot board identification string. When a |
| 1258 | * legacy bios is installed and when autodetection is not possible, these ids |
| 1259 | * can be used to identify the board through the -m command line argument. |
| 1260 | * |
| 1261 | * When a board is identified through its coreboot ids (in both cases), the |
| 1262 | * main pci ids are still required to match, as a safeguard. |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1263 | */ |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1264 | |
Uwe Hermann | deeebe2 | 2009-05-08 16:23:34 +0000 | [diff] [blame] | 1265 | /* Please keep this list alphabetically ordered by vendor/board name. */ |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1266 | struct board_pciid_enable board_pciid_enables[] = { |
Uwe Hermann | 5ab8889 | 2009-06-21 20:50:22 +0000 | [diff] [blame] | 1267 | |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1268 | /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ |
| 1269 | {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise}, |
Michael Karcher | b4a3d1c | 2010-03-03 16:15:12 +0000 | [diff] [blame] | 1270 | {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1271 | {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, |
| 1272 | {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, |
| 1273 | {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e}, |
| 1274 | {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A", 0, OK, w836xx_memw_enable_2e}, |
| 1275 | {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, NULL, "AOpen", "vKM400Am-S", 0, OK, it8705f_write_enable_2e}, |
| 1276 | {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x}, |
| 1277 | {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x}, |
Russ Dill | bd622d1 | 2010-03-09 16:57:06 +0000 | [diff] [blame^] | 1278 | {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1279 | {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V8X", 0, OK, board_asus_a7v8x}, |
Russ Dill | bd622d1 | 2010-03-09 16:57:06 +0000 | [diff] [blame^] | 1280 | {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1281 | {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e}, |
Michael Karcher | b2184c1 | 2010-03-07 16:42:55 +0000 | [diff] [blame] | 1282 | {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1283 | {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise}, |
| 1284 | {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise}, |
| 1285 | {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise}, |
| 1286 | {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, |
| 1287 | {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", "ASUS", "P5A", 0, OK, board_asus_p5a}, |
| 1288 | {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, |
| 1289 | {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, NULL, "Biostar", "P4M80-M4", 0, OK, it8705f_write_enable_2e}, |
| 1290 | {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise}, |
| 1291 | {0x1039, 0x5513, 0x1019, 0x0A41, 0x1039, 0x0018, 0, 0, NULL, NULL, NULL, "Elitegroup", "K7S6A", 0, OK, it8705f_write_enable_2e}, |
| 1292 | {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, "Elitegroup", "K7VTA3", 256, OK, it8705f_write_enable_2e}, |
| 1293 | {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e}, |
| 1294 | {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise}, |
| 1295 | {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", "EPoX", "EP-BX3", 0, OK, board_epox_ep_bx3}, |
| 1296 | {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, |
| 1297 | {0x1039, 0x0761, 0, 0, 0x10EC, 0x8168, 0, 0, NULL, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", 0, OK, it87xx_probe_spi_flash}, |
| 1298 | {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, NULL, "GIGABYTE", "GA-7VT600", 0, OK, it8705f_write_enable_2e}, |
| 1299 | {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, |
| 1300 | {0x10DE, 0x0360, 0x1458, 0x0C11, 0x10DE, 0x0369, 0x1458, 0x5001, NULL, "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", 0, OK, it87xx_probe_spi_flash}, |
| 1301 | {0x10de, 0x03e0, 0, 0, 0x10DE, 0x03D0, 0, 0, NULL, NULL, NULL, "GIGABYTE", "GA-M61P-S3", 0, OK, it87xx_probe_spi_flash}, |
| 1302 | {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb000, NULL, NULL, NULL, "GIGABYTE", "GA-MA78G-DS3H", 0, OK, it87xx_probe_spi_flash}, |
| 1303 | {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb002, NULL, NULL, NULL, "GIGABYTE", "GA-MA78GM-S2H", 0, OK, it87xx_probe_spi_flash}, |
| 1304 | {0x1002, 0x438d, 0x1458, 0x5001, 0x1002, 0x5956, 0x1002, 0x5956, NULL, NULL, NULL, "GIGABYTE", "GA-MA790FX-DQ6", 0, OK, it87xx_probe_spi_flash}, |
| 1305 | {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable}, |
| 1306 | {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400}, |
Michael Karcher | 03b80e9 | 2010-03-07 16:32:32 +0000 | [diff] [blame] | 1307 | {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "VL420 SFF", 0, OK, intel_ich_gpio22_raise}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1308 | {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455}, |
| 1309 | {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi}, |
| 1310 | {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, NULL, "iwill", "dk8_htx", "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e}, |
| 1311 | {0x8086, 0x27A0, 0, 0, 0x8086, 0x27b8, 0, 0, NULL, "kontron", "986lcd-m", "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m}, |
| 1312 | {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, "Mitac", "6513WU", 0, OK, board_mitac_6513wu}, |
| 1313 | {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v}, |
| 1314 | {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio4_4_raise_2e}, |
| 1315 | {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v}, |
| 1316 | {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, "MSI", "MS-7005 (651M-L)", 0, OK, board_msi_651ml}, |
| 1317 | {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise}, |
| 1318 | {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio4_4_raise_4e}, |
Michael Karcher | 5fdf270 | 2010-03-07 16:52:59 +0000 | [diff] [blame] | 1319 | {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8N GM2-L)", 0, NT, nvidia_mcp_gpio2_raise}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1320 | {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, |
| 1321 | {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e}, |
| 1322 | {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, it8705f_write_enable_2e}, |
| 1323 | {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, |
| 1324 | {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, OK, board_soyo_sy_7vca}, |
| 1325 | {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e}, |
| 1326 | {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, "Tekram", "P6Pro-A5", 256, OK, NULL}, |
| 1327 | {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise}, |
| 1328 | {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise}, |
| 1329 | {0x1106, 0x5337, 0x1458, 0xb003, 0x1106, 0x287e, 0x1106, 0x337e, NULL, NULL, NULL, "VIA", "PC3500G", 0, OK, it87xx_probe_spi_flash}, |
Luc Verhaegen | 93938c3 | 2010-01-20 14:45:03 +0000 | [diff] [blame] | 1330 | |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1331 | { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, NT, NULL}, /* end marker */ |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1332 | }; |
| 1333 | |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 1334 | /** |
Stefan Reinauer | e3f3e2e | 2008-01-18 15:33:10 +0000 | [diff] [blame] | 1335 | * Match boards on coreboot table gathered vendor and part name. |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 1336 | * Require main PCI IDs to match too as extra safety. |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1337 | */ |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 1338 | static struct board_pciid_enable *board_match_coreboot_name(const char *vendor, |
| 1339 | const char *part) |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1340 | { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1341 | struct board_pciid_enable *board = board_pciid_enables; |
Peter Stuge | 6b53fed | 2008-01-27 16:21:21 +0000 | [diff] [blame] | 1342 | struct board_pciid_enable *partmatch = NULL; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1343 | |
Uwe Hermann | a93045c | 2009-05-09 00:47:04 +0000 | [diff] [blame] | 1344 | for (; board->vendor_name; board++) { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 1345 | if (vendor && (!board->lb_vendor |
| 1346 | || strcasecmp(board->lb_vendor, vendor))) |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1347 | continue; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1348 | |
Peter Stuge | 0b9c5f3 | 2008-07-02 00:47:30 +0000 | [diff] [blame] | 1349 | if (!board->lb_part || strcasecmp(board->lb_part, part)) |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1350 | continue; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1351 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1352 | if (!pci_dev_find(board->first_vendor, board->first_device)) |
| 1353 | continue; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1354 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1355 | if (board->second_vendor && |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 1356 | !pci_dev_find(board->second_vendor, board->second_device)) |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1357 | continue; |
Peter Stuge | 6b53fed | 2008-01-27 16:21:21 +0000 | [diff] [blame] | 1358 | |
| 1359 | if (vendor) |
| 1360 | return board; |
| 1361 | |
| 1362 | if (partmatch) { |
| 1363 | /* a second entry has a matching part name */ |
| 1364 | printf("AMBIGUOUS BOARD NAME: %s\n", part); |
| 1365 | printf("At least vendors '%s' and '%s' match.\n", |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 1366 | partmatch->lb_vendor, board->lb_vendor); |
Peter Stuge | 6b53fed | 2008-01-27 16:21:21 +0000 | [diff] [blame] | 1367 | printf("Please use the full -m vendor:part syntax.\n"); |
| 1368 | return NULL; |
| 1369 | } |
| 1370 | partmatch = board; |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1371 | } |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 1372 | |
Peter Stuge | 6b53fed | 2008-01-27 16:21:21 +0000 | [diff] [blame] | 1373 | if (partmatch) |
| 1374 | return partmatch; |
| 1375 | |
Carl-Daniel Hailfinger | bc25f94 | 2009-07-30 13:30:17 +0000 | [diff] [blame] | 1376 | if (!partvendor_from_cbtable) { |
| 1377 | /* Only warn if the mainboard type was not gathered from the |
| 1378 | * coreboot table. If it was, the coreboot implementor is |
| 1379 | * expected to fix flashrom, too. |
| 1380 | */ |
| 1381 | printf("\nUnknown vendor:board from -m option: %s:%s\n\n", |
| 1382 | vendor, part); |
| 1383 | } |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1384 | return NULL; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1385 | } |
| 1386 | |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 1387 | /** |
| 1388 | * Match boards on PCI IDs and subsystem IDs. |
| 1389 | * Second set of IDs can be main only or missing completely. |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1390 | */ |
| 1391 | static struct board_pciid_enable *board_match_pci_card_ids(void) |
| 1392 | { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1393 | struct board_pciid_enable *board = board_pciid_enables; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1394 | |
Uwe Hermann | a93045c | 2009-05-09 00:47:04 +0000 | [diff] [blame] | 1395 | for (; board->vendor_name; board++) { |
Michael Karcher | 2eab70d | 2010-02-04 10:58:50 +0000 | [diff] [blame] | 1396 | if ((!board->first_card_vendor || !board->first_card_device) && |
| 1397 | !board->dmi_pattern) |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1398 | continue; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1399 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1400 | if (!pci_card_find(board->first_vendor, board->first_device, |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 1401 | board->first_card_vendor, |
| 1402 | board->first_card_device)) |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1403 | continue; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1404 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1405 | if (board->second_vendor) { |
| 1406 | if (board->second_card_vendor) { |
| 1407 | if (!pci_card_find(board->second_vendor, |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 1408 | board->second_device, |
| 1409 | board->second_card_vendor, |
| 1410 | board->second_card_device)) |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1411 | continue; |
| 1412 | } else { |
| 1413 | if (!pci_dev_find(board->second_vendor, |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 1414 | board->second_device)) |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1415 | continue; |
| 1416 | } |
| 1417 | } |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1418 | |
Michael Karcher | 6701ee8 | 2010-01-20 14:14:11 +0000 | [diff] [blame] | 1419 | if (board->dmi_pattern) { |
| 1420 | if (!has_dmi_support) { |
| 1421 | fprintf(stderr, "WARNING: Can't autodetect %s %s," |
| 1422 | " DMI info unavailable.\n", |
| 1423 | board->vendor_name, board->board_name); |
| 1424 | continue; |
| 1425 | } else { |
| 1426 | if (!dmi_match(board->dmi_pattern)) |
| 1427 | continue; |
| 1428 | } |
| 1429 | } |
| 1430 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1431 | return board; |
| 1432 | } |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1433 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1434 | return NULL; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1435 | } |
| 1436 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 1437 | int board_flash_enable(const char *vendor, const char *part) |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1438 | { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1439 | struct board_pciid_enable *board = NULL; |
| 1440 | int ret = 0; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1441 | |
Peter Stuge | 6b53fed | 2008-01-27 16:21:21 +0000 | [diff] [blame] | 1442 | if (part) |
Stefan Reinauer | e3f3e2e | 2008-01-18 15:33:10 +0000 | [diff] [blame] | 1443 | board = board_match_coreboot_name(vendor, part); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1444 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1445 | if (!board) |
| 1446 | board = board_match_pci_card_ids(); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1447 | |
Michael Karcher | 7f0c3ec | 2010-03-07 22:29:28 +0000 | [diff] [blame] | 1448 | if (board->status == NT) { |
| 1449 | if (!force_boardenable) |
| 1450 | { |
| 1451 | printf("WARNING: Your mainboard is %s %s, but the mainboard-specific\n" |
| 1452 | "code has not been tested, and thus will not not be executed by default.\n" |
| 1453 | "Depending on your hardware environment, erasing, writing or even probing\n" |
| 1454 | "can fail without running the board specific code.\n\n" |
| 1455 | "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n" |
| 1456 | "\"internal programmer\") for details\n", |
| 1457 | board->vendor_name, board->board_name); |
| 1458 | board = NULL; |
| 1459 | } |
| 1460 | else |
| 1461 | printf("NOTE: Running an untested board enable procedure.\n" |
| 1462 | "Please report success/failure to flashrom@flashrom.org\n"); |
| 1463 | } |
| 1464 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1465 | if (board) { |
Luc Verhaegen | 93938c3 | 2010-01-20 14:45:03 +0000 | [diff] [blame] | 1466 | if (board->max_rom_decode_parallel) |
| 1467 | max_rom_decode.parallel = |
| 1468 | board->max_rom_decode_parallel * 1024; |
| 1469 | |
Uwe Hermann | b1bd3e8 | 2010-01-28 19:02:36 +0000 | [diff] [blame] | 1470 | if (board->enable != NULL) { |
| 1471 | printf("Disabling flash write protection for " |
| 1472 | "board \"%s %s\"... ", board->vendor_name, |
| 1473 | board->board_name); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1474 | |
Uwe Hermann | b1bd3e8 | 2010-01-28 19:02:36 +0000 | [diff] [blame] | 1475 | ret = board->enable(board->vendor_name); |
| 1476 | if (ret) |
| 1477 | printf("FAILED!\n"); |
| 1478 | else |
| 1479 | printf("OK.\n"); |
| 1480 | } |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1481 | } |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1482 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1483 | return ret; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1484 | } |