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Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
5 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +00006 * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
Carl-Daniel Hailfinger92242622007-09-27 14:29:57 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00008 *
Uwe Hermannd1107642007-08-29 17:52:32 +00009 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000012 *
Uwe Hermannd1107642007-08-29 17:52:32 +000013 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000021 */
22
23/*
24 * Contains the board specific flash enables.
25 */
26
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000027#include <string.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000028#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000029#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000030#include "hwaccess.h"
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000031
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000032#if defined(__i386__) || defined(__x86_64__)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000033/*
Uwe Hermannffec5f32007-08-23 16:08:21 +000034 * Helper functions for many Winbond Super I/Os of the W836xx range.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000035 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000036/* Enter extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000037void w836xx_ext_enter(uint16_t port)
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000038{
Andriy Gapon65c1b862008-05-22 13:22:45 +000039 OUTB(0x87, port);
40 OUTB(0x87, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000041}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000042
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000043/* Leave extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000044void w836xx_ext_leave(uint16_t port)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000045{
Andriy Gapon65c1b862008-05-22 13:22:45 +000046 OUTB(0xAA, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000047}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000048
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000049/* Generic Super I/O helper functions */
50uint8_t sio_read(uint16_t port, uint8_t reg)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000051{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000052 OUTB(reg, port);
53 return INB(port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000054}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000055
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000056void sio_write(uint16_t port, uint8_t reg, uint8_t data)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000057{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000058 OUTB(reg, port);
59 OUTB(data, port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000060}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000061
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000062void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000063{
Ronald G. Minnichfa496922007-10-12 21:22:40 +000064 uint8_t tmp;
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000065
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000066 OUTB(reg, port);
67 tmp = INB(port + 1) & ~mask;
68 OUTB(tmp | (data & mask), port + 1);
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000069}
70
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +000071/* Winbond W83697 documentation indicates that the index register has to be written for each access. */
72void sio_mask_alzheimer(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
73{
74 uint8_t tmp;
75
76 OUTB(reg, port);
77 tmp = INB(port + 1) & ~mask;
78 OUTB(reg, port);
79 OUTB(tmp | (data & mask), port + 1);
80}
81
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000082/* Not used yet. */
83#if 0
84static int enable_flash_decode_superio(void)
85{
86 int ret;
87 uint8_t tmp;
88
89 switch (superio.vendor) {
90 case SUPERIO_VENDOR_NONE:
91 ret = -1;
92 break;
93 case SUPERIO_VENDOR_ITE:
94 enter_conf_mode_ite(superio.port);
Uwe Hermann43959702010-03-13 17:28:29 +000095 /* Enable flash mapping. Works for most old ITE style Super I/O. */
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000096 tmp = sio_read(superio.port, 0x24);
97 tmp |= 0xfc;
98 sio_write(superio.port, 0x24, tmp);
99 exit_conf_mode_ite(superio.port);
100 ret = 0;
101 break;
102 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000103 msg_pdbg("Unhandled Super I/O type!\n");
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +0000104 ret = -1;
105 break;
106 }
107 return ret;
108}
109#endif
110
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000111/*
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000112 * SMSC FDC37B787: Raise GPIO50
113 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000114static int fdc37b787_gpio50_raise(uint16_t port)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000115{
116 uint8_t id, val;
117
118 OUTB(0x55, port); /* enter conf mode */
119 id = sio_read(port, 0x20);
120 if (id != 0x44) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000121 msg_perr("\nERROR: FDC37B787: Wrong ID 0x%02X.\n", id);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000122 OUTB(0xAA, port); /* leave conf mode */
123 return -1;
124 }
125
126 sio_write(port, 0x07, 0x08); /* Select Aux I/O subdevice */
127
128 val = sio_read(port, 0xC8); /* GP50 */
129 if ((val & 0x1B) != 0x10) /* output, no invert, GPIO */
130 {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000131 msg_perr("\nERROR: GPIO50 mode 0x%02X unexpected.\n", val);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000132 OUTB(0xAA, port);
133 return -1;
134 }
135
136 sio_mask(port, 0xF9, 0x01, 0x01);
137
138 OUTB(0xAA, port); /* Leave conf mode */
139 return 0;
140}
141
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000142/*
143 * Suited for:
144 * - Nokia IP530: Intel 440BX + PIIX4 + FDC37B787
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000145 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000146static int fdc37b787_gpio50_raise_3f0(void)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000147{
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000148 return fdc37b787_gpio50_raise(0x3f0);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000149}
150
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000151struct winbond_mux {
152 uint8_t reg; /* 0 if the corresponding pin is not muxed */
153 uint8_t data; /* reg/data/mask may be directly ... */
154 uint8_t mask; /* ... passed to sio_mask */
155};
156
157struct winbond_port {
158 const struct winbond_mux *mux; /* NULL or pointer to mux info for the 8 bits */
159 uint8_t ldn; /* LDN this GPIO register is located in */
160 uint8_t enable_bit; /* bit in 0x30 of that LDN to enable
161 the GPIO port */
162 uint8_t base; /* base register in that LDN for the port */
163};
164
165struct winbond_chip {
166 uint8_t device_id; /* reg 0x20 of the expected w83626x */
167 uint8_t gpio_port_count;
168 const struct winbond_port *port;
169};
170
171
172#define UNIMPLEMENTED_PORT {NULL, 0, 0, 0}
173
174enum winbond_id {
175 WINBOND_W83627HF_ID = 0x52,
Michael Karcherea36c9c2010-06-27 15:07:52 +0000176 WINBOND_W83627EHF_ID = 0x88,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000177 WINBOND_W83627THF_ID = 0x82,
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000178 WINBOND_W83697HF_ID = 0x60,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000179};
180
181static const struct winbond_mux w83627hf_port2_mux[8] = {
182 {0x2A, 0x01, 0x01}, /* or MIDI */
183 {0x2B, 0x80, 0x80}, /* or SPI */
184 {0x2B, 0x40, 0x40}, /* or SPI */
185 {0x2B, 0x20, 0x20}, /* or power LED */
186 {0x2B, 0x10, 0x10}, /* or watchdog */
187 {0x2B, 0x08, 0x08}, /* or infra red */
188 {0x2B, 0x04, 0x04}, /* or infra red */
189 {0x2B, 0x03, 0x03} /* or IRQ1 input */
190};
191
192static const struct winbond_port w83627hf[3] = {
193 UNIMPLEMENTED_PORT,
194 {w83627hf_port2_mux, 0x08, 0, 0xF0},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000195 UNIMPLEMENTED_PORT,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000196};
197
Michael Karcherea36c9c2010-06-27 15:07:52 +0000198static const struct winbond_mux w83627ehf_port2_mux[8] = {
199 {0x29, 0x06, 0x02}, /* or MIDI */
200 {0x29, 0x06, 0x02},
201 {0x24, 0x02, 0x00}, /* or SPI ROM interface */
202 {0x24, 0x02, 0x00},
203 {0x2A, 0x01, 0x01}, /* or keyboard/mouse interface */
204 {0x2A, 0x01, 0x01},
205 {0x2A, 0x01, 0x01},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000206 {0x2A, 0x01, 0x01},
Michael Karcherea36c9c2010-06-27 15:07:52 +0000207};
208
209static const struct winbond_port w83627ehf[6] = {
210 UNIMPLEMENTED_PORT,
211 {w83627ehf_port2_mux, 0x09, 0, 0xE3},
212 UNIMPLEMENTED_PORT,
213 UNIMPLEMENTED_PORT,
214 UNIMPLEMENTED_PORT,
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000215 UNIMPLEMENTED_PORT,
Michael Karcherea36c9c2010-06-27 15:07:52 +0000216};
217
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000218static const struct winbond_mux w83627thf_port4_mux[8] = {
219 {0x2D, 0x01, 0x01}, /* or watchdog or VID level strap */
220 {0x2D, 0x02, 0x02}, /* or resume reset */
221 {0x2D, 0x04, 0x04}, /* or S3 input */
222 {0x2D, 0x08, 0x08}, /* or PSON# */
223 {0x2D, 0x10, 0x10}, /* or PWROK */
224 {0x2D, 0x20, 0x20}, /* or suspend LED */
225 {0x2D, 0x40, 0x40}, /* or panel switch input */
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000226 {0x2D, 0x80, 0x80}, /* or panel switch output */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000227};
228
229static const struct winbond_port w83627thf[5] = {
230 UNIMPLEMENTED_PORT, /* GPIO1 */
231 UNIMPLEMENTED_PORT, /* GPIO2 */
232 UNIMPLEMENTED_PORT, /* GPIO3 */
233 {w83627thf_port4_mux, 0x09, 1, 0xF4},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000234 UNIMPLEMENTED_PORT, /* GPIO5 */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000235};
236
237static const struct winbond_chip winbond_chips[] = {
238 {WINBOND_W83627HF_ID, ARRAY_SIZE(w83627hf), w83627hf },
Michael Karcherea36c9c2010-06-27 15:07:52 +0000239 {WINBOND_W83627EHF_ID, ARRAY_SIZE(w83627ehf), w83627ehf},
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000240 {WINBOND_W83627THF_ID, ARRAY_SIZE(w83627thf), w83627thf},
241};
242
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000243#define WINBOND_SUPERIO_PORT1 0x2e
244#define WINBOND_SUPERIO_PORT2 0x4e
245
246/* We don't really care about the hardware monitor, but it offers better (more specific) device ID info than
247 * the simple device ID in the normal configuration registers.
248 * Note: This function expects to be called while the Super I/O is in config mode.
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000249 */
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000250static uint8_t w836xx_deviceid_hwmon(uint16_t sio_port)
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000251{
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000252 uint16_t hwmport;
253 uint16_t hwm_vendorid;
254 uint8_t hwm_deviceid;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000255
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000256 sio_write(sio_port, 0x07, 0x0b); /* Select LDN 0xb (HWM). */
257 if ((sio_read(sio_port, 0x30) & (1 << 0)) != (1 << 0)) {
258 msg_pinfo("W836xx hardware monitor disabled or does not exist.\n");
259 return 0;
260 }
261 /* Get HWM base address (stored in LDN 0xb, index 0x60/0x61). */
262 hwmport = sio_read(sio_port, 0x60) << 8;
263 hwmport |= sio_read(sio_port, 0x61);
264 /* HWM address register = HWM base address + 5. */
265 hwmport += 5;
266 msg_pdbg2("W836xx Hardware Monitor at port %04x\n", hwmport);
267 /* FIXME: This busy check should happen before each HWM access. */
268 if (INB(hwmport) & 0x80) {
269 msg_pinfo("W836xx hardware monitor busy, ignoring it.\n");
270 return 0;
271 }
272 /* Set HBACS=1. */
273 sio_mask_alzheimer(hwmport, 0x4e, 0x80, 0x80);
274 /* Read upper byte of vendor ID. */
275 hwm_vendorid = sio_read(hwmport, 0x4f) << 8;
276 /* Set HBACS=0. */
277 sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x80);
278 /* Read lower byte of vendor ID. */
279 hwm_vendorid |= sio_read(hwmport, 0x4f);
280 if (hwm_vendorid != 0x5ca3) {
281 msg_pinfo("W836xx hardware monitor vendor ID weirdness: expected 0x5ca3, got %04x\n",
282 hwm_vendorid);
283 return 0;
284 }
285 /* Set Bank=0. */
286 sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x07);
287 /* Read "chip" ID. We call this one the device ID. */
288 hwm_deviceid = sio_read(hwmport, 0x58);
289 return hwm_deviceid;
290}
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000291
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000292void probe_superio_winbond(void)
293{
294 struct superio s = {};
295 uint16_t winbond_ports[] = {WINBOND_SUPERIO_PORT1, WINBOND_SUPERIO_PORT2, 0};
296 uint16_t *i = winbond_ports;
297 uint8_t model;
298 uint8_t tmp;
299
300 s.vendor = SUPERIO_VENDOR_WINBOND;
301 for (; *i; i++) {
302 s.port = *i;
303 /* If we're already in Super I/O config more, the W836xx enter sequence won't hurt. */
304 w836xx_ext_enter(s.port);
305 model = sio_read(s.port, 0x20);
306 /* No response, no point leaving the config mode. */
307 if (model == 0xff)
308 continue;
309 /* Try to leave config mode. If the ID register is still readable, it's not a Winbond chip. */
310 w836xx_ext_leave(s.port);
311 if (model == sio_read(s.port, 0x20)) {
312 msg_pdbg("W836xx enter config mode worked or we were already in config mode. W836xx "
313 "leave config mode had no effect.\n");
314 if (model == 0x87) {
315 /* ITE IT8707F and IT8710F are special: They need the W837xx enter sequence,
316 * but they want the ITE exit sequence. Handle them here.
317 */
318 tmp = sio_read(s.port, 0x21);
319 switch (tmp) {
320 case 0x07:
321 case 0x10:
322 s.vendor = SUPERIO_VENDOR_ITE;
323 s.model = (0x87 << 8) | tmp ;
324 msg_pdbg("Found ITE Super I/O, ID 0x%04hx on port "
325 "0x%x\n", s.model, s.port);
326 register_superio(s);
327 /* Exit ITE config mode. */
328 exit_conf_mode_ite(s.port);
329 /* Restore vendor for next loop iteration. */
330 s.vendor = SUPERIO_VENDOR_WINBOND;
331 continue;
332 }
333 }
334 msg_pinfo("Active config mode, unknown reg 0x20 ID: %02x.\n", model);
335 msg_pinfo("Please send the output of \"flashrom -V\" to \n"
336 "flashrom@flashrom.org with W836xx: your board name: flashrom -V\n"
337 "as the subject to help us finish support for your Super I/O. Thanks.\n");
338 continue;
339 }
340 /* The Super I/O reacts to W836xx enter and exit config mode, it's probably Winbond. */
341 w836xx_ext_enter(s.port);
342 s.model = sio_read(s.port, 0x20);
343 switch (s.model) {
344 case WINBOND_W83627HF_ID:
345 case WINBOND_W83627EHF_ID:
346 case WINBOND_W83627THF_ID:
347 msg_pdbg("Found Winbond Super I/O, id %02hx\n", s.model);
348 register_superio(s);
349 break;
350 case WINBOND_W83697HF_ID:
351 /* This code is extremely paranoid. */
352 tmp = sio_read(s.port, 0x26) & 0x40;
353 if (((tmp == 0x00) && (s.port != WINBOND_SUPERIO_PORT1)) ||
354 ((tmp == 0x40) && (s.port != WINBOND_SUPERIO_PORT2))) {
355 msg_pdbg("Winbond Super I/O probe weirdness: Port mismatch for ID "
356 "%02x at port %04x\n", s.model, s.port);
357 break;
358 }
359 tmp = w836xx_deviceid_hwmon(s.port);
360 /* FIXME: This might be too paranoid... */
361 if (!tmp) {
362 msg_pdbg("Probably not a Winbond Super I/O\n");
363 break;
364 }
365 if (tmp != s.model) {
366 msg_pinfo("W83 series hardware monitor device ID weirdness: expected %02x, "
367 "got %02x\n", WINBOND_W83697HF_ID, tmp);
368 break;
369 }
370 msg_pinfo("Found Winbond Super I/O, id %02hx\n", s.model);
371 register_superio(s);
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000372 break;
373 }
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000374 w836xx_ext_leave(s.port);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000375 }
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000376 return;
377}
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000378
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000379static const struct winbond_chip *winbond_superio_chipdef(void)
380{
381 int i, j;
382
383 for (i = 0; i < superio_count; i++) {
384 if (superios[i].vendor != SUPERIO_VENDOR_WINBOND)
385 continue;
386 for (j = 0; j < ARRAY_SIZE(winbond_chips); j++)
387 if (winbond_chips[j].device_id == superios[i].model)
388 return &winbond_chips[j];
389 }
390 return NULL;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000391}
392
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000393/*
394 * The chipid parameter goes away as soon as we have Super I/O matching in the
395 * board enable table. The call to winbond_superio_detect() goes away as
396 * soon as we have generic Super I/O detection code.
397 */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000398static int winbond_gpio_set(uint16_t base, enum winbond_id chipid,
399 int pin, int raise)
400{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000401 const struct winbond_chip *chip = NULL;
402 const struct winbond_port *gpio;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000403 int port = pin / 10;
404 int bit = pin % 10;
405
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000406 chip = winbond_superio_chipdef();
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000407 if (!chip) {
408 msg_perr("\nERROR: No supported Winbond Super I/O found\n");
409 return -1;
410 }
Michael Karcher979d9252010-06-29 14:44:40 +0000411 if (chip->device_id != chipid) {
412 msg_perr("\nERROR: Found Winbond chip with ID 0x%x, "
413 "expected %x\n", chip->device_id, chipid);
414 return -1;
415 }
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000416 if (bit >= 8 || port == 0 || port > chip->gpio_port_count) {
417 msg_perr("\nERROR: winbond_gpio_set: Invalid GPIO number %d\n",
418 pin);
419 return -1;
420 }
421
422 gpio = &chip->port[port - 1];
423
424 if (gpio->ldn == 0) {
425 msg_perr("\nERROR: GPIO%d is not supported yet on this"
426 " winbond chip\n", port);
427 return -1;
428 }
429
430 w836xx_ext_enter(base);
431
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000432 /* Select logical device. */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000433 sio_write(base, 0x07, gpio->ldn);
434
435 /* Activate logical device. */
436 sio_mask(base, 0x30, 1 << gpio->enable_bit, 1 << gpio->enable_bit);
437
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000438 /* Select GPIO function of that pin. */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000439 if (gpio->mux && gpio->mux[bit].reg)
440 sio_mask(base, gpio->mux[bit].reg,
441 gpio->mux[bit].data, gpio->mux[bit].mask);
442
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000443 sio_mask(base, gpio->base + 0, 0, 1 << bit); /* Make pin output */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000444 sio_mask(base, gpio->base + 2, 0, 1 << bit); /* Clear inversion */
445 sio_mask(base, gpio->base + 1, raise << bit, 1 << bit);
446
447 w836xx_ext_leave(base);
448
449 return 0;
450}
451
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000452/*
Uwe Hermannffec5f32007-08-23 16:08:21 +0000453 * Winbond W83627HF: Raise GPIO24.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000454 *
455 * Suited for:
Uwe Hermannffec5f32007-08-23 16:08:21 +0000456 * - Agami Aruma
457 * - IWILL DK8-HTX
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000458 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000459static int w83627hf_gpio24_raise_2e(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000460{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000461 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 24, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000462}
463
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000464/*
Joshua Roysf280a382010-08-07 21:49:11 +0000465 * Winbond W83627HF: Raise GPIO25.
466 *
467 * Suited for:
468 * - MSI MS-6577
469 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000470static int w83627hf_gpio25_raise_2e(void)
Joshua Roysf280a382010-08-07 21:49:11 +0000471{
472 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 25, 1);
473}
474
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000475/*
Stefan Taunerff80e682011-07-20 16:34:18 +0000476 * Winbond W83627EHF: Raise GPIO22.
Michael Karcherea36c9c2010-06-27 15:07:52 +0000477 *
478 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000479 * - ASUS A8N-VM CSM: AMD Socket 939 + GeForce 6150 (C51) + MCP51
Michael Karcherea36c9c2010-06-27 15:07:52 +0000480 */
Stefan Taunerff80e682011-07-20 16:34:18 +0000481static int w83627ehf_gpio22_raise_2e(void)
Michael Karcherea36c9c2010-06-27 15:07:52 +0000482{
Stefan Taunerff80e682011-07-20 16:34:18 +0000483 return winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, 22, 1);
Michael Karcherea36c9c2010-06-27 15:07:52 +0000484}
485
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000486/*
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000487 * Winbond W83627THF: Raise GPIO 44.
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000488 *
489 * Suited for:
Peter Stugecce26822008-07-21 17:48:40 +0000490 * - MSI K8T Neo2-F
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000491 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000492static int w83627thf_gpio44_raise_2e(void)
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000493{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000494 return winbond_gpio_set(0x2e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000495}
496
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000497/*
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000498 * Winbond W83627THF: Raise GPIO 44.
499 *
500 * Suited for:
501 * - MSI K8N Neo3
502 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000503static int w83627thf_gpio44_raise_4e(void)
Peter Stugecce26822008-07-21 17:48:40 +0000504{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000505 return winbond_gpio_set(0x4e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000506}
Uwe Hermann372eeb52007-12-04 21:49:06 +0000507
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000508/*
David Borgb6417a62010-08-02 08:29:34 +0000509 * Enable MEMW# and set ROM size to max.
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000510 * Supported chips: W83L517D, W83697HF/F/HG, W83697SF/UF/UG
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000511 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000512static void w836xx_memw_enable(uint16_t port)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000513{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000514 w836xx_ext_enter(port);
515 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000516 /* Enable MEMW# and set ROM size select to max. (4M). */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000517 sio_mask(port, 0x24, 0x28, 0x28);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000518 }
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000519 w836xx_ext_leave(port);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000520}
521
David Borgb02c62b2012-05-05 20:43:42 +0000522/**
523 * Enable MEMW# and set ROM size to max.
524 * Supported chips:
525 * W83697HF/F/HG, W83697SF/UF/UG
526 */
527void w83697xx_memw_enable(uint16_t port)
528{
529 w836xx_ext_enter(port);
530 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
531 if((sio_read(port, 0x2A) & 0xF0) == 0xF0) {
532
533 /* CR24 Bits 7 & 2 must be set to 0 enable the flash ROM */
534 /* address segments 000E0000h ~ 000FFFFFh on W83697SF/UF/UG */
535 /* These bits are reserved on W83697HF/F/HG */
536 /* Shouldn't be needed though. */
537
538 /* CR28 Bit3 must be set to 1 to enable flash access to */
539 /* FFE80000h ~ FFEFFFFFh on W83697SF/UF/UG. */
540 /* This bit is reserved on W83697HF/F/HG which default to 0 */
541 sio_mask(port, 0x28, 0x08, 0x08);
542
543 /* Enable MEMW# and set ROM size select to max. (4M)*/
544 sio_mask(port, 0x24, 0x28, 0x38);
545
546 } else {
547 msg_perr("WARNING: Flash interface in use by GPIO!\n");
548 }
549 } else {
550 msg_pinfo("BIOS ROM is disabled\n");
551 }
552 w836xx_ext_leave(port);
553}
554
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000555/*
Luc Verhaegen73d21192009-12-23 00:54:26 +0000556 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000557 * - EPoX EP-8K5A2: VIA KT333 + VT8235
558 * - Albatron PM266A Pro: VIA P4M266A + VT8235
559 * - Shuttle AK31 (all versions): VIA KT266 + VT8233
560 * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
561 * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237
Mattias Mattssone295eee2010-08-15 10:21:29 +0000562 * - MSI KM4M-V and KM4AM-V: VIA KM400/KM400A + VT8237
Mattias Mattssone8388242010-09-11 15:25:48 +0000563 * - MSI MS-6561 (745 Ultra): SiS 745 + W83697HF
Sergey A Lichackf3a4bff2010-09-07 18:14:53 +0000564 * - MSI MS-6787 (P4MAM-V/P4MAM-L): VIA P4M266 + VT8235
Uwe Hermann17da61e2010-10-05 21:48:43 +0000565 * - ASRock K7S41: SiS 741 + SiS 963 + W83697HF
Pawel Rozanski1d233072011-06-19 16:52:48 +0000566 * - ASRock K7S41GX: SiS 741GX + SiS 963L + W83697HF
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000567 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000568static int w836xx_memw_enable_2e(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000569{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000570 w836xx_memw_enable(0x2E);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000571
Luc Verhaegen73d21192009-12-23 00:54:26 +0000572 return 0;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000573}
574
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000575/*
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000576 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000577 * - Termtek TK-3370 (rev. 2.5b)
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000578 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000579static int w836xx_memw_enable_4e(void)
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000580{
581 w836xx_memw_enable(0x4E);
582
583 return 0;
584}
585
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000586/*
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000587 * Suited for all boards with ITE IT8705F.
588 * The SIS950 Super I/O probably requires a similar flash write enable.
Luc Verhaegen21f54962010-01-20 14:45:07 +0000589 */
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000590int it8705f_write_enable(uint8_t port)
Luc Verhaegen21f54962010-01-20 14:45:07 +0000591{
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000592 uint8_t tmp;
593 int ret = 0;
594
Luc Verhaegen21f54962010-01-20 14:45:07 +0000595 enter_conf_mode_ite(port);
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000596 tmp = sio_read(port, 0x24);
597 /* Check if at least one flash segment is enabled. */
598 if (tmp & 0xf0) {
599 /* The IT8705F will respond to LPC cycles and translate them. */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000600 internal_buses_supported = BUS_PARALLEL;
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000601 /* Flash ROM I/F Writes Enable */
602 tmp |= 0x04;
603 msg_pdbg("Enabling IT8705F flash ROM interface write.\n");
604 if (tmp & 0x02) {
605 /* The data sheet contradicts itself about max size. */
606 max_rom_decode.parallel = 1024 * 1024;
607 msg_pinfo("IT8705F with very unusual settings. Please "
608 "send the output of \"flashrom -V\" to \n"
Paul Menzelab6328f2010-10-08 11:03:02 +0000609 "flashrom@flashrom.org with "
610 "IT8705: your board name: flashrom -V\n"
611 "as the subject to help us finish "
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000612 "support for your Super I/O. Thanks.\n");
613 ret = 1;
614 } else if (tmp & 0x08) {
615 max_rom_decode.parallel = 512 * 1024;
616 } else {
617 max_rom_decode.parallel = 256 * 1024;
618 }
619 /* Safety checks. The data sheet is unclear here: Segments 1+3
620 * overlap, no segment seems to cover top - 1MB to top - 512kB.
621 * We assume that certain combinations make no sense.
622 */
623 if (((tmp & 0x02) && !(tmp & 0x08)) || /* 1 MB en, 512 kB dis */
624 (!(tmp & 0x10)) || /* 128 kB dis */
625 (!(tmp & 0x40))) { /* 256/512 kB dis */
626 msg_perr("Inconsistent IT8705F decode size!\n");
627 ret = 1;
628 }
629 if (sio_read(port, 0x25) != 0) {
630 msg_perr("IT8705F flash data pins disabled!\n");
631 ret = 1;
632 }
633 if (sio_read(port, 0x26) != 0) {
634 msg_perr("IT8705F flash address pins 0-7 disabled!\n");
635 ret = 1;
636 }
637 if (sio_read(port, 0x27) != 0) {
638 msg_perr("IT8705F flash address pins 8-15 disabled!\n");
639 ret = 1;
640 }
641 if ((sio_read(port, 0x29) & 0x10) != 0) {
642 msg_perr("IT8705F flash write enable pin disabled!\n");
643 ret = 1;
644 }
645 if ((sio_read(port, 0x29) & 0x08) != 0) {
646 msg_perr("IT8705F flash chip select pin disabled!\n");
647 ret = 1;
648 }
649 if ((sio_read(port, 0x29) & 0x04) != 0) {
650 msg_perr("IT8705F flash read strobe pin disabled!\n");
651 ret = 1;
652 }
653 if ((sio_read(port, 0x29) & 0x03) != 0) {
654 msg_perr("IT8705F flash address pins 16-17 disabled!\n");
655 /* Not really an error if you use flash chips smaller
656 * than 256 kByte, but such a configuration is unlikely.
657 */
658 ret = 1;
659 }
660 msg_pdbg("Maximum IT8705F parallel flash decode size is %u.\n",
661 max_rom_decode.parallel);
662 if (ret) {
663 msg_pinfo("Not enabling IT8705F flash write.\n");
664 } else {
665 sio_write(port, 0x24, tmp);
666 }
667 } else {
668 msg_pdbg("No IT8705F flash segment enabled.\n");
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000669 ret = 0;
670 }
Luc Verhaegen21f54962010-01-20 14:45:07 +0000671 exit_conf_mode_ite(port);
672
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000673 return ret;
Luc Verhaegen21f54962010-01-20 14:45:07 +0000674}
Luc Verhaegen73d21192009-12-23 00:54:26 +0000675
Mattias Mattssonfb60cec2010-09-13 19:39:25 +0000676/*
677 * The ITE IT8707F is a custom chip made by ITE exclusively for ASUS.
678 * It uses the Winbond command sequence to enter extended configuration
679 * mode and the ITE sequence to exit.
680 *
681 * Registers seems similar to the ones on ITE IT8710F.
682 */
683static int it8707f_write_enable(uint8_t port)
684{
685 uint8_t tmp;
686
687 w836xx_ext_enter(port);
688
689 /* Set bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A rw */
690 tmp = sio_read(port, 0x23);
691 tmp |= (1 << 3);
692 sio_write(port, 0x23, tmp);
693
694 /* Set bit 2 (FLASH_WE) and bit 3 (FLASH_IF_EN) of reg 0x24 */
695 tmp = sio_read(port, 0x24);
696 tmp |= (1 << 2) | (1 << 3);
697 sio_write(port, 0x24, tmp);
698
699 /* Clear bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A ro */
700 tmp = sio_read(port, 0x23);
701 tmp &= ~(1 << 3);
702 sio_write(port, 0x23, tmp);
703
704 exit_conf_mode_ite(port);
705
706 return 0;
707}
708
709/*
710 * Suited for:
711 * - ASUS P4SC-E: SiS 651 + 962 + ITE IT8707F
712 */
713static int it8707f_write_enable_2e(void)
714{
715 return it8707f_write_enable(0x2e);
716}
717
Michael Karchercba52de2011-03-06 12:07:19 +0000718#define PC87360_ID 0xE1
719#define PC87364_ID 0xE4
720
721static int pc8736x_gpio_set(uint8_t chipid, uint8_t gpio, int raise)
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000722{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000723 static const int bankbase[] = {0, 4, 8, 10, 12};
724 int gpio_bank = gpio / 8;
725 int gpio_pin = gpio % 8;
726 uint16_t baseport;
727 uint8_t id, val;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000728
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000729 if (gpio_bank > 4) {
Michael Karchercba52de2011-03-06 12:07:19 +0000730 msg_perr("PC8736x: Invalid GPIO %d\n", gpio);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000731 return -1;
732 }
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000733
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000734 id = sio_read(0x2E, 0x20);
Michael Karchercba52de2011-03-06 12:07:19 +0000735 if (id != chipid) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000736 msg_perr("PC8736x: unexpected ID %02x (expected %02x)\n",
737 id, chipid);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000738 return -1;
739 }
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000740
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000741 sio_write(0x2E, 0x07, 0x07); /* Select GPIO device. */
742 baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
743 if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) {
744 msg_perr("PC87360: invalid GPIO base address %04x\n",
745 baseport);
746 return -1;
747 }
748 sio_mask (0x2E, 0x30, 0x01, 0x01); /* Enable logical device. */
749 sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin);
750 sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output. */
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000751
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000752 val = INB(baseport + bankbase[gpio_bank]);
753 if (raise)
754 val |= 1 << gpio_pin;
755 else
756 val &= ~(1 << gpio_pin);
757 OUTB(val, baseport + bankbase[gpio_bank]);
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000758
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000759 return 0;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000760}
761
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000762/*
763 * VIA VT823x: Set one of the GPIO pins.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000764 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000765static int via_vt823x_gpio_set(uint8_t gpio, int raise)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000766{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000767 struct pci_dev *dev;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000768 uint16_t base;
David Bartleyf58d3642009-12-09 07:53:01 +0000769 uint8_t val, bit, offset;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000770
Luc Verhaegen73d21192009-12-23 00:54:26 +0000771 dev = pci_dev_find_vendorclass(0x1106, 0x0601);
772 switch (dev->device_id) {
773 case 0x3177: /* VT8235 */
774 case 0x3227: /* VT8237R */
775 case 0x3337: /* VT8237A */
776 break;
777 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000778 msg_perr("\nERROR: VT823x ISA bridge not found.\n");
Luc Verhaegen73d21192009-12-23 00:54:26 +0000779 return -1;
780 }
781
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000782 if ((gpio >= 12) && (gpio <= 15)) {
783 /* GPIO12-15 -> output */
784 val = pci_read_byte(dev, 0xE4);
785 val |= 0x10;
786 pci_write_byte(dev, 0xE4, val);
787 } else if (gpio == 9) {
788 /* GPIO9 -> Output */
789 val = pci_read_byte(dev, 0xE4);
790 val |= 0x20;
791 pci_write_byte(dev, 0xE4, val);
David Bartleyf58d3642009-12-09 07:53:01 +0000792 } else if (gpio == 5) {
793 val = pci_read_byte(dev, 0xE4);
794 val |= 0x01;
795 pci_write_byte(dev, 0xE4, val);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000796 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000797 msg_perr("\nERROR: "
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000798 "VT823x GPIO%02d is not implemented.\n", gpio);
Luc Verhaegen73d21192009-12-23 00:54:26 +0000799 return -1;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000800 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000801
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000802 /* We need the I/O Base Address for this board's flash enable. */
803 base = pci_read_word(dev, 0x88) & 0xff80;
804
David Bartleyf58d3642009-12-09 07:53:01 +0000805 offset = 0x4C + gpio / 8;
806 bit = 0x01 << (gpio % 8);
807
808 val = INB(base + offset);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000809 if (raise)
810 val |= bit;
811 else
812 val &= ~bit;
David Bartleyf58d3642009-12-09 07:53:01 +0000813 OUTB(val, base + offset);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000814
Uwe Hermanna7e05482007-05-09 10:17:44 +0000815 return 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000816}
817
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000818/*
819 * Suited for:
820 * - ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000821 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000822static int via_vt823x_gpio5_raise(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000823{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000824 /* On M2V-MX: GPO5 is connected to WP# and TBL#. */
825 return via_vt823x_gpio_set(5, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000826}
827
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000828/*
829 * Suited for:
830 * - VIA EPIA EK & N & NL
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000831 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000832static int via_vt823x_gpio9_raise(void)
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000833{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000834 return via_vt823x_gpio_set(9, 1);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000835}
836
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000837/*
838 * Suited for:
839 * - VIA EPIA M and MII (and maybe other CLE266 based EPIAs)
Luc Verhaegen73d21192009-12-23 00:54:26 +0000840 *
841 * We don't need to do this for EPIA M when using coreboot, GPIO15 is never
842 * lowered there.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000843 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000844static int via_vt823x_gpio15_raise(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000845{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000846 return via_vt823x_gpio_set(15, 1);
847}
848
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000849/*
Luc Verhaegen73d21192009-12-23 00:54:26 +0000850 * Winbond W83697HF Super I/O + VIA VT8235 southbridge
851 *
852 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000853 * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
854 * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
Luc Verhaegen73d21192009-12-23 00:54:26 +0000855 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000856static int board_msi_kt4v(void)
Luc Verhaegen73d21192009-12-23 00:54:26 +0000857{
858 int ret;
859
860 ret = via_vt823x_gpio_set(12, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000861 w836xx_memw_enable(0x2E);
Luc Verhaegen97866082008-02-09 02:03:06 +0000862
Luc Verhaegen73d21192009-12-23 00:54:26 +0000863 return ret;
Luc Verhaegen97866082008-02-09 02:03:06 +0000864}
865
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000866/*
867 * Suited for:
868 * - ASUS P5A
Luc Verhaegen6b141752007-05-20 16:16:13 +0000869 *
870 * This is rather nasty code, but there's no way to do this cleanly.
871 * We're basically talking to some unknown device on SMBus, my guess
872 * is that it is the Winbond W83781D that lives near the DIP BIOS.
873 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000874static int board_asus_p5a(void)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000875{
876 uint8_t tmp;
877 int i;
878
879#define ASUSP5A_LOOP 5000
880
Andriy Gapon65c1b862008-05-22 13:22:45 +0000881 OUTB(0x00, 0xE807);
882 OUTB(0xEF, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000883
Andriy Gapon65c1b862008-05-22 13:22:45 +0000884 OUTB(0xFF, 0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000885
886 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000887 OUTB(0xE1, 0xFF);
888 if (INB(0xE800) & 0x04)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000889 break;
890 }
891
892 if (i == ASUSP5A_LOOP) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000893 msg_perr("Unable to contact device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000894 return -1;
895 }
896
Andriy Gapon65c1b862008-05-22 13:22:45 +0000897 OUTB(0x20, 0xE801);
898 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000899
Andriy Gapon65c1b862008-05-22 13:22:45 +0000900 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000901
902 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000903 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000904 if (tmp & 0x70)
905 break;
906 }
907
908 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000909 msg_perr("Failed to read device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000910 return -1;
911 }
912
Andriy Gapon65c1b862008-05-22 13:22:45 +0000913 tmp = INB(0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000914 tmp &= ~0x02;
915
Andriy Gapon65c1b862008-05-22 13:22:45 +0000916 OUTB(0x00, 0xE807);
917 OUTB(0xEE, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000918
Andriy Gapon65c1b862008-05-22 13:22:45 +0000919 OUTB(tmp, 0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000920
Andriy Gapon65c1b862008-05-22 13:22:45 +0000921 OUTB(0xFF, 0xE800);
922 OUTB(0xE1, 0xFF);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000923
Andriy Gapon65c1b862008-05-22 13:22:45 +0000924 OUTB(0x20, 0xE801);
925 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000926
Andriy Gapon65c1b862008-05-22 13:22:45 +0000927 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000928
929 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000930 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000931 if (tmp & 0x70)
932 break;
933 }
934
935 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000936 msg_perr("Failed to write to device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000937 return -1;
938 }
939
940 return 0;
941}
942
Luc Verhaegena7e30502009-12-09 11:39:02 +0000943/*
944 * Set GPIO lines in the Broadcom HT-1000 southbridge.
945 *
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000946 * It's not a Super I/O but it uses the same index/data port method.
Luc Verhaegena7e30502009-12-09 11:39:02 +0000947 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000948static int board_hp_dl145_g3_enable(void)
Luc Verhaegena7e30502009-12-09 11:39:02 +0000949{
950 /* GPIO 0 reg from PM regs */
951 /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
952 sio_mask(0xcd6, 0x44, 0x24, 0x24);
953
954 return 0;
955}
956
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +0000957/*
958 * Set GPIO lines in the Broadcom HT-1000 southbridge.
959 *
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000960 * It's not a Super I/O but it uses the same index/data port method.
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +0000961 */
962static int board_hp_dl165_g6_enable(void)
963{
964 /* Variant of DL145, with slightly different pin placement. */
965 sio_mask(0xcd6, 0x44, 0x80, 0x80); /* TBL# */
966 sio_mask(0xcd6, 0x46, 0x04, 0x04); /* WP# */
967
968 return 0;
969}
970
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000971static int board_ibm_x3455(void)
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000972{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000973 /* Raise GPIO13. */
Carl-Daniel Hailfinger500b4232009-06-01 21:30:42 +0000974 sio_mask(0xcd6, 0x45, 0x20, 0x20);
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000975
976 return 0;
977}
978
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000979/*
980 * Suited for:
981 * - Shuttle FN25 (SN25P): AMD S939 + NVIDIA CK804 (nForce4)
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000982 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000983static int board_shuttle_fn25(void)
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000984{
985 struct pci_dev *dev;
986
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000987 dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA bridge. */
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000988 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000989 msg_perr("\nERROR: NVIDIA nForce4 ISA bridge not found.\n");
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000990 return -1;
991 }
992
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000993 /* One of those bits seems to be connected to TBL#, but -ENOINFO. */
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000994 pci_write_byte(dev, 0x92, 0);
995
996 return 0;
997}
998
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000999/*
Mattias Mattssonf4925162010-09-16 22:09:18 +00001000 * Suited for:
1001 * - Elitegroup GeForce6100SM-M: NVIDIA MCP61 + ITE IT8726F
1002 */
Mattias Mattssonf4925162010-09-16 22:09:18 +00001003static int board_ecs_geforce6100sm_m(void)
1004{
1005 struct pci_dev *dev;
1006 uint32_t tmp;
1007
1008 dev = pci_dev_find(0x10DE, 0x03EB); /* NVIDIA MCP61 SMBus. */
1009 if (!dev) {
1010 msg_perr("\nERROR: NVIDIA MCP61 SMBus not found.\n");
1011 return -1;
1012 }
1013
1014 tmp = pci_read_byte(dev, 0xE0);
1015 tmp &= ~(1 << 3);
1016 pci_write_byte(dev, 0xE0, tmp);
1017
1018 return 0;
1019}
1020
1021/*
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001022 * Very similar to AMD 8111 IO Hub.
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001023 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001024static int nvidia_mcp_gpio_set(int gpio, int raise)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001025{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001026 struct pci_dev *dev;
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001027 uint16_t base, devclass;
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001028 uint8_t tmp;
1029
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001030 if ((gpio < 0) || (gpio >= 0x40)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001031 msg_perr("\nERROR: unsupported GPIO: %d.\n", gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +00001032 return -1;
1033 }
1034
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001035 /* Check for the ISA bridge first. */
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001036 dev = pci_dev_find_vendorclass(0x10DE, 0x0601);
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001037 switch (dev->device_id) {
1038 case 0x0030: /* CK804 */
1039 case 0x0050: /* MCP04 */
1040 case 0x0060: /* MCP2 */
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001041 case 0x00E0: /* CK8 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001042 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +00001043 case 0x0260: /* MCP51 */
Michael Karcher242efd42011-03-06 12:09:05 +00001044 case 0x0261: /* MCP51 */
Joshua Roys6e48a022012-06-29 23:07:14 +00001045 case 0x0360: /* MCP55 */
Michael Karcher2ead2e22010-06-01 16:09:06 +00001046 case 0x0364: /* MCP55 */
1047 /* find SMBus controller on *this* southbridge */
1048 /* The infamous Tyan S2915-E has two south bridges; they are
1049 easily told apart from each other by the class of the
1050 LPC bridge, but have the same SMBus bridge IDs */
1051 if (dev->func != 0) {
1052 msg_perr("MCP LPC bridge at unexpected function"
1053 " number %d\n", dev->func);
1054 return -1;
1055 }
1056
Carl-Daniel Hailfinger44cd9ab2010-07-17 22:28:05 +00001057#if PCI_LIB_VERSION >= 0x020200
Michael Karcher2ead2e22010-06-01 16:09:06 +00001058 dev = pci_get_dev(pacc, dev->domain, dev->bus, dev->dev, 1);
Carl-Daniel Hailfinger44cd9ab2010-07-17 22:28:05 +00001059#else
1060 /* pciutils/libpci before version 2.2 is too old to support
1061 * PCI domains. Such old machines usually don't have domains
1062 * besides domain 0, so this is not a problem.
1063 */
1064 dev = pci_get_dev(pacc, dev->bus, dev->dev, 1);
1065#endif
Michael Karcher2ead2e22010-06-01 16:09:06 +00001066 if (!dev) {
1067 msg_perr("MCP SMBus controller could not be found\n");
1068 return -1;
1069 }
1070 devclass = pci_read_word(dev, PCI_CLASS_DEVICE);
1071 if (devclass != 0x0C05) {
1072 msg_perr("Unexpected device class %04x for SMBus"
1073 " controller\n", devclass);
1074 return -1;
1075 }
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001076 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +00001077 default:
Sean Nelson316a29f2010-05-07 20:09:04 +00001078 msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n");
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001079 return -1;
1080 }
1081
1082 base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */
1083 base += 0xC0;
1084
1085 tmp = INB(base + gpio);
1086 tmp &= ~0x0F; /* null lower nibble */
1087 tmp |= 0x04; /* gpio -> output. */
1088 if (raise)
1089 tmp |= 0x01;
1090 OUTB(tmp, base + gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +00001091
1092 return 0;
1093}
1094
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001095/*
1096 * Suited for:
Stefan Taunera9cbbac2011-08-07 13:17:20 +00001097 * - ASUS A8M2N-LA (HP OEM "NodusM3-GL8E"): NVIDIA MCP51
Sean Nelson0a247512010-08-15 14:36:18 +00001098 * - ASUS A8N-LA (HP OEM "Nagami-GL8E"): NVIDIA MCP51
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001099 * - ASUS M2NBP-VM CSM: NVIDIA MCP51
Michael Karcherb2184c12010-03-07 16:42:55 +00001100 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001101static int nvidia_mcp_gpio0_raise(void)
Michael Karcherb2184c12010-03-07 16:42:55 +00001102{
1103 return nvidia_mcp_gpio_set(0x00, 1);
1104}
1105
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001106/*
1107 * Suited for:
1108 * - abit KN8 Ultra: NVIDIA CK804
Sean Nelson92bc6bd2010-03-19 22:37:29 +00001109 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001110static int nvidia_mcp_gpio2_lower(void)
Sean Nelson92bc6bd2010-03-19 22:37:29 +00001111{
1112 return nvidia_mcp_gpio_set(0x02, 0);
1113}
1114
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001115/*
1116 * Suited for:
Michael Karcher2842db32011-04-14 23:14:27 +00001117 * - Foxconn 6150K8MD-8EKRSH: Socket 939 + NVIDIA MCP51
Uwe Hermannead705f2010-08-15 15:26:30 +00001118 * - MSI K8N Neo4: NVIDIA CK804. TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html.
1119 * - MSI K8NGM2-L: NVIDIA MCP51
Joshua Roys6e48a022012-06-29 23:07:14 +00001120 * - MSI K9N SLI: NVIDIA MCP55
Luc Verhaegen6c5f7332009-12-23 03:01:36 +00001121 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001122static int nvidia_mcp_gpio2_raise(void)
Luc Verhaegen6c5f7332009-12-23 03:01:36 +00001123{
1124 return nvidia_mcp_gpio_set(0x02, 1);
1125}
1126
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001127/*
1128 * Suited for:
Uwe Hermann83d349a2010-10-18 22:32:03 +00001129 * - EPoX EP-8NPA7I: Socket 754 + NVIDIA nForce4 4X
Jonathan Kollaschf8db9592010-10-15 23:02:15 +00001130 */
1131static int nvidia_mcp_gpio4_raise(void)
1132{
1133 return nvidia_mcp_gpio_set(0x04, 1);
1134}
1135
1136/*
1137 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001138 * - HP xw9400 (Tyan S2915-E OEM): Dual(!) NVIDIA MCP55
1139 *
1140 * Notes: a) There are two MCP55 chips, so also two SMBus bridges on that
1141 * board. We can't tell the SMBus logical devices apart, but we
1142 * can tell the LPC bridge functions apart.
1143 * We need to choose the SMBus bridge next to the LPC bridge with
1144 * ID 0x364 and the "LPC bridge" class.
1145 * b) #TBL is hardwired on that board to a pull-down. It can be
1146 * overridden by connecting the two solder points next to F2.
Michael Karcher2ead2e22010-06-01 16:09:06 +00001147 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001148static int nvidia_mcp_gpio5_raise(void)
Michael Karcher2ead2e22010-06-01 16:09:06 +00001149{
1150 return nvidia_mcp_gpio_set(0x05, 1);
1151}
1152
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001153/*
1154 * Suited for:
1155 * - abit NF7-S: NVIDIA CK804
Michael Karcher8f10d242010-04-11 21:01:06 +00001156 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001157static int nvidia_mcp_gpio8_raise(void)
Michael Karcher8f10d242010-04-11 21:01:06 +00001158{
1159 return nvidia_mcp_gpio_set(0x08, 1);
1160}
1161
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001162/*
1163 * Suited for:
Cristian Măgherușan-Stanciu9932c7b2011-07-07 19:56:58 +00001164 * - GIGABYTE GA-K8NS Pro-939: Socket 939 + NVIDIA nForce3 + CK8
Idwer Volleringd8a00a02011-06-13 16:58:54 +00001165 */
1166static int nvidia_mcp_gpio0a_raise(void)
1167{
1168 return nvidia_mcp_gpio_set(0x0a, 1);
1169}
1170
1171/*
1172 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001173 * - MSI K8N Neo2 Platinum: Socket 939 + nForce3 Ultra + CK8
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001174 */
Michael Karcher51825082010-06-12 23:14:03 +00001175static int nvidia_mcp_gpio0c_raise(void)
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001176{
1177 return nvidia_mcp_gpio_set(0x0c, 1);
1178}
1179
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001180/*
1181 * Suited for:
1182 * - abit NF-M2 nView: Socket AM2 + NVIDIA MCP51
Michael Karcherefd8af32010-07-24 22:50:54 +00001183 */
1184static int nvidia_mcp_gpio4_lower(void)
1185{
1186 return nvidia_mcp_gpio_set(0x04, 0);
1187}
1188
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001189/*
1190 * Suited for:
1191 * - ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001192 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001193static int nvidia_mcp_gpio10_raise(void)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001194{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001195 return nvidia_mcp_gpio_set(0x10, 1);
1196}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001197
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001198/*
1199 * Suited for:
1200 * - GIGABYTE GA-K8N-SLI: AMD socket 939 + NVIDIA CK804 + ITE IT8712F
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001201 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001202static int nvidia_mcp_gpio21_raise(void)
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001203{
1204 return nvidia_mcp_gpio_set(0x21, 0x01);
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001205}
1206
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001207/*
1208 * Suited for:
1209 * - EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001210 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001211static int nvidia_mcp_gpio31_raise(void)
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001212{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001213 return nvidia_mcp_gpio_set(0x31, 0x01);
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001214}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001215
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001216/*
1217 * Suited for:
Michael Karcher242efd42011-03-06 12:09:05 +00001218 * - GIGABYTE GA-K8N51GMF: Socket 754 + Geforce 6100 + MCP51
1219 * - GIGABYTE GA-K8N51GMF-9: Socket 939 + Geforce 6100 + MCP51
Joshua Roys2ee137f2010-09-07 17:52:09 +00001220 */
1221static int nvidia_mcp_gpio3b_raise(void)
1222{
1223 return nvidia_mcp_gpio_set(0x3b, 1);
1224}
1225
1226/*
1227 * Suited for:
Joshua Roysb992d342011-11-02 14:31:18 +00001228 * - Sun Ultra 40 M2: Dual Socket F (1207) + MCP55
1229 */
1230static int board_sun_ultra_40_m2(void)
1231{
1232 int ret;
1233 uint8_t reg;
1234 uint16_t base;
1235 struct pci_dev *dev;
1236
1237 ret = nvidia_mcp_gpio4_lower();
1238 if (ret)
1239 return ret;
1240
1241 dev = pci_dev_find(0x10de, 0x0364); /* NVIDIA MCP55 LPC bridge */
1242 if (!dev) {
1243 msg_perr("\nERROR: NVIDIA MCP55 LPC bridge not found.\n");
1244 return -1;
1245 }
1246
1247 base = pci_read_word(dev, 0xb4); /* some IO BAR? */
1248 if (!base)
1249 return -1;
1250
1251 reg = INB(base + 0x4b);
1252 reg |= 0x10;
1253 OUTB(reg, base + 0x4b);
1254
1255 return 0;
1256}
1257
1258/*
1259 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001260 * - Artec Group DBE61 and DBE62
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001261 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001262static int board_artecgroup_dbe6x(void)
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001263{
1264#define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001265#define DBE6x_PRI_BOOT_LOC_SHIFT 2
1266#define DBE6x_BOOT_OP_LATCHED_SHIFT 8
1267#define DBE6x_SEC_BOOT_LOC_SHIFT 10
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001268#define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT)
1269#define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT)
1270#define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT)
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001271#define DBE6x_BOOT_LOC_FLASH 2
1272#define DBE6x_BOOT_LOC_FWHUB 3
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001273
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001274 msr_t msr;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001275 unsigned long boot_loc;
1276
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001277 /* Geode only has a single core */
1278 if (setup_cpu_msr(0))
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001279 return -1;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001280
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001281 msr = rdmsr(DBE6x_MSR_DIVIL_BALL_OPTS);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001282
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001283 if ((msr.lo & (DBE6x_BOOT_OP_LATCHED)) ==
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001284 (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT))
1285 boot_loc = DBE6x_BOOT_LOC_FWHUB;
1286 else
1287 boot_loc = DBE6x_BOOT_LOC_FLASH;
1288
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001289 msr.lo &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC);
1290 msr.lo |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) |
Uwe Hermann394131e2008-10-18 21:14:13 +00001291 (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001292
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001293 wrmsr(DBE6x_MSR_DIVIL_BALL_OPTS, msr);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001294
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001295 cleanup_cpu_msr();
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001296
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001297 return 0;
1298}
1299
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001300/*
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001301 * Suited for:
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001302 * - ASUS A8AE-LE (Codename AmberineM; used in Compaq Presario 061)
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001303 * Datasheet(s) used:
1304 * - AMD document 43009 "AMD SB700/710/750 Register Reference Guide" rev. 1.00
1305 */
1306static int amd_sbxxx_gpio9_raise(void)
1307{
1308 struct pci_dev *dev;
1309 uint32_t reg;
1310
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001311 dev = pci_dev_find(0x1002, 0x4372); /* AMD SMBus controller */
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001312 if (!dev) {
1313 msg_perr("\nERROR: AMD SMBus Controller (0x4372) not found.\n");
1314 return -1;
1315 }
1316
1317 reg = pci_read_long(dev, 0xA8); /* GPIO_12_to_4_Cntrl CI_Reg: A8h-ABh */
1318 /* enable output (0: enable, 1: tristate):
1319 GPIO9 output enable is at bit 5 in 0xA9 */
1320 reg &= ~((uint32_t)1<<(8+5));
1321 /* raise:
1322 GPIO9 output register is at bit 5 in 0xA8 */
1323 reg |= (1<<5);
1324 pci_write_long(dev, 0xA8, reg);
1325
1326 return 0;
1327}
1328
1329/*
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001330 * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}.
Luc Verhaegenf5226912009-12-14 10:41:58 +00001331 */
1332static int intel_piix4_gpo_set(unsigned int gpo, int raise)
1333{
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001334 unsigned int gpo_byte, gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001335 struct pci_dev *dev;
1336 uint32_t tmp, base;
1337
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001338 /* GPO{0,8,27,28,30} are always available. */
1339 static const uint32_t nonmuxed_gpos = 0x58000101;
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001340
1341 static const struct {unsigned int reg, mask, value; } piix4_gpo[] = {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001342 {0},
1343 {0xB0, 0x0001, 0x0000}, /* GPO1... */
1344 {0xB0, 0x0001, 0x0000},
1345 {0xB0, 0x0001, 0x0000},
1346 {0xB0, 0x0001, 0x0000},
1347 {0xB0, 0x0001, 0x0000},
1348 {0xB0, 0x0001, 0x0000},
1349 {0xB0, 0x0001, 0x0000}, /* ...GPO7: GENCFG bit 0 */
1350 {0},
1351 {0xB0, 0x0100, 0x0000}, /* GPO9: GENCFG bit 8 */
1352 {0xB0, 0x0200, 0x0000}, /* GPO10: GENCFG bit 9 */
1353 {0xB0, 0x0400, 0x0000}, /* GPO11: GENCFG bit 10 */
1354 {0x4E, 0x0100, 0x0000}, /* GPO12... */
1355 {0x4E, 0x0100, 0x0000},
1356 {0x4E, 0x0100, 0x0000}, /* ...GPO14: XBCS bit 8 */
1357 {0xB2, 0x0002, 0x0002}, /* GPO15... */
1358 {0xB2, 0x0002, 0x0002}, /* ...GPO16: GENCFG bit 17 */
1359 {0xB2, 0x0004, 0x0004}, /* GPO17: GENCFG bit 18 */
1360 {0xB2, 0x0008, 0x0008}, /* GPO18: GENCFG bit 19 */
1361 {0xB2, 0x0010, 0x0010}, /* GPO19: GENCFG bit 20 */
1362 {0xB2, 0x0020, 0x0020}, /* GPO20: GENCFG bit 21 */
1363 {0xB2, 0x0040, 0x0040}, /* GPO21: GENCFG bit 22 */
1364 {0xB2, 0x1000, 0x1000}, /* GPO22... */
1365 {0xB2, 0x1000, 0x1000}, /* ...GPO23: GENCFG bit 28 */
1366 {0xB2, 0x2000, 0x2000}, /* GPO24: GENCFG bit 29 */
1367 {0xB2, 0x4000, 0x4000}, /* GPO25: GENCFG bit 30 */
1368 {0xB2, 0x8000, 0x8000}, /* GPO26: GENCFG bit 31 */
1369 {0},
1370 {0},
1371 {0x4E, 0x0100, 0x0000}, /* ...GPO29: XBCS bit 8 */
1372 {0}
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001373 };
1374
Luc Verhaegenf5226912009-12-14 10:41:58 +00001375 dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */
1376 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001377 msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +00001378 return -1;
1379 }
1380
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001381 /* Sanity check. */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001382 if (gpo > 30) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001383 msg_perr("\nERROR: Intel PIIX4 has no GPO%d.\n", gpo);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001384 return -1;
1385 }
1386
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001387 if ((((1 << gpo) & nonmuxed_gpos) == 0) &&
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001388 ((pci_read_word(dev, piix4_gpo[gpo].reg) & piix4_gpo[gpo].mask) !=
1389 piix4_gpo[gpo].value)) {
1390 msg_perr("\nERROR: PIIX4 GPO%d not programmed for output.\n", gpo);
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001391 return -1;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001392 }
1393
Luc Verhaegenf5226912009-12-14 10:41:58 +00001394 dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */
1395 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001396 msg_perr("\nERROR: Intel PIIX4 PM not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +00001397 return -1;
1398 }
1399
1400 /* PM IO base */
1401 base = pci_read_long(dev, 0x40) & 0x0000FFC0;
1402
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001403 gpo_byte = gpo >> 3;
1404 gpo_bit = gpo & 7;
1405 tmp = INB(base + 0x34 + gpo_byte); /* GPO register */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001406 if (raise)
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001407 tmp |= 0x01 << gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001408 else
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001409 tmp &= ~(0x01 << gpo_bit);
1410 OUTB(tmp, base + 0x34 + gpo_byte);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001411
1412 return 0;
1413}
1414
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001415/*
1416 * Suited for:
Joshua Roysd708fad2012-02-17 14:51:15 +00001417 * - ASUS OPLX-M
Mattias Mattsson85016b92010-09-01 01:21:34 +00001418 * - ASUS P2B-N
1419 */
1420static int intel_piix4_gpo18_lower(void)
1421{
1422 return intel_piix4_gpo_set(18, 0);
1423}
1424
1425/*
1426 * Suited for:
Mattias Mattssonc8ca3de2010-09-13 18:22:36 +00001427 * - MSI MS-6163 v2 (MS-6163 Pro): Intel 440BX + PIIX4E + Winbond W83977EF
1428 */
1429static int intel_piix4_gpo14_raise(void)
1430{
1431 return intel_piix4_gpo_set(14, 1);
1432}
1433
1434/*
1435 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001436 * - EPoX EP-BX3
Luc Verhaegenf5226912009-12-14 10:41:58 +00001437 */
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001438static int intel_piix4_gpo22_raise(void)
Luc Verhaegenf5226912009-12-14 10:41:58 +00001439{
1440 return intel_piix4_gpo_set(22, 1);
1441}
1442
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001443/*
1444 * Suited for:
Tim ter Laak4b933f02010-09-13 23:00:57 +00001445 * - abit BM6
1446 */
1447static int intel_piix4_gpo26_lower(void)
1448{
1449 return intel_piix4_gpo_set(26, 0);
1450}
1451
1452/*
1453 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001454 * - Intel SE440BX-2
Michael Karcher51cd0c92010-03-19 22:35:21 +00001455 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001456static int intel_piix4_gpo27_lower(void)
Michael Karcher51cd0c92010-03-19 22:35:21 +00001457{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001458 return intel_piix4_gpo_set(27, 0);
Michael Karcher51cd0c92010-03-19 22:35:21 +00001459}
1460
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001461/*
Mattias Mattsson2eaad632010-10-05 21:32:29 +00001462 * Suited for:
1463 * - Dell OptiPlex GX1
1464 */
1465static int intel_piix4_gpo30_lower(void)
1466{
1467 return intel_piix4_gpo_set(30, 0);
1468}
1469
1470/*
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001471 * Set a GPIO line on a given Intel ICH LPC controller.
Uwe Hermann93f66db2008-05-22 21:19:38 +00001472 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001473static int intel_ich_gpio_set(int gpio, int raise)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001474{
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001475 /* Table mapping the different Intel ICH LPC chipsets. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001476 static struct {
1477 uint16_t id;
1478 uint8_t base_reg;
1479 uint32_t bank0;
1480 uint32_t bank1;
1481 uint32_t bank2;
1482 } intel_ich_gpio_table[] = {
1483 {0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */
1484 {0x2420, 0x58, 0x0FE30000, 0, 0}, /* 82801AB (ICH0) */
1485 {0x2440, 0x58, 0x1BFF391B, 0, 0}, /* 82801BA (ICH2) */
1486 {0x244C, 0x58, 0x1A23399B, 0, 0}, /* 82801BAM (ICH2M) */
1487 {0x2450, 0x58, 0x1BFF0000, 0, 0}, /* 82801E (C-ICH) */
1488 {0x2480, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801CA (ICH3-S) */
1489 {0x248C, 0x58, 0x1A230000, 0x00000FFF, 0}, /* 82801CAM (ICH3-M) */
1490 {0x24C0, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801DB/DBL (ICH4/ICH4-L) */
1491 {0x24CC, 0x58, 0x1A030000, 0x00000FFF, 0}, /* 82801DBM (ICH4-M) */
1492 {0x24D0, 0x58, 0x1BFF0000, 0x00030305, 0}, /* 82801EB/ER (ICH5/ICH5R) */
1493 {0x2640, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FB/FR (ICH6/ICH6R) */
1494 {0x2641, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FBM (ICH6M) */
1495 {0x27B8, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GB/GR (ICH7 Family) */
1496 {0x27B9, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GBM (ICH7-M) */
1497 {0x27BD, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GHM (ICH7-M DH) */
1498 {0x2810, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HB/HR (ICH8/R) */
1499 {0x2811, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HBM (ICH8M-E) */
1500 {0x2812, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HH (ICH8DH) */
1501 {0x2814, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HO (ICH8DO) */
1502 {0x2815, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HEM (ICH8M) */
1503 {0x2912, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IH (ICH9DH) */
1504 {0x2914, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IO (ICH9DO) */
1505 {0x2916, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IR (ICH9R) */
1506 {0x2917, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IEM (ICH9M-E) */
1507 {0x2918, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IB (ICH9) */
1508 {0x2919, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IBM (ICH9M) */
1509 {0x3A14, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JDO (ICH10DO) */
1510 {0x3A16, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIR (ICH10R) */
1511 {0x3A18, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIB (ICH10) */
1512 {0x3A1A, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JD (ICH10D) */
1513 {0, 0, 0, 0, 0} /* end marker */
1514 };
Uwe Hermann93f66db2008-05-22 21:19:38 +00001515
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001516 struct pci_dev *dev;
1517 uint16_t base;
1518 uint32_t tmp;
1519 int i, allowed;
1520
1521 /* First, look for a known LPC bridge */
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001522 for (dev = pacc->devices; dev; dev = dev->next) {
Carl-Daniel Hailfingerd175e062010-05-21 23:00:56 +00001523 uint16_t device_class;
1524 /* libpci before version 2.2.4 does not store class info. */
1525 device_class = pci_read_word(dev, PCI_CLASS_DEVICE);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001526 if ((dev->vendor_id == 0x8086) &&
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001527 (device_class == 0x0601)) { /* ISA bridge */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001528 /* Is this device in our list? */
1529 for (i = 0; intel_ich_gpio_table[i].id; i++)
1530 if (dev->device_id == intel_ich_gpio_table[i].id)
1531 break;
1532
1533 if (intel_ich_gpio_table[i].id)
1534 break;
1535 }
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001536 }
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001537
Uwe Hermann93f66db2008-05-22 21:19:38 +00001538 if (!dev) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001539 msg_perr("\nERROR: No known Intel LPC bridge found.\n");
Uwe Hermann93f66db2008-05-22 21:19:38 +00001540 return -1;
1541 }
1542
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001543 /*
1544 * According to the datasheets, all Intel ICHs have the GPIO bar 5:1
1545 * strapped to zero. From some mobile ICH9 version on, this becomes
1546 * 6:1. The mask below catches all.
1547 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001548 base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0;
Uwe Hermann93f66db2008-05-22 21:19:38 +00001549
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001550 /* Check whether the line is allowed. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001551 if (gpio < 32)
1552 allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01;
1553 else if (gpio < 64)
1554 allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01;
1555 else
1556 allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01;
1557
1558 if (!allowed) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001559 msg_perr("\nERROR: This Intel LPC bridge does not allow"
1560 " setting GPIO%02d\n", gpio);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001561 return -1;
1562 }
1563
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001564 msg_pdbg("\nIntel ICH LPC bridge: %sing GPIO%02d.\n",
1565 raise ? "Rais" : "Dropp", gpio);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001566
1567 if (gpio < 32) {
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001568 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001569 tmp = INL(base);
1570 /* ICH/ICH0 multiplexes 27/28 on the line set. */
1571 if ((gpio == 28) &&
1572 ((dev->device_id == 0x2410) || (dev->device_id == 0x2420)))
1573 tmp |= 1 << 27;
1574 else
1575 tmp |= 1 << gpio;
1576 OUTL(tmp, base);
1577
1578 /* As soon as we are talking to ICH8 and above, this register
1579 decides whether we can set the gpio or not. */
1580 if (dev->device_id > 0x2800) {
1581 tmp = INL(base);
1582 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001583 msg_perr("\nERROR: This Intel LPC bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001584 " does not allow setting GPIO%02d\n",
1585 gpio);
1586 return -1;
1587 }
1588 }
1589
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001590 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001591 tmp = INL(base + 0x04);
1592 tmp &= ~(1 << gpio);
1593 OUTL(tmp, base + 0x04);
1594
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001595 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001596 tmp = INL(base + 0x0C);
1597 if (raise)
1598 tmp |= 1 << gpio;
1599 else
1600 tmp &= ~(1 << gpio);
1601 OUTL(tmp, base + 0x0C);
1602 } else if (gpio < 64) {
1603 gpio -= 32;
1604
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001605 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001606 tmp = INL(base + 0x30);
1607 tmp |= 1 << gpio;
1608 OUTL(tmp, base + 0x30);
1609
1610 /* As soon as we are talking to ICH8 and above, this register
1611 decides whether we can set the gpio or not. */
1612 if (dev->device_id > 0x2800) {
1613 tmp = INL(base + 30);
1614 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001615 msg_perr("\nERROR: This Intel LPC bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001616 " does not allow setting GPIO%02d\n",
1617 gpio + 32);
1618 return -1;
1619 }
1620 }
1621
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001622 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001623 tmp = INL(base + 0x34);
1624 tmp &= ~(1 << gpio);
1625 OUTL(tmp, base + 0x34);
1626
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001627 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001628 tmp = INL(base + 0x38);
1629 if (raise)
1630 tmp |= 1 << gpio;
1631 else
1632 tmp &= ~(1 << gpio);
1633 OUTL(tmp, base + 0x38);
1634 } else {
1635 gpio -= 64;
1636
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001637 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001638 tmp = INL(base + 0x40);
1639 tmp |= 1 << gpio;
1640 OUTL(tmp, base + 0x40);
1641
1642 tmp = INL(base + 40);
1643 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001644 msg_perr("\nERROR: This Intel LPC bridge does "
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001645 "not allow setting GPIO%02d\n", gpio + 64);
1646 return -1;
1647 }
1648
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001649 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001650 tmp = INL(base + 0x44);
1651 tmp &= ~(1 << gpio);
1652 OUTL(tmp, base + 0x44);
1653
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001654 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001655 tmp = INL(base + 0x48);
1656 if (raise)
1657 tmp |= 1 << gpio;
1658 else
1659 tmp &= ~(1 << gpio);
1660 OUTL(tmp, base + 0x48);
1661 }
Uwe Hermann93f66db2008-05-22 21:19:38 +00001662
1663 return 0;
1664}
1665
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001666/*
1667 * Suited for:
1668 * - abit IP35: Intel P35 + ICH9R
1669 * - abit IP35 Pro: Intel P35 + ICH9R
Joshua Roysac8b2a12011-08-11 04:21:34 +00001670 * - ASUS P5LD2
Uwe Hermann93f66db2008-05-22 21:19:38 +00001671 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001672static int intel_ich_gpio16_raise(void)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001673{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001674 return intel_ich_gpio_set(16, 1);
Uwe Hermann93f66db2008-05-22 21:19:38 +00001675}
1676
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001677/*
1678 * Suited for:
1679 * - HP Puffer2-UL8E (ASUS PTGD-LA OEM): LGA775 + 915 + ICH6
Michael Karchere57957c2010-07-24 11:14:37 +00001680 */
1681static int intel_ich_gpio18_raise(void)
1682{
1683 return intel_ich_gpio_set(18, 1);
1684}
1685
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001686/*
1687 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001688 * - MSI MS-7046: LGA775 + 915P + ICH6
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001689 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001690static int intel_ich_gpio19_raise(void)
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001691{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001692 return intel_ich_gpio_set(19, 1);
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001693}
1694
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001695/*
Luc Verhaegen6c5d4cc2009-11-28 18:26:21 +00001696 * Suited for:
Stefan Tauner027e0182012-05-02 19:48:21 +00001697 * - ASUS P5BV-R: LGA775 + 3200 + ICH7
1698 */
1699static int intel_ich_gpio20_raise(void)
1700{
1701 return intel_ich_gpio_set(20, 1);
1702}
1703
1704/*
1705 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001706 * - ASUS P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2
1707 * - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5
Michael Karcherf4b58792010-09-10 14:54:18 +00001708 * - ASUS P4P800: Intel socket478 + 865PE + ICH5R
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001709 * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R
Diego Elio Pettenòc6f71462011-03-06 22:52:55 +00001710 * - ASUS P4P800-VM: Intel socket478 + 865PE + ICH5R
Michael Karcher4a23e442010-09-10 14:46:46 +00001711 * - ASUS P5GD1 Pro: Intel LGA 775 + 915P + ICH6R
Joshua Roys1fd4f9e2011-08-11 05:47:32 +00001712 * - ASUS P5GD2 Premium: Intel LGA775 + 915G + ICH6R
Joshua Roysb1d980f2010-09-13 14:02:22 +00001713 * - ASUS P5GDC Deluxe: Intel socket775 + 915P + ICH6R
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001714 * - ASUS P5PE-VM: Intel LGA775 + 865G + ICH5
Stefan Taunerded71e52012-03-10 19:22:13 +00001715 * - ASUS TUSL2-C: Intel socket370 + 815 + ICH2
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001716 * - Samsung Polaris 32: socket478 + 865P + ICH5
Peter Stuge09c13332009-02-02 22:55:26 +00001717 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001718static int intel_ich_gpio21_raise(void)
Peter Stuge09c13332009-02-02 22:55:26 +00001719{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001720 return intel_ich_gpio_set(21, 1);
Peter Stuge09c13332009-02-02 22:55:26 +00001721}
1722
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001723/*
Michael Karcher03b80e92010-03-07 16:32:32 +00001724 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001725 * - ASUS P4B266: socket478 + Intel 845D + ICH2
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001726 * - ASUS P4B533-E: socket478 + 845E + ICH4
1727 * - ASUS P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2
Michael Karcherbfd89a52012-02-12 00:13:14 +00001728 * - TriGem Anaheim-3: socket370 + Intel 810 + ICH
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001729 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001730static int intel_ich_gpio22_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001731{
1732 return intel_ich_gpio_set(22, 1);
1733}
1734
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001735/*
1736 * Suited for:
Stefan Tauner716e0982011-07-25 20:38:52 +00001737 * - ASUS A8Jm (laptop): Intel 945 + ICH7
Michael Karcher14ab8d42011-08-25 14:06:50 +00001738 * - ASUS P5LP-LE used in ...
1739 * - HP Media Center m7270.fr Desktop PC as "Lithium-UL8E"
1740 * - Epson Endeavor MT7700
Stefan Tauner716e0982011-07-25 20:38:52 +00001741 */
1742static int intel_ich_gpio34_raise(void)
1743{
1744 return intel_ich_gpio_set(34, 1);
1745}
1746
1747/*
1748 * Suited for:
Stefan Taunerc6782182012-01-19 17:50:32 +00001749 * - AOpen i945GMx-VFX: Intel 945GM + ICH7-M used in ...
Paul Menzelac427b22012-02-16 21:07:07 +00001750 * - FSC ESPRIMO Q5010 (SMBIOS: D2544-B1)
Stefan Taunerc6782182012-01-19 17:50:32 +00001751 */
1752static int intel_ich_gpio38_raise(void)
1753{
1754 return intel_ich_gpio_set(38, 1);
1755}
1756
1757/*
1758 * Suited for:
Joshua Roysc73e2812011-07-09 19:46:53 +00001759 * - ASUS M6Ne (laptop): socket 479M (guessed) + Intel 855PM + ICH4-M
1760 */
1761static int intel_ich_gpio43_raise(void)
1762{
1763 return intel_ich_gpio_set(43, 1);
1764}
1765
1766/*
1767 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001768 * - HP Vectra VL400: 815 + ICH + PC87360
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001769 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001770static int board_hp_vl400(void)
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001771{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001772 int ret;
1773 ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */
1774 if (!ret)
Michael Karchercba52de2011-03-06 12:07:19 +00001775 ret = pc8736x_gpio_set(PC87360_ID, 0x09, 1); /* #WP ? */
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001776 if (!ret)
Michael Karchercba52de2011-03-06 12:07:19 +00001777 ret = pc8736x_gpio_set(PC87360_ID, 0x27, 1); /* #TBL */
1778 return ret;
1779}
1780
1781/*
1782 * Suited for:
1783 * - HP e-Vectra P2706T: 810E + ICH + PC87364
1784 */
1785static int board_hp_p2706t(void)
1786{
1787 int ret;
1788 ret = pc8736x_gpio_set(PC87364_ID, 0x25, 1);
1789 if (!ret)
1790 ret = pc8736x_gpio_set(PC87364_ID, 0x26, 1);
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001791 return ret;
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001792}
1793
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001794/*
Luc Verhaegen1265d8d2009-11-28 18:16:31 +00001795 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001796 * - Dell PowerEdge 1850: Intel PPGA604 + E7520 + ICH5R
1797 * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R
1798 * - ASRock 775i65G: Intel LGA 775 + 865G + ICH5
Uwe Hermann742999c2010-12-02 21:57:42 +00001799 * - MSI MS-6391 (845 Pro4): Intel Socket478 + 845 + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001800 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001801static int intel_ich_gpio23_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001802{
1803 return intel_ich_gpio_set(23, 1);
1804}
1805
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001806/*
1807 * Suited for:
Michael Karcher39dcdec2010-10-05 17:29:35 +00001808 * - GIGABYTE GA-6IEM: Intel Socket370 + i815 + ICH2
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001809 * - GIGABYTE GA-8IRML: Intel Socket478 + i845 + ICH2
Michael Karcherc7a1ffb2010-07-24 22:27:29 +00001810 */
1811static int intel_ich_gpio25_raise(void)
1812{
1813 return intel_ich_gpio_set(25, 1);
1814}
1815
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001816/*
1817 * Suited for:
1818 * - IBASE MB899: i945GM + ICH7
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001819 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001820static int intel_ich_gpio26_raise(void)
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001821{
1822 return intel_ich_gpio_set(26, 1);
1823}
1824
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001825/*
1826 * Suited for:
1827 * - P4SD-LA (HP OEM): i865 + ICH5
Joshua Roys9d9a1042011-06-13 16:59:01 +00001828 * - GIGABYTE GA-8IP775: 865P + ICH5
Michael Karcherc8613242010-08-13 12:49:01 +00001829 * - GIGABYTE GA-8PE667 Ultra 2: socket 478 + i845PE + ICH4
Maciej Pijanka6add0942011-06-09 20:59:30 +00001830 * - MSI MS-6788-40 (aka 848P Neo-V)
Michael Karcher87c90992010-07-24 11:03:48 +00001831 */
Idwer Vollering19dceac2010-07-24 18:47:45 +00001832static int intel_ich_gpio32_raise(void)
Michael Karcher87c90992010-07-24 11:03:48 +00001833{
1834 return intel_ich_gpio_set(32, 1);
1835}
1836
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001837/*
1838 * Suited for:
Joshua Roys7225ccd2011-05-18 01:32:16 +00001839 * - AOpen i975Xa-YDG: i975X + ICH7 + W83627EHF
1840 */
1841static int board_aopen_i975xa_ydg(void)
1842{
1843 int ret;
1844
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001845 /* Vendor BIOS ends up in LDN6... maybe the board enable is wrong,
Joshua Roys7225ccd2011-05-18 01:32:16 +00001846 * or perhaps it's not needed at all?
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001847 * The regs it tries to touch are 0xF0, 0xF1, 0xF2 which means if it
1848 * were in the right LDN, it would have to be GPIO1 or GPIO3.
Joshua Roys7225ccd2011-05-18 01:32:16 +00001849 */
1850/*
1851 ret = winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, x, 0)
1852 if (!ret)
1853*/
1854 ret = intel_ich_gpio_set(33, 1);
1855
1856 return ret;
1857}
1858
1859/*
1860 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001861 * - Acorp 6A815EPD: socket 370 + intel 815 + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001862 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001863static int board_acorp_6a815epd(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001864{
1865 int ret;
1866
1867 /* Lower Blocks Lock -- pin 7 of PLCC32 */
1868 ret = intel_ich_gpio_set(22, 1);
1869 if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */
1870 ret = intel_ich_gpio_set(23, 1);
1871
1872 return ret;
1873}
1874
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001875/*
1876 * Suited for:
1877 * - Kontron 986LCD-M: Socket478 + 915GM + ICH7R
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001878 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001879static int board_kontron_986lcd_m(void)
Stefan Reinauerac378972008-03-17 22:59:40 +00001880{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001881 int ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001882
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001883 ret = intel_ich_gpio_set(34, 1); /* #TBL */
1884 if (!ret)
1885 ret = intel_ich_gpio_set(35, 1); /* #WP */
Stefan Reinauerac378972008-03-17 22:59:40 +00001886
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001887 return ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001888}
1889
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001890/*
1891 * Suited for:
1892 * - Soyo SY-7VCA: Pro133A + VT82C686
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001893 */
Michael Karcher06477332010-03-19 22:49:09 +00001894static int via_apollo_gpo_set(int gpio, int raise)
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001895{
Michael Karcher06477332010-03-19 22:49:09 +00001896 struct pci_dev *dev;
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001897 uint32_t base, tmp;
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001898
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001899 /* VT82C686 power management */
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001900 dev = pci_dev_find(0x1106, 0x3057);
1901 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001902 msg_perr("\nERROR: VT82C686 PM device not found.\n");
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001903 return -1;
1904 }
1905
Sean Nelson316a29f2010-05-07 20:09:04 +00001906 msg_pdbg("\nVIA Apollo ACPI: %sing GPIO%02d.\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001907 raise ? "Rais" : "Dropp", gpio);
Michael Karcher06477332010-03-19 22:49:09 +00001908
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001909 /* Select GPO function on multiplexed pins. */
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001910 tmp = pci_read_byte(dev, 0x54);
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001911 switch (gpio) {
1912 case 0:
1913 tmp &= ~0x03;
1914 break;
1915 case 1:
1916 tmp |= 0x04;
1917 break;
1918 case 2:
1919 tmp |= 0x08;
1920 break;
1921 case 3:
1922 tmp |= 0x10;
1923 break;
Michael Karcher06477332010-03-19 22:49:09 +00001924 }
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001925 pci_write_byte(dev, 0x54, tmp);
1926
1927 /* PM IO base */
1928 base = pci_read_long(dev, 0x48) & 0x0000FF00;
1929
1930 /* Drop GPO0 */
Michael Karcher06477332010-03-19 22:49:09 +00001931 tmp = INL(base + 0x4C);
1932 if (raise)
1933 tmp |= 1U << gpio;
1934 else
1935 tmp &= ~(1U << gpio);
1936 OUTL(tmp, base + 0x4C);
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001937
1938 return 0;
1939}
1940
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001941/*
1942 * Suited for:
1943 * - abit VT6X4: Pro133x + VT82C686A
Mattias Mattssone3df96e2010-08-15 22:43:23 +00001944 * - abit VA6: Pro133x + VT82C686A
Michael Karcher187a46a2010-03-19 22:30:49 +00001945 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001946static int via_apollo_gpo4_lower(void)
Michael Karcher187a46a2010-03-19 22:30:49 +00001947{
1948 return via_apollo_gpo_set(4, 0);
1949}
1950
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001951/*
1952 * Suited for:
1953 * - Soyo SY-7VCA: Pro133A + VT82C686
Michael Karcher06477332010-03-19 22:49:09 +00001954 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001955static int via_apollo_gpo0_lower(void)
Michael Karcher06477332010-03-19 22:49:09 +00001956{
1957 return via_apollo_gpo_set(0, 0);
1958}
1959
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001960/*
Michael Karchera08d0f22011-07-25 17:25:24 +00001961 * Enable some GPIO pin on SiS southbridge and enables SIO flash writes.
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001962 *
1963 * Suited for:
1964 * - MSI 651M-L: SiS651 / SiS962
Michael Karchera08d0f22011-07-25 17:25:24 +00001965 * - GIGABYTE GA-8SIMLH
Michael Karcher9f9e6132010-01-09 17:36:06 +00001966 */
Michael Karchera08d0f22011-07-25 17:25:24 +00001967static int sis_gpio0_raise_and_w836xx_memw(void)
Michael Karcher9f9e6132010-01-09 17:36:06 +00001968{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001969 struct pci_dev *dev;
Uwe Hermann43959702010-03-13 17:28:29 +00001970 uint16_t base, temp;
Michael Karcher9f9e6132010-01-09 17:36:06 +00001971
1972 dev = pci_dev_find(0x1039, 0x0962);
1973 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001974 msg_perr("Expected south bridge not found\n");
Michael Karcher9f9e6132010-01-09 17:36:06 +00001975 return 1;
1976 }
1977
Michael Karcher9f9e6132010-01-09 17:36:06 +00001978 base = pci_read_word(dev, 0x74);
1979 temp = INW(base + 0x68);
1980 temp &= ~(1 << 0); /* Make pin output? */
Michael Karcher0435dfd2010-01-09 23:31:13 +00001981 OUTW(temp, base + 0x68);
Michael Karcher9f9e6132010-01-09 17:36:06 +00001982
1983 temp = INW(base + 0x64);
1984 temp |= (1 << 0); /* Raise output? */
1985 OUTW(temp, base + 0x64);
1986
1987 w836xx_memw_enable(0x2E);
1988
1989 return 0;
1990}
1991
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001992/*
Michael Gold6d52e472009-06-19 13:00:24 +00001993 * Find the runtime registers of an SMSC Super I/O, after verifying its
1994 * chip ID.
1995 *
1996 * Returns the base port of the runtime register block, or 0 on error.
1997 */
1998static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id,
1999 uint8_t logical_device)
2000{
2001 uint16_t rt_port = 0;
2002
2003 /* Verify the chip ID. */
Uwe Hermann1432a602009-06-28 23:26:37 +00002004 OUTB(0x55, sio_port); /* Enable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00002005 if (sio_read(sio_port, 0x20) != chip_id) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002006 msg_perr("\nERROR: SMSC Super I/O not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +00002007 goto out;
2008 }
2009
2010 /* If the runtime block is active, get its address. */
2011 sio_write(sio_port, 0x07, logical_device);
2012 if (sio_read(sio_port, 0x30) & 1) {
2013 rt_port = (sio_read(sio_port, 0x60) << 8)
2014 | sio_read(sio_port, 0x61);
2015 }
2016
2017 if (rt_port == 0) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002018 msg_perr("\nERROR: "
Michael Gold6d52e472009-06-19 13:00:24 +00002019 "Super I/O runtime interface not available.\n");
2020 }
2021out:
Uwe Hermann1432a602009-06-28 23:26:37 +00002022 OUTB(0xaa, sio_port); /* Disable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00002023 return rt_port;
2024}
2025
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002026/*
2027 * Disable write protection on the Mitac 6513WU. WP# on the FWH is
Michael Gold6d52e472009-06-19 13:00:24 +00002028 * connected to GP30 on the Super I/O, and TBL# is always high.
2029 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00002030static int board_mitac_6513wu(void)
Michael Gold6d52e472009-06-19 13:00:24 +00002031{
2032 struct pci_dev *dev;
2033 uint16_t rt_port;
2034 uint8_t val;
2035
2036 dev = pci_dev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */
2037 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002038 msg_perr("\nERROR: Intel 82801AA ISA bridge not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +00002039 return -1;
2040 }
2041
Uwe Hermann1432a602009-06-28 23:26:37 +00002042 rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa);
Michael Gold6d52e472009-06-19 13:00:24 +00002043 if (rt_port == 0)
2044 return -1;
2045
2046 /* Configure the GPIO pin. */
2047 val = INB(rt_port + 0x33); /* GP30 config */
Uwe Hermann1432a602009-06-28 23:26:37 +00002048 val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */
Michael Gold6d52e472009-06-19 13:00:24 +00002049 OUTB(val, rt_port + 0x33);
2050
2051 /* Disable write protection. */
2052 val = INB(rt_port + 0x4d); /* GP3 values */
Uwe Hermann1432a602009-06-28 23:26:37 +00002053 val |= 0x01; /* Set GP30 high. */
Michael Gold6d52e472009-06-19 13:00:24 +00002054 OUTB(val, rt_port + 0x4d);
2055
2056 return 0;
2057}
2058
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002059/*
2060 * Suited for:
Christoph Grenzd13a3942011-10-21 13:20:11 +00002061 * - abit AV8: Socket939 + K8T800Pro + VT8237
2062 */
2063static int board_abit_av8(void)
2064{
2065 uint8_t val;
2066
2067 /* Raise GPO pins GP22 & GP23 */
2068 val = INB(0x404E);
2069 val |= 0xC0;
2070 OUTB(val, 0x404E);
2071
2072 return 0;
2073}
2074
2075/*
2076 * Suited for:
Uwe Hermann45bd1442010-09-14 23:20:35 +00002077 * - ASUS A7V333: VIA KT333 + VT8233A + IT8703F
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002078 * - ASUS A7V8X: VIA KT400 + VT8235 + IT8703F
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002079 */
Uwe Hermann45bd1442010-09-14 23:20:35 +00002080static int it8703f_gpio51_raise(void)
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002081{
2082 uint16_t id, base;
2083 uint8_t tmp;
2084
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002085 /* Find the IT8703F. */
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002086 w836xx_ext_enter(0x2E);
2087 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
2088 w836xx_ext_leave(0x2E);
2089
2090 if (id != 0x8701) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002091 msg_perr("\nERROR: IT8703F Super I/O not found.\n");
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002092 return -1;
2093 }
2094
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002095 /* Get the GP567 I/O base. */
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002096 w836xx_ext_enter(0x2E);
2097 sio_write(0x2E, 0x07, 0x0C);
2098 base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
2099 w836xx_ext_leave(0x2E);
2100
2101 if (!base) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002102 msg_perr("\nERROR: Failed to read IT8703F Super I/O GPIO"
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002103 " Base.\n");
2104 return -1;
2105 }
2106
2107 /* Raise GP51. */
2108 tmp = INB(base);
2109 tmp |= 0x02;
2110 OUTB(tmp, base);
2111
2112 return 0;
2113}
2114
Luc Verhaegen72272912009-09-01 21:22:23 +00002115/*
Joshua Roysa2f37222011-11-14 13:00:12 +00002116 * General routine for raising/dropping GPIO lines on the ITE IT87xx.
Luc Verhaegen72272912009-09-01 21:22:23 +00002117 */
Joshua Roysa2f37222011-11-14 13:00:12 +00002118static int it87_gpio_set(unsigned int gpio, int raise)
Luc Verhaegen72272912009-09-01 21:22:23 +00002119{
Joshua Roysa2f37222011-11-14 13:00:12 +00002120 int allowed, sio;
Luc Verhaegen72272912009-09-01 21:22:23 +00002121 unsigned int port;
Joshua Roysa2f37222011-11-14 13:00:12 +00002122 uint16_t base, sioport;
Luc Verhaegen72272912009-09-01 21:22:23 +00002123 uint8_t tmp;
2124
Joshua Roysa2f37222011-11-14 13:00:12 +00002125 /* IT87 GPIO configuration table */
2126 static const struct it87cfg {
2127 uint16_t id;
2128 uint8_t base_reg;
2129 uint32_t bank0;
2130 uint32_t bank1;
2131 uint32_t bank2;
2132 } it87_gpio_table[] = {
2133 {0x8712, 0x62, 0xCFF3FC00, 0x00FCFF3F, 0},
2134 {0x8718, 0x62, 0xCFF37C00, 0xF3FCDF3F, 0x0000000F},
2135 {0, 0, 0, 0, 0} /* end marker */
2136 };
2137 const struct it87cfg *cfg = NULL;
Luc Verhaegen72272912009-09-01 21:22:23 +00002138
Joshua Roysa2f37222011-11-14 13:00:12 +00002139 /* Find the Super I/O in the probed list */
2140 for (sio = 0; sio < superio_count; sio++) {
2141 int i;
2142 if (superios[sio].vendor != SUPERIO_VENDOR_ITE)
2143 continue;
2144
2145 /* Is this device in our list? */
2146 for (i = 0; it87_gpio_table[i].id; i++)
2147 if (superios[sio].model == it87_gpio_table[i].id) {
2148 cfg = &it87_gpio_table[i];
2149 goto found;
2150 }
2151 }
2152
2153 if (cfg == NULL) {
2154 msg_perr("\nERROR: No IT87 Super I/O GPIO configuration "
2155 "found.\n");
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002156 return -1;
Luc Verhaegen72272912009-09-01 21:22:23 +00002157 }
2158
Joshua Roysa2f37222011-11-14 13:00:12 +00002159found:
2160 /* Check whether the gpio is allowed. */
2161 if (gpio < 32)
2162 allowed = (cfg->bank0 >> gpio) & 0x01;
2163 else if (gpio < 64)
2164 allowed = (cfg->bank1 >> (gpio - 32)) & 0x01;
2165 else if (gpio < 96)
2166 allowed = (cfg->bank2 >> (gpio - 64)) & 0x01;
2167 else
2168 allowed = 0;
Luc Verhaegen72272912009-09-01 21:22:23 +00002169
Joshua Roysa2f37222011-11-14 13:00:12 +00002170 if (!allowed) {
2171 msg_perr("\nERROR: IT%02X does not allow setting GPIO%02u.\n",
2172 cfg->id, gpio);
Luc Verhaegen72272912009-09-01 21:22:23 +00002173 return -1;
2174 }
2175
Joshua Roysa2f37222011-11-14 13:00:12 +00002176 /* Read the Simple I/O Base Address Register */
2177 sioport = superios[sio].port;
2178 enter_conf_mode_ite(sioport);
2179 sio_write(sioport, 0x07, 0x07);
2180 base = (sio_read(sioport, cfg->base_reg) << 8) |
2181 sio_read(sioport, cfg->base_reg + 1);
2182 exit_conf_mode_ite(sioport);
Luc Verhaegen72272912009-09-01 21:22:23 +00002183
2184 if (!base) {
Joshua Roysa2f37222011-11-14 13:00:12 +00002185 msg_perr("\nERROR: Failed to read IT87 Super I/O GPIO Base.\n");
Luc Verhaegen72272912009-09-01 21:22:23 +00002186 return -1;
2187 }
2188
Joshua Roysa2f37222011-11-14 13:00:12 +00002189 msg_pdbg("Using IT87 GPIO base 0x%04x\n", base);
2190
2191 port = gpio / 10 - 1;
2192 gpio %= 10;
2193
2194 /* set GPIO. */
Luc Verhaegen72272912009-09-01 21:22:23 +00002195 tmp = INB(base + port);
2196 if (raise)
Joshua Roysa2f37222011-11-14 13:00:12 +00002197 tmp |= 1 << gpio;
Luc Verhaegen72272912009-09-01 21:22:23 +00002198 else
Joshua Roysa2f37222011-11-14 13:00:12 +00002199 tmp &= ~(1 << gpio);
Luc Verhaegen72272912009-09-01 21:22:23 +00002200 OUTB(tmp, base + port);
2201
2202 return 0;
2203}
2204
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002205/*
Russ Dillbd622d12010-03-09 16:57:06 +00002206 * Suited for:
Joshua Roys8ca42552011-11-19 19:31:17 +00002207 * - ASUS A7N8X-VM/400: NVIDIA nForce2 IGP2 + IT8712F
2208 */
2209static int it8712f_gpio12_raise(void)
2210{
2211 return it87_gpio_set(12, 1);
2212}
2213
2214/*
2215 * Suited for:
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00002216 * - ASUS A7V600-X: VIA KT600 + VT8237 + IT8712F
2217 * - ASUS A7V8X-X: VIA KT400 + VT8235 + IT8712F
Luc Verhaegen72272912009-09-01 21:22:23 +00002218 */
Joshua Roysa2f37222011-11-14 13:00:12 +00002219static int it8712f_gpio31_raise(void)
Luc Verhaegen72272912009-09-01 21:22:23 +00002220{
Joshua Roysa2f37222011-11-14 13:00:12 +00002221 return it87_gpio_set(32, 1);
2222}
2223
2224/*
2225 * Suited for:
2226 * - ASUS P5N-D: NVIDIA MCP51 + IT8718F
2227 * - ASUS P5N-E SLI: NVIDIA MCP51 + IT8718F
2228 */
2229static int it8718f_gpio63_raise(void)
2230{
2231 return it87_gpio_set(63, 1);
Luc Verhaegen72272912009-09-01 21:22:23 +00002232}
2233
Ingo Feldschmid8a0f9b02012-01-31 06:51:56 +00002234/*
2235 * Suited for all boards with ambiguous DMI chassis information, which should be
2236 * whitelisted because they are known to work:
2237 * - MSC Q7 Tunnel Creek Module (Q7-TCTC)
2238 */
2239static int p2_not_a_laptop(void)
2240{
2241 /* label this board as not a laptop */
2242 is_laptop = 0;
2243 msg_pdbg("Laptop detection overridden by P2 board enable.\n");
2244 return 0;
2245}
2246
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00002247#endif
2248
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002249/*
Uwe Hermannd0e347d2009-10-06 13:00:00 +00002250 * Below is the list of boards which need a special "board enable" code in
2251 * flashrom before their ROM chip can be accessed/written to.
2252 *
2253 * NOTE: Please add boards that _don't_ need such enables or don't work yet
2254 * to the respective tables in print.c. Thanks!
2255 *
Uwe Hermannffec5f32007-08-23 16:08:21 +00002256 * We use 2 sets of IDs here, you're free to choose which is which. This
2257 * is to provide a very high degree of certainty when matching a board on
2258 * the basis of subsystem/card IDs. As not every vendor handles
2259 * subsystem/card IDs in a sane manner.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002260 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00002261 * Keep the second set NULLed if it should be ignored. Keep the subsystem IDs
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00002262 * NULLed if they don't identify the board fully and if you can't use DMI.
2263 * But please take care to provide an as complete set of pci ids as possible;
2264 * autodetection is the preferred behaviour and we would like to make sure that
2265 * matches are unique.
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00002266 *
Michael Karcher6701ee82010-01-20 14:14:11 +00002267 * If PCI IDs are not sufficient for board matching, the match can be further
2268 * constrained by a string that has to be present in the DMI database for
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00002269 * the baseboard or the system entry. The pattern is matched by case sensitive
Michael Karcher6701ee82010-01-20 14:14:11 +00002270 * substring match, unless it is anchored to the beginning (with a ^ in front)
2271 * or the end (with a $ at the end). Both anchors may be specified at the
2272 * same time to match the full field.
2273 *
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00002274 * When a board is matched through DMI, the first and second main PCI IDs
2275 * and the first subsystem PCI ID have to match as well. If you specify the
2276 * first subsystem ID as 0x0:0x0, the DMI matching code expects that the
2277 * subsystem ID of that device is indeed zero.
2278 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00002279 * The coreboot ids are used two fold. When running with a coreboot firmware,
2280 * the ids uniquely matches the coreboot board identification string. When a
2281 * legacy bios is installed and when autodetection is not possible, these ids
Carl-Daniel Hailfinger2d927fb2012-01-04 00:48:27 +00002282 * can be used to identify the board through the -p internal:mainboard=
2283 * programmer parameter.
Luc Verhaegenc5210162009-04-20 12:38:17 +00002284 *
2285 * When a board is identified through its coreboot ids (in both cases), the
2286 * main pci ids are still required to match, as a safeguard.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002287 */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002288
Uwe Hermanndeeebe22009-05-08 16:23:34 +00002289/* Please keep this list alphabetically ordered by vendor/board name. */
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002290const struct board_match board_matches[] = {
Uwe Hermann5ab88892009-06-21 20:50:22 +00002291
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002292 /* first pci-id set [4], second pci-id set [4], dmi identifier, coreboot id [2], phase, vendor name, board name max_rom_... OK? flash enable */
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00002293#if defined(__i386__) || defined(__x86_64__)
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002294 {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, P3, "abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise},
Christoph Grenzd13a3942011-10-21 13:20:11 +00002295 {0x1106, 0x0282, 0x147B, 0x1415, 0x1106, 0x3227, 0x147B, 0x1415, "^AV8 ", NULL, NULL, P3, "abit", "AV8", 0, OK, board_abit_av8},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002296 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^i440BX-W977 (BM6)$", NULL, NULL, P3, "abit", "BM6", 0, OK, intel_piix4_gpo26_lower},
2297 {0x8086, 0x24d3, 0x147b, 0x1014, 0x8086, 0x2578, 0x147b, 0x1014, NULL, NULL, NULL, P3, "abit", "IC7", 0, NT, intel_ich_gpio23_raise},
2298 {0x8086, 0x2930, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, P3, "abit", "IP35", 0, OK, intel_ich_gpio16_raise},
2299 {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, P3, "abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise},
2300 {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, P3, "abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower},
2301 {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, P3, "abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise},
Paul Menzelac427b22012-02-16 21:07:07 +00002302 {0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0260, 0x147b, 0x1c26, NULL, NULL, NULL, P3, "abit", "NF-M2 nView", 0, OK, nvidia_mcp_gpio4_lower},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002303 {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, "(VA6)$", NULL, NULL, P3, "abit", "VA6", 0, OK, via_apollo_gpo4_lower},
2304 {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", P3, "abit", "VT6X4", 0, OK, via_apollo_gpo4_lower},
2305 {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, P3, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd},
2306 {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", P3, "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e},
2307 {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, P3, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e},
2308 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", P3, "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x},
2309 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", P3, "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x},
Stefan Taunerc6782182012-01-19 17:50:32 +00002310 {0x8086, 0x27b9, 0xa0a0, 0x0632, 0x8086, 0x27da, 0xa0a0, 0x0632, NULL, NULL, NULL, P3, "AOpen", "i945GMx-VFX", 0, OK, intel_ich_gpio38_raise},
Joshua Roys7225ccd2011-05-18 01:32:16 +00002311 {0x8086, 0x277c, 0xa0a0, 0x060b, 0x8086, 0x27da, 0xa0a0, 0x060b, NULL, NULL, NULL, P3, "AOpen", "i975Xa-YDG", 0, OK, board_aopen_i975xa_ydg},
Joshua Roysea3aed02011-11-16 22:08:11 +00002312 {0x8086, 0x27b8, 0x1849, 0x27b8, 0x8086, 0x27da, 0x1849, 0x27da, "^ConRoeXFire-eSATA2", NULL, NULL, P3, "ASRock", "ConRoeXFire-eSATA2", 0, OK, intel_ich_gpio16_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002313 {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41 $", NULL, NULL, P3, "ASRock", "K7S41", 0, OK, w836xx_memw_enable_2e},
Pawel Rozanski1d233072011-06-19 16:52:48 +00002314 {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41GX$", NULL, NULL, P3, "ASRock", "K7S41GX", 0, OK, w836xx_memw_enable_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002315 {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, P3, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise},
2316 {0x8086, 0x2570, 0x1849, 0x2570, 0x8086, 0x24d3, 0x1849, 0x24d0, NULL, NULL, NULL, P3, "ASRock", "775i65G", 0, OK, intel_ich_gpio23_raise},
Joshua Roys8ca42552011-11-19 19:31:17 +00002317 {0x10DE, 0x0060, 0x1043, 0x80AD, 0x10DE, 0x01E0, 0x1043, 0x80C0, NULL, NULL, NULL, P3, "ASUS", "A7N8X-VM/400", 0, OK, it8712f_gpio12_raise},
Joshua Roysa2f37222011-11-14 13:00:12 +00002318 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, P3, "ASUS", "A7V600-X", 0, OK, it8712f_gpio31_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002319 {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, P3, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e},
2320 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V8X", 0, OK, it8703f_gpio51_raise},
2321 {0x1106, 0x3099, 0x1043, 0x807F, 0x1106, 0x3147, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V333", 0, OK, it8703f_gpio51_raise},
Joshua Roysa2f37222011-11-14 13:00:12 +00002322 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, P3, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio31_raise},
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00002323 {0x1002, 0x4372, 0x103c, 0x2a26, 0x1002, 0x4377, 0x103c, 0x2a26, NULL, NULL, NULL, P3, "ASUS", "A8AE-LE", 0, OK, amd_sbxxx_gpio9_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002324 {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, P3, "ASUS", "A8Jm", 0, NT, intel_ich_gpio34_raise},
Stefan Taunera9cbbac2011-08-07 13:17:20 +00002325 {0x10DE, 0x0260, 0x103C, 0x2A34, 0x10DE, 0x0264, 0x103C, 0x2A34, "NODUSM3", NULL, NULL, P3, "ASUS", "A8M2N-LA (NodusM3-GL8E)", 0, OK, nvidia_mcp_gpio0_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002326 {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI2L", NULL, NULL, P3, "ASUS", "A8N-LA (Nagami-GL8E)", 0, OK, nvidia_mcp_gpio0_raise},
Stefan Tauner2414e092011-08-06 16:16:45 +00002327 {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, "^A8N-SLI DELUXE", NULL, NULL, P3, "ASUS", "A8N-SLI Deluxe", 0, NT, board_shuttle_fn25},
Stefan Taunerff80e682011-07-20 16:34:18 +00002328 {0x10de, 0x0264, 0x1043, 0x81bc, 0x10de, 0x02f0, 0x1043, 0x81cd, NULL, NULL, NULL, P3, "ASUS", "A8N-VM CSM", 0, OK, w83627ehf_gpio22_raise_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002329 {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, P3, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise},
2330 {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, P3, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise},
Joshua Roysc73e2812011-07-09 19:46:53 +00002331 {0x8086, 0x24cc, 0, 0, 0x8086, 0x24c3, 0x1043, 0x1869, "^M6Ne$", NULL, NULL, P3, "ASUS", "M6Ne", 0, NT, intel_ich_gpio43_raise},
Joshua Roysd708fad2012-02-17 14:51:15 +00002332 {0x8086, 0x7180, 0, 0, 0x8086, 0x7110, 0, 0, "^OPLX-M$", NULL, NULL, P3, "ASUS", "OPLX-M", 0, NT, intel_piix4_gpo18_lower},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002333 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^P2B-N$", NULL, NULL, P3, "ASUS", "P2B-N", 0, OK, intel_piix4_gpo18_lower},
2334 {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, P3, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise},
2335 {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, P3, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise},
2336 {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, P3, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise},
Joshua Roysa5f5a152011-11-15 08:08:15 +00002337 {0x8086, 0x2560, 0x103C, 0x2A00, 0x8086, 0x24C3, 0x103C, 0x2A01, "^Guppy", NULL, NULL, P3, "ASUS", "P4GV-LA (Guppy)", 0, OK, intel_ich_gpio21_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002338 {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, P3, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
2339 {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D5, 0x1043, 0x80F3, NULL, NULL, NULL, P3, "ASUS", "P4P800", 0, NT, intel_ich_gpio21_raise},
Sylvain "ythier" Hitier3093f8f2011-09-03 11:22:27 +00002340 {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D3, 0x1043, 0x80A6, "^P4P800-E$", NULL, NULL, P3, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002341 {0x8086, 0x2570, 0x1043, 0x80A5, 0x8086, 0x24d0, 0, 0, NULL, NULL, NULL, P3, "ASUS", "P4P800-VM", 0, OK, intel_ich_gpio21_raise},
2342 {0x1039, 0x0651, 0x1043, 0x8081, 0x1039, 0x0962, 0, 0, NULL, NULL, NULL, P3, "ASUS", "P4SC-E", 0, OK, it8707f_write_enable_2e},
2343 {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, P3, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise},
2344 {0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x5513, 0x1043, 0x8087, NULL, NULL, NULL, P3, "ASUS", "P4S800-MX", 512, OK, w836xx_memw_enable_2e},
2345 {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", P3, "ASUS", "P5A", 0, OK, board_asus_p5a},
Stefan Tauner027e0182012-05-02 19:48:21 +00002346 {0x8086, 0x27b8, 0x1043, 0x819e, 0x8086, 0x29f0, 0x1043, 0x82a5, "^P5BV-R$", NULL, NULL, P3, "ASUS", "P5BV-R", 0, OK, intel_ich_gpio20_raise},
Stefan Taunera4f14472011-10-22 22:01:09 +00002347 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, "^P5GD1 PRO$", NULL, NULL, P3, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise},
2348 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, "^P5GD1-VM$", NULL, NULL, P3, "ASUS", "P5GD1-VM/S", 0, OK, intel_ich_gpio21_raise},
2349 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, P3, "ASUS", "P5GD1(-VM)", 0, NT, intel_ich_gpio21_raise},
Joshua Roys1fd4f9e2011-08-11 05:47:32 +00002350 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GD2-Premium$", NULL, NULL, P3, "ASUS", "P5GD2 Premium", 0, OK, intel_ich_gpio21_raise},
Stefan Taunerd94d25d2012-07-28 03:17:15 +00002351 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x81a6, "^P5GD2-X$", NULL, NULL, P3, "ASUS", "P5GD2-X", 0, OK, intel_ich_gpio21_raise},
Stefan Taunera4f14472011-10-22 22:01:09 +00002352 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GDC-V$", NULL, NULL, P3, "ASUS", "P5GDC-V Deluxe", 0, OK, intel_ich_gpio21_raise},
2353 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GDC$", NULL, NULL, P3, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise},
2354 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, P3, "ASUS", "P5GD2/C variants", 0, NT, intel_ich_gpio21_raise},
Michael Karcher14ab8d42011-08-25 14:06:50 +00002355 {0x8086, 0x27b8, 0x103c, 0x2a22, 0x8086, 0x2770, 0x103c, 0x2a22, "^LITHIUM$", NULL, NULL, P3, "ASUS", "P5LP-LE (Lithium-UL8E)",0, OK, intel_ich_gpio34_raise},
2356 {0x8086, 0x27b8, 0x1043, 0x2a22, 0x8086, 0x2770, 0x1043, 0x2a22, "^P5LP-LE$", NULL, NULL, P3, "ASUS", "P5LP-LE (Epson OEM)", 0, OK, intel_ich_gpio34_raise},
Joshua Roys1fd4f9e2011-08-11 05:47:32 +00002357 {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, NT, intel_ich_gpio16_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002358 {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, P3, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise},
Joshua Roysa2f37222011-11-14 13:00:12 +00002359 {0x10DE, 0x0260, 0x1043, 0x81BC, 0x10DE, 0x026C, 0x1043, 0x829E, "^P5N-D$", NULL, NULL, P3, "ASUS", "P5N-D", 0, OK, it8718f_gpio63_raise},
2360 {0x10DE, 0x0260, 0x1043, 0x81BC, 0x10DE, 0x026C, 0x1043, 0x8249, "^P5N-E SLI$",NULL, NULL, P3, "ASUS", "P5N-E SLI", 0, NT, it8718f_gpio63_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002361 {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, P3, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise},
Stefan Taunerded71e52012-03-10 19:22:13 +00002362 {0x8086, 0x2443, 0x1043, 0x8027, 0x8086, 0x1130, 0x1043, 0x8027, NULL, NULL, NULL, P3, "ASUS", "TUSL2-C", 0, NT, intel_ich_gpio21_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002363 {0x10b7, 0x9055, 0x1028, 0x0082, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Dell", "OptiPlex GX1", 0, OK, intel_piix4_gpo30_lower},
2364 {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, P3, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise},
2365 {0x10de, 0x03ea, 0x1019, 0x2602, 0x10de, 0x03e0, 0x1019, 0x2602, NULL, NULL, NULL, P3, "Elitegroup", "GeForce6100SM-M", 0, OK, board_ecs_geforce6100sm_m},
2366 {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, P3, "Elitegroup", "K7VTA3", 256, OK, NULL},
2367 {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, P3, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e},
Stefan Tauneraf4b1582011-08-06 16:16:33 +00002368 {0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, "8NPA7I", NULL, NULL, P3, "EPoX", "EP-8NPA7I", 0, OK, nvidia_mcp_gpio4_raise},
2369 {0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, "9NPA7I", NULL, NULL, P3, "EPoX", "EP-9NPA7I", 0, OK, nvidia_mcp_gpio4_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002370 {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, P3, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise},
2371 {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", P3, "EPoX", "EP-BX3", 0, NT, intel_piix4_gpo22_raise},
2372 {0x10de, 0x02f0, 0x105b, 0x0d01, 0x10de, 0x0264, 0x105b, 0x0d01, NULL, NULL, NULL, P3, "Foxconn", "6150K8MD-8EKRSH", 0, NT, nvidia_mcp_gpio2_raise},
2373 {0x8086, 0x2443, 0x8086, 0x2442, 0x8086, 0x1130, 0x8086, 0x1130, "^6IEM ", NULL, NULL, P3, "GIGABYTE", "GA-6IEM", 0, NT, intel_ich_gpio25_raise},
2374 {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-7ZM", 512, OK, NULL},
Joshua Roys9d9a1042011-06-13 16:59:01 +00002375 {0x8086, 0x2570, 0x1458, 0x2570, 0x8086, 0x24d0, 0, 0, "^8IP775/-G$",NULL, NULL, P3, "GIGABYTE", "GA-8IP775", 0, OK, intel_ich_gpio32_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002376 {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise},
2377 {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise},
Stefan Tauner716e0982011-07-25 20:38:52 +00002378 {0x1039, 0x0651, 0x1039, 0x0651, 0x1039, 0x7002, 0x1458, 0x5004, "^GA-8SIMLH$",NULL, NULL, P3, "GIGABYTE", "GA-8SIMLH", 0, OK, sis_gpio0_raise_and_w836xx_memw},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002379 {0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise},
2380 {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise},
Idwer Volleringd8a00a02011-06-13 16:58:54 +00002381 {0x10de, 0x00e4, 0x1458, 0x0c11, 0x10de, 0x00e0, 0x1458, 0x0c11, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8NS Pro-939", 0, NT, nvidia_mcp_gpio0a_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002382 {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise},
Idwer Volleringd8a00a02011-06-13 16:58:54 +00002383 {0x8086, 0x2415, 0x103c, 0x1250, 0x10b7, 0x9200, 0x103c, 0x1247, NULL, NULL, NULL, P3, "HP", "e-Vectra P2706T", 0, OK, board_hp_p2706t},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002384 {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", P3, "HP", "ProLiant DL145 G3", 0, OK, board_hp_dl145_g3_enable},
2385 {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", P3, "HP", "ProLiant DL165 G6", 0, OK, board_hp_dl165_g6_enable},
2386 {0x8086, 0x2580, 0x103c, 0x2a08, 0x8086, 0x2640, 0x103c, 0x2a0a, NULL, NULL, NULL, P3, "HP", "Puffer2-UL8E", 0, OK, intel_ich_gpio18_raise},
Idwer Volleringd8a00a02011-06-13 16:58:54 +00002387 {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, P3, "HP", "Vectra VL400", 0, OK, board_hp_vl400},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002388 {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, P3, "HP", "Vectra VL420 SFF", 0, OK, intel_ich_gpio22_raise},
2389 {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, "hp", "xw9400", P3, "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise},
2390 {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", P3, "IBASE", "MB899", 0, OK, intel_ich_gpio26_raise},
2391 {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, P3, "IBM", "x3455", 0, OK, board_ibm_x3455},
2392 {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, P3, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi},
2393 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, P3, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower},
2394 {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, NULL, "iwill", "dk8_htx", P3, "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e},
2395 {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", P3, "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m},
2396 {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, P3, "Mitac", "6513WU", 0, OK, board_mitac_6513wu},
Ingo Feldschmid8a0f9b02012-01-31 06:51:56 +00002397 {0x8086, 0x8186, 0x8086, 0x8186, 0x8086, 0x8800, 0x0000, 0x0000, "^MSC Vertriebs GmbH$", NULL, NULL, P2, "MSC", "Q7-TCTC", 0, OK, p2_not_a_laptop},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002398 {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, P3, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, /* TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html. */
2399 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^MS-6163 (i440BX)$", NULL, NULL, P3, "MSI", "MS-6163 (MS-6163 Pro)", 0, OK, intel_piix4_gpo14_raise},
2400 {0x1039, 0x0745, 0, 0, 0x1039, 0x0018, 0, 0, "^MS-6561", NULL, NULL, P3, "MSI", "MS-6561 (745 Ultra)", 0, OK, w836xx_memw_enable_2e},
2401 {0x8086, 0x2560, 0x1462, 0x5770, 0x8086, 0x2562, 0x1462, 0x5778, NULL, NULL, NULL, P3, "MSI", "MS-6577 (Xenon)", 0, OK, w83627hf_gpio25_raise_2e},
2402 {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, P3, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v},
2403 {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, P3, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio44_raise_2e},
2404 {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, P3, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v},
2405 {0x1106, 0x3148, 0 , 0 , 0x1106, 0x3177, 0 , 0 , NULL, "msi", "ms6787", P3, "MSI", "MS-6787 (P4MAM-V/P4MAM-L)", 0, OK, w836xx_memw_enable_2e},
Maciej Pijanka6add0942011-06-09 20:59:30 +00002406 {0x8086, 0x24d3, 0x1462, 0x7880, 0x8086, 0x2570, 0, 0, NULL, NULL, NULL, P3, "MSI", "MS-6788-040 (848P NeoV)", 0, OK, intel_ich_gpio32_raise},
Michael Karchera08d0f22011-07-25 17:25:24 +00002407 {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, P3, "MSI", "MS-7005 (651M-L)", 0, OK, sis_gpio0_raise_and_w836xx_memw},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002408 {0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, P3, "MSI", "MS-7025 (K8N Neo2 Platinum)", 0, OK, nvidia_mcp_gpio0c_raise},
2409 {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, P3, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise},
2410 {0x8086, 0x244b, 0x1462, 0x3910, 0x8086, 0x2442, 0x1462, 0x3910, NULL, NULL, NULL, P3, "MSI", "MS-6391 (845 Pro4)", 0, OK, intel_ich_gpio23_raise},
2411 {0x1106, 0x3149, 0x1462, 0x7061, 0x1106, 0x3227, 0, 0, NULL, NULL, NULL, P3, "MSI", "MS-7061 (KM4M-V/KM4AM-V)", 0, OK, w836xx_memw_enable_2e},
2412 {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", P3, "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio44_raise_4e},
2413 {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, P3, "MSI", "MS-7207 (K8NGM2-L)", 0, NT, nvidia_mcp_gpio2_raise},
Joshua Roys6e48a022012-06-29 23:07:14 +00002414 {0x10DE, 0x0360, 0x1462, 0x7250, 0x10DE, 0x0368, 0x1462, 0x7250, NULL, NULL, NULL, P3, "MSI", "MS-7250 (K9N SLI)", 0, OK, nvidia_mcp_gpio2_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002415 {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0},
2416 {0x8086, 0x24d3, 0x144d, 0xb025, 0x8086, 0x1050, 0x144d, 0xb025, NULL, NULL, NULL, P3, "Samsung", "Polaris 32", 0, OK, intel_ich_gpio21_raise},
2417 {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", P3, "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e},
2418 {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, P3, "Shuttle", "AK38N", 256, OK, NULL},
2419 {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, P3, "Shuttle", "FN25", 0, OK, board_shuttle_fn25},
2420 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, P3, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower},
Joshua Roysb992d342011-11-02 14:31:18 +00002421 {0x10de, 0x0364, 0x108e, 0x6676, 0x10de, 0x0369, 0x108e, 0x6676, "^Sun Ultra 40 M2", NULL, NULL, P3, "Sun", "Ultra 40 M2", 0, OK, board_sun_ultra_40_m2},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002422 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, P3, "Tekram", "P6Pro-A5", 256, OK, NULL},
2423 {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, P3, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e},
Michael Karcherbfd89a52012-02-12 00:13:14 +00002424 {0x8086, 0x7120, 0x109f, 0x3157, 0x8086, 0x2410, 0, 0, NULL, NULL, NULL, P3, "TriGem", "Anaheim-3", 0, OK, intel_ich_gpio22_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002425 {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, P3, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e},
2426 {0x1106, 0x0259, 0x1106, 0xAA07, 0x1106, 0x3227, 0x1106, 0xAA07, NULL, NULL, NULL, P3, "VIA", "EPIA EK", 0, NT, via_vt823x_gpio9_raise},
2427 {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, P3, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise},
2428 {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, P3, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise},
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00002429#endif
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002430 { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, P3, NULL, NULL, 0, NT, NULL}, /* end marker */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002431};
2432
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002433/*
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +00002434 * Match boards on coreboot table gathered vendor and part name.
Uwe Hermannffec5f32007-08-23 16:08:21 +00002435 * Require main PCI IDs to match too as extra safety.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002436 */
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002437static const struct board_match *board_match_cbname(const char *vendor,
2438 const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002439{
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002440 const struct board_match *board = board_matches;
2441 const struct board_match *partmatch = NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002442
Uwe Hermanna93045c2009-05-09 00:47:04 +00002443 for (; board->vendor_name; board++) {
Uwe Hermann394131e2008-10-18 21:14:13 +00002444 if (vendor && (!board->lb_vendor
2445 || strcasecmp(board->lb_vendor, vendor)))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002446 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002447
Peter Stuge0b9c5f32008-07-02 00:47:30 +00002448 if (!board->lb_part || strcasecmp(board->lb_part, part))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002449 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002450
Uwe Hermanna7e05482007-05-09 10:17:44 +00002451 if (!pci_dev_find(board->first_vendor, board->first_device))
2452 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002453
Uwe Hermanna7e05482007-05-09 10:17:44 +00002454 if (board->second_vendor &&
Uwe Hermann394131e2008-10-18 21:14:13 +00002455 !pci_dev_find(board->second_vendor, board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002456 continue;
Peter Stuge6b53fed2008-01-27 16:21:21 +00002457
2458 if (vendor)
2459 return board;
2460
2461 if (partmatch) {
2462 /* a second entry has a matching part name */
Sean Nelson316a29f2010-05-07 20:09:04 +00002463 msg_pinfo("AMBIGUOUS BOARD NAME: %s\n", part);
2464 msg_pinfo("At least vendors '%s' and '%s' match.\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002465 partmatch->lb_vendor, board->lb_vendor);
Carl-Daniel Hailfinger2d927fb2012-01-04 00:48:27 +00002466 msg_perr("Please use the full -p internal:mainboard="
2467 "vendor:part syntax.\n");
Peter Stuge6b53fed2008-01-27 16:21:21 +00002468 return NULL;
2469 }
2470 partmatch = board;
Uwe Hermanna7e05482007-05-09 10:17:44 +00002471 }
Uwe Hermann372eeb52007-12-04 21:49:06 +00002472
Peter Stuge6b53fed2008-01-27 16:21:21 +00002473 if (partmatch)
2474 return partmatch;
2475
Carl-Daniel Hailfingerbc25f942009-07-30 13:30:17 +00002476 if (!partvendor_from_cbtable) {
2477 /* Only warn if the mainboard type was not gathered from the
2478 * coreboot table. If it was, the coreboot implementor is
2479 * expected to fix flashrom, too.
2480 */
Carl-Daniel Hailfinger2d927fb2012-01-04 00:48:27 +00002481 msg_perr("\nUnknown vendor:board from -p internal:mainboard="
2482 " programmer parameter:\n%s:%s\n\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002483 vendor, part);
Carl-Daniel Hailfingerbc25f942009-07-30 13:30:17 +00002484 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00002485 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002486}
2487
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002488/*
Uwe Hermannffec5f32007-08-23 16:08:21 +00002489 * Match boards on PCI IDs and subsystem IDs.
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002490 * Second set of IDs can be either main+subsystem IDs, main IDs or no IDs.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002491 */
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002492const static struct board_match *board_match_pci_ids(enum board_match_phase phase)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002493{
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002494 const struct board_match *board = board_matches;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002495
Uwe Hermanna93045c2009-05-09 00:47:04 +00002496 for (; board->vendor_name; board++) {
Michael Karcher2eab70d2010-02-04 10:58:50 +00002497 if ((!board->first_card_vendor || !board->first_card_device) &&
2498 !board->dmi_pattern)
Uwe Hermanna7e05482007-05-09 10:17:44 +00002499 continue;
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002500 if (board->phase != phase)
2501 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002502
Uwe Hermanna7e05482007-05-09 10:17:44 +00002503 if (!pci_card_find(board->first_vendor, board->first_device,
Uwe Hermann394131e2008-10-18 21:14:13 +00002504 board->first_card_vendor,
2505 board->first_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002506 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002507
Uwe Hermanna7e05482007-05-09 10:17:44 +00002508 if (board->second_vendor) {
2509 if (board->second_card_vendor) {
2510 if (!pci_card_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00002511 board->second_device,
2512 board->second_card_vendor,
2513 board->second_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002514 continue;
2515 } else {
2516 if (!pci_dev_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00002517 board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002518 continue;
2519 }
2520 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002521
Michael Karcher6701ee82010-01-20 14:14:11 +00002522 if (board->dmi_pattern) {
2523 if (!has_dmi_support) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002524 msg_perr("WARNING: Can't autodetect %s %s,"
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002525 " DMI info unavailable.\n",
2526 board->vendor_name, board->board_name);
Michael Karcher6701ee82010-01-20 14:14:11 +00002527 continue;
2528 } else {
2529 if (!dmi_match(board->dmi_pattern))
2530 continue;
2531 }
2532 }
2533
Uwe Hermanna7e05482007-05-09 10:17:44 +00002534 return board;
2535 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002536
Uwe Hermanna7e05482007-05-09 10:17:44 +00002537 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002538}
2539
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002540static int unsafe_board_handler(const struct board_match *board)
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002541{
2542 if (!board)
2543 return 1;
2544
2545 if (board->status == OK)
2546 return 0;
2547
2548 if (!force_boardenable) {
2549 msg_pinfo("WARNING: Your mainboard is %s %s, but the mainboard-specific\n"
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002550 "code has not been tested, and thus will not be executed by default.\n"
2551 "Depending on your hardware environment, erasing, writing or even probing\n"
2552 "can fail without running the board specific code.\n\n"
2553 "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n"
2554 "\"internal programmer\") for details.\n",
2555 board->vendor_name, board->board_name);
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002556 return 1;
2557 }
2558 msg_pinfo("NOTE: Running an untested board enable procedure.\n"
2559 "Please report success/failure to flashrom@flashrom.org\n"
2560 "with your board name and SUCCESS or FAILURE in the subject.\n");
2561 return 0;
2562}
2563
2564/* FIXME: Should this be identical to board_flash_enable? */
2565static int board_handle_phase(enum board_match_phase phase)
2566{
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002567 const struct board_match *board = NULL;
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002568
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002569 board = board_match_pci_ids(phase);
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002570
2571 if (unsafe_board_handler(board))
2572 board = NULL;
2573
2574 if (!board)
2575 return 0;
2576
2577 if (!board->enable) {
2578 /* Not sure if there is a valid case for this. */
2579 msg_perr("Board match found, but nothing to do?\n");
2580 return 0;
2581 }
2582
2583 return board->enable();
2584}
2585
2586void board_handle_before_superio(void)
2587{
2588 board_handle_phase(P1);
2589}
2590
2591void board_handle_before_laptop(void)
2592{
2593 board_handle_phase(P2);
2594}
2595
Uwe Hermann372eeb52007-12-04 21:49:06 +00002596int board_flash_enable(const char *vendor, const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002597{
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002598 const struct board_match *board = NULL;
Uwe Hermanna7e05482007-05-09 10:17:44 +00002599 int ret = 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002600
Peter Stuge6b53fed2008-01-27 16:21:21 +00002601 if (part)
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002602 board = board_match_cbname(vendor, part);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002603
Uwe Hermanna7e05482007-05-09 10:17:44 +00002604 if (!board)
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002605 board = board_match_pci_ids(P3);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002606
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002607 if (unsafe_board_handler(board))
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002608 board = NULL;
Michael Karcher7f0c3ec2010-03-07 22:29:28 +00002609
Uwe Hermanna7e05482007-05-09 10:17:44 +00002610 if (board) {
Luc Verhaegen93938c32010-01-20 14:45:03 +00002611 if (board->max_rom_decode_parallel)
2612 max_rom_decode.parallel =
2613 board->max_rom_decode_parallel * 1024;
2614
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00002615 if (board->enable != NULL) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002616 msg_pinfo("Disabling flash write protection for "
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002617 "board \"%s %s\"... ", board->vendor_name,
2618 board->board_name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002619
Uwe Hermann36dec8b2010-06-07 19:06:26 +00002620 ret = board->enable();
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00002621 if (ret)
Sean Nelson316a29f2010-05-07 20:09:04 +00002622 msg_pinfo("FAILED!\n");
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00002623 else
Sean Nelson316a29f2010-05-07 20:09:04 +00002624 msg_pinfo("OK.\n");
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00002625 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00002626 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002627
Uwe Hermanna7e05482007-05-09 10:17:44 +00002628 return ret;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002629}