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Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
5 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +00006 * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
Carl-Daniel Hailfinger92242622007-09-27 14:29:57 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00008 *
Uwe Hermannd1107642007-08-29 17:52:32 +00009 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000012 *
Uwe Hermannd1107642007-08-29 17:52:32 +000013 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000021 */
22
23/*
24 * Contains the board specific flash enables.
25 */
26
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000027#include <string.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000028#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000029#include "programmer.h"
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000030
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000031#if defined(__i386__) || defined(__x86_64__)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000032/*
Uwe Hermannffec5f32007-08-23 16:08:21 +000033 * Helper functions for many Winbond Super I/Os of the W836xx range.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000034 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000035/* Enter extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000036void w836xx_ext_enter(uint16_t port)
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000037{
Andriy Gapon65c1b862008-05-22 13:22:45 +000038 OUTB(0x87, port);
39 OUTB(0x87, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000040}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000041
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000042/* Leave extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000043void w836xx_ext_leave(uint16_t port)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000044{
Andriy Gapon65c1b862008-05-22 13:22:45 +000045 OUTB(0xAA, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000046}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000047
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000048/* Generic Super I/O helper functions */
49uint8_t sio_read(uint16_t port, uint8_t reg)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000050{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000051 OUTB(reg, port);
52 return INB(port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000053}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000054
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000055void sio_write(uint16_t port, uint8_t reg, uint8_t data)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000056{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000057 OUTB(reg, port);
58 OUTB(data, port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000059}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000060
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000061void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000062{
Ronald G. Minnichfa496922007-10-12 21:22:40 +000063 uint8_t tmp;
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000064
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000065 OUTB(reg, port);
66 tmp = INB(port + 1) & ~mask;
67 OUTB(tmp | (data & mask), port + 1);
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000068}
69
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +000070/* Winbond W83697 documentation indicates that the index register has to be written for each access. */
71void sio_mask_alzheimer(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
72{
73 uint8_t tmp;
74
75 OUTB(reg, port);
76 tmp = INB(port + 1) & ~mask;
77 OUTB(reg, port);
78 OUTB(tmp | (data & mask), port + 1);
79}
80
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000081/* Not used yet. */
82#if 0
83static int enable_flash_decode_superio(void)
84{
85 int ret;
86 uint8_t tmp;
87
88 switch (superio.vendor) {
89 case SUPERIO_VENDOR_NONE:
90 ret = -1;
91 break;
92 case SUPERIO_VENDOR_ITE:
93 enter_conf_mode_ite(superio.port);
Uwe Hermann43959702010-03-13 17:28:29 +000094 /* Enable flash mapping. Works for most old ITE style Super I/O. */
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000095 tmp = sio_read(superio.port, 0x24);
96 tmp |= 0xfc;
97 sio_write(superio.port, 0x24, tmp);
98 exit_conf_mode_ite(superio.port);
99 ret = 0;
100 break;
101 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000102 msg_pdbg("Unhandled Super I/O type!\n");
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +0000103 ret = -1;
104 break;
105 }
106 return ret;
107}
108#endif
109
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000110/*
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000111 * SMSC FDC37B787: Raise GPIO50
112 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000113static int fdc37b787_gpio50_raise(uint16_t port)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000114{
115 uint8_t id, val;
116
117 OUTB(0x55, port); /* enter conf mode */
118 id = sio_read(port, 0x20);
119 if (id != 0x44) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000120 msg_perr("\nERROR: FDC37B787: Wrong ID 0x%02X.\n", id);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000121 OUTB(0xAA, port); /* leave conf mode */
122 return -1;
123 }
124
125 sio_write(port, 0x07, 0x08); /* Select Aux I/O subdevice */
126
127 val = sio_read(port, 0xC8); /* GP50 */
128 if ((val & 0x1B) != 0x10) /* output, no invert, GPIO */
129 {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000130 msg_perr("\nERROR: GPIO50 mode 0x%02X unexpected.\n", val);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000131 OUTB(0xAA, port);
132 return -1;
133 }
134
135 sio_mask(port, 0xF9, 0x01, 0x01);
136
137 OUTB(0xAA, port); /* Leave conf mode */
138 return 0;
139}
140
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000141/*
142 * Suited for:
143 * - Nokia IP530: Intel 440BX + PIIX4 + FDC37B787
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000144 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000145static int fdc37b787_gpio50_raise_3f0(void)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000146{
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000147 return fdc37b787_gpio50_raise(0x3f0);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000148}
149
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000150struct winbond_mux {
151 uint8_t reg; /* 0 if the corresponding pin is not muxed */
152 uint8_t data; /* reg/data/mask may be directly ... */
153 uint8_t mask; /* ... passed to sio_mask */
154};
155
156struct winbond_port {
157 const struct winbond_mux *mux; /* NULL or pointer to mux info for the 8 bits */
158 uint8_t ldn; /* LDN this GPIO register is located in */
159 uint8_t enable_bit; /* bit in 0x30 of that LDN to enable
160 the GPIO port */
161 uint8_t base; /* base register in that LDN for the port */
162};
163
164struct winbond_chip {
165 uint8_t device_id; /* reg 0x20 of the expected w83626x */
166 uint8_t gpio_port_count;
167 const struct winbond_port *port;
168};
169
170
171#define UNIMPLEMENTED_PORT {NULL, 0, 0, 0}
172
173enum winbond_id {
174 WINBOND_W83627HF_ID = 0x52,
Michael Karcherea36c9c2010-06-27 15:07:52 +0000175 WINBOND_W83627EHF_ID = 0x88,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000176 WINBOND_W83627THF_ID = 0x82,
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000177 WINBOND_W83697HF_ID = 0x60,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000178};
179
180static const struct winbond_mux w83627hf_port2_mux[8] = {
181 {0x2A, 0x01, 0x01}, /* or MIDI */
182 {0x2B, 0x80, 0x80}, /* or SPI */
183 {0x2B, 0x40, 0x40}, /* or SPI */
184 {0x2B, 0x20, 0x20}, /* or power LED */
185 {0x2B, 0x10, 0x10}, /* or watchdog */
186 {0x2B, 0x08, 0x08}, /* or infra red */
187 {0x2B, 0x04, 0x04}, /* or infra red */
188 {0x2B, 0x03, 0x03} /* or IRQ1 input */
189};
190
191static const struct winbond_port w83627hf[3] = {
192 UNIMPLEMENTED_PORT,
193 {w83627hf_port2_mux, 0x08, 0, 0xF0},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000194 UNIMPLEMENTED_PORT,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000195};
196
Michael Karcherea36c9c2010-06-27 15:07:52 +0000197static const struct winbond_mux w83627ehf_port2_mux[8] = {
198 {0x29, 0x06, 0x02}, /* or MIDI */
199 {0x29, 0x06, 0x02},
200 {0x24, 0x02, 0x00}, /* or SPI ROM interface */
201 {0x24, 0x02, 0x00},
202 {0x2A, 0x01, 0x01}, /* or keyboard/mouse interface */
203 {0x2A, 0x01, 0x01},
204 {0x2A, 0x01, 0x01},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000205 {0x2A, 0x01, 0x01},
Michael Karcherea36c9c2010-06-27 15:07:52 +0000206};
207
208static const struct winbond_port w83627ehf[6] = {
209 UNIMPLEMENTED_PORT,
210 {w83627ehf_port2_mux, 0x09, 0, 0xE3},
211 UNIMPLEMENTED_PORT,
212 UNIMPLEMENTED_PORT,
213 UNIMPLEMENTED_PORT,
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000214 UNIMPLEMENTED_PORT,
Michael Karcherea36c9c2010-06-27 15:07:52 +0000215};
216
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000217static const struct winbond_mux w83627thf_port4_mux[8] = {
218 {0x2D, 0x01, 0x01}, /* or watchdog or VID level strap */
219 {0x2D, 0x02, 0x02}, /* or resume reset */
220 {0x2D, 0x04, 0x04}, /* or S3 input */
221 {0x2D, 0x08, 0x08}, /* or PSON# */
222 {0x2D, 0x10, 0x10}, /* or PWROK */
223 {0x2D, 0x20, 0x20}, /* or suspend LED */
224 {0x2D, 0x40, 0x40}, /* or panel switch input */
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000225 {0x2D, 0x80, 0x80}, /* or panel switch output */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000226};
227
228static const struct winbond_port w83627thf[5] = {
229 UNIMPLEMENTED_PORT, /* GPIO1 */
230 UNIMPLEMENTED_PORT, /* GPIO2 */
231 UNIMPLEMENTED_PORT, /* GPIO3 */
232 {w83627thf_port4_mux, 0x09, 1, 0xF4},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000233 UNIMPLEMENTED_PORT, /* GPIO5 */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000234};
235
236static const struct winbond_chip winbond_chips[] = {
237 {WINBOND_W83627HF_ID, ARRAY_SIZE(w83627hf), w83627hf },
Michael Karcherea36c9c2010-06-27 15:07:52 +0000238 {WINBOND_W83627EHF_ID, ARRAY_SIZE(w83627ehf), w83627ehf},
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000239 {WINBOND_W83627THF_ID, ARRAY_SIZE(w83627thf), w83627thf},
240};
241
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000242#define WINBOND_SUPERIO_PORT1 0x2e
243#define WINBOND_SUPERIO_PORT2 0x4e
244
245/* We don't really care about the hardware monitor, but it offers better (more specific) device ID info than
246 * the simple device ID in the normal configuration registers.
247 * Note: This function expects to be called while the Super I/O is in config mode.
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000248 */
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000249static uint8_t w836xx_deviceid_hwmon(uint16_t sio_port)
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000250{
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000251 uint16_t hwmport;
252 uint16_t hwm_vendorid;
253 uint8_t hwm_deviceid;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000254
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000255 sio_write(sio_port, 0x07, 0x0b); /* Select LDN 0xb (HWM). */
256 if ((sio_read(sio_port, 0x30) & (1 << 0)) != (1 << 0)) {
257 msg_pinfo("W836xx hardware monitor disabled or does not exist.\n");
258 return 0;
259 }
260 /* Get HWM base address (stored in LDN 0xb, index 0x60/0x61). */
261 hwmport = sio_read(sio_port, 0x60) << 8;
262 hwmport |= sio_read(sio_port, 0x61);
263 /* HWM address register = HWM base address + 5. */
264 hwmport += 5;
265 msg_pdbg2("W836xx Hardware Monitor at port %04x\n", hwmport);
266 /* FIXME: This busy check should happen before each HWM access. */
267 if (INB(hwmport) & 0x80) {
268 msg_pinfo("W836xx hardware monitor busy, ignoring it.\n");
269 return 0;
270 }
271 /* Set HBACS=1. */
272 sio_mask_alzheimer(hwmport, 0x4e, 0x80, 0x80);
273 /* Read upper byte of vendor ID. */
274 hwm_vendorid = sio_read(hwmport, 0x4f) << 8;
275 /* Set HBACS=0. */
276 sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x80);
277 /* Read lower byte of vendor ID. */
278 hwm_vendorid |= sio_read(hwmport, 0x4f);
279 if (hwm_vendorid != 0x5ca3) {
280 msg_pinfo("W836xx hardware monitor vendor ID weirdness: expected 0x5ca3, got %04x\n",
281 hwm_vendorid);
282 return 0;
283 }
284 /* Set Bank=0. */
285 sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x07);
286 /* Read "chip" ID. We call this one the device ID. */
287 hwm_deviceid = sio_read(hwmport, 0x58);
288 return hwm_deviceid;
289}
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000290
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000291void probe_superio_winbond(void)
292{
293 struct superio s = {};
294 uint16_t winbond_ports[] = {WINBOND_SUPERIO_PORT1, WINBOND_SUPERIO_PORT2, 0};
295 uint16_t *i = winbond_ports;
296 uint8_t model;
297 uint8_t tmp;
298
299 s.vendor = SUPERIO_VENDOR_WINBOND;
300 for (; *i; i++) {
301 s.port = *i;
302 /* If we're already in Super I/O config more, the W836xx enter sequence won't hurt. */
303 w836xx_ext_enter(s.port);
304 model = sio_read(s.port, 0x20);
305 /* No response, no point leaving the config mode. */
306 if (model == 0xff)
307 continue;
308 /* Try to leave config mode. If the ID register is still readable, it's not a Winbond chip. */
309 w836xx_ext_leave(s.port);
310 if (model == sio_read(s.port, 0x20)) {
311 msg_pdbg("W836xx enter config mode worked or we were already in config mode. W836xx "
312 "leave config mode had no effect.\n");
313 if (model == 0x87) {
314 /* ITE IT8707F and IT8710F are special: They need the W837xx enter sequence,
315 * but they want the ITE exit sequence. Handle them here.
316 */
317 tmp = sio_read(s.port, 0x21);
318 switch (tmp) {
319 case 0x07:
320 case 0x10:
321 s.vendor = SUPERIO_VENDOR_ITE;
322 s.model = (0x87 << 8) | tmp ;
323 msg_pdbg("Found ITE Super I/O, ID 0x%04hx on port "
324 "0x%x\n", s.model, s.port);
325 register_superio(s);
326 /* Exit ITE config mode. */
327 exit_conf_mode_ite(s.port);
328 /* Restore vendor for next loop iteration. */
329 s.vendor = SUPERIO_VENDOR_WINBOND;
330 continue;
331 }
332 }
333 msg_pinfo("Active config mode, unknown reg 0x20 ID: %02x.\n", model);
334 msg_pinfo("Please send the output of \"flashrom -V\" to \n"
335 "flashrom@flashrom.org with W836xx: your board name: flashrom -V\n"
336 "as the subject to help us finish support for your Super I/O. Thanks.\n");
337 continue;
338 }
339 /* The Super I/O reacts to W836xx enter and exit config mode, it's probably Winbond. */
340 w836xx_ext_enter(s.port);
341 s.model = sio_read(s.port, 0x20);
342 switch (s.model) {
343 case WINBOND_W83627HF_ID:
344 case WINBOND_W83627EHF_ID:
345 case WINBOND_W83627THF_ID:
346 msg_pdbg("Found Winbond Super I/O, id %02hx\n", s.model);
347 register_superio(s);
348 break;
349 case WINBOND_W83697HF_ID:
350 /* This code is extremely paranoid. */
351 tmp = sio_read(s.port, 0x26) & 0x40;
352 if (((tmp == 0x00) && (s.port != WINBOND_SUPERIO_PORT1)) ||
353 ((tmp == 0x40) && (s.port != WINBOND_SUPERIO_PORT2))) {
354 msg_pdbg("Winbond Super I/O probe weirdness: Port mismatch for ID "
355 "%02x at port %04x\n", s.model, s.port);
356 break;
357 }
358 tmp = w836xx_deviceid_hwmon(s.port);
359 /* FIXME: This might be too paranoid... */
360 if (!tmp) {
361 msg_pdbg("Probably not a Winbond Super I/O\n");
362 break;
363 }
364 if (tmp != s.model) {
365 msg_pinfo("W83 series hardware monitor device ID weirdness: expected %02x, "
366 "got %02x\n", WINBOND_W83697HF_ID, tmp);
367 break;
368 }
369 msg_pinfo("Found Winbond Super I/O, id %02hx\n", s.model);
370 register_superio(s);
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000371 break;
372 }
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000373 w836xx_ext_leave(s.port);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000374 }
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000375 return;
376}
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000377
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000378static const struct winbond_chip *winbond_superio_chipdef(void)
379{
380 int i, j;
381
382 for (i = 0; i < superio_count; i++) {
383 if (superios[i].vendor != SUPERIO_VENDOR_WINBOND)
384 continue;
385 for (j = 0; j < ARRAY_SIZE(winbond_chips); j++)
386 if (winbond_chips[j].device_id == superios[i].model)
387 return &winbond_chips[j];
388 }
389 return NULL;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000390}
391
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000392/*
393 * The chipid parameter goes away as soon as we have Super I/O matching in the
394 * board enable table. The call to winbond_superio_detect() goes away as
395 * soon as we have generic Super I/O detection code.
396 */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000397static int winbond_gpio_set(uint16_t base, enum winbond_id chipid,
398 int pin, int raise)
399{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000400 const struct winbond_chip *chip = NULL;
401 const struct winbond_port *gpio;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000402 int port = pin / 10;
403 int bit = pin % 10;
404
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000405 chip = winbond_superio_chipdef();
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000406 if (!chip) {
407 msg_perr("\nERROR: No supported Winbond Super I/O found\n");
408 return -1;
409 }
Michael Karcher979d9252010-06-29 14:44:40 +0000410 if (chip->device_id != chipid) {
411 msg_perr("\nERROR: Found Winbond chip with ID 0x%x, "
412 "expected %x\n", chip->device_id, chipid);
413 return -1;
414 }
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000415 if (bit >= 8 || port == 0 || port > chip->gpio_port_count) {
416 msg_perr("\nERROR: winbond_gpio_set: Invalid GPIO number %d\n",
417 pin);
418 return -1;
419 }
420
421 gpio = &chip->port[port - 1];
422
423 if (gpio->ldn == 0) {
424 msg_perr("\nERROR: GPIO%d is not supported yet on this"
425 " winbond chip\n", port);
426 return -1;
427 }
428
429 w836xx_ext_enter(base);
430
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000431 /* Select logical device. */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000432 sio_write(base, 0x07, gpio->ldn);
433
434 /* Activate logical device. */
435 sio_mask(base, 0x30, 1 << gpio->enable_bit, 1 << gpio->enable_bit);
436
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000437 /* Select GPIO function of that pin. */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000438 if (gpio->mux && gpio->mux[bit].reg)
439 sio_mask(base, gpio->mux[bit].reg,
440 gpio->mux[bit].data, gpio->mux[bit].mask);
441
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000442 sio_mask(base, gpio->base + 0, 0, 1 << bit); /* Make pin output */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000443 sio_mask(base, gpio->base + 2, 0, 1 << bit); /* Clear inversion */
444 sio_mask(base, gpio->base + 1, raise << bit, 1 << bit);
445
446 w836xx_ext_leave(base);
447
448 return 0;
449}
450
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000451/*
Uwe Hermannffec5f32007-08-23 16:08:21 +0000452 * Winbond W83627HF: Raise GPIO24.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000453 *
454 * Suited for:
Uwe Hermannffec5f32007-08-23 16:08:21 +0000455 * - Agami Aruma
456 * - IWILL DK8-HTX
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000457 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000458static int w83627hf_gpio24_raise_2e(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000459{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000460 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 24, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000461}
462
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000463/*
Joshua Roysf280a382010-08-07 21:49:11 +0000464 * Winbond W83627HF: Raise GPIO25.
465 *
466 * Suited for:
467 * - MSI MS-6577
468 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000469static int w83627hf_gpio25_raise_2e(void)
Joshua Roysf280a382010-08-07 21:49:11 +0000470{
471 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 25, 1);
472}
473
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000474/*
Stefan Taunerff80e682011-07-20 16:34:18 +0000475 * Winbond W83627EHF: Raise GPIO22.
Michael Karcherea36c9c2010-06-27 15:07:52 +0000476 *
477 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000478 * - ASUS A8N-VM CSM: AMD Socket 939 + GeForce 6150 (C51) + MCP51
Michael Karcherea36c9c2010-06-27 15:07:52 +0000479 */
Stefan Taunerff80e682011-07-20 16:34:18 +0000480static int w83627ehf_gpio22_raise_2e(void)
Michael Karcherea36c9c2010-06-27 15:07:52 +0000481{
Stefan Taunerff80e682011-07-20 16:34:18 +0000482 return winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, 22, 1);
Michael Karcherea36c9c2010-06-27 15:07:52 +0000483}
484
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000485/*
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000486 * Winbond W83627THF: Raise GPIO 44.
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000487 *
488 * Suited for:
Peter Stugecce26822008-07-21 17:48:40 +0000489 * - MSI K8T Neo2-F
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000490 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000491static int w83627thf_gpio44_raise_2e(void)
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000492{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000493 return winbond_gpio_set(0x2e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000494}
495
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000496/*
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000497 * Winbond W83627THF: Raise GPIO 44.
498 *
499 * Suited for:
500 * - MSI K8N Neo3
501 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000502static int w83627thf_gpio44_raise_4e(void)
Peter Stugecce26822008-07-21 17:48:40 +0000503{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000504 return winbond_gpio_set(0x4e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000505}
Uwe Hermann372eeb52007-12-04 21:49:06 +0000506
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000507/*
David Borgb6417a62010-08-02 08:29:34 +0000508 * Enable MEMW# and set ROM size to max.
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000509 * Supported chips: W83L517D, W83697HF/F/HG, W83697SF/UF/UG
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000510 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000511static void w836xx_memw_enable(uint16_t port)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000512{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000513 w836xx_ext_enter(port);
514 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000515 /* Enable MEMW# and set ROM size select to max. (4M). */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000516 sio_mask(port, 0x24, 0x28, 0x28);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000517 }
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000518 w836xx_ext_leave(port);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000519}
520
David Borgb02c62b2012-05-05 20:43:42 +0000521/**
522 * Enable MEMW# and set ROM size to max.
523 * Supported chips:
524 * W83697HF/F/HG, W83697SF/UF/UG
525 */
526void w83697xx_memw_enable(uint16_t port)
527{
528 w836xx_ext_enter(port);
529 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
530 if((sio_read(port, 0x2A) & 0xF0) == 0xF0) {
531
532 /* CR24 Bits 7 & 2 must be set to 0 enable the flash ROM */
533 /* address segments 000E0000h ~ 000FFFFFh on W83697SF/UF/UG */
534 /* These bits are reserved on W83697HF/F/HG */
535 /* Shouldn't be needed though. */
536
537 /* CR28 Bit3 must be set to 1 to enable flash access to */
538 /* FFE80000h ~ FFEFFFFFh on W83697SF/UF/UG. */
539 /* This bit is reserved on W83697HF/F/HG which default to 0 */
540 sio_mask(port, 0x28, 0x08, 0x08);
541
542 /* Enable MEMW# and set ROM size select to max. (4M)*/
543 sio_mask(port, 0x24, 0x28, 0x38);
544
545 } else {
546 msg_perr("WARNING: Flash interface in use by GPIO!\n");
547 }
548 } else {
549 msg_pinfo("BIOS ROM is disabled\n");
550 }
551 w836xx_ext_leave(port);
552}
553
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000554/*
Luc Verhaegen73d21192009-12-23 00:54:26 +0000555 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000556 * - EPoX EP-8K5A2: VIA KT333 + VT8235
557 * - Albatron PM266A Pro: VIA P4M266A + VT8235
558 * - Shuttle AK31 (all versions): VIA KT266 + VT8233
559 * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
560 * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237
Mattias Mattssone295eee2010-08-15 10:21:29 +0000561 * - MSI KM4M-V and KM4AM-V: VIA KM400/KM400A + VT8237
Mattias Mattssone8388242010-09-11 15:25:48 +0000562 * - MSI MS-6561 (745 Ultra): SiS 745 + W83697HF
Sergey A Lichackf3a4bff2010-09-07 18:14:53 +0000563 * - MSI MS-6787 (P4MAM-V/P4MAM-L): VIA P4M266 + VT8235
Uwe Hermann17da61e2010-10-05 21:48:43 +0000564 * - ASRock K7S41: SiS 741 + SiS 963 + W83697HF
Pawel Rozanski1d233072011-06-19 16:52:48 +0000565 * - ASRock K7S41GX: SiS 741GX + SiS 963L + W83697HF
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000566 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000567static int w836xx_memw_enable_2e(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000568{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000569 w836xx_memw_enable(0x2E);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000570
Luc Verhaegen73d21192009-12-23 00:54:26 +0000571 return 0;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000572}
573
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000574/*
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000575 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000576 * - Termtek TK-3370 (rev. 2.5b)
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000577 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000578static int w836xx_memw_enable_4e(void)
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000579{
580 w836xx_memw_enable(0x4E);
581
582 return 0;
583}
584
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000585/*
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000586 * Suited for all boards with ITE IT8705F.
587 * The SIS950 Super I/O probably requires a similar flash write enable.
Luc Verhaegen21f54962010-01-20 14:45:07 +0000588 */
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000589int it8705f_write_enable(uint8_t port)
Luc Verhaegen21f54962010-01-20 14:45:07 +0000590{
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000591 uint8_t tmp;
592 int ret = 0;
593
Luc Verhaegen21f54962010-01-20 14:45:07 +0000594 enter_conf_mode_ite(port);
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000595 tmp = sio_read(port, 0x24);
596 /* Check if at least one flash segment is enabled. */
597 if (tmp & 0xf0) {
598 /* The IT8705F will respond to LPC cycles and translate them. */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000599 internal_buses_supported = BUS_PARALLEL;
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000600 /* Flash ROM I/F Writes Enable */
601 tmp |= 0x04;
602 msg_pdbg("Enabling IT8705F flash ROM interface write.\n");
603 if (tmp & 0x02) {
604 /* The data sheet contradicts itself about max size. */
605 max_rom_decode.parallel = 1024 * 1024;
606 msg_pinfo("IT8705F with very unusual settings. Please "
607 "send the output of \"flashrom -V\" to \n"
Paul Menzelab6328f2010-10-08 11:03:02 +0000608 "flashrom@flashrom.org with "
609 "IT8705: your board name: flashrom -V\n"
610 "as the subject to help us finish "
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000611 "support for your Super I/O. Thanks.\n");
612 ret = 1;
613 } else if (tmp & 0x08) {
614 max_rom_decode.parallel = 512 * 1024;
615 } else {
616 max_rom_decode.parallel = 256 * 1024;
617 }
618 /* Safety checks. The data sheet is unclear here: Segments 1+3
619 * overlap, no segment seems to cover top - 1MB to top - 512kB.
620 * We assume that certain combinations make no sense.
621 */
622 if (((tmp & 0x02) && !(tmp & 0x08)) || /* 1 MB en, 512 kB dis */
623 (!(tmp & 0x10)) || /* 128 kB dis */
624 (!(tmp & 0x40))) { /* 256/512 kB dis */
625 msg_perr("Inconsistent IT8705F decode size!\n");
626 ret = 1;
627 }
628 if (sio_read(port, 0x25) != 0) {
629 msg_perr("IT8705F flash data pins disabled!\n");
630 ret = 1;
631 }
632 if (sio_read(port, 0x26) != 0) {
633 msg_perr("IT8705F flash address pins 0-7 disabled!\n");
634 ret = 1;
635 }
636 if (sio_read(port, 0x27) != 0) {
637 msg_perr("IT8705F flash address pins 8-15 disabled!\n");
638 ret = 1;
639 }
640 if ((sio_read(port, 0x29) & 0x10) != 0) {
641 msg_perr("IT8705F flash write enable pin disabled!\n");
642 ret = 1;
643 }
644 if ((sio_read(port, 0x29) & 0x08) != 0) {
645 msg_perr("IT8705F flash chip select pin disabled!\n");
646 ret = 1;
647 }
648 if ((sio_read(port, 0x29) & 0x04) != 0) {
649 msg_perr("IT8705F flash read strobe pin disabled!\n");
650 ret = 1;
651 }
652 if ((sio_read(port, 0x29) & 0x03) != 0) {
653 msg_perr("IT8705F flash address pins 16-17 disabled!\n");
654 /* Not really an error if you use flash chips smaller
655 * than 256 kByte, but such a configuration is unlikely.
656 */
657 ret = 1;
658 }
659 msg_pdbg("Maximum IT8705F parallel flash decode size is %u.\n",
660 max_rom_decode.parallel);
661 if (ret) {
662 msg_pinfo("Not enabling IT8705F flash write.\n");
663 } else {
664 sio_write(port, 0x24, tmp);
665 }
666 } else {
667 msg_pdbg("No IT8705F flash segment enabled.\n");
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000668 ret = 0;
669 }
Luc Verhaegen21f54962010-01-20 14:45:07 +0000670 exit_conf_mode_ite(port);
671
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000672 return ret;
Luc Verhaegen21f54962010-01-20 14:45:07 +0000673}
Luc Verhaegen73d21192009-12-23 00:54:26 +0000674
Mattias Mattssonfb60cec2010-09-13 19:39:25 +0000675/*
676 * The ITE IT8707F is a custom chip made by ITE exclusively for ASUS.
677 * It uses the Winbond command sequence to enter extended configuration
678 * mode and the ITE sequence to exit.
679 *
680 * Registers seems similar to the ones on ITE IT8710F.
681 */
682static int it8707f_write_enable(uint8_t port)
683{
684 uint8_t tmp;
685
686 w836xx_ext_enter(port);
687
688 /* Set bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A rw */
689 tmp = sio_read(port, 0x23);
690 tmp |= (1 << 3);
691 sio_write(port, 0x23, tmp);
692
693 /* Set bit 2 (FLASH_WE) and bit 3 (FLASH_IF_EN) of reg 0x24 */
694 tmp = sio_read(port, 0x24);
695 tmp |= (1 << 2) | (1 << 3);
696 sio_write(port, 0x24, tmp);
697
698 /* Clear bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A ro */
699 tmp = sio_read(port, 0x23);
700 tmp &= ~(1 << 3);
701 sio_write(port, 0x23, tmp);
702
703 exit_conf_mode_ite(port);
704
705 return 0;
706}
707
708/*
709 * Suited for:
710 * - ASUS P4SC-E: SiS 651 + 962 + ITE IT8707F
711 */
712static int it8707f_write_enable_2e(void)
713{
714 return it8707f_write_enable(0x2e);
715}
716
Michael Karchercba52de2011-03-06 12:07:19 +0000717#define PC87360_ID 0xE1
718#define PC87364_ID 0xE4
719
720static int pc8736x_gpio_set(uint8_t chipid, uint8_t gpio, int raise)
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000721{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000722 static const int bankbase[] = {0, 4, 8, 10, 12};
723 int gpio_bank = gpio / 8;
724 int gpio_pin = gpio % 8;
725 uint16_t baseport;
726 uint8_t id, val;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000727
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000728 if (gpio_bank > 4) {
Michael Karchercba52de2011-03-06 12:07:19 +0000729 msg_perr("PC8736x: Invalid GPIO %d\n", gpio);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000730 return -1;
731 }
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000732
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000733 id = sio_read(0x2E, 0x20);
Michael Karchercba52de2011-03-06 12:07:19 +0000734 if (id != chipid) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000735 msg_perr("PC8736x: unexpected ID %02x (expected %02x)\n",
736 id, chipid);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000737 return -1;
738 }
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000739
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000740 sio_write(0x2E, 0x07, 0x07); /* Select GPIO device. */
741 baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
742 if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) {
743 msg_perr("PC87360: invalid GPIO base address %04x\n",
744 baseport);
745 return -1;
746 }
747 sio_mask (0x2E, 0x30, 0x01, 0x01); /* Enable logical device. */
748 sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin);
749 sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output. */
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000750
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000751 val = INB(baseport + bankbase[gpio_bank]);
752 if (raise)
753 val |= 1 << gpio_pin;
754 else
755 val &= ~(1 << gpio_pin);
756 OUTB(val, baseport + bankbase[gpio_bank]);
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000757
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000758 return 0;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000759}
760
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000761/*
762 * VIA VT823x: Set one of the GPIO pins.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000763 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000764static int via_vt823x_gpio_set(uint8_t gpio, int raise)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000765{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000766 struct pci_dev *dev;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000767 uint16_t base;
David Bartleyf58d3642009-12-09 07:53:01 +0000768 uint8_t val, bit, offset;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000769
Luc Verhaegen73d21192009-12-23 00:54:26 +0000770 dev = pci_dev_find_vendorclass(0x1106, 0x0601);
771 switch (dev->device_id) {
772 case 0x3177: /* VT8235 */
773 case 0x3227: /* VT8237R */
774 case 0x3337: /* VT8237A */
775 break;
776 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000777 msg_perr("\nERROR: VT823x ISA bridge not found.\n");
Luc Verhaegen73d21192009-12-23 00:54:26 +0000778 return -1;
779 }
780
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000781 if ((gpio >= 12) && (gpio <= 15)) {
782 /* GPIO12-15 -> output */
783 val = pci_read_byte(dev, 0xE4);
784 val |= 0x10;
785 pci_write_byte(dev, 0xE4, val);
786 } else if (gpio == 9) {
787 /* GPIO9 -> Output */
788 val = pci_read_byte(dev, 0xE4);
789 val |= 0x20;
790 pci_write_byte(dev, 0xE4, val);
David Bartleyf58d3642009-12-09 07:53:01 +0000791 } else if (gpio == 5) {
792 val = pci_read_byte(dev, 0xE4);
793 val |= 0x01;
794 pci_write_byte(dev, 0xE4, val);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000795 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000796 msg_perr("\nERROR: "
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000797 "VT823x GPIO%02d is not implemented.\n", gpio);
Luc Verhaegen73d21192009-12-23 00:54:26 +0000798 return -1;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000799 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000800
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000801 /* We need the I/O Base Address for this board's flash enable. */
802 base = pci_read_word(dev, 0x88) & 0xff80;
803
David Bartleyf58d3642009-12-09 07:53:01 +0000804 offset = 0x4C + gpio / 8;
805 bit = 0x01 << (gpio % 8);
806
807 val = INB(base + offset);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000808 if (raise)
809 val |= bit;
810 else
811 val &= ~bit;
David Bartleyf58d3642009-12-09 07:53:01 +0000812 OUTB(val, base + offset);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000813
Uwe Hermanna7e05482007-05-09 10:17:44 +0000814 return 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000815}
816
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000817/*
818 * Suited for:
819 * - ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000820 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000821static int via_vt823x_gpio5_raise(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000822{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000823 /* On M2V-MX: GPO5 is connected to WP# and TBL#. */
824 return via_vt823x_gpio_set(5, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000825}
826
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000827/*
828 * Suited for:
829 * - VIA EPIA EK & N & NL
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000830 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000831static int via_vt823x_gpio9_raise(void)
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000832{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000833 return via_vt823x_gpio_set(9, 1);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000834}
835
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000836/*
837 * Suited for:
838 * - VIA EPIA M and MII (and maybe other CLE266 based EPIAs)
Luc Verhaegen73d21192009-12-23 00:54:26 +0000839 *
840 * We don't need to do this for EPIA M when using coreboot, GPIO15 is never
841 * lowered there.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000842 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000843static int via_vt823x_gpio15_raise(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000844{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000845 return via_vt823x_gpio_set(15, 1);
846}
847
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000848/*
Luc Verhaegen73d21192009-12-23 00:54:26 +0000849 * Winbond W83697HF Super I/O + VIA VT8235 southbridge
850 *
851 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000852 * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
853 * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
Luc Verhaegen73d21192009-12-23 00:54:26 +0000854 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000855static int board_msi_kt4v(void)
Luc Verhaegen73d21192009-12-23 00:54:26 +0000856{
857 int ret;
858
859 ret = via_vt823x_gpio_set(12, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000860 w836xx_memw_enable(0x2E);
Luc Verhaegen97866082008-02-09 02:03:06 +0000861
Luc Verhaegen73d21192009-12-23 00:54:26 +0000862 return ret;
Luc Verhaegen97866082008-02-09 02:03:06 +0000863}
864
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000865/*
866 * Suited for:
867 * - ASUS P5A
Luc Verhaegen6b141752007-05-20 16:16:13 +0000868 *
869 * This is rather nasty code, but there's no way to do this cleanly.
870 * We're basically talking to some unknown device on SMBus, my guess
871 * is that it is the Winbond W83781D that lives near the DIP BIOS.
872 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000873static int board_asus_p5a(void)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000874{
875 uint8_t tmp;
876 int i;
877
878#define ASUSP5A_LOOP 5000
879
Andriy Gapon65c1b862008-05-22 13:22:45 +0000880 OUTB(0x00, 0xE807);
881 OUTB(0xEF, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000882
Andriy Gapon65c1b862008-05-22 13:22:45 +0000883 OUTB(0xFF, 0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000884
885 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000886 OUTB(0xE1, 0xFF);
887 if (INB(0xE800) & 0x04)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000888 break;
889 }
890
891 if (i == ASUSP5A_LOOP) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000892 msg_perr("Unable to contact device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000893 return -1;
894 }
895
Andriy Gapon65c1b862008-05-22 13:22:45 +0000896 OUTB(0x20, 0xE801);
897 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000898
Andriy Gapon65c1b862008-05-22 13:22:45 +0000899 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000900
901 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000902 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000903 if (tmp & 0x70)
904 break;
905 }
906
907 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000908 msg_perr("Failed to read device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000909 return -1;
910 }
911
Andriy Gapon65c1b862008-05-22 13:22:45 +0000912 tmp = INB(0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000913 tmp &= ~0x02;
914
Andriy Gapon65c1b862008-05-22 13:22:45 +0000915 OUTB(0x00, 0xE807);
916 OUTB(0xEE, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000917
Andriy Gapon65c1b862008-05-22 13:22:45 +0000918 OUTB(tmp, 0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000919
Andriy Gapon65c1b862008-05-22 13:22:45 +0000920 OUTB(0xFF, 0xE800);
921 OUTB(0xE1, 0xFF);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000922
Andriy Gapon65c1b862008-05-22 13:22:45 +0000923 OUTB(0x20, 0xE801);
924 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000925
Andriy Gapon65c1b862008-05-22 13:22:45 +0000926 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000927
928 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000929 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000930 if (tmp & 0x70)
931 break;
932 }
933
934 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000935 msg_perr("Failed to write to device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000936 return -1;
937 }
938
939 return 0;
940}
941
Luc Verhaegena7e30502009-12-09 11:39:02 +0000942/*
943 * Set GPIO lines in the Broadcom HT-1000 southbridge.
944 *
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000945 * It's not a Super I/O but it uses the same index/data port method.
Luc Verhaegena7e30502009-12-09 11:39:02 +0000946 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000947static int board_hp_dl145_g3_enable(void)
Luc Verhaegena7e30502009-12-09 11:39:02 +0000948{
949 /* GPIO 0 reg from PM regs */
950 /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
951 sio_mask(0xcd6, 0x44, 0x24, 0x24);
952
953 return 0;
954}
955
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +0000956/*
957 * Set GPIO lines in the Broadcom HT-1000 southbridge.
958 *
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000959 * It's not a Super I/O but it uses the same index/data port method.
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +0000960 */
961static int board_hp_dl165_g6_enable(void)
962{
963 /* Variant of DL145, with slightly different pin placement. */
964 sio_mask(0xcd6, 0x44, 0x80, 0x80); /* TBL# */
965 sio_mask(0xcd6, 0x46, 0x04, 0x04); /* WP# */
966
967 return 0;
968}
969
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000970static int board_ibm_x3455(void)
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000971{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000972 /* Raise GPIO13. */
Carl-Daniel Hailfinger500b4232009-06-01 21:30:42 +0000973 sio_mask(0xcd6, 0x45, 0x20, 0x20);
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000974
975 return 0;
976}
977
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000978/*
979 * Suited for:
980 * - Shuttle FN25 (SN25P): AMD S939 + NVIDIA CK804 (nForce4)
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000981 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000982static int board_shuttle_fn25(void)
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000983{
984 struct pci_dev *dev;
985
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000986 dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA bridge. */
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000987 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000988 msg_perr("\nERROR: NVIDIA nForce4 ISA bridge not found.\n");
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000989 return -1;
990 }
991
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000992 /* One of those bits seems to be connected to TBL#, but -ENOINFO. */
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000993 pci_write_byte(dev, 0x92, 0);
994
995 return 0;
996}
997
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000998/*
Mattias Mattssonf4925162010-09-16 22:09:18 +0000999 * Suited for:
1000 * - Elitegroup GeForce6100SM-M: NVIDIA MCP61 + ITE IT8726F
1001 */
Mattias Mattssonf4925162010-09-16 22:09:18 +00001002static int board_ecs_geforce6100sm_m(void)
1003{
1004 struct pci_dev *dev;
1005 uint32_t tmp;
1006
1007 dev = pci_dev_find(0x10DE, 0x03EB); /* NVIDIA MCP61 SMBus. */
1008 if (!dev) {
1009 msg_perr("\nERROR: NVIDIA MCP61 SMBus not found.\n");
1010 return -1;
1011 }
1012
1013 tmp = pci_read_byte(dev, 0xE0);
1014 tmp &= ~(1 << 3);
1015 pci_write_byte(dev, 0xE0, tmp);
1016
1017 return 0;
1018}
1019
1020/*
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001021 * Very similar to AMD 8111 IO Hub.
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001022 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001023static int nvidia_mcp_gpio_set(int gpio, int raise)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001024{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001025 struct pci_dev *dev;
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001026 uint16_t base, devclass;
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001027 uint8_t tmp;
1028
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001029 if ((gpio < 0) || (gpio >= 0x40)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001030 msg_perr("\nERROR: unsupported GPIO: %d.\n", gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +00001031 return -1;
1032 }
1033
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001034 /* Check for the ISA bridge first. */
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001035 dev = pci_dev_find_vendorclass(0x10DE, 0x0601);
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001036 switch (dev->device_id) {
1037 case 0x0030: /* CK804 */
1038 case 0x0050: /* MCP04 */
1039 case 0x0060: /* MCP2 */
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001040 case 0x00E0: /* CK8 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001041 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +00001042 case 0x0260: /* MCP51 */
Michael Karcher242efd42011-03-06 12:09:05 +00001043 case 0x0261: /* MCP51 */
Michael Karcher2ead2e22010-06-01 16:09:06 +00001044 case 0x0364: /* MCP55 */
1045 /* find SMBus controller on *this* southbridge */
1046 /* The infamous Tyan S2915-E has two south bridges; they are
1047 easily told apart from each other by the class of the
1048 LPC bridge, but have the same SMBus bridge IDs */
1049 if (dev->func != 0) {
1050 msg_perr("MCP LPC bridge at unexpected function"
1051 " number %d\n", dev->func);
1052 return -1;
1053 }
1054
Carl-Daniel Hailfinger44cd9ab2010-07-17 22:28:05 +00001055#if PCI_LIB_VERSION >= 0x020200
Michael Karcher2ead2e22010-06-01 16:09:06 +00001056 dev = pci_get_dev(pacc, dev->domain, dev->bus, dev->dev, 1);
Carl-Daniel Hailfinger44cd9ab2010-07-17 22:28:05 +00001057#else
1058 /* pciutils/libpci before version 2.2 is too old to support
1059 * PCI domains. Such old machines usually don't have domains
1060 * besides domain 0, so this is not a problem.
1061 */
1062 dev = pci_get_dev(pacc, dev->bus, dev->dev, 1);
1063#endif
Michael Karcher2ead2e22010-06-01 16:09:06 +00001064 if (!dev) {
1065 msg_perr("MCP SMBus controller could not be found\n");
1066 return -1;
1067 }
1068 devclass = pci_read_word(dev, PCI_CLASS_DEVICE);
1069 if (devclass != 0x0C05) {
1070 msg_perr("Unexpected device class %04x for SMBus"
1071 " controller\n", devclass);
1072 return -1;
1073 }
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001074 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +00001075 default:
Sean Nelson316a29f2010-05-07 20:09:04 +00001076 msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n");
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001077 return -1;
1078 }
1079
1080 base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */
1081 base += 0xC0;
1082
1083 tmp = INB(base + gpio);
1084 tmp &= ~0x0F; /* null lower nibble */
1085 tmp |= 0x04; /* gpio -> output. */
1086 if (raise)
1087 tmp |= 0x01;
1088 OUTB(tmp, base + gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +00001089
1090 return 0;
1091}
1092
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001093/*
1094 * Suited for:
Stefan Taunera9cbbac2011-08-07 13:17:20 +00001095 * - ASUS A8M2N-LA (HP OEM "NodusM3-GL8E"): NVIDIA MCP51
Sean Nelson0a247512010-08-15 14:36:18 +00001096 * - ASUS A8N-LA (HP OEM "Nagami-GL8E"): NVIDIA MCP51
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001097 * - ASUS M2NBP-VM CSM: NVIDIA MCP51
Michael Karcherb2184c12010-03-07 16:42:55 +00001098 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001099static int nvidia_mcp_gpio0_raise(void)
Michael Karcherb2184c12010-03-07 16:42:55 +00001100{
1101 return nvidia_mcp_gpio_set(0x00, 1);
1102}
1103
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001104/*
1105 * Suited for:
1106 * - abit KN8 Ultra: NVIDIA CK804
Sean Nelson92bc6bd2010-03-19 22:37:29 +00001107 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001108static int nvidia_mcp_gpio2_lower(void)
Sean Nelson92bc6bd2010-03-19 22:37:29 +00001109{
1110 return nvidia_mcp_gpio_set(0x02, 0);
1111}
1112
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001113/*
1114 * Suited for:
Michael Karcher2842db32011-04-14 23:14:27 +00001115 * - Foxconn 6150K8MD-8EKRSH: Socket 939 + NVIDIA MCP51
Uwe Hermannead705f2010-08-15 15:26:30 +00001116 * - MSI K8N Neo4: NVIDIA CK804. TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html.
1117 * - MSI K8NGM2-L: NVIDIA MCP51
Luc Verhaegen6c5f7332009-12-23 03:01:36 +00001118 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001119static int nvidia_mcp_gpio2_raise(void)
Luc Verhaegen6c5f7332009-12-23 03:01:36 +00001120{
1121 return nvidia_mcp_gpio_set(0x02, 1);
1122}
1123
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001124/*
1125 * Suited for:
Uwe Hermann83d349a2010-10-18 22:32:03 +00001126 * - EPoX EP-8NPA7I: Socket 754 + NVIDIA nForce4 4X
Jonathan Kollaschf8db9592010-10-15 23:02:15 +00001127 */
1128static int nvidia_mcp_gpio4_raise(void)
1129{
1130 return nvidia_mcp_gpio_set(0x04, 1);
1131}
1132
1133/*
1134 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001135 * - HP xw9400 (Tyan S2915-E OEM): Dual(!) NVIDIA MCP55
1136 *
1137 * Notes: a) There are two MCP55 chips, so also two SMBus bridges on that
1138 * board. We can't tell the SMBus logical devices apart, but we
1139 * can tell the LPC bridge functions apart.
1140 * We need to choose the SMBus bridge next to the LPC bridge with
1141 * ID 0x364 and the "LPC bridge" class.
1142 * b) #TBL is hardwired on that board to a pull-down. It can be
1143 * overridden by connecting the two solder points next to F2.
Michael Karcher2ead2e22010-06-01 16:09:06 +00001144 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001145static int nvidia_mcp_gpio5_raise(void)
Michael Karcher2ead2e22010-06-01 16:09:06 +00001146{
1147 return nvidia_mcp_gpio_set(0x05, 1);
1148}
1149
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001150/*
1151 * Suited for:
1152 * - abit NF7-S: NVIDIA CK804
Michael Karcher8f10d242010-04-11 21:01:06 +00001153 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001154static int nvidia_mcp_gpio8_raise(void)
Michael Karcher8f10d242010-04-11 21:01:06 +00001155{
1156 return nvidia_mcp_gpio_set(0x08, 1);
1157}
1158
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001159/*
1160 * Suited for:
Cristian Măgherușan-Stanciu9932c7b2011-07-07 19:56:58 +00001161 * - GIGABYTE GA-K8NS Pro-939: Socket 939 + NVIDIA nForce3 + CK8
Idwer Volleringd8a00a02011-06-13 16:58:54 +00001162 */
1163static int nvidia_mcp_gpio0a_raise(void)
1164{
1165 return nvidia_mcp_gpio_set(0x0a, 1);
1166}
1167
1168/*
1169 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001170 * - MSI K8N Neo2 Platinum: Socket 939 + nForce3 Ultra + CK8
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001171 */
Michael Karcher51825082010-06-12 23:14:03 +00001172static int nvidia_mcp_gpio0c_raise(void)
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001173{
1174 return nvidia_mcp_gpio_set(0x0c, 1);
1175}
1176
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001177/*
1178 * Suited for:
1179 * - abit NF-M2 nView: Socket AM2 + NVIDIA MCP51
Michael Karcherefd8af32010-07-24 22:50:54 +00001180 */
1181static int nvidia_mcp_gpio4_lower(void)
1182{
1183 return nvidia_mcp_gpio_set(0x04, 0);
1184}
1185
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001186/*
1187 * Suited for:
1188 * - ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001189 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001190static int nvidia_mcp_gpio10_raise(void)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001191{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001192 return nvidia_mcp_gpio_set(0x10, 1);
1193}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001194
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001195/*
1196 * Suited for:
1197 * - GIGABYTE GA-K8N-SLI: AMD socket 939 + NVIDIA CK804 + ITE IT8712F
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001198 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001199static int nvidia_mcp_gpio21_raise(void)
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001200{
1201 return nvidia_mcp_gpio_set(0x21, 0x01);
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001202}
1203
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001204/*
1205 * Suited for:
1206 * - EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001207 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001208static int nvidia_mcp_gpio31_raise(void)
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001209{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001210 return nvidia_mcp_gpio_set(0x31, 0x01);
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001211}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001212
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001213/*
1214 * Suited for:
Michael Karcher242efd42011-03-06 12:09:05 +00001215 * - GIGABYTE GA-K8N51GMF: Socket 754 + Geforce 6100 + MCP51
1216 * - GIGABYTE GA-K8N51GMF-9: Socket 939 + Geforce 6100 + MCP51
Joshua Roys2ee137f2010-09-07 17:52:09 +00001217 */
1218static int nvidia_mcp_gpio3b_raise(void)
1219{
1220 return nvidia_mcp_gpio_set(0x3b, 1);
1221}
1222
1223/*
1224 * Suited for:
Joshua Roysb992d342011-11-02 14:31:18 +00001225 * - Sun Ultra 40 M2: Dual Socket F (1207) + MCP55
1226 */
1227static int board_sun_ultra_40_m2(void)
1228{
1229 int ret;
1230 uint8_t reg;
1231 uint16_t base;
1232 struct pci_dev *dev;
1233
1234 ret = nvidia_mcp_gpio4_lower();
1235 if (ret)
1236 return ret;
1237
1238 dev = pci_dev_find(0x10de, 0x0364); /* NVIDIA MCP55 LPC bridge */
1239 if (!dev) {
1240 msg_perr("\nERROR: NVIDIA MCP55 LPC bridge not found.\n");
1241 return -1;
1242 }
1243
1244 base = pci_read_word(dev, 0xb4); /* some IO BAR? */
1245 if (!base)
1246 return -1;
1247
1248 reg = INB(base + 0x4b);
1249 reg |= 0x10;
1250 OUTB(reg, base + 0x4b);
1251
1252 return 0;
1253}
1254
1255/*
1256 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001257 * - Artec Group DBE61 and DBE62
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001258 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001259static int board_artecgroup_dbe6x(void)
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001260{
1261#define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001262#define DBE6x_PRI_BOOT_LOC_SHIFT 2
1263#define DBE6x_BOOT_OP_LATCHED_SHIFT 8
1264#define DBE6x_SEC_BOOT_LOC_SHIFT 10
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001265#define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT)
1266#define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT)
1267#define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT)
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001268#define DBE6x_BOOT_LOC_FLASH 2
1269#define DBE6x_BOOT_LOC_FWHUB 3
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001270
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001271 msr_t msr;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001272 unsigned long boot_loc;
1273
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001274 /* Geode only has a single core */
1275 if (setup_cpu_msr(0))
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001276 return -1;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001277
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001278 msr = rdmsr(DBE6x_MSR_DIVIL_BALL_OPTS);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001279
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001280 if ((msr.lo & (DBE6x_BOOT_OP_LATCHED)) ==
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001281 (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT))
1282 boot_loc = DBE6x_BOOT_LOC_FWHUB;
1283 else
1284 boot_loc = DBE6x_BOOT_LOC_FLASH;
1285
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001286 msr.lo &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC);
1287 msr.lo |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) |
Uwe Hermann394131e2008-10-18 21:14:13 +00001288 (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001289
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001290 wrmsr(DBE6x_MSR_DIVIL_BALL_OPTS, msr);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001291
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001292 cleanup_cpu_msr();
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001293
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001294 return 0;
1295}
1296
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001297/*
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001298 * Suited for:
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001299 * - ASUS A8AE-LE (Codename AmberineM; used in Compaq Presario 061)
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001300 * Datasheet(s) used:
1301 * - AMD document 43009 "AMD SB700/710/750 Register Reference Guide" rev. 1.00
1302 */
1303static int amd_sbxxx_gpio9_raise(void)
1304{
1305 struct pci_dev *dev;
1306 uint32_t reg;
1307
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001308 dev = pci_dev_find(0x1002, 0x4372); /* AMD SMBus controller */
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001309 if (!dev) {
1310 msg_perr("\nERROR: AMD SMBus Controller (0x4372) not found.\n");
1311 return -1;
1312 }
1313
1314 reg = pci_read_long(dev, 0xA8); /* GPIO_12_to_4_Cntrl CI_Reg: A8h-ABh */
1315 /* enable output (0: enable, 1: tristate):
1316 GPIO9 output enable is at bit 5 in 0xA9 */
1317 reg &= ~((uint32_t)1<<(8+5));
1318 /* raise:
1319 GPIO9 output register is at bit 5 in 0xA8 */
1320 reg |= (1<<5);
1321 pci_write_long(dev, 0xA8, reg);
1322
1323 return 0;
1324}
1325
1326/*
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001327 * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}.
Luc Verhaegenf5226912009-12-14 10:41:58 +00001328 */
1329static int intel_piix4_gpo_set(unsigned int gpo, int raise)
1330{
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001331 unsigned int gpo_byte, gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001332 struct pci_dev *dev;
1333 uint32_t tmp, base;
1334
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001335 /* GPO{0,8,27,28,30} are always available. */
1336 static const uint32_t nonmuxed_gpos = 0x58000101;
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001337
1338 static const struct {unsigned int reg, mask, value; } piix4_gpo[] = {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001339 {0},
1340 {0xB0, 0x0001, 0x0000}, /* GPO1... */
1341 {0xB0, 0x0001, 0x0000},
1342 {0xB0, 0x0001, 0x0000},
1343 {0xB0, 0x0001, 0x0000},
1344 {0xB0, 0x0001, 0x0000},
1345 {0xB0, 0x0001, 0x0000},
1346 {0xB0, 0x0001, 0x0000}, /* ...GPO7: GENCFG bit 0 */
1347 {0},
1348 {0xB0, 0x0100, 0x0000}, /* GPO9: GENCFG bit 8 */
1349 {0xB0, 0x0200, 0x0000}, /* GPO10: GENCFG bit 9 */
1350 {0xB0, 0x0400, 0x0000}, /* GPO11: GENCFG bit 10 */
1351 {0x4E, 0x0100, 0x0000}, /* GPO12... */
1352 {0x4E, 0x0100, 0x0000},
1353 {0x4E, 0x0100, 0x0000}, /* ...GPO14: XBCS bit 8 */
1354 {0xB2, 0x0002, 0x0002}, /* GPO15... */
1355 {0xB2, 0x0002, 0x0002}, /* ...GPO16: GENCFG bit 17 */
1356 {0xB2, 0x0004, 0x0004}, /* GPO17: GENCFG bit 18 */
1357 {0xB2, 0x0008, 0x0008}, /* GPO18: GENCFG bit 19 */
1358 {0xB2, 0x0010, 0x0010}, /* GPO19: GENCFG bit 20 */
1359 {0xB2, 0x0020, 0x0020}, /* GPO20: GENCFG bit 21 */
1360 {0xB2, 0x0040, 0x0040}, /* GPO21: GENCFG bit 22 */
1361 {0xB2, 0x1000, 0x1000}, /* GPO22... */
1362 {0xB2, 0x1000, 0x1000}, /* ...GPO23: GENCFG bit 28 */
1363 {0xB2, 0x2000, 0x2000}, /* GPO24: GENCFG bit 29 */
1364 {0xB2, 0x4000, 0x4000}, /* GPO25: GENCFG bit 30 */
1365 {0xB2, 0x8000, 0x8000}, /* GPO26: GENCFG bit 31 */
1366 {0},
1367 {0},
1368 {0x4E, 0x0100, 0x0000}, /* ...GPO29: XBCS bit 8 */
1369 {0}
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001370 };
1371
Luc Verhaegenf5226912009-12-14 10:41:58 +00001372 dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */
1373 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001374 msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +00001375 return -1;
1376 }
1377
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001378 /* Sanity check. */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001379 if (gpo > 30) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001380 msg_perr("\nERROR: Intel PIIX4 has no GPO%d.\n", gpo);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001381 return -1;
1382 }
1383
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001384 if ((((1 << gpo) & nonmuxed_gpos) == 0) &&
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001385 ((pci_read_word(dev, piix4_gpo[gpo].reg) & piix4_gpo[gpo].mask) !=
1386 piix4_gpo[gpo].value)) {
1387 msg_perr("\nERROR: PIIX4 GPO%d not programmed for output.\n", gpo);
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001388 return -1;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001389 }
1390
Luc Verhaegenf5226912009-12-14 10:41:58 +00001391 dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */
1392 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001393 msg_perr("\nERROR: Intel PIIX4 PM not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +00001394 return -1;
1395 }
1396
1397 /* PM IO base */
1398 base = pci_read_long(dev, 0x40) & 0x0000FFC0;
1399
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001400 gpo_byte = gpo >> 3;
1401 gpo_bit = gpo & 7;
1402 tmp = INB(base + 0x34 + gpo_byte); /* GPO register */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001403 if (raise)
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001404 tmp |= 0x01 << gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001405 else
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001406 tmp &= ~(0x01 << gpo_bit);
1407 OUTB(tmp, base + 0x34 + gpo_byte);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001408
1409 return 0;
1410}
1411
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001412/*
1413 * Suited for:
Joshua Roysd708fad2012-02-17 14:51:15 +00001414 * - ASUS OPLX-M
Mattias Mattsson85016b92010-09-01 01:21:34 +00001415 * - ASUS P2B-N
1416 */
1417static int intel_piix4_gpo18_lower(void)
1418{
1419 return intel_piix4_gpo_set(18, 0);
1420}
1421
1422/*
1423 * Suited for:
Mattias Mattssonc8ca3de2010-09-13 18:22:36 +00001424 * - MSI MS-6163 v2 (MS-6163 Pro): Intel 440BX + PIIX4E + Winbond W83977EF
1425 */
1426static int intel_piix4_gpo14_raise(void)
1427{
1428 return intel_piix4_gpo_set(14, 1);
1429}
1430
1431/*
1432 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001433 * - EPoX EP-BX3
Luc Verhaegenf5226912009-12-14 10:41:58 +00001434 */
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001435static int intel_piix4_gpo22_raise(void)
Luc Verhaegenf5226912009-12-14 10:41:58 +00001436{
1437 return intel_piix4_gpo_set(22, 1);
1438}
1439
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001440/*
1441 * Suited for:
Tim ter Laak4b933f02010-09-13 23:00:57 +00001442 * - abit BM6
1443 */
1444static int intel_piix4_gpo26_lower(void)
1445{
1446 return intel_piix4_gpo_set(26, 0);
1447}
1448
1449/*
1450 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001451 * - Intel SE440BX-2
Michael Karcher51cd0c92010-03-19 22:35:21 +00001452 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001453static int intel_piix4_gpo27_lower(void)
Michael Karcher51cd0c92010-03-19 22:35:21 +00001454{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001455 return intel_piix4_gpo_set(27, 0);
Michael Karcher51cd0c92010-03-19 22:35:21 +00001456}
1457
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001458/*
Mattias Mattsson2eaad632010-10-05 21:32:29 +00001459 * Suited for:
1460 * - Dell OptiPlex GX1
1461 */
1462static int intel_piix4_gpo30_lower(void)
1463{
1464 return intel_piix4_gpo_set(30, 0);
1465}
1466
1467/*
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001468 * Set a GPIO line on a given Intel ICH LPC controller.
Uwe Hermann93f66db2008-05-22 21:19:38 +00001469 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001470static int intel_ich_gpio_set(int gpio, int raise)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001471{
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001472 /* Table mapping the different Intel ICH LPC chipsets. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001473 static struct {
1474 uint16_t id;
1475 uint8_t base_reg;
1476 uint32_t bank0;
1477 uint32_t bank1;
1478 uint32_t bank2;
1479 } intel_ich_gpio_table[] = {
1480 {0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */
1481 {0x2420, 0x58, 0x0FE30000, 0, 0}, /* 82801AB (ICH0) */
1482 {0x2440, 0x58, 0x1BFF391B, 0, 0}, /* 82801BA (ICH2) */
1483 {0x244C, 0x58, 0x1A23399B, 0, 0}, /* 82801BAM (ICH2M) */
1484 {0x2450, 0x58, 0x1BFF0000, 0, 0}, /* 82801E (C-ICH) */
1485 {0x2480, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801CA (ICH3-S) */
1486 {0x248C, 0x58, 0x1A230000, 0x00000FFF, 0}, /* 82801CAM (ICH3-M) */
1487 {0x24C0, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801DB/DBL (ICH4/ICH4-L) */
1488 {0x24CC, 0x58, 0x1A030000, 0x00000FFF, 0}, /* 82801DBM (ICH4-M) */
1489 {0x24D0, 0x58, 0x1BFF0000, 0x00030305, 0}, /* 82801EB/ER (ICH5/ICH5R) */
1490 {0x2640, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FB/FR (ICH6/ICH6R) */
1491 {0x2641, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FBM (ICH6M) */
1492 {0x27B8, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GB/GR (ICH7 Family) */
1493 {0x27B9, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GBM (ICH7-M) */
1494 {0x27BD, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GHM (ICH7-M DH) */
1495 {0x2810, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HB/HR (ICH8/R) */
1496 {0x2811, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HBM (ICH8M-E) */
1497 {0x2812, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HH (ICH8DH) */
1498 {0x2814, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HO (ICH8DO) */
1499 {0x2815, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HEM (ICH8M) */
1500 {0x2912, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IH (ICH9DH) */
1501 {0x2914, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IO (ICH9DO) */
1502 {0x2916, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IR (ICH9R) */
1503 {0x2917, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IEM (ICH9M-E) */
1504 {0x2918, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IB (ICH9) */
1505 {0x2919, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IBM (ICH9M) */
1506 {0x3A14, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JDO (ICH10DO) */
1507 {0x3A16, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIR (ICH10R) */
1508 {0x3A18, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIB (ICH10) */
1509 {0x3A1A, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JD (ICH10D) */
1510 {0, 0, 0, 0, 0} /* end marker */
1511 };
Uwe Hermann93f66db2008-05-22 21:19:38 +00001512
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001513 struct pci_dev *dev;
1514 uint16_t base;
1515 uint32_t tmp;
1516 int i, allowed;
1517
1518 /* First, look for a known LPC bridge */
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001519 for (dev = pacc->devices; dev; dev = dev->next) {
Carl-Daniel Hailfingerd175e062010-05-21 23:00:56 +00001520 uint16_t device_class;
1521 /* libpci before version 2.2.4 does not store class info. */
1522 device_class = pci_read_word(dev, PCI_CLASS_DEVICE);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001523 if ((dev->vendor_id == 0x8086) &&
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001524 (device_class == 0x0601)) { /* ISA bridge */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001525 /* Is this device in our list? */
1526 for (i = 0; intel_ich_gpio_table[i].id; i++)
1527 if (dev->device_id == intel_ich_gpio_table[i].id)
1528 break;
1529
1530 if (intel_ich_gpio_table[i].id)
1531 break;
1532 }
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001533 }
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001534
Uwe Hermann93f66db2008-05-22 21:19:38 +00001535 if (!dev) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001536 msg_perr("\nERROR: No known Intel LPC bridge found.\n");
Uwe Hermann93f66db2008-05-22 21:19:38 +00001537 return -1;
1538 }
1539
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001540 /*
1541 * According to the datasheets, all Intel ICHs have the GPIO bar 5:1
1542 * strapped to zero. From some mobile ICH9 version on, this becomes
1543 * 6:1. The mask below catches all.
1544 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001545 base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0;
Uwe Hermann93f66db2008-05-22 21:19:38 +00001546
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001547 /* Check whether the line is allowed. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001548 if (gpio < 32)
1549 allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01;
1550 else if (gpio < 64)
1551 allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01;
1552 else
1553 allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01;
1554
1555 if (!allowed) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001556 msg_perr("\nERROR: This Intel LPC bridge does not allow"
1557 " setting GPIO%02d\n", gpio);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001558 return -1;
1559 }
1560
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001561 msg_pdbg("\nIntel ICH LPC bridge: %sing GPIO%02d.\n",
1562 raise ? "Rais" : "Dropp", gpio);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001563
1564 if (gpio < 32) {
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001565 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001566 tmp = INL(base);
1567 /* ICH/ICH0 multiplexes 27/28 on the line set. */
1568 if ((gpio == 28) &&
1569 ((dev->device_id == 0x2410) || (dev->device_id == 0x2420)))
1570 tmp |= 1 << 27;
1571 else
1572 tmp |= 1 << gpio;
1573 OUTL(tmp, base);
1574
1575 /* As soon as we are talking to ICH8 and above, this register
1576 decides whether we can set the gpio or not. */
1577 if (dev->device_id > 0x2800) {
1578 tmp = INL(base);
1579 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001580 msg_perr("\nERROR: This Intel LPC bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001581 " does not allow setting GPIO%02d\n",
1582 gpio);
1583 return -1;
1584 }
1585 }
1586
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001587 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001588 tmp = INL(base + 0x04);
1589 tmp &= ~(1 << gpio);
1590 OUTL(tmp, base + 0x04);
1591
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001592 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001593 tmp = INL(base + 0x0C);
1594 if (raise)
1595 tmp |= 1 << gpio;
1596 else
1597 tmp &= ~(1 << gpio);
1598 OUTL(tmp, base + 0x0C);
1599 } else if (gpio < 64) {
1600 gpio -= 32;
1601
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001602 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001603 tmp = INL(base + 0x30);
1604 tmp |= 1 << gpio;
1605 OUTL(tmp, base + 0x30);
1606
1607 /* As soon as we are talking to ICH8 and above, this register
1608 decides whether we can set the gpio or not. */
1609 if (dev->device_id > 0x2800) {
1610 tmp = INL(base + 30);
1611 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001612 msg_perr("\nERROR: This Intel LPC bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001613 " does not allow setting GPIO%02d\n",
1614 gpio + 32);
1615 return -1;
1616 }
1617 }
1618
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001619 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001620 tmp = INL(base + 0x34);
1621 tmp &= ~(1 << gpio);
1622 OUTL(tmp, base + 0x34);
1623
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001624 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001625 tmp = INL(base + 0x38);
1626 if (raise)
1627 tmp |= 1 << gpio;
1628 else
1629 tmp &= ~(1 << gpio);
1630 OUTL(tmp, base + 0x38);
1631 } else {
1632 gpio -= 64;
1633
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001634 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001635 tmp = INL(base + 0x40);
1636 tmp |= 1 << gpio;
1637 OUTL(tmp, base + 0x40);
1638
1639 tmp = INL(base + 40);
1640 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001641 msg_perr("\nERROR: This Intel LPC bridge does "
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001642 "not allow setting GPIO%02d\n", gpio + 64);
1643 return -1;
1644 }
1645
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001646 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001647 tmp = INL(base + 0x44);
1648 tmp &= ~(1 << gpio);
1649 OUTL(tmp, base + 0x44);
1650
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001651 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001652 tmp = INL(base + 0x48);
1653 if (raise)
1654 tmp |= 1 << gpio;
1655 else
1656 tmp &= ~(1 << gpio);
1657 OUTL(tmp, base + 0x48);
1658 }
Uwe Hermann93f66db2008-05-22 21:19:38 +00001659
1660 return 0;
1661}
1662
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001663/*
1664 * Suited for:
1665 * - abit IP35: Intel P35 + ICH9R
1666 * - abit IP35 Pro: Intel P35 + ICH9R
Joshua Roysac8b2a12011-08-11 04:21:34 +00001667 * - ASUS P5LD2
Uwe Hermann93f66db2008-05-22 21:19:38 +00001668 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001669static int intel_ich_gpio16_raise(void)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001670{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001671 return intel_ich_gpio_set(16, 1);
Uwe Hermann93f66db2008-05-22 21:19:38 +00001672}
1673
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001674/*
1675 * Suited for:
1676 * - HP Puffer2-UL8E (ASUS PTGD-LA OEM): LGA775 + 915 + ICH6
Michael Karchere57957c2010-07-24 11:14:37 +00001677 */
1678static int intel_ich_gpio18_raise(void)
1679{
1680 return intel_ich_gpio_set(18, 1);
1681}
1682
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001683/*
1684 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001685 * - MSI MS-7046: LGA775 + 915P + ICH6
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001686 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001687static int intel_ich_gpio19_raise(void)
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001688{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001689 return intel_ich_gpio_set(19, 1);
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001690}
1691
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001692/*
Luc Verhaegen6c5d4cc2009-11-28 18:26:21 +00001693 * Suited for:
Stefan Tauner027e0182012-05-02 19:48:21 +00001694 * - ASUS P5BV-R: LGA775 + 3200 + ICH7
1695 */
1696static int intel_ich_gpio20_raise(void)
1697{
1698 return intel_ich_gpio_set(20, 1);
1699}
1700
1701/*
1702 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001703 * - ASUS P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2
1704 * - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5
Michael Karcherf4b58792010-09-10 14:54:18 +00001705 * - ASUS P4P800: Intel socket478 + 865PE + ICH5R
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001706 * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R
Diego Elio Pettenòc6f71462011-03-06 22:52:55 +00001707 * - ASUS P4P800-VM: Intel socket478 + 865PE + ICH5R
Michael Karcher4a23e442010-09-10 14:46:46 +00001708 * - ASUS P5GD1 Pro: Intel LGA 775 + 915P + ICH6R
Joshua Roys1fd4f9e2011-08-11 05:47:32 +00001709 * - ASUS P5GD2 Premium: Intel LGA775 + 915G + ICH6R
Joshua Roysb1d980f2010-09-13 14:02:22 +00001710 * - ASUS P5GDC Deluxe: Intel socket775 + 915P + ICH6R
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001711 * - ASUS P5PE-VM: Intel LGA775 + 865G + ICH5
Stefan Taunerded71e52012-03-10 19:22:13 +00001712 * - ASUS TUSL2-C: Intel socket370 + 815 + ICH2
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001713 * - Samsung Polaris 32: socket478 + 865P + ICH5
Peter Stuge09c13332009-02-02 22:55:26 +00001714 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001715static int intel_ich_gpio21_raise(void)
Peter Stuge09c13332009-02-02 22:55:26 +00001716{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001717 return intel_ich_gpio_set(21, 1);
Peter Stuge09c13332009-02-02 22:55:26 +00001718}
1719
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001720/*
Michael Karcher03b80e92010-03-07 16:32:32 +00001721 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001722 * - ASUS P4B266: socket478 + Intel 845D + ICH2
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001723 * - ASUS P4B533-E: socket478 + 845E + ICH4
1724 * - ASUS P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2
Michael Karcherbfd89a52012-02-12 00:13:14 +00001725 * - TriGem Anaheim-3: socket370 + Intel 810 + ICH
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001726 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001727static int intel_ich_gpio22_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001728{
1729 return intel_ich_gpio_set(22, 1);
1730}
1731
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001732/*
1733 * Suited for:
Stefan Tauner716e0982011-07-25 20:38:52 +00001734 * - ASUS A8Jm (laptop): Intel 945 + ICH7
Michael Karcher14ab8d42011-08-25 14:06:50 +00001735 * - ASUS P5LP-LE used in ...
1736 * - HP Media Center m7270.fr Desktop PC as "Lithium-UL8E"
1737 * - Epson Endeavor MT7700
Stefan Tauner716e0982011-07-25 20:38:52 +00001738 */
1739static int intel_ich_gpio34_raise(void)
1740{
1741 return intel_ich_gpio_set(34, 1);
1742}
1743
1744/*
1745 * Suited for:
Stefan Taunerc6782182012-01-19 17:50:32 +00001746 * - AOpen i945GMx-VFX: Intel 945GM + ICH7-M used in ...
Paul Menzelac427b22012-02-16 21:07:07 +00001747 * - FSC ESPRIMO Q5010 (SMBIOS: D2544-B1)
Stefan Taunerc6782182012-01-19 17:50:32 +00001748 */
1749static int intel_ich_gpio38_raise(void)
1750{
1751 return intel_ich_gpio_set(38, 1);
1752}
1753
1754/*
1755 * Suited for:
Joshua Roysc73e2812011-07-09 19:46:53 +00001756 * - ASUS M6Ne (laptop): socket 479M (guessed) + Intel 855PM + ICH4-M
1757 */
1758static int intel_ich_gpio43_raise(void)
1759{
1760 return intel_ich_gpio_set(43, 1);
1761}
1762
1763/*
1764 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001765 * - HP Vectra VL400: 815 + ICH + PC87360
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001766 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001767static int board_hp_vl400(void)
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001768{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001769 int ret;
1770 ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */
1771 if (!ret)
Michael Karchercba52de2011-03-06 12:07:19 +00001772 ret = pc8736x_gpio_set(PC87360_ID, 0x09, 1); /* #WP ? */
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001773 if (!ret)
Michael Karchercba52de2011-03-06 12:07:19 +00001774 ret = pc8736x_gpio_set(PC87360_ID, 0x27, 1); /* #TBL */
1775 return ret;
1776}
1777
1778/*
1779 * Suited for:
1780 * - HP e-Vectra P2706T: 810E + ICH + PC87364
1781 */
1782static int board_hp_p2706t(void)
1783{
1784 int ret;
1785 ret = pc8736x_gpio_set(PC87364_ID, 0x25, 1);
1786 if (!ret)
1787 ret = pc8736x_gpio_set(PC87364_ID, 0x26, 1);
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001788 return ret;
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001789}
1790
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001791/*
Luc Verhaegen1265d8d2009-11-28 18:16:31 +00001792 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001793 * - Dell PowerEdge 1850: Intel PPGA604 + E7520 + ICH5R
1794 * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R
1795 * - ASRock 775i65G: Intel LGA 775 + 865G + ICH5
Uwe Hermann742999c2010-12-02 21:57:42 +00001796 * - MSI MS-6391 (845 Pro4): Intel Socket478 + 845 + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001797 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001798static int intel_ich_gpio23_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001799{
1800 return intel_ich_gpio_set(23, 1);
1801}
1802
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001803/*
1804 * Suited for:
Michael Karcher39dcdec2010-10-05 17:29:35 +00001805 * - GIGABYTE GA-6IEM: Intel Socket370 + i815 + ICH2
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001806 * - GIGABYTE GA-8IRML: Intel Socket478 + i845 + ICH2
Michael Karcherc7a1ffb2010-07-24 22:27:29 +00001807 */
1808static int intel_ich_gpio25_raise(void)
1809{
1810 return intel_ich_gpio_set(25, 1);
1811}
1812
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001813/*
1814 * Suited for:
1815 * - IBASE MB899: i945GM + ICH7
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001816 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001817static int intel_ich_gpio26_raise(void)
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001818{
1819 return intel_ich_gpio_set(26, 1);
1820}
1821
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001822/*
1823 * Suited for:
1824 * - P4SD-LA (HP OEM): i865 + ICH5
Joshua Roys9d9a1042011-06-13 16:59:01 +00001825 * - GIGABYTE GA-8IP775: 865P + ICH5
Michael Karcherc8613242010-08-13 12:49:01 +00001826 * - GIGABYTE GA-8PE667 Ultra 2: socket 478 + i845PE + ICH4
Maciej Pijanka6add0942011-06-09 20:59:30 +00001827 * - MSI MS-6788-40 (aka 848P Neo-V)
Michael Karcher87c90992010-07-24 11:03:48 +00001828 */
Idwer Vollering19dceac2010-07-24 18:47:45 +00001829static int intel_ich_gpio32_raise(void)
Michael Karcher87c90992010-07-24 11:03:48 +00001830{
1831 return intel_ich_gpio_set(32, 1);
1832}
1833
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001834/*
1835 * Suited for:
Joshua Roys7225ccd2011-05-18 01:32:16 +00001836 * - AOpen i975Xa-YDG: i975X + ICH7 + W83627EHF
1837 */
1838static int board_aopen_i975xa_ydg(void)
1839{
1840 int ret;
1841
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001842 /* Vendor BIOS ends up in LDN6... maybe the board enable is wrong,
Joshua Roys7225ccd2011-05-18 01:32:16 +00001843 * or perhaps it's not needed at all?
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001844 * The regs it tries to touch are 0xF0, 0xF1, 0xF2 which means if it
1845 * were in the right LDN, it would have to be GPIO1 or GPIO3.
Joshua Roys7225ccd2011-05-18 01:32:16 +00001846 */
1847/*
1848 ret = winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, x, 0)
1849 if (!ret)
1850*/
1851 ret = intel_ich_gpio_set(33, 1);
1852
1853 return ret;
1854}
1855
1856/*
1857 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001858 * - Acorp 6A815EPD: socket 370 + intel 815 + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001859 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001860static int board_acorp_6a815epd(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001861{
1862 int ret;
1863
1864 /* Lower Blocks Lock -- pin 7 of PLCC32 */
1865 ret = intel_ich_gpio_set(22, 1);
1866 if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */
1867 ret = intel_ich_gpio_set(23, 1);
1868
1869 return ret;
1870}
1871
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001872/*
1873 * Suited for:
1874 * - Kontron 986LCD-M: Socket478 + 915GM + ICH7R
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001875 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001876static int board_kontron_986lcd_m(void)
Stefan Reinauerac378972008-03-17 22:59:40 +00001877{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001878 int ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001879
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001880 ret = intel_ich_gpio_set(34, 1); /* #TBL */
1881 if (!ret)
1882 ret = intel_ich_gpio_set(35, 1); /* #WP */
Stefan Reinauerac378972008-03-17 22:59:40 +00001883
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001884 return ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001885}
1886
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001887/*
1888 * Suited for:
1889 * - Soyo SY-7VCA: Pro133A + VT82C686
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001890 */
Michael Karcher06477332010-03-19 22:49:09 +00001891static int via_apollo_gpo_set(int gpio, int raise)
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001892{
Michael Karcher06477332010-03-19 22:49:09 +00001893 struct pci_dev *dev;
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001894 uint32_t base, tmp;
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001895
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001896 /* VT82C686 power management */
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001897 dev = pci_dev_find(0x1106, 0x3057);
1898 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001899 msg_perr("\nERROR: VT82C686 PM device not found.\n");
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001900 return -1;
1901 }
1902
Sean Nelson316a29f2010-05-07 20:09:04 +00001903 msg_pdbg("\nVIA Apollo ACPI: %sing GPIO%02d.\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001904 raise ? "Rais" : "Dropp", gpio);
Michael Karcher06477332010-03-19 22:49:09 +00001905
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001906 /* Select GPO function on multiplexed pins. */
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001907 tmp = pci_read_byte(dev, 0x54);
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001908 switch (gpio) {
1909 case 0:
1910 tmp &= ~0x03;
1911 break;
1912 case 1:
1913 tmp |= 0x04;
1914 break;
1915 case 2:
1916 tmp |= 0x08;
1917 break;
1918 case 3:
1919 tmp |= 0x10;
1920 break;
Michael Karcher06477332010-03-19 22:49:09 +00001921 }
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001922 pci_write_byte(dev, 0x54, tmp);
1923
1924 /* PM IO base */
1925 base = pci_read_long(dev, 0x48) & 0x0000FF00;
1926
1927 /* Drop GPO0 */
Michael Karcher06477332010-03-19 22:49:09 +00001928 tmp = INL(base + 0x4C);
1929 if (raise)
1930 tmp |= 1U << gpio;
1931 else
1932 tmp &= ~(1U << gpio);
1933 OUTL(tmp, base + 0x4C);
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001934
1935 return 0;
1936}
1937
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001938/*
1939 * Suited for:
1940 * - abit VT6X4: Pro133x + VT82C686A
Mattias Mattssone3df96e2010-08-15 22:43:23 +00001941 * - abit VA6: Pro133x + VT82C686A
Michael Karcher187a46a2010-03-19 22:30:49 +00001942 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001943static int via_apollo_gpo4_lower(void)
Michael Karcher187a46a2010-03-19 22:30:49 +00001944{
1945 return via_apollo_gpo_set(4, 0);
1946}
1947
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001948/*
1949 * Suited for:
1950 * - Soyo SY-7VCA: Pro133A + VT82C686
Michael Karcher06477332010-03-19 22:49:09 +00001951 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001952static int via_apollo_gpo0_lower(void)
Michael Karcher06477332010-03-19 22:49:09 +00001953{
1954 return via_apollo_gpo_set(0, 0);
1955}
1956
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001957/*
Michael Karchera08d0f22011-07-25 17:25:24 +00001958 * Enable some GPIO pin on SiS southbridge and enables SIO flash writes.
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001959 *
1960 * Suited for:
1961 * - MSI 651M-L: SiS651 / SiS962
Michael Karchera08d0f22011-07-25 17:25:24 +00001962 * - GIGABYTE GA-8SIMLH
Michael Karcher9f9e6132010-01-09 17:36:06 +00001963 */
Michael Karchera08d0f22011-07-25 17:25:24 +00001964static int sis_gpio0_raise_and_w836xx_memw(void)
Michael Karcher9f9e6132010-01-09 17:36:06 +00001965{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001966 struct pci_dev *dev;
Uwe Hermann43959702010-03-13 17:28:29 +00001967 uint16_t base, temp;
Michael Karcher9f9e6132010-01-09 17:36:06 +00001968
1969 dev = pci_dev_find(0x1039, 0x0962);
1970 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001971 msg_perr("Expected south bridge not found\n");
Michael Karcher9f9e6132010-01-09 17:36:06 +00001972 return 1;
1973 }
1974
Michael Karcher9f9e6132010-01-09 17:36:06 +00001975 base = pci_read_word(dev, 0x74);
1976 temp = INW(base + 0x68);
1977 temp &= ~(1 << 0); /* Make pin output? */
Michael Karcher0435dfd2010-01-09 23:31:13 +00001978 OUTW(temp, base + 0x68);
Michael Karcher9f9e6132010-01-09 17:36:06 +00001979
1980 temp = INW(base + 0x64);
1981 temp |= (1 << 0); /* Raise output? */
1982 OUTW(temp, base + 0x64);
1983
1984 w836xx_memw_enable(0x2E);
1985
1986 return 0;
1987}
1988
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001989/*
Michael Gold6d52e472009-06-19 13:00:24 +00001990 * Find the runtime registers of an SMSC Super I/O, after verifying its
1991 * chip ID.
1992 *
1993 * Returns the base port of the runtime register block, or 0 on error.
1994 */
1995static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id,
1996 uint8_t logical_device)
1997{
1998 uint16_t rt_port = 0;
1999
2000 /* Verify the chip ID. */
Uwe Hermann1432a602009-06-28 23:26:37 +00002001 OUTB(0x55, sio_port); /* Enable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00002002 if (sio_read(sio_port, 0x20) != chip_id) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002003 msg_perr("\nERROR: SMSC Super I/O not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +00002004 goto out;
2005 }
2006
2007 /* If the runtime block is active, get its address. */
2008 sio_write(sio_port, 0x07, logical_device);
2009 if (sio_read(sio_port, 0x30) & 1) {
2010 rt_port = (sio_read(sio_port, 0x60) << 8)
2011 | sio_read(sio_port, 0x61);
2012 }
2013
2014 if (rt_port == 0) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002015 msg_perr("\nERROR: "
Michael Gold6d52e472009-06-19 13:00:24 +00002016 "Super I/O runtime interface not available.\n");
2017 }
2018out:
Uwe Hermann1432a602009-06-28 23:26:37 +00002019 OUTB(0xaa, sio_port); /* Disable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00002020 return rt_port;
2021}
2022
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002023/*
2024 * Disable write protection on the Mitac 6513WU. WP# on the FWH is
Michael Gold6d52e472009-06-19 13:00:24 +00002025 * connected to GP30 on the Super I/O, and TBL# is always high.
2026 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00002027static int board_mitac_6513wu(void)
Michael Gold6d52e472009-06-19 13:00:24 +00002028{
2029 struct pci_dev *dev;
2030 uint16_t rt_port;
2031 uint8_t val;
2032
2033 dev = pci_dev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */
2034 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002035 msg_perr("\nERROR: Intel 82801AA ISA bridge not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +00002036 return -1;
2037 }
2038
Uwe Hermann1432a602009-06-28 23:26:37 +00002039 rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa);
Michael Gold6d52e472009-06-19 13:00:24 +00002040 if (rt_port == 0)
2041 return -1;
2042
2043 /* Configure the GPIO pin. */
2044 val = INB(rt_port + 0x33); /* GP30 config */
Uwe Hermann1432a602009-06-28 23:26:37 +00002045 val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */
Michael Gold6d52e472009-06-19 13:00:24 +00002046 OUTB(val, rt_port + 0x33);
2047
2048 /* Disable write protection. */
2049 val = INB(rt_port + 0x4d); /* GP3 values */
Uwe Hermann1432a602009-06-28 23:26:37 +00002050 val |= 0x01; /* Set GP30 high. */
Michael Gold6d52e472009-06-19 13:00:24 +00002051 OUTB(val, rt_port + 0x4d);
2052
2053 return 0;
2054}
2055
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002056/*
2057 * Suited for:
Christoph Grenzd13a3942011-10-21 13:20:11 +00002058 * - abit AV8: Socket939 + K8T800Pro + VT8237
2059 */
2060static int board_abit_av8(void)
2061{
2062 uint8_t val;
2063
2064 /* Raise GPO pins GP22 & GP23 */
2065 val = INB(0x404E);
2066 val |= 0xC0;
2067 OUTB(val, 0x404E);
2068
2069 return 0;
2070}
2071
2072/*
2073 * Suited for:
Uwe Hermann45bd1442010-09-14 23:20:35 +00002074 * - ASUS A7V333: VIA KT333 + VT8233A + IT8703F
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002075 * - ASUS A7V8X: VIA KT400 + VT8235 + IT8703F
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002076 */
Uwe Hermann45bd1442010-09-14 23:20:35 +00002077static int it8703f_gpio51_raise(void)
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002078{
2079 uint16_t id, base;
2080 uint8_t tmp;
2081
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002082 /* Find the IT8703F. */
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002083 w836xx_ext_enter(0x2E);
2084 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
2085 w836xx_ext_leave(0x2E);
2086
2087 if (id != 0x8701) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002088 msg_perr("\nERROR: IT8703F Super I/O not found.\n");
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002089 return -1;
2090 }
2091
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002092 /* Get the GP567 I/O base. */
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002093 w836xx_ext_enter(0x2E);
2094 sio_write(0x2E, 0x07, 0x0C);
2095 base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
2096 w836xx_ext_leave(0x2E);
2097
2098 if (!base) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002099 msg_perr("\nERROR: Failed to read IT8703F Super I/O GPIO"
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002100 " Base.\n");
2101 return -1;
2102 }
2103
2104 /* Raise GP51. */
2105 tmp = INB(base);
2106 tmp |= 0x02;
2107 OUTB(tmp, base);
2108
2109 return 0;
2110}
2111
Luc Verhaegen72272912009-09-01 21:22:23 +00002112/*
Joshua Roysa2f37222011-11-14 13:00:12 +00002113 * General routine for raising/dropping GPIO lines on the ITE IT87xx.
Luc Verhaegen72272912009-09-01 21:22:23 +00002114 */
Joshua Roysa2f37222011-11-14 13:00:12 +00002115static int it87_gpio_set(unsigned int gpio, int raise)
Luc Verhaegen72272912009-09-01 21:22:23 +00002116{
Joshua Roysa2f37222011-11-14 13:00:12 +00002117 int allowed, sio;
Luc Verhaegen72272912009-09-01 21:22:23 +00002118 unsigned int port;
Joshua Roysa2f37222011-11-14 13:00:12 +00002119 uint16_t base, sioport;
Luc Verhaegen72272912009-09-01 21:22:23 +00002120 uint8_t tmp;
2121
Joshua Roysa2f37222011-11-14 13:00:12 +00002122 /* IT87 GPIO configuration table */
2123 static const struct it87cfg {
2124 uint16_t id;
2125 uint8_t base_reg;
2126 uint32_t bank0;
2127 uint32_t bank1;
2128 uint32_t bank2;
2129 } it87_gpio_table[] = {
2130 {0x8712, 0x62, 0xCFF3FC00, 0x00FCFF3F, 0},
2131 {0x8718, 0x62, 0xCFF37C00, 0xF3FCDF3F, 0x0000000F},
2132 {0, 0, 0, 0, 0} /* end marker */
2133 };
2134 const struct it87cfg *cfg = NULL;
Luc Verhaegen72272912009-09-01 21:22:23 +00002135
Joshua Roysa2f37222011-11-14 13:00:12 +00002136 /* Find the Super I/O in the probed list */
2137 for (sio = 0; sio < superio_count; sio++) {
2138 int i;
2139 if (superios[sio].vendor != SUPERIO_VENDOR_ITE)
2140 continue;
2141
2142 /* Is this device in our list? */
2143 for (i = 0; it87_gpio_table[i].id; i++)
2144 if (superios[sio].model == it87_gpio_table[i].id) {
2145 cfg = &it87_gpio_table[i];
2146 goto found;
2147 }
2148 }
2149
2150 if (cfg == NULL) {
2151 msg_perr("\nERROR: No IT87 Super I/O GPIO configuration "
2152 "found.\n");
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002153 return -1;
Luc Verhaegen72272912009-09-01 21:22:23 +00002154 }
2155
Joshua Roysa2f37222011-11-14 13:00:12 +00002156found:
2157 /* Check whether the gpio is allowed. */
2158 if (gpio < 32)
2159 allowed = (cfg->bank0 >> gpio) & 0x01;
2160 else if (gpio < 64)
2161 allowed = (cfg->bank1 >> (gpio - 32)) & 0x01;
2162 else if (gpio < 96)
2163 allowed = (cfg->bank2 >> (gpio - 64)) & 0x01;
2164 else
2165 allowed = 0;
Luc Verhaegen72272912009-09-01 21:22:23 +00002166
Joshua Roysa2f37222011-11-14 13:00:12 +00002167 if (!allowed) {
2168 msg_perr("\nERROR: IT%02X does not allow setting GPIO%02u.\n",
2169 cfg->id, gpio);
Luc Verhaegen72272912009-09-01 21:22:23 +00002170 return -1;
2171 }
2172
Joshua Roysa2f37222011-11-14 13:00:12 +00002173 /* Read the Simple I/O Base Address Register */
2174 sioport = superios[sio].port;
2175 enter_conf_mode_ite(sioport);
2176 sio_write(sioport, 0x07, 0x07);
2177 base = (sio_read(sioport, cfg->base_reg) << 8) |
2178 sio_read(sioport, cfg->base_reg + 1);
2179 exit_conf_mode_ite(sioport);
Luc Verhaegen72272912009-09-01 21:22:23 +00002180
2181 if (!base) {
Joshua Roysa2f37222011-11-14 13:00:12 +00002182 msg_perr("\nERROR: Failed to read IT87 Super I/O GPIO Base.\n");
Luc Verhaegen72272912009-09-01 21:22:23 +00002183 return -1;
2184 }
2185
Joshua Roysa2f37222011-11-14 13:00:12 +00002186 msg_pdbg("Using IT87 GPIO base 0x%04x\n", base);
2187
2188 port = gpio / 10 - 1;
2189 gpio %= 10;
2190
2191 /* set GPIO. */
Luc Verhaegen72272912009-09-01 21:22:23 +00002192 tmp = INB(base + port);
2193 if (raise)
Joshua Roysa2f37222011-11-14 13:00:12 +00002194 tmp |= 1 << gpio;
Luc Verhaegen72272912009-09-01 21:22:23 +00002195 else
Joshua Roysa2f37222011-11-14 13:00:12 +00002196 tmp &= ~(1 << gpio);
Luc Verhaegen72272912009-09-01 21:22:23 +00002197 OUTB(tmp, base + port);
2198
2199 return 0;
2200}
2201
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002202/*
Russ Dillbd622d12010-03-09 16:57:06 +00002203 * Suited for:
Joshua Roys8ca42552011-11-19 19:31:17 +00002204 * - ASUS A7N8X-VM/400: NVIDIA nForce2 IGP2 + IT8712F
2205 */
2206static int it8712f_gpio12_raise(void)
2207{
2208 return it87_gpio_set(12, 1);
2209}
2210
2211/*
2212 * Suited for:
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00002213 * - ASUS A7V600-X: VIA KT600 + VT8237 + IT8712F
2214 * - ASUS A7V8X-X: VIA KT400 + VT8235 + IT8712F
Luc Verhaegen72272912009-09-01 21:22:23 +00002215 */
Joshua Roysa2f37222011-11-14 13:00:12 +00002216static int it8712f_gpio31_raise(void)
Luc Verhaegen72272912009-09-01 21:22:23 +00002217{
Joshua Roysa2f37222011-11-14 13:00:12 +00002218 return it87_gpio_set(32, 1);
2219}
2220
2221/*
2222 * Suited for:
2223 * - ASUS P5N-D: NVIDIA MCP51 + IT8718F
2224 * - ASUS P5N-E SLI: NVIDIA MCP51 + IT8718F
2225 */
2226static int it8718f_gpio63_raise(void)
2227{
2228 return it87_gpio_set(63, 1);
Luc Verhaegen72272912009-09-01 21:22:23 +00002229}
2230
Ingo Feldschmid8a0f9b02012-01-31 06:51:56 +00002231/*
2232 * Suited for all boards with ambiguous DMI chassis information, which should be
2233 * whitelisted because they are known to work:
2234 * - MSC Q7 Tunnel Creek Module (Q7-TCTC)
2235 */
2236static int p2_not_a_laptop(void)
2237{
2238 /* label this board as not a laptop */
2239 is_laptop = 0;
2240 msg_pdbg("Laptop detection overridden by P2 board enable.\n");
2241 return 0;
2242}
2243
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00002244#endif
2245
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002246/*
Uwe Hermannd0e347d2009-10-06 13:00:00 +00002247 * Below is the list of boards which need a special "board enable" code in
2248 * flashrom before their ROM chip can be accessed/written to.
2249 *
2250 * NOTE: Please add boards that _don't_ need such enables or don't work yet
2251 * to the respective tables in print.c. Thanks!
2252 *
Uwe Hermannffec5f32007-08-23 16:08:21 +00002253 * We use 2 sets of IDs here, you're free to choose which is which. This
2254 * is to provide a very high degree of certainty when matching a board on
2255 * the basis of subsystem/card IDs. As not every vendor handles
2256 * subsystem/card IDs in a sane manner.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002257 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00002258 * Keep the second set NULLed if it should be ignored. Keep the subsystem IDs
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00002259 * NULLed if they don't identify the board fully and if you can't use DMI.
2260 * But please take care to provide an as complete set of pci ids as possible;
2261 * autodetection is the preferred behaviour and we would like to make sure that
2262 * matches are unique.
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00002263 *
Michael Karcher6701ee82010-01-20 14:14:11 +00002264 * If PCI IDs are not sufficient for board matching, the match can be further
2265 * constrained by a string that has to be present in the DMI database for
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00002266 * the baseboard or the system entry. The pattern is matched by case sensitive
Michael Karcher6701ee82010-01-20 14:14:11 +00002267 * substring match, unless it is anchored to the beginning (with a ^ in front)
2268 * or the end (with a $ at the end). Both anchors may be specified at the
2269 * same time to match the full field.
2270 *
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00002271 * When a board is matched through DMI, the first and second main PCI IDs
2272 * and the first subsystem PCI ID have to match as well. If you specify the
2273 * first subsystem ID as 0x0:0x0, the DMI matching code expects that the
2274 * subsystem ID of that device is indeed zero.
2275 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00002276 * The coreboot ids are used two fold. When running with a coreboot firmware,
2277 * the ids uniquely matches the coreboot board identification string. When a
2278 * legacy bios is installed and when autodetection is not possible, these ids
Carl-Daniel Hailfinger2d927fb2012-01-04 00:48:27 +00002279 * can be used to identify the board through the -p internal:mainboard=
2280 * programmer parameter.
Luc Verhaegenc5210162009-04-20 12:38:17 +00002281 *
2282 * When a board is identified through its coreboot ids (in both cases), the
2283 * main pci ids are still required to match, as a safeguard.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002284 */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002285
Uwe Hermanndeeebe22009-05-08 16:23:34 +00002286/* Please keep this list alphabetically ordered by vendor/board name. */
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002287const struct board_match board_matches[] = {
Uwe Hermann5ab88892009-06-21 20:50:22 +00002288
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002289 /* first pci-id set [4], second pci-id set [4], dmi identifier, coreboot id [2], phase, vendor name, board name max_rom_... OK? flash enable */
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00002290#if defined(__i386__) || defined(__x86_64__)
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002291 {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, P3, "abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise},
Christoph Grenzd13a3942011-10-21 13:20:11 +00002292 {0x1106, 0x0282, 0x147B, 0x1415, 0x1106, 0x3227, 0x147B, 0x1415, "^AV8 ", NULL, NULL, P3, "abit", "AV8", 0, OK, board_abit_av8},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002293 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^i440BX-W977 (BM6)$", NULL, NULL, P3, "abit", "BM6", 0, OK, intel_piix4_gpo26_lower},
2294 {0x8086, 0x24d3, 0x147b, 0x1014, 0x8086, 0x2578, 0x147b, 0x1014, NULL, NULL, NULL, P3, "abit", "IC7", 0, NT, intel_ich_gpio23_raise},
2295 {0x8086, 0x2930, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, P3, "abit", "IP35", 0, OK, intel_ich_gpio16_raise},
2296 {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, P3, "abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise},
2297 {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, P3, "abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower},
2298 {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, P3, "abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise},
Paul Menzelac427b22012-02-16 21:07:07 +00002299 {0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0260, 0x147b, 0x1c26, NULL, NULL, NULL, P3, "abit", "NF-M2 nView", 0, OK, nvidia_mcp_gpio4_lower},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002300 {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, "(VA6)$", NULL, NULL, P3, "abit", "VA6", 0, OK, via_apollo_gpo4_lower},
2301 {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", P3, "abit", "VT6X4", 0, OK, via_apollo_gpo4_lower},
2302 {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, P3, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd},
2303 {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", P3, "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e},
2304 {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, P3, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e},
2305 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", P3, "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x},
2306 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", P3, "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x},
Stefan Taunerc6782182012-01-19 17:50:32 +00002307 {0x8086, 0x27b9, 0xa0a0, 0x0632, 0x8086, 0x27da, 0xa0a0, 0x0632, NULL, NULL, NULL, P3, "AOpen", "i945GMx-VFX", 0, OK, intel_ich_gpio38_raise},
Joshua Roys7225ccd2011-05-18 01:32:16 +00002308 {0x8086, 0x277c, 0xa0a0, 0x060b, 0x8086, 0x27da, 0xa0a0, 0x060b, NULL, NULL, NULL, P3, "AOpen", "i975Xa-YDG", 0, OK, board_aopen_i975xa_ydg},
Joshua Roysea3aed02011-11-16 22:08:11 +00002309 {0x8086, 0x27b8, 0x1849, 0x27b8, 0x8086, 0x27da, 0x1849, 0x27da, "^ConRoeXFire-eSATA2", NULL, NULL, P3, "ASRock", "ConRoeXFire-eSATA2", 0, OK, intel_ich_gpio16_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002310 {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41 $", NULL, NULL, P3, "ASRock", "K7S41", 0, OK, w836xx_memw_enable_2e},
Pawel Rozanski1d233072011-06-19 16:52:48 +00002311 {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41GX$", NULL, NULL, P3, "ASRock", "K7S41GX", 0, OK, w836xx_memw_enable_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002312 {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, P3, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise},
2313 {0x8086, 0x2570, 0x1849, 0x2570, 0x8086, 0x24d3, 0x1849, 0x24d0, NULL, NULL, NULL, P3, "ASRock", "775i65G", 0, OK, intel_ich_gpio23_raise},
Joshua Roys8ca42552011-11-19 19:31:17 +00002314 {0x10DE, 0x0060, 0x1043, 0x80AD, 0x10DE, 0x01E0, 0x1043, 0x80C0, NULL, NULL, NULL, P3, "ASUS", "A7N8X-VM/400", 0, OK, it8712f_gpio12_raise},
Joshua Roysa2f37222011-11-14 13:00:12 +00002315 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, P3, "ASUS", "A7V600-X", 0, OK, it8712f_gpio31_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002316 {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, P3, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e},
2317 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V8X", 0, OK, it8703f_gpio51_raise},
2318 {0x1106, 0x3099, 0x1043, 0x807F, 0x1106, 0x3147, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V333", 0, OK, it8703f_gpio51_raise},
Joshua Roysa2f37222011-11-14 13:00:12 +00002319 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, P3, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio31_raise},
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00002320 {0x1002, 0x4372, 0x103c, 0x2a26, 0x1002, 0x4377, 0x103c, 0x2a26, NULL, NULL, NULL, P3, "ASUS", "A8AE-LE", 0, OK, amd_sbxxx_gpio9_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002321 {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, P3, "ASUS", "A8Jm", 0, NT, intel_ich_gpio34_raise},
Stefan Taunera9cbbac2011-08-07 13:17:20 +00002322 {0x10DE, 0x0260, 0x103C, 0x2A34, 0x10DE, 0x0264, 0x103C, 0x2A34, "NODUSM3", NULL, NULL, P3, "ASUS", "A8M2N-LA (NodusM3-GL8E)", 0, OK, nvidia_mcp_gpio0_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002323 {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI2L", NULL, NULL, P3, "ASUS", "A8N-LA (Nagami-GL8E)", 0, OK, nvidia_mcp_gpio0_raise},
Stefan Tauner2414e092011-08-06 16:16:45 +00002324 {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, "^A8N-SLI DELUXE", NULL, NULL, P3, "ASUS", "A8N-SLI Deluxe", 0, NT, board_shuttle_fn25},
Stefan Taunerff80e682011-07-20 16:34:18 +00002325 {0x10de, 0x0264, 0x1043, 0x81bc, 0x10de, 0x02f0, 0x1043, 0x81cd, NULL, NULL, NULL, P3, "ASUS", "A8N-VM CSM", 0, OK, w83627ehf_gpio22_raise_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002326 {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, P3, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise},
2327 {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, P3, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise},
Joshua Roysc73e2812011-07-09 19:46:53 +00002328 {0x8086, 0x24cc, 0, 0, 0x8086, 0x24c3, 0x1043, 0x1869, "^M6Ne$", NULL, NULL, P3, "ASUS", "M6Ne", 0, NT, intel_ich_gpio43_raise},
Joshua Roysd708fad2012-02-17 14:51:15 +00002329 {0x8086, 0x7180, 0, 0, 0x8086, 0x7110, 0, 0, "^OPLX-M$", NULL, NULL, P3, "ASUS", "OPLX-M", 0, NT, intel_piix4_gpo18_lower},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002330 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^P2B-N$", NULL, NULL, P3, "ASUS", "P2B-N", 0, OK, intel_piix4_gpo18_lower},
2331 {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, P3, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise},
2332 {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, P3, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise},
2333 {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, P3, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise},
Joshua Roysa5f5a152011-11-15 08:08:15 +00002334 {0x8086, 0x2560, 0x103C, 0x2A00, 0x8086, 0x24C3, 0x103C, 0x2A01, "^Guppy", NULL, NULL, P3, "ASUS", "P4GV-LA (Guppy)", 0, OK, intel_ich_gpio21_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002335 {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, P3, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
2336 {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D5, 0x1043, 0x80F3, NULL, NULL, NULL, P3, "ASUS", "P4P800", 0, NT, intel_ich_gpio21_raise},
Sylvain "ythier" Hitier3093f8f2011-09-03 11:22:27 +00002337 {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D3, 0x1043, 0x80A6, "^P4P800-E$", NULL, NULL, P3, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002338 {0x8086, 0x2570, 0x1043, 0x80A5, 0x8086, 0x24d0, 0, 0, NULL, NULL, NULL, P3, "ASUS", "P4P800-VM", 0, OK, intel_ich_gpio21_raise},
2339 {0x1039, 0x0651, 0x1043, 0x8081, 0x1039, 0x0962, 0, 0, NULL, NULL, NULL, P3, "ASUS", "P4SC-E", 0, OK, it8707f_write_enable_2e},
2340 {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, P3, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise},
2341 {0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x5513, 0x1043, 0x8087, NULL, NULL, NULL, P3, "ASUS", "P4S800-MX", 512, OK, w836xx_memw_enable_2e},
2342 {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", P3, "ASUS", "P5A", 0, OK, board_asus_p5a},
Stefan Tauner027e0182012-05-02 19:48:21 +00002343 {0x8086, 0x27b8, 0x1043, 0x819e, 0x8086, 0x29f0, 0x1043, 0x82a5, "^P5BV-R$", NULL, NULL, P3, "ASUS", "P5BV-R", 0, OK, intel_ich_gpio20_raise},
Stefan Taunera4f14472011-10-22 22:01:09 +00002344 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, "^P5GD1 PRO$", NULL, NULL, P3, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise},
2345 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, "^P5GD1-VM$", NULL, NULL, P3, "ASUS", "P5GD1-VM/S", 0, OK, intel_ich_gpio21_raise},
2346 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, P3, "ASUS", "P5GD1(-VM)", 0, NT, intel_ich_gpio21_raise},
Joshua Roys1fd4f9e2011-08-11 05:47:32 +00002347 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GD2-Premium$", NULL, NULL, P3, "ASUS", "P5GD2 Premium", 0, OK, intel_ich_gpio21_raise},
Stefan Taunera4f14472011-10-22 22:01:09 +00002348 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GDC-V$", NULL, NULL, P3, "ASUS", "P5GDC-V Deluxe", 0, OK, intel_ich_gpio21_raise},
2349 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GDC$", NULL, NULL, P3, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise},
2350 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, P3, "ASUS", "P5GD2/C variants", 0, NT, intel_ich_gpio21_raise},
Michael Karcher14ab8d42011-08-25 14:06:50 +00002351 {0x8086, 0x27b8, 0x103c, 0x2a22, 0x8086, 0x2770, 0x103c, 0x2a22, "^LITHIUM$", NULL, NULL, P3, "ASUS", "P5LP-LE (Lithium-UL8E)",0, OK, intel_ich_gpio34_raise},
2352 {0x8086, 0x27b8, 0x1043, 0x2a22, 0x8086, 0x2770, 0x1043, 0x2a22, "^P5LP-LE$", NULL, NULL, P3, "ASUS", "P5LP-LE (Epson OEM)", 0, OK, intel_ich_gpio34_raise},
Joshua Roys1fd4f9e2011-08-11 05:47:32 +00002353 {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, NT, intel_ich_gpio16_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002354 {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, P3, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise},
Joshua Roysa2f37222011-11-14 13:00:12 +00002355 {0x10DE, 0x0260, 0x1043, 0x81BC, 0x10DE, 0x026C, 0x1043, 0x829E, "^P5N-D$", NULL, NULL, P3, "ASUS", "P5N-D", 0, OK, it8718f_gpio63_raise},
2356 {0x10DE, 0x0260, 0x1043, 0x81BC, 0x10DE, 0x026C, 0x1043, 0x8249, "^P5N-E SLI$",NULL, NULL, P3, "ASUS", "P5N-E SLI", 0, NT, it8718f_gpio63_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002357 {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, P3, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise},
Stefan Taunerded71e52012-03-10 19:22:13 +00002358 {0x8086, 0x2443, 0x1043, 0x8027, 0x8086, 0x1130, 0x1043, 0x8027, NULL, NULL, NULL, P3, "ASUS", "TUSL2-C", 0, NT, intel_ich_gpio21_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002359 {0x10b7, 0x9055, 0x1028, 0x0082, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Dell", "OptiPlex GX1", 0, OK, intel_piix4_gpo30_lower},
2360 {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, P3, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise},
2361 {0x10de, 0x03ea, 0x1019, 0x2602, 0x10de, 0x03e0, 0x1019, 0x2602, NULL, NULL, NULL, P3, "Elitegroup", "GeForce6100SM-M", 0, OK, board_ecs_geforce6100sm_m},
2362 {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, P3, "Elitegroup", "K7VTA3", 256, OK, NULL},
2363 {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, P3, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e},
Stefan Tauneraf4b1582011-08-06 16:16:33 +00002364 {0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, "8NPA7I", NULL, NULL, P3, "EPoX", "EP-8NPA7I", 0, OK, nvidia_mcp_gpio4_raise},
2365 {0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, "9NPA7I", NULL, NULL, P3, "EPoX", "EP-9NPA7I", 0, OK, nvidia_mcp_gpio4_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002366 {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, P3, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise},
2367 {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", P3, "EPoX", "EP-BX3", 0, NT, intel_piix4_gpo22_raise},
2368 {0x10de, 0x02f0, 0x105b, 0x0d01, 0x10de, 0x0264, 0x105b, 0x0d01, NULL, NULL, NULL, P3, "Foxconn", "6150K8MD-8EKRSH", 0, NT, nvidia_mcp_gpio2_raise},
2369 {0x8086, 0x2443, 0x8086, 0x2442, 0x8086, 0x1130, 0x8086, 0x1130, "^6IEM ", NULL, NULL, P3, "GIGABYTE", "GA-6IEM", 0, NT, intel_ich_gpio25_raise},
2370 {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-7ZM", 512, OK, NULL},
Joshua Roys9d9a1042011-06-13 16:59:01 +00002371 {0x8086, 0x2570, 0x1458, 0x2570, 0x8086, 0x24d0, 0, 0, "^8IP775/-G$",NULL, NULL, P3, "GIGABYTE", "GA-8IP775", 0, OK, intel_ich_gpio32_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002372 {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise},
2373 {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise},
Stefan Tauner716e0982011-07-25 20:38:52 +00002374 {0x1039, 0x0651, 0x1039, 0x0651, 0x1039, 0x7002, 0x1458, 0x5004, "^GA-8SIMLH$",NULL, NULL, P3, "GIGABYTE", "GA-8SIMLH", 0, OK, sis_gpio0_raise_and_w836xx_memw},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002375 {0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise},
2376 {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise},
Idwer Volleringd8a00a02011-06-13 16:58:54 +00002377 {0x10de, 0x00e4, 0x1458, 0x0c11, 0x10de, 0x00e0, 0x1458, 0x0c11, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8NS Pro-939", 0, NT, nvidia_mcp_gpio0a_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002378 {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise},
Idwer Volleringd8a00a02011-06-13 16:58:54 +00002379 {0x8086, 0x2415, 0x103c, 0x1250, 0x10b7, 0x9200, 0x103c, 0x1247, NULL, NULL, NULL, P3, "HP", "e-Vectra P2706T", 0, OK, board_hp_p2706t},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002380 {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", P3, "HP", "ProLiant DL145 G3", 0, OK, board_hp_dl145_g3_enable},
2381 {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", P3, "HP", "ProLiant DL165 G6", 0, OK, board_hp_dl165_g6_enable},
2382 {0x8086, 0x2580, 0x103c, 0x2a08, 0x8086, 0x2640, 0x103c, 0x2a0a, NULL, NULL, NULL, P3, "HP", "Puffer2-UL8E", 0, OK, intel_ich_gpio18_raise},
Idwer Volleringd8a00a02011-06-13 16:58:54 +00002383 {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, P3, "HP", "Vectra VL400", 0, OK, board_hp_vl400},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002384 {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, P3, "HP", "Vectra VL420 SFF", 0, OK, intel_ich_gpio22_raise},
2385 {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, "hp", "xw9400", P3, "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise},
2386 {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", P3, "IBASE", "MB899", 0, OK, intel_ich_gpio26_raise},
2387 {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, P3, "IBM", "x3455", 0, OK, board_ibm_x3455},
2388 {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, P3, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi},
2389 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, P3, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower},
2390 {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, NULL, "iwill", "dk8_htx", P3, "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e},
2391 {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", P3, "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m},
2392 {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, P3, "Mitac", "6513WU", 0, OK, board_mitac_6513wu},
Ingo Feldschmid8a0f9b02012-01-31 06:51:56 +00002393 {0x8086, 0x8186, 0x8086, 0x8186, 0x8086, 0x8800, 0x0000, 0x0000, "^MSC Vertriebs GmbH$", NULL, NULL, P2, "MSC", "Q7-TCTC", 0, OK, p2_not_a_laptop},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002394 {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, P3, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, /* TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html. */
2395 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^MS-6163 (i440BX)$", NULL, NULL, P3, "MSI", "MS-6163 (MS-6163 Pro)", 0, OK, intel_piix4_gpo14_raise},
2396 {0x1039, 0x0745, 0, 0, 0x1039, 0x0018, 0, 0, "^MS-6561", NULL, NULL, P3, "MSI", "MS-6561 (745 Ultra)", 0, OK, w836xx_memw_enable_2e},
2397 {0x8086, 0x2560, 0x1462, 0x5770, 0x8086, 0x2562, 0x1462, 0x5778, NULL, NULL, NULL, P3, "MSI", "MS-6577 (Xenon)", 0, OK, w83627hf_gpio25_raise_2e},
2398 {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, P3, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v},
2399 {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, P3, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio44_raise_2e},
2400 {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, P3, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v},
2401 {0x1106, 0x3148, 0 , 0 , 0x1106, 0x3177, 0 , 0 , NULL, "msi", "ms6787", P3, "MSI", "MS-6787 (P4MAM-V/P4MAM-L)", 0, OK, w836xx_memw_enable_2e},
Maciej Pijanka6add0942011-06-09 20:59:30 +00002402 {0x8086, 0x24d3, 0x1462, 0x7880, 0x8086, 0x2570, 0, 0, NULL, NULL, NULL, P3, "MSI", "MS-6788-040 (848P NeoV)", 0, OK, intel_ich_gpio32_raise},
Michael Karchera08d0f22011-07-25 17:25:24 +00002403 {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, P3, "MSI", "MS-7005 (651M-L)", 0, OK, sis_gpio0_raise_and_w836xx_memw},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002404 {0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, P3, "MSI", "MS-7025 (K8N Neo2 Platinum)", 0, OK, nvidia_mcp_gpio0c_raise},
2405 {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, P3, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise},
2406 {0x8086, 0x244b, 0x1462, 0x3910, 0x8086, 0x2442, 0x1462, 0x3910, NULL, NULL, NULL, P3, "MSI", "MS-6391 (845 Pro4)", 0, OK, intel_ich_gpio23_raise},
2407 {0x1106, 0x3149, 0x1462, 0x7061, 0x1106, 0x3227, 0, 0, NULL, NULL, NULL, P3, "MSI", "MS-7061 (KM4M-V/KM4AM-V)", 0, OK, w836xx_memw_enable_2e},
2408 {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", P3, "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio44_raise_4e},
2409 {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, P3, "MSI", "MS-7207 (K8NGM2-L)", 0, NT, nvidia_mcp_gpio2_raise},
2410 {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0},
2411 {0x8086, 0x24d3, 0x144d, 0xb025, 0x8086, 0x1050, 0x144d, 0xb025, NULL, NULL, NULL, P3, "Samsung", "Polaris 32", 0, OK, intel_ich_gpio21_raise},
2412 {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", P3, "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e},
2413 {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, P3, "Shuttle", "AK38N", 256, OK, NULL},
2414 {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, P3, "Shuttle", "FN25", 0, OK, board_shuttle_fn25},
2415 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, P3, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower},
Joshua Roysb992d342011-11-02 14:31:18 +00002416 {0x10de, 0x0364, 0x108e, 0x6676, 0x10de, 0x0369, 0x108e, 0x6676, "^Sun Ultra 40 M2", NULL, NULL, P3, "Sun", "Ultra 40 M2", 0, OK, board_sun_ultra_40_m2},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002417 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, P3, "Tekram", "P6Pro-A5", 256, OK, NULL},
2418 {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, P3, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e},
Michael Karcherbfd89a52012-02-12 00:13:14 +00002419 {0x8086, 0x7120, 0x109f, 0x3157, 0x8086, 0x2410, 0, 0, NULL, NULL, NULL, P3, "TriGem", "Anaheim-3", 0, OK, intel_ich_gpio22_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002420 {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, P3, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e},
2421 {0x1106, 0x0259, 0x1106, 0xAA07, 0x1106, 0x3227, 0x1106, 0xAA07, NULL, NULL, NULL, P3, "VIA", "EPIA EK", 0, NT, via_vt823x_gpio9_raise},
2422 {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, P3, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise},
2423 {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, P3, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise},
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00002424#endif
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002425 { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, P3, NULL, NULL, 0, NT, NULL}, /* end marker */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002426};
2427
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002428/*
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +00002429 * Match boards on coreboot table gathered vendor and part name.
Uwe Hermannffec5f32007-08-23 16:08:21 +00002430 * Require main PCI IDs to match too as extra safety.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002431 */
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002432static const struct board_match *board_match_cbname(const char *vendor,
2433 const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002434{
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002435 const struct board_match *board = board_matches;
2436 const struct board_match *partmatch = NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002437
Uwe Hermanna93045c2009-05-09 00:47:04 +00002438 for (; board->vendor_name; board++) {
Uwe Hermann394131e2008-10-18 21:14:13 +00002439 if (vendor && (!board->lb_vendor
2440 || strcasecmp(board->lb_vendor, vendor)))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002441 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002442
Peter Stuge0b9c5f32008-07-02 00:47:30 +00002443 if (!board->lb_part || strcasecmp(board->lb_part, part))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002444 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002445
Uwe Hermanna7e05482007-05-09 10:17:44 +00002446 if (!pci_dev_find(board->first_vendor, board->first_device))
2447 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002448
Uwe Hermanna7e05482007-05-09 10:17:44 +00002449 if (board->second_vendor &&
Uwe Hermann394131e2008-10-18 21:14:13 +00002450 !pci_dev_find(board->second_vendor, board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002451 continue;
Peter Stuge6b53fed2008-01-27 16:21:21 +00002452
2453 if (vendor)
2454 return board;
2455
2456 if (partmatch) {
2457 /* a second entry has a matching part name */
Sean Nelson316a29f2010-05-07 20:09:04 +00002458 msg_pinfo("AMBIGUOUS BOARD NAME: %s\n", part);
2459 msg_pinfo("At least vendors '%s' and '%s' match.\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002460 partmatch->lb_vendor, board->lb_vendor);
Carl-Daniel Hailfinger2d927fb2012-01-04 00:48:27 +00002461 msg_perr("Please use the full -p internal:mainboard="
2462 "vendor:part syntax.\n");
Peter Stuge6b53fed2008-01-27 16:21:21 +00002463 return NULL;
2464 }
2465 partmatch = board;
Uwe Hermanna7e05482007-05-09 10:17:44 +00002466 }
Uwe Hermann372eeb52007-12-04 21:49:06 +00002467
Peter Stuge6b53fed2008-01-27 16:21:21 +00002468 if (partmatch)
2469 return partmatch;
2470
Carl-Daniel Hailfingerbc25f942009-07-30 13:30:17 +00002471 if (!partvendor_from_cbtable) {
2472 /* Only warn if the mainboard type was not gathered from the
2473 * coreboot table. If it was, the coreboot implementor is
2474 * expected to fix flashrom, too.
2475 */
Carl-Daniel Hailfinger2d927fb2012-01-04 00:48:27 +00002476 msg_perr("\nUnknown vendor:board from -p internal:mainboard="
2477 " programmer parameter:\n%s:%s\n\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002478 vendor, part);
Carl-Daniel Hailfingerbc25f942009-07-30 13:30:17 +00002479 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00002480 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002481}
2482
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002483/*
Uwe Hermannffec5f32007-08-23 16:08:21 +00002484 * Match boards on PCI IDs and subsystem IDs.
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002485 * Second set of IDs can be either main+subsystem IDs, main IDs or no IDs.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002486 */
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002487const static struct board_match *board_match_pci_ids(enum board_match_phase phase)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002488{
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002489 const struct board_match *board = board_matches;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002490
Uwe Hermanna93045c2009-05-09 00:47:04 +00002491 for (; board->vendor_name; board++) {
Michael Karcher2eab70d2010-02-04 10:58:50 +00002492 if ((!board->first_card_vendor || !board->first_card_device) &&
2493 !board->dmi_pattern)
Uwe Hermanna7e05482007-05-09 10:17:44 +00002494 continue;
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002495 if (board->phase != phase)
2496 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002497
Uwe Hermanna7e05482007-05-09 10:17:44 +00002498 if (!pci_card_find(board->first_vendor, board->first_device,
Uwe Hermann394131e2008-10-18 21:14:13 +00002499 board->first_card_vendor,
2500 board->first_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002501 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002502
Uwe Hermanna7e05482007-05-09 10:17:44 +00002503 if (board->second_vendor) {
2504 if (board->second_card_vendor) {
2505 if (!pci_card_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00002506 board->second_device,
2507 board->second_card_vendor,
2508 board->second_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002509 continue;
2510 } else {
2511 if (!pci_dev_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00002512 board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002513 continue;
2514 }
2515 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002516
Michael Karcher6701ee82010-01-20 14:14:11 +00002517 if (board->dmi_pattern) {
2518 if (!has_dmi_support) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002519 msg_perr("WARNING: Can't autodetect %s %s,"
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002520 " DMI info unavailable.\n",
2521 board->vendor_name, board->board_name);
Michael Karcher6701ee82010-01-20 14:14:11 +00002522 continue;
2523 } else {
2524 if (!dmi_match(board->dmi_pattern))
2525 continue;
2526 }
2527 }
2528
Uwe Hermanna7e05482007-05-09 10:17:44 +00002529 return board;
2530 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002531
Uwe Hermanna7e05482007-05-09 10:17:44 +00002532 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002533}
2534
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002535static int unsafe_board_handler(const struct board_match *board)
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002536{
2537 if (!board)
2538 return 1;
2539
2540 if (board->status == OK)
2541 return 0;
2542
2543 if (!force_boardenable) {
2544 msg_pinfo("WARNING: Your mainboard is %s %s, but the mainboard-specific\n"
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002545 "code has not been tested, and thus will not be executed by default.\n"
2546 "Depending on your hardware environment, erasing, writing or even probing\n"
2547 "can fail without running the board specific code.\n\n"
2548 "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n"
2549 "\"internal programmer\") for details.\n",
2550 board->vendor_name, board->board_name);
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002551 return 1;
2552 }
2553 msg_pinfo("NOTE: Running an untested board enable procedure.\n"
2554 "Please report success/failure to flashrom@flashrom.org\n"
2555 "with your board name and SUCCESS or FAILURE in the subject.\n");
2556 return 0;
2557}
2558
2559/* FIXME: Should this be identical to board_flash_enable? */
2560static int board_handle_phase(enum board_match_phase phase)
2561{
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002562 const struct board_match *board = NULL;
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002563
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002564 board = board_match_pci_ids(phase);
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002565
2566 if (unsafe_board_handler(board))
2567 board = NULL;
2568
2569 if (!board)
2570 return 0;
2571
2572 if (!board->enable) {
2573 /* Not sure if there is a valid case for this. */
2574 msg_perr("Board match found, but nothing to do?\n");
2575 return 0;
2576 }
2577
2578 return board->enable();
2579}
2580
2581void board_handle_before_superio(void)
2582{
2583 board_handle_phase(P1);
2584}
2585
2586void board_handle_before_laptop(void)
2587{
2588 board_handle_phase(P2);
2589}
2590
Uwe Hermann372eeb52007-12-04 21:49:06 +00002591int board_flash_enable(const char *vendor, const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002592{
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002593 const struct board_match *board = NULL;
Uwe Hermanna7e05482007-05-09 10:17:44 +00002594 int ret = 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002595
Peter Stuge6b53fed2008-01-27 16:21:21 +00002596 if (part)
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002597 board = board_match_cbname(vendor, part);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002598
Uwe Hermanna7e05482007-05-09 10:17:44 +00002599 if (!board)
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002600 board = board_match_pci_ids(P3);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002601
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002602 if (unsafe_board_handler(board))
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002603 board = NULL;
Michael Karcher7f0c3ec2010-03-07 22:29:28 +00002604
Uwe Hermanna7e05482007-05-09 10:17:44 +00002605 if (board) {
Luc Verhaegen93938c32010-01-20 14:45:03 +00002606 if (board->max_rom_decode_parallel)
2607 max_rom_decode.parallel =
2608 board->max_rom_decode_parallel * 1024;
2609
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00002610 if (board->enable != NULL) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002611 msg_pinfo("Disabling flash write protection for "
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002612 "board \"%s %s\"... ", board->vendor_name,
2613 board->board_name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002614
Uwe Hermann36dec8b2010-06-07 19:06:26 +00002615 ret = board->enable();
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00002616 if (ret)
Sean Nelson316a29f2010-05-07 20:09:04 +00002617 msg_pinfo("FAILED!\n");
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00002618 else
Sean Nelson316a29f2010-05-07 20:09:04 +00002619 msg_pinfo("OK.\n");
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00002620 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00002621 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002622
Uwe Hermanna7e05482007-05-09 10:17:44 +00002623 return ret;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002624}