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Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
5 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +00006 * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
Carl-Daniel Hailfinger92242622007-09-27 14:29:57 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00008 *
Uwe Hermannd1107642007-08-29 17:52:32 +00009 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000012 *
Uwe Hermannd1107642007-08-29 17:52:32 +000013 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000021 */
22
23/*
24 * Contains the board specific flash enables.
25 */
26
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000027#include <strings.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000028#include <string.h>
Stefan Taunerb4e06bd2012-08-20 00:24:22 +000029#include <stdlib.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000030#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000031#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000032#include "hwaccess.h"
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000033
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000034#if defined(__i386__) || defined(__x86_64__)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000035/*
Uwe Hermannffec5f32007-08-23 16:08:21 +000036 * Helper functions for many Winbond Super I/Os of the W836xx range.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000037 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000038/* Enter extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000039void w836xx_ext_enter(uint16_t port)
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000040{
Andriy Gapon65c1b862008-05-22 13:22:45 +000041 OUTB(0x87, port);
42 OUTB(0x87, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000043}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000044
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000045/* Leave extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000046void w836xx_ext_leave(uint16_t port)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000047{
Andriy Gapon65c1b862008-05-22 13:22:45 +000048 OUTB(0xAA, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000049}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000050
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000051/* Generic Super I/O helper functions */
52uint8_t sio_read(uint16_t port, uint8_t reg)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000053{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000054 OUTB(reg, port);
55 return INB(port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000056}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000057
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000058void sio_write(uint16_t port, uint8_t reg, uint8_t data)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000059{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000060 OUTB(reg, port);
61 OUTB(data, port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000062}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000063
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000064void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000065{
Ronald G. Minnichfa496922007-10-12 21:22:40 +000066 uint8_t tmp;
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000067
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000068 OUTB(reg, port);
69 tmp = INB(port + 1) & ~mask;
70 OUTB(tmp | (data & mask), port + 1);
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000071}
72
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +000073/* Winbond W83697 documentation indicates that the index register has to be written for each access. */
74void sio_mask_alzheimer(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
75{
76 uint8_t tmp;
77
78 OUTB(reg, port);
79 tmp = INB(port + 1) & ~mask;
80 OUTB(reg, port);
81 OUTB(tmp | (data & mask), port + 1);
82}
83
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000084/* Not used yet. */
85#if 0
86static int enable_flash_decode_superio(void)
87{
88 int ret;
89 uint8_t tmp;
90
91 switch (superio.vendor) {
92 case SUPERIO_VENDOR_NONE:
93 ret = -1;
94 break;
95 case SUPERIO_VENDOR_ITE:
96 enter_conf_mode_ite(superio.port);
Uwe Hermann43959702010-03-13 17:28:29 +000097 /* Enable flash mapping. Works for most old ITE style Super I/O. */
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000098 tmp = sio_read(superio.port, 0x24);
99 tmp |= 0xfc;
100 sio_write(superio.port, 0x24, tmp);
101 exit_conf_mode_ite(superio.port);
102 ret = 0;
103 break;
104 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000105 msg_pdbg("Unhandled Super I/O type!\n");
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +0000106 ret = -1;
107 break;
108 }
109 return ret;
110}
111#endif
112
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000113/*
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000114 * SMSC FDC37B787: Raise GPIO50
115 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000116static int fdc37b787_gpio50_raise(uint16_t port)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000117{
118 uint8_t id, val;
119
120 OUTB(0x55, port); /* enter conf mode */
121 id = sio_read(port, 0x20);
122 if (id != 0x44) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000123 msg_perr("\nERROR: FDC37B787: Wrong ID 0x%02X.\n", id);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000124 OUTB(0xAA, port); /* leave conf mode */
125 return -1;
126 }
127
128 sio_write(port, 0x07, 0x08); /* Select Aux I/O subdevice */
129
130 val = sio_read(port, 0xC8); /* GP50 */
131 if ((val & 0x1B) != 0x10) /* output, no invert, GPIO */
132 {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000133 msg_perr("\nERROR: GPIO50 mode 0x%02X unexpected.\n", val);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000134 OUTB(0xAA, port);
135 return -1;
136 }
137
138 sio_mask(port, 0xF9, 0x01, 0x01);
139
140 OUTB(0xAA, port); /* Leave conf mode */
141 return 0;
142}
143
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000144/*
145 * Suited for:
146 * - Nokia IP530: Intel 440BX + PIIX4 + FDC37B787
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000147 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000148static int fdc37b787_gpio50_raise_3f0(void)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000149{
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000150 return fdc37b787_gpio50_raise(0x3f0);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000151}
152
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000153struct winbond_mux {
154 uint8_t reg; /* 0 if the corresponding pin is not muxed */
155 uint8_t data; /* reg/data/mask may be directly ... */
156 uint8_t mask; /* ... passed to sio_mask */
157};
158
159struct winbond_port {
160 const struct winbond_mux *mux; /* NULL or pointer to mux info for the 8 bits */
161 uint8_t ldn; /* LDN this GPIO register is located in */
162 uint8_t enable_bit; /* bit in 0x30 of that LDN to enable
163 the GPIO port */
164 uint8_t base; /* base register in that LDN for the port */
165};
166
167struct winbond_chip {
168 uint8_t device_id; /* reg 0x20 of the expected w83626x */
169 uint8_t gpio_port_count;
170 const struct winbond_port *port;
171};
172
173
174#define UNIMPLEMENTED_PORT {NULL, 0, 0, 0}
175
176enum winbond_id {
177 WINBOND_W83627HF_ID = 0x52,
Michael Karcherea36c9c2010-06-27 15:07:52 +0000178 WINBOND_W83627EHF_ID = 0x88,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000179 WINBOND_W83627THF_ID = 0x82,
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000180 WINBOND_W83697HF_ID = 0x60,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000181};
182
183static const struct winbond_mux w83627hf_port2_mux[8] = {
184 {0x2A, 0x01, 0x01}, /* or MIDI */
185 {0x2B, 0x80, 0x80}, /* or SPI */
186 {0x2B, 0x40, 0x40}, /* or SPI */
187 {0x2B, 0x20, 0x20}, /* or power LED */
188 {0x2B, 0x10, 0x10}, /* or watchdog */
189 {0x2B, 0x08, 0x08}, /* or infra red */
190 {0x2B, 0x04, 0x04}, /* or infra red */
191 {0x2B, 0x03, 0x03} /* or IRQ1 input */
192};
193
194static const struct winbond_port w83627hf[3] = {
195 UNIMPLEMENTED_PORT,
196 {w83627hf_port2_mux, 0x08, 0, 0xF0},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000197 UNIMPLEMENTED_PORT,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000198};
199
Michael Karcherea36c9c2010-06-27 15:07:52 +0000200static const struct winbond_mux w83627ehf_port2_mux[8] = {
201 {0x29, 0x06, 0x02}, /* or MIDI */
202 {0x29, 0x06, 0x02},
203 {0x24, 0x02, 0x00}, /* or SPI ROM interface */
204 {0x24, 0x02, 0x00},
205 {0x2A, 0x01, 0x01}, /* or keyboard/mouse interface */
206 {0x2A, 0x01, 0x01},
207 {0x2A, 0x01, 0x01},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000208 {0x2A, 0x01, 0x01},
Michael Karcherea36c9c2010-06-27 15:07:52 +0000209};
210
211static const struct winbond_port w83627ehf[6] = {
212 UNIMPLEMENTED_PORT,
213 {w83627ehf_port2_mux, 0x09, 0, 0xE3},
214 UNIMPLEMENTED_PORT,
215 UNIMPLEMENTED_PORT,
216 UNIMPLEMENTED_PORT,
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000217 UNIMPLEMENTED_PORT,
Michael Karcherea36c9c2010-06-27 15:07:52 +0000218};
219
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000220static const struct winbond_mux w83627thf_port4_mux[8] = {
221 {0x2D, 0x01, 0x01}, /* or watchdog or VID level strap */
222 {0x2D, 0x02, 0x02}, /* or resume reset */
223 {0x2D, 0x04, 0x04}, /* or S3 input */
224 {0x2D, 0x08, 0x08}, /* or PSON# */
225 {0x2D, 0x10, 0x10}, /* or PWROK */
226 {0x2D, 0x20, 0x20}, /* or suspend LED */
227 {0x2D, 0x40, 0x40}, /* or panel switch input */
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000228 {0x2D, 0x80, 0x80}, /* or panel switch output */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000229};
230
231static const struct winbond_port w83627thf[5] = {
232 UNIMPLEMENTED_PORT, /* GPIO1 */
233 UNIMPLEMENTED_PORT, /* GPIO2 */
234 UNIMPLEMENTED_PORT, /* GPIO3 */
235 {w83627thf_port4_mux, 0x09, 1, 0xF4},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000236 UNIMPLEMENTED_PORT, /* GPIO5 */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000237};
238
239static const struct winbond_chip winbond_chips[] = {
240 {WINBOND_W83627HF_ID, ARRAY_SIZE(w83627hf), w83627hf },
Michael Karcherea36c9c2010-06-27 15:07:52 +0000241 {WINBOND_W83627EHF_ID, ARRAY_SIZE(w83627ehf), w83627ehf},
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000242 {WINBOND_W83627THF_ID, ARRAY_SIZE(w83627thf), w83627thf},
243};
244
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000245#define WINBOND_SUPERIO_PORT1 0x2e
246#define WINBOND_SUPERIO_PORT2 0x4e
247
248/* We don't really care about the hardware monitor, but it offers better (more specific) device ID info than
249 * the simple device ID in the normal configuration registers.
250 * Note: This function expects to be called while the Super I/O is in config mode.
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000251 */
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000252static uint8_t w836xx_deviceid_hwmon(uint16_t sio_port)
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000253{
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000254 uint16_t hwmport;
255 uint16_t hwm_vendorid;
256 uint8_t hwm_deviceid;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000257
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000258 sio_write(sio_port, 0x07, 0x0b); /* Select LDN 0xb (HWM). */
259 if ((sio_read(sio_port, 0x30) & (1 << 0)) != (1 << 0)) {
260 msg_pinfo("W836xx hardware monitor disabled or does not exist.\n");
261 return 0;
262 }
263 /* Get HWM base address (stored in LDN 0xb, index 0x60/0x61). */
264 hwmport = sio_read(sio_port, 0x60) << 8;
265 hwmport |= sio_read(sio_port, 0x61);
266 /* HWM address register = HWM base address + 5. */
267 hwmport += 5;
268 msg_pdbg2("W836xx Hardware Monitor at port %04x\n", hwmport);
269 /* FIXME: This busy check should happen before each HWM access. */
270 if (INB(hwmport) & 0x80) {
271 msg_pinfo("W836xx hardware monitor busy, ignoring it.\n");
272 return 0;
273 }
274 /* Set HBACS=1. */
275 sio_mask_alzheimer(hwmport, 0x4e, 0x80, 0x80);
276 /* Read upper byte of vendor ID. */
277 hwm_vendorid = sio_read(hwmport, 0x4f) << 8;
278 /* Set HBACS=0. */
279 sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x80);
280 /* Read lower byte of vendor ID. */
281 hwm_vendorid |= sio_read(hwmport, 0x4f);
282 if (hwm_vendorid != 0x5ca3) {
283 msg_pinfo("W836xx hardware monitor vendor ID weirdness: expected 0x5ca3, got %04x\n",
284 hwm_vendorid);
285 return 0;
286 }
287 /* Set Bank=0. */
288 sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x07);
289 /* Read "chip" ID. We call this one the device ID. */
290 hwm_deviceid = sio_read(hwmport, 0x58);
291 return hwm_deviceid;
292}
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000293
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000294void probe_superio_winbond(void)
295{
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +0000296 struct superio s = {0};
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000297 uint16_t winbond_ports[] = {WINBOND_SUPERIO_PORT1, WINBOND_SUPERIO_PORT2, 0};
298 uint16_t *i = winbond_ports;
299 uint8_t model;
300 uint8_t tmp;
301
302 s.vendor = SUPERIO_VENDOR_WINBOND;
303 for (; *i; i++) {
304 s.port = *i;
305 /* If we're already in Super I/O config more, the W836xx enter sequence won't hurt. */
306 w836xx_ext_enter(s.port);
307 model = sio_read(s.port, 0x20);
308 /* No response, no point leaving the config mode. */
309 if (model == 0xff)
310 continue;
311 /* Try to leave config mode. If the ID register is still readable, it's not a Winbond chip. */
312 w836xx_ext_leave(s.port);
313 if (model == sio_read(s.port, 0x20)) {
314 msg_pdbg("W836xx enter config mode worked or we were already in config mode. W836xx "
315 "leave config mode had no effect.\n");
316 if (model == 0x87) {
317 /* ITE IT8707F and IT8710F are special: They need the W837xx enter sequence,
318 * but they want the ITE exit sequence. Handle them here.
319 */
320 tmp = sio_read(s.port, 0x21);
321 switch (tmp) {
322 case 0x07:
323 case 0x10:
324 s.vendor = SUPERIO_VENDOR_ITE;
325 s.model = (0x87 << 8) | tmp ;
326 msg_pdbg("Found ITE Super I/O, ID 0x%04hx on port "
327 "0x%x\n", s.model, s.port);
328 register_superio(s);
329 /* Exit ITE config mode. */
330 exit_conf_mode_ite(s.port);
331 /* Restore vendor for next loop iteration. */
332 s.vendor = SUPERIO_VENDOR_WINBOND;
333 continue;
334 }
335 }
336 msg_pinfo("Active config mode, unknown reg 0x20 ID: %02x.\n", model);
Stefan Taunerc2eec2c2014-05-03 21:33:01 +0000337 msg_pinfo("Please send the output of \"flashrom -V -p internal\" to \n"
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000338 "flashrom@flashrom.org with W836xx: your board name: flashrom -V\n"
339 "as the subject to help us finish support for your Super I/O. Thanks.\n");
340 continue;
341 }
342 /* The Super I/O reacts to W836xx enter and exit config mode, it's probably Winbond. */
343 w836xx_ext_enter(s.port);
344 s.model = sio_read(s.port, 0x20);
345 switch (s.model) {
346 case WINBOND_W83627HF_ID:
347 case WINBOND_W83627EHF_ID:
348 case WINBOND_W83627THF_ID:
Stefan Taunereb582572012-09-21 12:52:50 +0000349 msg_pdbg("Found Winbond Super I/O, id 0x%02hx\n", s.model);
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000350 register_superio(s);
351 break;
352 case WINBOND_W83697HF_ID:
353 /* This code is extremely paranoid. */
354 tmp = sio_read(s.port, 0x26) & 0x40;
355 if (((tmp == 0x00) && (s.port != WINBOND_SUPERIO_PORT1)) ||
356 ((tmp == 0x40) && (s.port != WINBOND_SUPERIO_PORT2))) {
357 msg_pdbg("Winbond Super I/O probe weirdness: Port mismatch for ID "
Stefan Taunereb582572012-09-21 12:52:50 +0000358 "0x%02x at port 0x%04x\n", s.model, s.port);
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000359 break;
360 }
361 tmp = w836xx_deviceid_hwmon(s.port);
362 /* FIXME: This might be too paranoid... */
363 if (!tmp) {
364 msg_pdbg("Probably not a Winbond Super I/O\n");
365 break;
366 }
367 if (tmp != s.model) {
Stefan Taunereb582572012-09-21 12:52:50 +0000368 msg_pinfo("W83 series hardware monitor device ID weirdness: expected 0x%02x, "
369 "got 0x%02x\n", WINBOND_W83697HF_ID, tmp);
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000370 break;
371 }
Stefan Taunereb582572012-09-21 12:52:50 +0000372 msg_pinfo("Found Winbond Super I/O, id 0x%02hx\n", s.model);
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000373 register_superio(s);
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000374 break;
375 }
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000376 w836xx_ext_leave(s.port);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000377 }
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000378 return;
379}
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000380
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000381static const struct winbond_chip *winbond_superio_chipdef(void)
382{
383 int i, j;
384
385 for (i = 0; i < superio_count; i++) {
386 if (superios[i].vendor != SUPERIO_VENDOR_WINBOND)
387 continue;
388 for (j = 0; j < ARRAY_SIZE(winbond_chips); j++)
389 if (winbond_chips[j].device_id == superios[i].model)
390 return &winbond_chips[j];
391 }
392 return NULL;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000393}
394
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000395/*
396 * The chipid parameter goes away as soon as we have Super I/O matching in the
397 * board enable table. The call to winbond_superio_detect() goes away as
398 * soon as we have generic Super I/O detection code.
399 */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000400static int winbond_gpio_set(uint16_t base, enum winbond_id chipid,
401 int pin, int raise)
402{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000403 const struct winbond_chip *chip = NULL;
404 const struct winbond_port *gpio;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000405 int port = pin / 10;
406 int bit = pin % 10;
407
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000408 chip = winbond_superio_chipdef();
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000409 if (!chip) {
410 msg_perr("\nERROR: No supported Winbond Super I/O found\n");
411 return -1;
412 }
Michael Karcher979d9252010-06-29 14:44:40 +0000413 if (chip->device_id != chipid) {
414 msg_perr("\nERROR: Found Winbond chip with ID 0x%x, "
415 "expected %x\n", chip->device_id, chipid);
416 return -1;
417 }
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000418 if (bit >= 8 || port == 0 || port > chip->gpio_port_count) {
419 msg_perr("\nERROR: winbond_gpio_set: Invalid GPIO number %d\n",
420 pin);
421 return -1;
422 }
423
424 gpio = &chip->port[port - 1];
425
426 if (gpio->ldn == 0) {
427 msg_perr("\nERROR: GPIO%d is not supported yet on this"
428 " winbond chip\n", port);
429 return -1;
430 }
431
432 w836xx_ext_enter(base);
433
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000434 /* Select logical device. */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000435 sio_write(base, 0x07, gpio->ldn);
436
437 /* Activate logical device. */
438 sio_mask(base, 0x30, 1 << gpio->enable_bit, 1 << gpio->enable_bit);
439
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000440 /* Select GPIO function of that pin. */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000441 if (gpio->mux && gpio->mux[bit].reg)
442 sio_mask(base, gpio->mux[bit].reg,
443 gpio->mux[bit].data, gpio->mux[bit].mask);
444
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000445 sio_mask(base, gpio->base + 0, 0, 1 << bit); /* Make pin output */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000446 sio_mask(base, gpio->base + 2, 0, 1 << bit); /* Clear inversion */
447 sio_mask(base, gpio->base + 1, raise << bit, 1 << bit);
448
449 w836xx_ext_leave(base);
450
451 return 0;
452}
453
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000454/*
Uwe Hermannffec5f32007-08-23 16:08:21 +0000455 * Winbond W83627HF: Raise GPIO24.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000456 *
457 * Suited for:
Uwe Hermannffec5f32007-08-23 16:08:21 +0000458 * - Agami Aruma
459 * - IWILL DK8-HTX
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000460 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000461static int w83627hf_gpio24_raise_2e(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000462{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000463 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 24, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000464}
465
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000466/*
Joshua Roysf280a382010-08-07 21:49:11 +0000467 * Winbond W83627HF: Raise GPIO25.
468 *
469 * Suited for:
470 * - MSI MS-6577
471 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000472static int w83627hf_gpio25_raise_2e(void)
Joshua Roysf280a382010-08-07 21:49:11 +0000473{
474 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 25, 1);
475}
476
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000477/*
Stefan Taunerff80e682011-07-20 16:34:18 +0000478 * Winbond W83627EHF: Raise GPIO22.
Michael Karcherea36c9c2010-06-27 15:07:52 +0000479 *
480 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000481 * - ASUS A8N-VM CSM: AMD Socket 939 + GeForce 6150 (C51) + MCP51
Michael Karcherea36c9c2010-06-27 15:07:52 +0000482 */
Stefan Taunerff80e682011-07-20 16:34:18 +0000483static int w83627ehf_gpio22_raise_2e(void)
Michael Karcherea36c9c2010-06-27 15:07:52 +0000484{
Stefan Taunerff80e682011-07-20 16:34:18 +0000485 return winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, 22, 1);
Michael Karcherea36c9c2010-06-27 15:07:52 +0000486}
487
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000488/*
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000489 * Winbond W83627THF: Raise GPIO 44.
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000490 *
491 * Suited for:
Stefan Taunerc2eec2c2014-05-03 21:33:01 +0000492 * - MSI K8T Neo2-F V2.0
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000493 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000494static int w83627thf_gpio44_raise_2e(void)
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000495{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000496 return winbond_gpio_set(0x2e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000497}
498
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000499/*
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000500 * Winbond W83627THF: Raise GPIO 44.
501 *
502 * Suited for:
503 * - MSI K8N Neo3
504 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000505static int w83627thf_gpio44_raise_4e(void)
Peter Stugecce26822008-07-21 17:48:40 +0000506{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000507 return winbond_gpio_set(0x4e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000508}
Uwe Hermann372eeb52007-12-04 21:49:06 +0000509
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000510/*
David Borgb6417a62010-08-02 08:29:34 +0000511 * Enable MEMW# and set ROM size to max.
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000512 * Supported chips: W83L517D, W83697HF/F/HG, W83697SF/UF/UG
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000513 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000514static void w836xx_memw_enable(uint16_t port)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000515{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000516 w836xx_ext_enter(port);
517 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000518 /* Enable MEMW# and set ROM size select to max. (4M). */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000519 sio_mask(port, 0x24, 0x28, 0x28);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000520 }
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000521 w836xx_ext_leave(port);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000522}
523
David Borgb02c62b2012-05-05 20:43:42 +0000524/**
525 * Enable MEMW# and set ROM size to max.
526 * Supported chips:
527 * W83697HF/F/HG, W83697SF/UF/UG
528 */
529void w83697xx_memw_enable(uint16_t port)
530{
531 w836xx_ext_enter(port);
532 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
533 if((sio_read(port, 0x2A) & 0xF0) == 0xF0) {
534
535 /* CR24 Bits 7 & 2 must be set to 0 enable the flash ROM */
536 /* address segments 000E0000h ~ 000FFFFFh on W83697SF/UF/UG */
537 /* These bits are reserved on W83697HF/F/HG */
538 /* Shouldn't be needed though. */
539
540 /* CR28 Bit3 must be set to 1 to enable flash access to */
541 /* FFE80000h ~ FFEFFFFFh on W83697SF/UF/UG. */
542 /* This bit is reserved on W83697HF/F/HG which default to 0 */
543 sio_mask(port, 0x28, 0x08, 0x08);
544
545 /* Enable MEMW# and set ROM size select to max. (4M)*/
546 sio_mask(port, 0x24, 0x28, 0x38);
547
548 } else {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +0000549 msg_pwarn("Warning: Flash interface in use by GPIO!\n");
David Borgb02c62b2012-05-05 20:43:42 +0000550 }
551 } else {
552 msg_pinfo("BIOS ROM is disabled\n");
553 }
554 w836xx_ext_leave(port);
555}
556
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000557/*
Luc Verhaegen73d21192009-12-23 00:54:26 +0000558 * Suited for:
Stefan Taunerb6304c12012-08-09 23:25:27 +0000559 * - Biostar M7VIQ: VIA KM266 + VT8235
560 */
561static int w83697xx_memw_enable_2e(void)
562{
563 w83697xx_memw_enable(0x2E);
564
565 return 0;
566}
567
568
569/*
570 * Suited for:
Tadas Slotkus3dcdc032012-08-25 03:53:12 +0000571 * - DFI AD77: VIA KT400 + VT8235 + W83697HF
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000572 * - EPoX EP-8K5A2: VIA KT333 + VT8235
573 * - Albatron PM266A Pro: VIA P4M266A + VT8235
574 * - Shuttle AK31 (all versions): VIA KT266 + VT8233
575 * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
576 * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237
Mattias Mattssone295eee2010-08-15 10:21:29 +0000577 * - MSI KM4M-V and KM4AM-V: VIA KM400/KM400A + VT8237
Mattias Mattssone8388242010-09-11 15:25:48 +0000578 * - MSI MS-6561 (745 Ultra): SiS 745 + W83697HF
Sergey A Lichackf3a4bff2010-09-07 18:14:53 +0000579 * - MSI MS-6787 (P4MAM-V/P4MAM-L): VIA P4M266 + VT8235
Uwe Hermann17da61e2010-10-05 21:48:43 +0000580 * - ASRock K7S41: SiS 741 + SiS 963 + W83697HF
Pawel Rozanski1d233072011-06-19 16:52:48 +0000581 * - ASRock K7S41GX: SiS 741GX + SiS 963L + W83697HF
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000582 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000583static int w836xx_memw_enable_2e(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000584{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000585 w836xx_memw_enable(0x2E);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000586
Luc Verhaegen73d21192009-12-23 00:54:26 +0000587 return 0;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000588}
589
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000590/*
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000591 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000592 * - Termtek TK-3370 (rev. 2.5b)
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000593 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000594static int w836xx_memw_enable_4e(void)
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000595{
596 w836xx_memw_enable(0x4E);
597
598 return 0;
599}
600
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000601/*
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000602 * Suited for all boards with ITE IT8705F.
603 * The SIS950 Super I/O probably requires a similar flash write enable.
Luc Verhaegen21f54962010-01-20 14:45:07 +0000604 */
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000605int it8705f_write_enable(uint8_t port)
Luc Verhaegen21f54962010-01-20 14:45:07 +0000606{
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000607 uint8_t tmp;
608 int ret = 0;
609
Luc Verhaegen21f54962010-01-20 14:45:07 +0000610 enter_conf_mode_ite(port);
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000611 tmp = sio_read(port, 0x24);
612 /* Check if at least one flash segment is enabled. */
613 if (tmp & 0xf0) {
614 /* The IT8705F will respond to LPC cycles and translate them. */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000615 internal_buses_supported = BUS_PARALLEL;
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000616 /* Flash ROM I/F Writes Enable */
617 tmp |= 0x04;
618 msg_pdbg("Enabling IT8705F flash ROM interface write.\n");
619 if (tmp & 0x02) {
620 /* The data sheet contradicts itself about max size. */
621 max_rom_decode.parallel = 1024 * 1024;
Stefan Taunerc2eec2c2014-05-03 21:33:01 +0000622 msg_pinfo("IT8705F with very unusual settings.\n"
623 "Please send the output of \"flashrom -V -p internal\" to flashrom@flashrom.org\n"
624 "with \"IT8705: your board name: flashrom -V\" as the subject to help us finish\n"
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000625 "support for your Super I/O. Thanks.\n");
626 ret = 1;
627 } else if (tmp & 0x08) {
628 max_rom_decode.parallel = 512 * 1024;
629 } else {
630 max_rom_decode.parallel = 256 * 1024;
631 }
632 /* Safety checks. The data sheet is unclear here: Segments 1+3
633 * overlap, no segment seems to cover top - 1MB to top - 512kB.
634 * We assume that certain combinations make no sense.
635 */
636 if (((tmp & 0x02) && !(tmp & 0x08)) || /* 1 MB en, 512 kB dis */
637 (!(tmp & 0x10)) || /* 128 kB dis */
638 (!(tmp & 0x40))) { /* 256/512 kB dis */
639 msg_perr("Inconsistent IT8705F decode size!\n");
640 ret = 1;
641 }
642 if (sio_read(port, 0x25) != 0) {
643 msg_perr("IT8705F flash data pins disabled!\n");
644 ret = 1;
645 }
646 if (sio_read(port, 0x26) != 0) {
647 msg_perr("IT8705F flash address pins 0-7 disabled!\n");
648 ret = 1;
649 }
650 if (sio_read(port, 0x27) != 0) {
651 msg_perr("IT8705F flash address pins 8-15 disabled!\n");
652 ret = 1;
653 }
654 if ((sio_read(port, 0x29) & 0x10) != 0) {
655 msg_perr("IT8705F flash write enable pin disabled!\n");
656 ret = 1;
657 }
658 if ((sio_read(port, 0x29) & 0x08) != 0) {
659 msg_perr("IT8705F flash chip select pin disabled!\n");
660 ret = 1;
661 }
662 if ((sio_read(port, 0x29) & 0x04) != 0) {
663 msg_perr("IT8705F flash read strobe pin disabled!\n");
664 ret = 1;
665 }
666 if ((sio_read(port, 0x29) & 0x03) != 0) {
667 msg_perr("IT8705F flash address pins 16-17 disabled!\n");
668 /* Not really an error if you use flash chips smaller
669 * than 256 kByte, but such a configuration is unlikely.
670 */
671 ret = 1;
672 }
673 msg_pdbg("Maximum IT8705F parallel flash decode size is %u.\n",
674 max_rom_decode.parallel);
675 if (ret) {
676 msg_pinfo("Not enabling IT8705F flash write.\n");
677 } else {
678 sio_write(port, 0x24, tmp);
679 }
680 } else {
681 msg_pdbg("No IT8705F flash segment enabled.\n");
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000682 ret = 0;
683 }
Luc Verhaegen21f54962010-01-20 14:45:07 +0000684 exit_conf_mode_ite(port);
685
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000686 return ret;
Luc Verhaegen21f54962010-01-20 14:45:07 +0000687}
Luc Verhaegen73d21192009-12-23 00:54:26 +0000688
Mattias Mattssonfb60cec2010-09-13 19:39:25 +0000689/*
690 * The ITE IT8707F is a custom chip made by ITE exclusively for ASUS.
691 * It uses the Winbond command sequence to enter extended configuration
692 * mode and the ITE sequence to exit.
693 *
694 * Registers seems similar to the ones on ITE IT8710F.
695 */
696static int it8707f_write_enable(uint8_t port)
697{
698 uint8_t tmp;
699
700 w836xx_ext_enter(port);
701
702 /* Set bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A rw */
703 tmp = sio_read(port, 0x23);
704 tmp |= (1 << 3);
705 sio_write(port, 0x23, tmp);
706
707 /* Set bit 2 (FLASH_WE) and bit 3 (FLASH_IF_EN) of reg 0x24 */
708 tmp = sio_read(port, 0x24);
709 tmp |= (1 << 2) | (1 << 3);
710 sio_write(port, 0x24, tmp);
711
712 /* Clear bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A ro */
713 tmp = sio_read(port, 0x23);
714 tmp &= ~(1 << 3);
715 sio_write(port, 0x23, tmp);
716
717 exit_conf_mode_ite(port);
718
719 return 0;
720}
721
722/*
723 * Suited for:
724 * - ASUS P4SC-E: SiS 651 + 962 + ITE IT8707F
725 */
726static int it8707f_write_enable_2e(void)
727{
728 return it8707f_write_enable(0x2e);
729}
730
Michael Karchercba52de2011-03-06 12:07:19 +0000731#define PC87360_ID 0xE1
732#define PC87364_ID 0xE4
733
734static int pc8736x_gpio_set(uint8_t chipid, uint8_t gpio, int raise)
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000735{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000736 static const int bankbase[] = {0, 4, 8, 10, 12};
737 int gpio_bank = gpio / 8;
738 int gpio_pin = gpio % 8;
739 uint16_t baseport;
740 uint8_t id, val;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000741
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000742 if (gpio_bank > 4) {
Michael Karchercba52de2011-03-06 12:07:19 +0000743 msg_perr("PC8736x: Invalid GPIO %d\n", gpio);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000744 return -1;
745 }
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000746
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000747 id = sio_read(0x2E, 0x20);
Michael Karchercba52de2011-03-06 12:07:19 +0000748 if (id != chipid) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000749 msg_perr("PC8736x: unexpected ID %02x (expected %02x)\n",
750 id, chipid);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000751 return -1;
752 }
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000753
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000754 sio_write(0x2E, 0x07, 0x07); /* Select GPIO device. */
755 baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
756 if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) {
757 msg_perr("PC87360: invalid GPIO base address %04x\n",
758 baseport);
759 return -1;
760 }
761 sio_mask (0x2E, 0x30, 0x01, 0x01); /* Enable logical device. */
762 sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin);
763 sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output. */
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000764
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000765 val = INB(baseport + bankbase[gpio_bank]);
766 if (raise)
767 val |= 1 << gpio_pin;
768 else
769 val &= ~(1 << gpio_pin);
770 OUTB(val, baseport + bankbase[gpio_bank]);
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000771
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000772 return 0;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000773}
774
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000775/*
776 * VIA VT823x: Set one of the GPIO pins.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000777 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000778static int via_vt823x_gpio_set(uint8_t gpio, int raise)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000779{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000780 struct pci_dev *dev;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000781 uint16_t base;
David Bartleyf58d3642009-12-09 07:53:01 +0000782 uint8_t val, bit, offset;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000783
Luc Verhaegen73d21192009-12-23 00:54:26 +0000784 dev = pci_dev_find_vendorclass(0x1106, 0x0601);
785 switch (dev->device_id) {
786 case 0x3177: /* VT8235 */
Helge Wagnerdd73d832012-08-24 23:03:46 +0000787 case 0x3227: /* VT8237/VT8237R */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000788 case 0x3337: /* VT8237A */
789 break;
790 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000791 msg_perr("\nERROR: VT823x ISA bridge not found.\n");
Luc Verhaegen73d21192009-12-23 00:54:26 +0000792 return -1;
793 }
794
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000795 if ((gpio >= 12) && (gpio <= 15)) {
796 /* GPIO12-15 -> output */
797 val = pci_read_byte(dev, 0xE4);
798 val |= 0x10;
799 pci_write_byte(dev, 0xE4, val);
800 } else if (gpio == 9) {
801 /* GPIO9 -> Output */
802 val = pci_read_byte(dev, 0xE4);
803 val |= 0x20;
804 pci_write_byte(dev, 0xE4, val);
David Bartleyf58d3642009-12-09 07:53:01 +0000805 } else if (gpio == 5) {
806 val = pci_read_byte(dev, 0xE4);
807 val |= 0x01;
808 pci_write_byte(dev, 0xE4, val);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000809 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000810 msg_perr("\nERROR: "
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000811 "VT823x GPIO%02d is not implemented.\n", gpio);
Luc Verhaegen73d21192009-12-23 00:54:26 +0000812 return -1;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000813 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000814
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000815 /* We need the I/O Base Address for this board's flash enable. */
816 base = pci_read_word(dev, 0x88) & 0xff80;
817
David Bartleyf58d3642009-12-09 07:53:01 +0000818 offset = 0x4C + gpio / 8;
819 bit = 0x01 << (gpio % 8);
820
821 val = INB(base + offset);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000822 if (raise)
823 val |= bit;
824 else
825 val &= ~bit;
David Bartleyf58d3642009-12-09 07:53:01 +0000826 OUTB(val, base + offset);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000827
Uwe Hermanna7e05482007-05-09 10:17:44 +0000828 return 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000829}
830
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000831/*
832 * Suited for:
833 * - ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000834 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000835static int via_vt823x_gpio5_raise(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000836{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000837 /* On M2V-MX: GPO5 is connected to WP# and TBL#. */
838 return via_vt823x_gpio_set(5, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000839}
840
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000841/*
842 * Suited for:
843 * - VIA EPIA EK & N & NL
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000844 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000845static int via_vt823x_gpio9_raise(void)
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000846{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000847 return via_vt823x_gpio_set(9, 1);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000848}
849
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000850/*
851 * Suited for:
852 * - VIA EPIA M and MII (and maybe other CLE266 based EPIAs)
Luc Verhaegen73d21192009-12-23 00:54:26 +0000853 *
854 * We don't need to do this for EPIA M when using coreboot, GPIO15 is never
855 * lowered there.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000856 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000857static int via_vt823x_gpio15_raise(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000858{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000859 return via_vt823x_gpio_set(15, 1);
860}
861
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000862/*
Luc Verhaegen73d21192009-12-23 00:54:26 +0000863 * Winbond W83697HF Super I/O + VIA VT8235 southbridge
864 *
865 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000866 * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
867 * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
Luc Verhaegen73d21192009-12-23 00:54:26 +0000868 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000869static int board_msi_kt4v(void)
Luc Verhaegen73d21192009-12-23 00:54:26 +0000870{
871 int ret;
872
873 ret = via_vt823x_gpio_set(12, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000874 w836xx_memw_enable(0x2E);
Luc Verhaegen97866082008-02-09 02:03:06 +0000875
Luc Verhaegen73d21192009-12-23 00:54:26 +0000876 return ret;
Luc Verhaegen97866082008-02-09 02:03:06 +0000877}
878
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000879/*
880 * Suited for:
881 * - ASUS P5A
Luc Verhaegen6b141752007-05-20 16:16:13 +0000882 *
883 * This is rather nasty code, but there's no way to do this cleanly.
884 * We're basically talking to some unknown device on SMBus, my guess
885 * is that it is the Winbond W83781D that lives near the DIP BIOS.
886 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000887static int board_asus_p5a(void)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000888{
889 uint8_t tmp;
890 int i;
891
892#define ASUSP5A_LOOP 5000
893
Andriy Gapon65c1b862008-05-22 13:22:45 +0000894 OUTB(0x00, 0xE807);
895 OUTB(0xEF, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000896
Andriy Gapon65c1b862008-05-22 13:22:45 +0000897 OUTB(0xFF, 0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000898
899 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000900 OUTB(0xE1, 0xFF);
901 if (INB(0xE800) & 0x04)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000902 break;
903 }
904
905 if (i == ASUSP5A_LOOP) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000906 msg_perr("Unable to contact device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000907 return -1;
908 }
909
Andriy Gapon65c1b862008-05-22 13:22:45 +0000910 OUTB(0x20, 0xE801);
911 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000912
Andriy Gapon65c1b862008-05-22 13:22:45 +0000913 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000914
915 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000916 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000917 if (tmp & 0x70)
918 break;
919 }
920
921 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000922 msg_perr("Failed to read device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000923 return -1;
924 }
925
Andriy Gapon65c1b862008-05-22 13:22:45 +0000926 tmp = INB(0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000927 tmp &= ~0x02;
928
Andriy Gapon65c1b862008-05-22 13:22:45 +0000929 OUTB(0x00, 0xE807);
930 OUTB(0xEE, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000931
Andriy Gapon65c1b862008-05-22 13:22:45 +0000932 OUTB(tmp, 0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000933
Andriy Gapon65c1b862008-05-22 13:22:45 +0000934 OUTB(0xFF, 0xE800);
935 OUTB(0xE1, 0xFF);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000936
Andriy Gapon65c1b862008-05-22 13:22:45 +0000937 OUTB(0x20, 0xE801);
938 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000939
Andriy Gapon65c1b862008-05-22 13:22:45 +0000940 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000941
942 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000943 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000944 if (tmp & 0x70)
945 break;
946 }
947
948 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000949 msg_perr("Failed to write to device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000950 return -1;
951 }
952
953 return 0;
954}
955
Luc Verhaegena7e30502009-12-09 11:39:02 +0000956/*
957 * Set GPIO lines in the Broadcom HT-1000 southbridge.
958 *
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000959 * It's not a Super I/O but it uses the same index/data port method.
Luc Verhaegena7e30502009-12-09 11:39:02 +0000960 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000961static int board_hp_dl145_g3_enable(void)
Luc Verhaegena7e30502009-12-09 11:39:02 +0000962{
963 /* GPIO 0 reg from PM regs */
964 /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
965 sio_mask(0xcd6, 0x44, 0x24, 0x24);
966
967 return 0;
968}
969
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +0000970/*
971 * Set GPIO lines in the Broadcom HT-1000 southbridge.
972 *
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000973 * It's not a Super I/O but it uses the same index/data port method.
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +0000974 */
975static int board_hp_dl165_g6_enable(void)
976{
977 /* Variant of DL145, with slightly different pin placement. */
978 sio_mask(0xcd6, 0x44, 0x80, 0x80); /* TBL# */
979 sio_mask(0xcd6, 0x46, 0x04, 0x04); /* WP# */
980
981 return 0;
982}
983
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000984static int board_ibm_x3455(void)
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000985{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000986 /* Raise GPIO13. */
Carl-Daniel Hailfinger500b4232009-06-01 21:30:42 +0000987 sio_mask(0xcd6, 0x45, 0x20, 0x20);
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000988
989 return 0;
990}
991
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000992/*
993 * Suited for:
Mattias Mattssonf4925162010-09-16 22:09:18 +0000994 * - Elitegroup GeForce6100SM-M: NVIDIA MCP61 + ITE IT8726F
995 */
Mattias Mattssonf4925162010-09-16 22:09:18 +0000996static int board_ecs_geforce6100sm_m(void)
997{
998 struct pci_dev *dev;
999 uint32_t tmp;
1000
1001 dev = pci_dev_find(0x10DE, 0x03EB); /* NVIDIA MCP61 SMBus. */
1002 if (!dev) {
1003 msg_perr("\nERROR: NVIDIA MCP61 SMBus not found.\n");
1004 return -1;
1005 }
1006
1007 tmp = pci_read_byte(dev, 0xE0);
1008 tmp &= ~(1 << 3);
1009 pci_write_byte(dev, 0xE0, tmp);
1010
1011 return 0;
1012}
1013
1014/*
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001015 * Very similar to AMD 8111 IO Hub.
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001016 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001017static int nvidia_mcp_gpio_set(int gpio, int raise)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001018{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001019 struct pci_dev *dev;
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001020 uint16_t base, devclass;
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001021 uint8_t tmp;
1022
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001023 if ((gpio < 0) || (gpio >= 0x40)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001024 msg_perr("\nERROR: unsupported GPIO: %d.\n", gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +00001025 return -1;
1026 }
1027
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001028 /* Check for the ISA bridge first. */
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001029 dev = pci_dev_find_vendorclass(0x10DE, 0x0601);
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001030 switch (dev->device_id) {
1031 case 0x0030: /* CK804 */
1032 case 0x0050: /* MCP04 */
1033 case 0x0060: /* MCP2 */
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001034 case 0x00E0: /* CK8 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001035 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +00001036 case 0x0260: /* MCP51 */
Michael Karcher242efd42011-03-06 12:09:05 +00001037 case 0x0261: /* MCP51 */
Joshua Roys6e48a022012-06-29 23:07:14 +00001038 case 0x0360: /* MCP55 */
Michael Karcher2ead2e22010-06-01 16:09:06 +00001039 case 0x0364: /* MCP55 */
1040 /* find SMBus controller on *this* southbridge */
1041 /* The infamous Tyan S2915-E has two south bridges; they are
1042 easily told apart from each other by the class of the
1043 LPC bridge, but have the same SMBus bridge IDs */
1044 if (dev->func != 0) {
1045 msg_perr("MCP LPC bridge at unexpected function"
1046 " number %d\n", dev->func);
1047 return -1;
1048 }
1049
Carl-Daniel Hailfinger44cd9ab2010-07-17 22:28:05 +00001050#if PCI_LIB_VERSION >= 0x020200
Michael Karcher2ead2e22010-06-01 16:09:06 +00001051 dev = pci_get_dev(pacc, dev->domain, dev->bus, dev->dev, 1);
Carl-Daniel Hailfinger44cd9ab2010-07-17 22:28:05 +00001052#else
1053 /* pciutils/libpci before version 2.2 is too old to support
1054 * PCI domains. Such old machines usually don't have domains
1055 * besides domain 0, so this is not a problem.
1056 */
1057 dev = pci_get_dev(pacc, dev->bus, dev->dev, 1);
1058#endif
Michael Karcher2ead2e22010-06-01 16:09:06 +00001059 if (!dev) {
1060 msg_perr("MCP SMBus controller could not be found\n");
1061 return -1;
1062 }
1063 devclass = pci_read_word(dev, PCI_CLASS_DEVICE);
1064 if (devclass != 0x0C05) {
1065 msg_perr("Unexpected device class %04x for SMBus"
1066 " controller\n", devclass);
1067 return -1;
1068 }
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001069 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +00001070 default:
Sean Nelson316a29f2010-05-07 20:09:04 +00001071 msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n");
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001072 return -1;
1073 }
1074
1075 base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */
1076 base += 0xC0;
1077
1078 tmp = INB(base + gpio);
1079 tmp &= ~0x0F; /* null lower nibble */
1080 tmp |= 0x04; /* gpio -> output. */
1081 if (raise)
1082 tmp |= 0x01;
1083 OUTB(tmp, base + gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +00001084
1085 return 0;
1086}
1087
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001088/*
1089 * Suited for:
Stefan Taunera9cbbac2011-08-07 13:17:20 +00001090 * - ASUS A8M2N-LA (HP OEM "NodusM3-GL8E"): NVIDIA MCP51
Sean Nelson0a247512010-08-15 14:36:18 +00001091 * - ASUS A8N-LA (HP OEM "Nagami-GL8E"): NVIDIA MCP51
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001092 * - ASUS M2NBP-VM CSM: NVIDIA MCP51
Michael Karcherb2184c12010-03-07 16:42:55 +00001093 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001094static int nvidia_mcp_gpio0_raise(void)
Michael Karcherb2184c12010-03-07 16:42:55 +00001095{
1096 return nvidia_mcp_gpio_set(0x00, 1);
1097}
1098
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001099/*
1100 * Suited for:
1101 * - abit KN8 Ultra: NVIDIA CK804
Sean Nelson92bc6bd2010-03-19 22:37:29 +00001102 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001103static int nvidia_mcp_gpio2_lower(void)
Sean Nelson92bc6bd2010-03-19 22:37:29 +00001104{
1105 return nvidia_mcp_gpio_set(0x02, 0);
1106}
1107
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001108/*
1109 * Suited for:
Michael Karcher2842db32011-04-14 23:14:27 +00001110 * - Foxconn 6150K8MD-8EKRSH: Socket 939 + NVIDIA MCP51
Stefan Taunerc2eec2c2014-05-03 21:33:01 +00001111 * - MSI K8N Neo4(-F/-FI/-FX/Platinum): NVIDIA CK804
Uwe Hermannead705f2010-08-15 15:26:30 +00001112 * - MSI K8NGM2-L: NVIDIA MCP51
Joshua Roys6e48a022012-06-29 23:07:14 +00001113 * - MSI K9N SLI: NVIDIA MCP55
Luc Verhaegen6c5f7332009-12-23 03:01:36 +00001114 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001115static int nvidia_mcp_gpio2_raise(void)
Luc Verhaegen6c5f7332009-12-23 03:01:36 +00001116{
1117 return nvidia_mcp_gpio_set(0x02, 1);
1118}
1119
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001120/*
1121 * Suited for:
Uwe Hermann83d349a2010-10-18 22:32:03 +00001122 * - EPoX EP-8NPA7I: Socket 754 + NVIDIA nForce4 4X
Jonathan Kollaschf8db9592010-10-15 23:02:15 +00001123 */
1124static int nvidia_mcp_gpio4_raise(void)
1125{
1126 return nvidia_mcp_gpio_set(0x04, 1);
1127}
1128
1129/*
1130 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001131 * - HP xw9400 (Tyan S2915-E OEM): Dual(!) NVIDIA MCP55
1132 *
1133 * Notes: a) There are two MCP55 chips, so also two SMBus bridges on that
1134 * board. We can't tell the SMBus logical devices apart, but we
1135 * can tell the LPC bridge functions apart.
1136 * We need to choose the SMBus bridge next to the LPC bridge with
1137 * ID 0x364 and the "LPC bridge" class.
1138 * b) #TBL is hardwired on that board to a pull-down. It can be
1139 * overridden by connecting the two solder points next to F2.
Michael Karcher2ead2e22010-06-01 16:09:06 +00001140 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001141static int nvidia_mcp_gpio5_raise(void)
Michael Karcher2ead2e22010-06-01 16:09:06 +00001142{
1143 return nvidia_mcp_gpio_set(0x05, 1);
1144}
1145
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001146/*
1147 * Suited for:
1148 * - abit NF7-S: NVIDIA CK804
Michael Karcher8f10d242010-04-11 21:01:06 +00001149 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001150static int nvidia_mcp_gpio8_raise(void)
Michael Karcher8f10d242010-04-11 21:01:06 +00001151{
1152 return nvidia_mcp_gpio_set(0x08, 1);
1153}
1154
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001155/*
1156 * Suited for:
Cristian Măgherușan-Stanciu9932c7b2011-07-07 19:56:58 +00001157 * - GIGABYTE GA-K8NS Pro-939: Socket 939 + NVIDIA nForce3 + CK8
Idwer Volleringd8a00a02011-06-13 16:58:54 +00001158 */
1159static int nvidia_mcp_gpio0a_raise(void)
1160{
1161 return nvidia_mcp_gpio_set(0x0a, 1);
1162}
1163
1164/*
1165 * Suited for:
Stefan Tauner33366a02012-09-15 15:51:09 +00001166 * - MSI K8N Neo Platinum: Socket 754 + nForce3 Ultra + CK8
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001167 * - MSI K8N Neo2 Platinum: Socket 939 + nForce3 Ultra + CK8
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001168 */
Michael Karcher51825082010-06-12 23:14:03 +00001169static int nvidia_mcp_gpio0c_raise(void)
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001170{
1171 return nvidia_mcp_gpio_set(0x0c, 1);
1172}
1173
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001174/*
1175 * Suited for:
1176 * - abit NF-M2 nView: Socket AM2 + NVIDIA MCP51
Michael Karcherefd8af32010-07-24 22:50:54 +00001177 */
1178static int nvidia_mcp_gpio4_lower(void)
1179{
1180 return nvidia_mcp_gpio_set(0x04, 0);
1181}
1182
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001183/*
1184 * Suited for:
1185 * - ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001186 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001187static int nvidia_mcp_gpio10_raise(void)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001188{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001189 return nvidia_mcp_gpio_set(0x10, 1);
1190}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001191
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001192/*
1193 * Suited for:
1194 * - GIGABYTE GA-K8N-SLI: AMD socket 939 + NVIDIA CK804 + ITE IT8712F
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001195 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001196static int nvidia_mcp_gpio21_raise(void)
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001197{
1198 return nvidia_mcp_gpio_set(0x21, 0x01);
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001199}
1200
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001201/*
1202 * Suited for:
1203 * - EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001204 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001205static int nvidia_mcp_gpio31_raise(void)
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001206{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001207 return nvidia_mcp_gpio_set(0x31, 0x01);
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001208}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001209
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001210/*
1211 * Suited for:
Michael Karcher242efd42011-03-06 12:09:05 +00001212 * - GIGABYTE GA-K8N51GMF: Socket 754 + Geforce 6100 + MCP51
1213 * - GIGABYTE GA-K8N51GMF-9: Socket 939 + Geforce 6100 + MCP51
Joshua Roys2ee137f2010-09-07 17:52:09 +00001214 */
1215static int nvidia_mcp_gpio3b_raise(void)
1216{
1217 return nvidia_mcp_gpio_set(0x3b, 1);
1218}
1219
1220/*
1221 * Suited for:
Joshua Roysb992d342011-11-02 14:31:18 +00001222 * - Sun Ultra 40 M2: Dual Socket F (1207) + MCP55
1223 */
1224static int board_sun_ultra_40_m2(void)
1225{
1226 int ret;
1227 uint8_t reg;
1228 uint16_t base;
1229 struct pci_dev *dev;
1230
1231 ret = nvidia_mcp_gpio4_lower();
1232 if (ret)
1233 return ret;
1234
1235 dev = pci_dev_find(0x10de, 0x0364); /* NVIDIA MCP55 LPC bridge */
1236 if (!dev) {
1237 msg_perr("\nERROR: NVIDIA MCP55 LPC bridge not found.\n");
1238 return -1;
1239 }
1240
1241 base = pci_read_word(dev, 0xb4); /* some IO BAR? */
1242 if (!base)
1243 return -1;
1244
1245 reg = INB(base + 0x4b);
1246 reg |= 0x10;
1247 OUTB(reg, base + 0x4b);
1248
1249 return 0;
1250}
1251
1252/*
1253 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001254 * - Artec Group DBE61 and DBE62
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001255 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001256static int board_artecgroup_dbe6x(void)
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001257{
1258#define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001259#define DBE6x_PRI_BOOT_LOC_SHIFT 2
1260#define DBE6x_BOOT_OP_LATCHED_SHIFT 8
1261#define DBE6x_SEC_BOOT_LOC_SHIFT 10
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001262#define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT)
1263#define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT)
1264#define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT)
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001265#define DBE6x_BOOT_LOC_FLASH 2
1266#define DBE6x_BOOT_LOC_FWHUB 3
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001267
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001268 msr_t msr;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001269 unsigned long boot_loc;
1270
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001271 /* Geode only has a single core */
1272 if (setup_cpu_msr(0))
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001273 return -1;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001274
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001275 msr = rdmsr(DBE6x_MSR_DIVIL_BALL_OPTS);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001276
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001277 if ((msr.lo & (DBE6x_BOOT_OP_LATCHED)) ==
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001278 (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT))
1279 boot_loc = DBE6x_BOOT_LOC_FWHUB;
1280 else
1281 boot_loc = DBE6x_BOOT_LOC_FLASH;
1282
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001283 msr.lo &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC);
1284 msr.lo |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) |
Uwe Hermann394131e2008-10-18 21:14:13 +00001285 (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001286
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001287 wrmsr(DBE6x_MSR_DIVIL_BALL_OPTS, msr);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001288
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001289 cleanup_cpu_msr();
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001290
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001291 return 0;
1292}
1293
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001294/*
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001295 * Suited for:
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001296 * - ASUS A8AE-LE (Codename AmberineM; used in Compaq Presario 061)
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001297 * Datasheet(s) used:
1298 * - AMD document 43009 "AMD SB700/710/750 Register Reference Guide" rev. 1.00
1299 */
1300static int amd_sbxxx_gpio9_raise(void)
1301{
1302 struct pci_dev *dev;
1303 uint32_t reg;
1304
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001305 dev = pci_dev_find(0x1002, 0x4372); /* AMD SMBus controller */
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001306 if (!dev) {
1307 msg_perr("\nERROR: AMD SMBus Controller (0x4372) not found.\n");
1308 return -1;
1309 }
1310
1311 reg = pci_read_long(dev, 0xA8); /* GPIO_12_to_4_Cntrl CI_Reg: A8h-ABh */
1312 /* enable output (0: enable, 1: tristate):
1313 GPIO9 output enable is at bit 5 in 0xA9 */
1314 reg &= ~((uint32_t)1<<(8+5));
1315 /* raise:
1316 GPIO9 output register is at bit 5 in 0xA8 */
1317 reg |= (1<<5);
1318 pci_write_long(dev, 0xA8, reg);
1319
1320 return 0;
1321}
1322
1323/*
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001324 * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}.
Luc Verhaegenf5226912009-12-14 10:41:58 +00001325 */
1326static int intel_piix4_gpo_set(unsigned int gpo, int raise)
1327{
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001328 unsigned int gpo_byte, gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001329 struct pci_dev *dev;
1330 uint32_t tmp, base;
1331
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001332 /* GPO{0,8,27,28,30} are always available. */
1333 static const uint32_t nonmuxed_gpos = 0x58000101;
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001334
1335 static const struct {unsigned int reg, mask, value; } piix4_gpo[] = {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001336 {0},
1337 {0xB0, 0x0001, 0x0000}, /* GPO1... */
1338 {0xB0, 0x0001, 0x0000},
1339 {0xB0, 0x0001, 0x0000},
1340 {0xB0, 0x0001, 0x0000},
1341 {0xB0, 0x0001, 0x0000},
1342 {0xB0, 0x0001, 0x0000},
1343 {0xB0, 0x0001, 0x0000}, /* ...GPO7: GENCFG bit 0 */
1344 {0},
1345 {0xB0, 0x0100, 0x0000}, /* GPO9: GENCFG bit 8 */
1346 {0xB0, 0x0200, 0x0000}, /* GPO10: GENCFG bit 9 */
1347 {0xB0, 0x0400, 0x0000}, /* GPO11: GENCFG bit 10 */
1348 {0x4E, 0x0100, 0x0000}, /* GPO12... */
1349 {0x4E, 0x0100, 0x0000},
1350 {0x4E, 0x0100, 0x0000}, /* ...GPO14: XBCS bit 8 */
1351 {0xB2, 0x0002, 0x0002}, /* GPO15... */
1352 {0xB2, 0x0002, 0x0002}, /* ...GPO16: GENCFG bit 17 */
1353 {0xB2, 0x0004, 0x0004}, /* GPO17: GENCFG bit 18 */
1354 {0xB2, 0x0008, 0x0008}, /* GPO18: GENCFG bit 19 */
1355 {0xB2, 0x0010, 0x0010}, /* GPO19: GENCFG bit 20 */
1356 {0xB2, 0x0020, 0x0020}, /* GPO20: GENCFG bit 21 */
1357 {0xB2, 0x0040, 0x0040}, /* GPO21: GENCFG bit 22 */
1358 {0xB2, 0x1000, 0x1000}, /* GPO22... */
1359 {0xB2, 0x1000, 0x1000}, /* ...GPO23: GENCFG bit 28 */
1360 {0xB2, 0x2000, 0x2000}, /* GPO24: GENCFG bit 29 */
1361 {0xB2, 0x4000, 0x4000}, /* GPO25: GENCFG bit 30 */
1362 {0xB2, 0x8000, 0x8000}, /* GPO26: GENCFG bit 31 */
1363 {0},
1364 {0},
1365 {0x4E, 0x0100, 0x0000}, /* ...GPO29: XBCS bit 8 */
1366 {0}
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001367 };
1368
Luc Verhaegenf5226912009-12-14 10:41:58 +00001369 dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */
1370 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001371 msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +00001372 return -1;
1373 }
1374
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001375 /* Sanity check. */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001376 if (gpo > 30) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001377 msg_perr("\nERROR: Intel PIIX4 has no GPO%d.\n", gpo);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001378 return -1;
1379 }
1380
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001381 if ((((1 << gpo) & nonmuxed_gpos) == 0) &&
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001382 ((pci_read_word(dev, piix4_gpo[gpo].reg) & piix4_gpo[gpo].mask) !=
1383 piix4_gpo[gpo].value)) {
1384 msg_perr("\nERROR: PIIX4 GPO%d not programmed for output.\n", gpo);
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001385 return -1;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001386 }
1387
Luc Verhaegenf5226912009-12-14 10:41:58 +00001388 dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */
1389 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001390 msg_perr("\nERROR: Intel PIIX4 PM not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +00001391 return -1;
1392 }
1393
1394 /* PM IO base */
1395 base = pci_read_long(dev, 0x40) & 0x0000FFC0;
1396
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001397 gpo_byte = gpo >> 3;
1398 gpo_bit = gpo & 7;
1399 tmp = INB(base + 0x34 + gpo_byte); /* GPO register */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001400 if (raise)
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001401 tmp |= 0x01 << gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001402 else
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001403 tmp &= ~(0x01 << gpo_bit);
1404 OUTB(tmp, base + 0x34 + gpo_byte);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001405
1406 return 0;
1407}
1408
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001409/*
1410 * Suited for:
Joshua Roysd708fad2012-02-17 14:51:15 +00001411 * - ASUS OPLX-M
Mattias Mattsson85016b92010-09-01 01:21:34 +00001412 * - ASUS P2B-N
1413 */
1414static int intel_piix4_gpo18_lower(void)
1415{
1416 return intel_piix4_gpo_set(18, 0);
1417}
1418
1419/*
1420 * Suited for:
Mattias Mattssonc8ca3de2010-09-13 18:22:36 +00001421 * - MSI MS-6163 v2 (MS-6163 Pro): Intel 440BX + PIIX4E + Winbond W83977EF
1422 */
1423static int intel_piix4_gpo14_raise(void)
1424{
1425 return intel_piix4_gpo_set(14, 1);
1426}
1427
1428/*
1429 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001430 * - EPoX EP-BX3
Luc Verhaegenf5226912009-12-14 10:41:58 +00001431 */
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001432static int intel_piix4_gpo22_raise(void)
Luc Verhaegenf5226912009-12-14 10:41:58 +00001433{
1434 return intel_piix4_gpo_set(22, 1);
1435}
1436
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001437/*
1438 * Suited for:
Tim ter Laak4b933f02010-09-13 23:00:57 +00001439 * - abit BM6
1440 */
1441static int intel_piix4_gpo26_lower(void)
1442{
1443 return intel_piix4_gpo_set(26, 0);
1444}
1445
1446/*
1447 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001448 * - Intel SE440BX-2
Michael Karcher51cd0c92010-03-19 22:35:21 +00001449 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001450static int intel_piix4_gpo27_lower(void)
Michael Karcher51cd0c92010-03-19 22:35:21 +00001451{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001452 return intel_piix4_gpo_set(27, 0);
Michael Karcher51cd0c92010-03-19 22:35:21 +00001453}
1454
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001455/*
Mattias Mattsson2eaad632010-10-05 21:32:29 +00001456 * Suited for:
1457 * - Dell OptiPlex GX1
1458 */
1459static int intel_piix4_gpo30_lower(void)
1460{
1461 return intel_piix4_gpo_set(30, 0);
1462}
1463
1464/*
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001465 * Set a GPIO line on a given Intel ICH LPC controller.
Uwe Hermann93f66db2008-05-22 21:19:38 +00001466 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001467static int intel_ich_gpio_set(int gpio, int raise)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001468{
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001469 /* Table mapping the different Intel ICH LPC chipsets. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001470 static struct {
1471 uint16_t id;
1472 uint8_t base_reg;
1473 uint32_t bank0;
1474 uint32_t bank1;
1475 uint32_t bank2;
1476 } intel_ich_gpio_table[] = {
1477 {0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */
1478 {0x2420, 0x58, 0x0FE30000, 0, 0}, /* 82801AB (ICH0) */
1479 {0x2440, 0x58, 0x1BFF391B, 0, 0}, /* 82801BA (ICH2) */
1480 {0x244C, 0x58, 0x1A23399B, 0, 0}, /* 82801BAM (ICH2M) */
1481 {0x2450, 0x58, 0x1BFF0000, 0, 0}, /* 82801E (C-ICH) */
1482 {0x2480, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801CA (ICH3-S) */
1483 {0x248C, 0x58, 0x1A230000, 0x00000FFF, 0}, /* 82801CAM (ICH3-M) */
1484 {0x24C0, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801DB/DBL (ICH4/ICH4-L) */
1485 {0x24CC, 0x58, 0x1A030000, 0x00000FFF, 0}, /* 82801DBM (ICH4-M) */
1486 {0x24D0, 0x58, 0x1BFF0000, 0x00030305, 0}, /* 82801EB/ER (ICH5/ICH5R) */
1487 {0x2640, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FB/FR (ICH6/ICH6R) */
1488 {0x2641, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FBM (ICH6M) */
Stefan Tauner309dd2c2013-11-21 15:59:52 +00001489 {0x27B0, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GDH (ICH7 DH) */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001490 {0x27B8, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GB/GR (ICH7 Family) */
1491 {0x27B9, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GBM (ICH7-M) */
1492 {0x27BD, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GHM (ICH7-M DH) */
1493 {0x2810, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HB/HR (ICH8/R) */
1494 {0x2811, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HBM (ICH8M-E) */
1495 {0x2812, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HH (ICH8DH) */
1496 {0x2814, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HO (ICH8DO) */
1497 {0x2815, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HEM (ICH8M) */
1498 {0x2912, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IH (ICH9DH) */
1499 {0x2914, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IO (ICH9DO) */
1500 {0x2916, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IR (ICH9R) */
1501 {0x2917, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IEM (ICH9M-E) */
1502 {0x2918, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IB (ICH9) */
1503 {0x2919, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IBM (ICH9M) */
1504 {0x3A14, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JDO (ICH10DO) */
1505 {0x3A16, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIR (ICH10R) */
1506 {0x3A18, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIB (ICH10) */
1507 {0x3A1A, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JD (ICH10D) */
1508 {0, 0, 0, 0, 0} /* end marker */
1509 };
Uwe Hermann93f66db2008-05-22 21:19:38 +00001510
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001511 struct pci_dev *dev;
1512 uint16_t base;
1513 uint32_t tmp;
1514 int i, allowed;
1515
1516 /* First, look for a known LPC bridge */
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001517 for (dev = pacc->devices; dev; dev = dev->next) {
Carl-Daniel Hailfingerd175e062010-05-21 23:00:56 +00001518 uint16_t device_class;
1519 /* libpci before version 2.2.4 does not store class info. */
1520 device_class = pci_read_word(dev, PCI_CLASS_DEVICE);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001521 if ((dev->vendor_id == 0x8086) &&
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001522 (device_class == 0x0601)) { /* ISA bridge */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001523 /* Is this device in our list? */
1524 for (i = 0; intel_ich_gpio_table[i].id; i++)
1525 if (dev->device_id == intel_ich_gpio_table[i].id)
1526 break;
1527
1528 if (intel_ich_gpio_table[i].id)
1529 break;
1530 }
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001531 }
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001532
Uwe Hermann93f66db2008-05-22 21:19:38 +00001533 if (!dev) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001534 msg_perr("\nERROR: No known Intel LPC bridge found.\n");
Uwe Hermann93f66db2008-05-22 21:19:38 +00001535 return -1;
1536 }
1537
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001538 /*
1539 * According to the datasheets, all Intel ICHs have the GPIO bar 5:1
1540 * strapped to zero. From some mobile ICH9 version on, this becomes
1541 * 6:1. The mask below catches all.
1542 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001543 base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0;
Uwe Hermann93f66db2008-05-22 21:19:38 +00001544
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001545 /* Check whether the line is allowed. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001546 if (gpio < 32)
1547 allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01;
1548 else if (gpio < 64)
1549 allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01;
1550 else
1551 allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01;
1552
1553 if (!allowed) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001554 msg_perr("\nERROR: This Intel LPC bridge does not allow"
1555 " setting GPIO%02d\n", gpio);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001556 return -1;
1557 }
1558
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001559 msg_pdbg("\nIntel ICH LPC bridge: %sing GPIO%02d.\n",
1560 raise ? "Rais" : "Dropp", gpio);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001561
1562 if (gpio < 32) {
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001563 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001564 tmp = INL(base);
1565 /* ICH/ICH0 multiplexes 27/28 on the line set. */
1566 if ((gpio == 28) &&
1567 ((dev->device_id == 0x2410) || (dev->device_id == 0x2420)))
1568 tmp |= 1 << 27;
1569 else
1570 tmp |= 1 << gpio;
1571 OUTL(tmp, base);
1572
1573 /* As soon as we are talking to ICH8 and above, this register
1574 decides whether we can set the gpio or not. */
1575 if (dev->device_id > 0x2800) {
1576 tmp = INL(base);
1577 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001578 msg_perr("\nERROR: This Intel LPC bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001579 " does not allow setting GPIO%02d\n",
1580 gpio);
1581 return -1;
1582 }
1583 }
1584
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001585 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001586 tmp = INL(base + 0x04);
1587 tmp &= ~(1 << gpio);
1588 OUTL(tmp, base + 0x04);
1589
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001590 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001591 tmp = INL(base + 0x0C);
1592 if (raise)
1593 tmp |= 1 << gpio;
1594 else
1595 tmp &= ~(1 << gpio);
1596 OUTL(tmp, base + 0x0C);
1597 } else if (gpio < 64) {
1598 gpio -= 32;
1599
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001600 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001601 tmp = INL(base + 0x30);
1602 tmp |= 1 << gpio;
1603 OUTL(tmp, base + 0x30);
1604
1605 /* As soon as we are talking to ICH8 and above, this register
1606 decides whether we can set the gpio or not. */
1607 if (dev->device_id > 0x2800) {
1608 tmp = INL(base + 30);
1609 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001610 msg_perr("\nERROR: This Intel LPC bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001611 " does not allow setting GPIO%02d\n",
1612 gpio + 32);
1613 return -1;
1614 }
1615 }
1616
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001617 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001618 tmp = INL(base + 0x34);
1619 tmp &= ~(1 << gpio);
1620 OUTL(tmp, base + 0x34);
1621
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001622 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001623 tmp = INL(base + 0x38);
1624 if (raise)
1625 tmp |= 1 << gpio;
1626 else
1627 tmp &= ~(1 << gpio);
1628 OUTL(tmp, base + 0x38);
1629 } else {
1630 gpio -= 64;
1631
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001632 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001633 tmp = INL(base + 0x40);
1634 tmp |= 1 << gpio;
1635 OUTL(tmp, base + 0x40);
1636
1637 tmp = INL(base + 40);
1638 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001639 msg_perr("\nERROR: This Intel LPC bridge does "
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001640 "not allow setting GPIO%02d\n", gpio + 64);
1641 return -1;
1642 }
1643
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001644 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001645 tmp = INL(base + 0x44);
1646 tmp &= ~(1 << gpio);
1647 OUTL(tmp, base + 0x44);
1648
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001649 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001650 tmp = INL(base + 0x48);
1651 if (raise)
1652 tmp |= 1 << gpio;
1653 else
1654 tmp &= ~(1 << gpio);
1655 OUTL(tmp, base + 0x48);
1656 }
Uwe Hermann93f66db2008-05-22 21:19:38 +00001657
1658 return 0;
1659}
1660
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001661/*
1662 * Suited for:
1663 * - abit IP35: Intel P35 + ICH9R
1664 * - abit IP35 Pro: Intel P35 + ICH9R
Joshua Roysac8b2a12011-08-11 04:21:34 +00001665 * - ASUS P5LD2
Idwer Vollering4d0cde12012-09-07 08:27:46 +00001666 * - ASUS P5LD2-VM
Stefan Tauner309dd2c2013-11-21 15:59:52 +00001667 * - ASUS P5LD2-VM DH
Uwe Hermann93f66db2008-05-22 21:19:38 +00001668 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001669static int intel_ich_gpio16_raise(void)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001670{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001671 return intel_ich_gpio_set(16, 1);
Uwe Hermann93f66db2008-05-22 21:19:38 +00001672}
1673
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001674/*
1675 * Suited for:
1676 * - HP Puffer2-UL8E (ASUS PTGD-LA OEM): LGA775 + 915 + ICH6
Michael Karchere57957c2010-07-24 11:14:37 +00001677 */
1678static int intel_ich_gpio18_raise(void)
1679{
1680 return intel_ich_gpio_set(18, 1);
1681}
1682
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001683/*
1684 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001685 * - MSI MS-7046: LGA775 + 915P + ICH6
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001686 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001687static int intel_ich_gpio19_raise(void)
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001688{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001689 return intel_ich_gpio_set(19, 1);
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001690}
1691
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001692/*
Luc Verhaegen6c5d4cc2009-11-28 18:26:21 +00001693 * Suited for:
Stefan Tauner027e0182012-05-02 19:48:21 +00001694 * - ASUS P5BV-R: LGA775 + 3200 + ICH7
1695 */
1696static int intel_ich_gpio20_raise(void)
1697{
1698 return intel_ich_gpio_set(20, 1);
1699}
1700
1701/*
1702 * Suited for:
Stefan Taunereb582572012-09-21 12:52:50 +00001703 * - ASUS CUSL2-C: Intel socket370 + 815 + ICH2
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001704 * - ASUS P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2
1705 * - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5
Michael Karcherf4b58792010-09-10 14:54:18 +00001706 * - ASUS P4P800: Intel socket478 + 865PE + ICH5R
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001707 * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R
Diego Elio Pettenòc6f71462011-03-06 22:52:55 +00001708 * - ASUS P4P800-VM: Intel socket478 + 865PE + ICH5R
Stefan Taunereb582572012-09-21 12:52:50 +00001709 * - ASUS P4P800-X: Intel socket478 + 865PE + ICH5R
Michael Karcher4a23e442010-09-10 14:46:46 +00001710 * - ASUS P5GD1 Pro: Intel LGA 775 + 915P + ICH6R
Joshua Roys1fd4f9e2011-08-11 05:47:32 +00001711 * - ASUS P5GD2 Premium: Intel LGA775 + 915G + ICH6R
Joshua Roysb1d980f2010-09-13 14:02:22 +00001712 * - ASUS P5GDC Deluxe: Intel socket775 + 915P + ICH6R
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001713 * - ASUS P5PE-VM: Intel LGA775 + 865G + ICH5
Stefan Taunerded71e52012-03-10 19:22:13 +00001714 * - ASUS TUSL2-C: Intel socket370 + 815 + ICH2
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001715 * - Samsung Polaris 32: socket478 + 865P + ICH5
Peter Stuge09c13332009-02-02 22:55:26 +00001716 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001717static int intel_ich_gpio21_raise(void)
Peter Stuge09c13332009-02-02 22:55:26 +00001718{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001719 return intel_ich_gpio_set(21, 1);
Peter Stuge09c13332009-02-02 22:55:26 +00001720}
1721
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001722/*
Michael Karcher03b80e92010-03-07 16:32:32 +00001723 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001724 * - ASUS P4B266: socket478 + Intel 845D + ICH2
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001725 * - ASUS P4B533-E: socket478 + 845E + ICH4
1726 * - ASUS P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2
Michael Karcherbfd89a52012-02-12 00:13:14 +00001727 * - TriGem Anaheim-3: socket370 + Intel 810 + ICH
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001728 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001729static int intel_ich_gpio22_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001730{
1731 return intel_ich_gpio_set(22, 1);
1732}
1733
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001734/*
1735 * Suited for:
Stefan Tauner716e0982011-07-25 20:38:52 +00001736 * - ASUS A8Jm (laptop): Intel 945 + ICH7
Michael Karcher14ab8d42011-08-25 14:06:50 +00001737 * - ASUS P5LP-LE used in ...
1738 * - HP Media Center m7270.fr Desktop PC as "Lithium-UL8E"
1739 * - Epson Endeavor MT7700
Stefan Tauner716e0982011-07-25 20:38:52 +00001740 */
1741static int intel_ich_gpio34_raise(void)
1742{
1743 return intel_ich_gpio_set(34, 1);
1744}
1745
1746/*
1747 * Suited for:
Stefan Taunerc6782182012-01-19 17:50:32 +00001748 * - AOpen i945GMx-VFX: Intel 945GM + ICH7-M used in ...
Paul Menzelac427b22012-02-16 21:07:07 +00001749 * - FSC ESPRIMO Q5010 (SMBIOS: D2544-B1)
Stefan Taunerc6782182012-01-19 17:50:32 +00001750 */
1751static int intel_ich_gpio38_raise(void)
1752{
1753 return intel_ich_gpio_set(38, 1);
1754}
1755
1756/*
1757 * Suited for:
Joshua Roysc73e2812011-07-09 19:46:53 +00001758 * - ASUS M6Ne (laptop): socket 479M (guessed) + Intel 855PM + ICH4-M
1759 */
1760static int intel_ich_gpio43_raise(void)
1761{
1762 return intel_ich_gpio_set(43, 1);
1763}
1764
1765/*
1766 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001767 * - HP Vectra VL400: 815 + ICH + PC87360
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001768 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001769static int board_hp_vl400(void)
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001770{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001771 int ret;
1772 ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */
1773 if (!ret)
Michael Karchercba52de2011-03-06 12:07:19 +00001774 ret = pc8736x_gpio_set(PC87360_ID, 0x09, 1); /* #WP ? */
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001775 if (!ret)
Michael Karchercba52de2011-03-06 12:07:19 +00001776 ret = pc8736x_gpio_set(PC87360_ID, 0x27, 1); /* #TBL */
1777 return ret;
1778}
1779
1780/*
1781 * Suited for:
1782 * - HP e-Vectra P2706T: 810E + ICH + PC87364
1783 */
1784static int board_hp_p2706t(void)
1785{
1786 int ret;
1787 ret = pc8736x_gpio_set(PC87364_ID, 0x25, 1);
1788 if (!ret)
1789 ret = pc8736x_gpio_set(PC87364_ID, 0x26, 1);
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001790 return ret;
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001791}
1792
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001793/*
Luc Verhaegen1265d8d2009-11-28 18:16:31 +00001794 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001795 * - Dell PowerEdge 1850: Intel PPGA604 + E7520 + ICH5R
1796 * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R
1797 * - ASRock 775i65G: Intel LGA 775 + 865G + ICH5
Uwe Hermann742999c2010-12-02 21:57:42 +00001798 * - MSI MS-6391 (845 Pro4): Intel Socket478 + 845 + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001799 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001800static int intel_ich_gpio23_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001801{
1802 return intel_ich_gpio_set(23, 1);
1803}
1804
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001805/*
1806 * Suited for:
Michael Karcher39dcdec2010-10-05 17:29:35 +00001807 * - GIGABYTE GA-6IEM: Intel Socket370 + i815 + ICH2
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001808 * - GIGABYTE GA-8IRML: Intel Socket478 + i845 + ICH2
Michael Karcherc7a1ffb2010-07-24 22:27:29 +00001809 */
1810static int intel_ich_gpio25_raise(void)
1811{
1812 return intel_ich_gpio_set(25, 1);
1813}
1814
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001815/*
1816 * Suited for:
1817 * - IBASE MB899: i945GM + ICH7
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001818 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001819static int intel_ich_gpio26_raise(void)
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001820{
1821 return intel_ich_gpio_set(26, 1);
1822}
1823
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001824/*
1825 * Suited for:
Stefan Tauner98546c92012-11-05 12:20:29 +00001826 * - ASUS DSAN-DX
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001827 * - P4SD-LA (HP OEM): i865 + ICH5
Joshua Roys9d9a1042011-06-13 16:59:01 +00001828 * - GIGABYTE GA-8IP775: 865P + ICH5
Michael Karcherc8613242010-08-13 12:49:01 +00001829 * - GIGABYTE GA-8PE667 Ultra 2: socket 478 + i845PE + ICH4
Maciej Pijanka6add0942011-06-09 20:59:30 +00001830 * - MSI MS-6788-40 (aka 848P Neo-V)
Michael Karcher87c90992010-07-24 11:03:48 +00001831 */
Idwer Vollering19dceac2010-07-24 18:47:45 +00001832static int intel_ich_gpio32_raise(void)
Michael Karcher87c90992010-07-24 11:03:48 +00001833{
1834 return intel_ich_gpio_set(32, 1);
1835}
1836
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001837/*
1838 * Suited for:
Joshua Roys7225ccd2011-05-18 01:32:16 +00001839 * - AOpen i975Xa-YDG: i975X + ICH7 + W83627EHF
1840 */
1841static int board_aopen_i975xa_ydg(void)
1842{
1843 int ret;
1844
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001845 /* Vendor BIOS ends up in LDN6... maybe the board enable is wrong,
Joshua Roys7225ccd2011-05-18 01:32:16 +00001846 * or perhaps it's not needed at all?
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001847 * The regs it tries to touch are 0xF0, 0xF1, 0xF2 which means if it
1848 * were in the right LDN, it would have to be GPIO1 or GPIO3.
Joshua Roys7225ccd2011-05-18 01:32:16 +00001849 */
1850/*
1851 ret = winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, x, 0)
1852 if (!ret)
1853*/
1854 ret = intel_ich_gpio_set(33, 1);
1855
1856 return ret;
1857}
1858
1859/*
1860 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001861 * - Acorp 6A815EPD: socket 370 + intel 815 + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001862 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001863static int board_acorp_6a815epd(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001864{
1865 int ret;
1866
1867 /* Lower Blocks Lock -- pin 7 of PLCC32 */
1868 ret = intel_ich_gpio_set(22, 1);
1869 if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */
1870 ret = intel_ich_gpio_set(23, 1);
1871
1872 return ret;
1873}
1874
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001875/*
1876 * Suited for:
1877 * - Kontron 986LCD-M: Socket478 + 915GM + ICH7R
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001878 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001879static int board_kontron_986lcd_m(void)
Stefan Reinauerac378972008-03-17 22:59:40 +00001880{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001881 int ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001882
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001883 ret = intel_ich_gpio_set(34, 1); /* #TBL */
1884 if (!ret)
1885 ret = intel_ich_gpio_set(35, 1); /* #WP */
Stefan Reinauerac378972008-03-17 22:59:40 +00001886
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001887 return ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001888}
1889
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001890/*
1891 * Suited for:
1892 * - Soyo SY-7VCA: Pro133A + VT82C686
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001893 */
Michael Karcher06477332010-03-19 22:49:09 +00001894static int via_apollo_gpo_set(int gpio, int raise)
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001895{
Michael Karcher06477332010-03-19 22:49:09 +00001896 struct pci_dev *dev;
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001897 uint32_t base, tmp;
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001898
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001899 /* VT82C686 power management */
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001900 dev = pci_dev_find(0x1106, 0x3057);
1901 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001902 msg_perr("\nERROR: VT82C686 PM device not found.\n");
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001903 return -1;
1904 }
1905
Sean Nelson316a29f2010-05-07 20:09:04 +00001906 msg_pdbg("\nVIA Apollo ACPI: %sing GPIO%02d.\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001907 raise ? "Rais" : "Dropp", gpio);
Michael Karcher06477332010-03-19 22:49:09 +00001908
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001909 /* Select GPO function on multiplexed pins. */
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001910 tmp = pci_read_byte(dev, 0x54);
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001911 switch (gpio) {
1912 case 0:
1913 tmp &= ~0x03;
1914 break;
1915 case 1:
1916 tmp |= 0x04;
1917 break;
1918 case 2:
1919 tmp |= 0x08;
1920 break;
1921 case 3:
1922 tmp |= 0x10;
1923 break;
Michael Karcher06477332010-03-19 22:49:09 +00001924 }
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001925 pci_write_byte(dev, 0x54, tmp);
1926
1927 /* PM IO base */
1928 base = pci_read_long(dev, 0x48) & 0x0000FF00;
1929
1930 /* Drop GPO0 */
Michael Karcher06477332010-03-19 22:49:09 +00001931 tmp = INL(base + 0x4C);
1932 if (raise)
1933 tmp |= 1U << gpio;
1934 else
1935 tmp &= ~(1U << gpio);
1936 OUTL(tmp, base + 0x4C);
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001937
1938 return 0;
1939}
1940
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001941/*
1942 * Suited for:
1943 * - abit VT6X4: Pro133x + VT82C686A
Mattias Mattssone3df96e2010-08-15 22:43:23 +00001944 * - abit VA6: Pro133x + VT82C686A
Michael Karcher187a46a2010-03-19 22:30:49 +00001945 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001946static int via_apollo_gpo4_lower(void)
Michael Karcher187a46a2010-03-19 22:30:49 +00001947{
1948 return via_apollo_gpo_set(4, 0);
1949}
1950
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001951/*
1952 * Suited for:
1953 * - Soyo SY-7VCA: Pro133A + VT82C686
Michael Karcher06477332010-03-19 22:49:09 +00001954 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001955static int via_apollo_gpo0_lower(void)
Michael Karcher06477332010-03-19 22:49:09 +00001956{
1957 return via_apollo_gpo_set(0, 0);
1958}
1959
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001960/*
Michael Karchera08d0f22011-07-25 17:25:24 +00001961 * Enable some GPIO pin on SiS southbridge and enables SIO flash writes.
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001962 *
1963 * Suited for:
1964 * - MSI 651M-L: SiS651 / SiS962
Michael Karchera08d0f22011-07-25 17:25:24 +00001965 * - GIGABYTE GA-8SIMLH
Michael Karcher9f9e6132010-01-09 17:36:06 +00001966 */
Michael Karchera08d0f22011-07-25 17:25:24 +00001967static int sis_gpio0_raise_and_w836xx_memw(void)
Michael Karcher9f9e6132010-01-09 17:36:06 +00001968{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001969 struct pci_dev *dev;
Uwe Hermann43959702010-03-13 17:28:29 +00001970 uint16_t base, temp;
Michael Karcher9f9e6132010-01-09 17:36:06 +00001971
1972 dev = pci_dev_find(0x1039, 0x0962);
1973 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001974 msg_perr("Expected south bridge not found\n");
Michael Karcher9f9e6132010-01-09 17:36:06 +00001975 return 1;
1976 }
1977
Michael Karcher9f9e6132010-01-09 17:36:06 +00001978 base = pci_read_word(dev, 0x74);
1979 temp = INW(base + 0x68);
1980 temp &= ~(1 << 0); /* Make pin output? */
Michael Karcher0435dfd2010-01-09 23:31:13 +00001981 OUTW(temp, base + 0x68);
Michael Karcher9f9e6132010-01-09 17:36:06 +00001982
1983 temp = INW(base + 0x64);
1984 temp |= (1 << 0); /* Raise output? */
1985 OUTW(temp, base + 0x64);
1986
1987 w836xx_memw_enable(0x2E);
1988
1989 return 0;
1990}
1991
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001992/*
Michael Gold6d52e472009-06-19 13:00:24 +00001993 * Find the runtime registers of an SMSC Super I/O, after verifying its
1994 * chip ID.
1995 *
1996 * Returns the base port of the runtime register block, or 0 on error.
1997 */
1998static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id,
1999 uint8_t logical_device)
2000{
2001 uint16_t rt_port = 0;
2002
2003 /* Verify the chip ID. */
Uwe Hermann1432a602009-06-28 23:26:37 +00002004 OUTB(0x55, sio_port); /* Enable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00002005 if (sio_read(sio_port, 0x20) != chip_id) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002006 msg_perr("\nERROR: SMSC Super I/O not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +00002007 goto out;
2008 }
2009
2010 /* If the runtime block is active, get its address. */
2011 sio_write(sio_port, 0x07, logical_device);
2012 if (sio_read(sio_port, 0x30) & 1) {
2013 rt_port = (sio_read(sio_port, 0x60) << 8)
2014 | sio_read(sio_port, 0x61);
2015 }
2016
2017 if (rt_port == 0) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002018 msg_perr("\nERROR: "
Michael Gold6d52e472009-06-19 13:00:24 +00002019 "Super I/O runtime interface not available.\n");
2020 }
2021out:
Uwe Hermann1432a602009-06-28 23:26:37 +00002022 OUTB(0xaa, sio_port); /* Disable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00002023 return rt_port;
2024}
2025
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002026/*
2027 * Disable write protection on the Mitac 6513WU. WP# on the FWH is
Michael Gold6d52e472009-06-19 13:00:24 +00002028 * connected to GP30 on the Super I/O, and TBL# is always high.
2029 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00002030static int board_mitac_6513wu(void)
Michael Gold6d52e472009-06-19 13:00:24 +00002031{
2032 struct pci_dev *dev;
2033 uint16_t rt_port;
2034 uint8_t val;
2035
2036 dev = pci_dev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */
2037 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002038 msg_perr("\nERROR: Intel 82801AA ISA bridge not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +00002039 return -1;
2040 }
2041
Uwe Hermann1432a602009-06-28 23:26:37 +00002042 rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa);
Michael Gold6d52e472009-06-19 13:00:24 +00002043 if (rt_port == 0)
2044 return -1;
2045
2046 /* Configure the GPIO pin. */
2047 val = INB(rt_port + 0x33); /* GP30 config */
Uwe Hermann1432a602009-06-28 23:26:37 +00002048 val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */
Michael Gold6d52e472009-06-19 13:00:24 +00002049 OUTB(val, rt_port + 0x33);
2050
2051 /* Disable write protection. */
2052 val = INB(rt_port + 0x4d); /* GP3 values */
Uwe Hermann1432a602009-06-28 23:26:37 +00002053 val |= 0x01; /* Set GP30 high. */
Michael Gold6d52e472009-06-19 13:00:24 +00002054 OUTB(val, rt_port + 0x4d);
2055
2056 return 0;
2057}
2058
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002059/*
2060 * Suited for:
Christoph Grenzd13a3942011-10-21 13:20:11 +00002061 * - abit AV8: Socket939 + K8T800Pro + VT8237
2062 */
2063static int board_abit_av8(void)
2064{
2065 uint8_t val;
2066
2067 /* Raise GPO pins GP22 & GP23 */
2068 val = INB(0x404E);
2069 val |= 0xC0;
2070 OUTB(val, 0x404E);
2071
2072 return 0;
2073}
2074
2075/*
2076 * Suited for:
Uwe Hermann45bd1442010-09-14 23:20:35 +00002077 * - ASUS A7V333: VIA KT333 + VT8233A + IT8703F
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002078 * - ASUS A7V8X: VIA KT400 + VT8235 + IT8703F
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002079 */
Uwe Hermann45bd1442010-09-14 23:20:35 +00002080static int it8703f_gpio51_raise(void)
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002081{
2082 uint16_t id, base;
2083 uint8_t tmp;
2084
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002085 /* Find the IT8703F. */
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002086 w836xx_ext_enter(0x2E);
2087 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
2088 w836xx_ext_leave(0x2E);
2089
2090 if (id != 0x8701) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002091 msg_perr("\nERROR: IT8703F Super I/O not found.\n");
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002092 return -1;
2093 }
2094
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002095 /* Get the GP567 I/O base. */
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002096 w836xx_ext_enter(0x2E);
2097 sio_write(0x2E, 0x07, 0x0C);
2098 base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
2099 w836xx_ext_leave(0x2E);
2100
2101 if (!base) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002102 msg_perr("\nERROR: Failed to read IT8703F Super I/O GPIO"
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002103 " Base.\n");
2104 return -1;
2105 }
2106
2107 /* Raise GP51. */
2108 tmp = INB(base);
2109 tmp |= 0x02;
2110 OUTB(tmp, base);
2111
2112 return 0;
2113}
2114
Luc Verhaegen72272912009-09-01 21:22:23 +00002115/*
Joshua Roysa2f37222011-11-14 13:00:12 +00002116 * General routine for raising/dropping GPIO lines on the ITE IT87xx.
Luc Verhaegen72272912009-09-01 21:22:23 +00002117 */
Joshua Roysa2f37222011-11-14 13:00:12 +00002118static int it87_gpio_set(unsigned int gpio, int raise)
Luc Verhaegen72272912009-09-01 21:22:23 +00002119{
Joshua Roysa2f37222011-11-14 13:00:12 +00002120 int allowed, sio;
Luc Verhaegen72272912009-09-01 21:22:23 +00002121 unsigned int port;
Joshua Roysa2f37222011-11-14 13:00:12 +00002122 uint16_t base, sioport;
Luc Verhaegen72272912009-09-01 21:22:23 +00002123 uint8_t tmp;
2124
Joshua Roysa2f37222011-11-14 13:00:12 +00002125 /* IT87 GPIO configuration table */
2126 static const struct it87cfg {
2127 uint16_t id;
2128 uint8_t base_reg;
2129 uint32_t bank0;
2130 uint32_t bank1;
2131 uint32_t bank2;
2132 } it87_gpio_table[] = {
2133 {0x8712, 0x62, 0xCFF3FC00, 0x00FCFF3F, 0},
2134 {0x8718, 0x62, 0xCFF37C00, 0xF3FCDF3F, 0x0000000F},
2135 {0, 0, 0, 0, 0} /* end marker */
2136 };
2137 const struct it87cfg *cfg = NULL;
Luc Verhaegen72272912009-09-01 21:22:23 +00002138
Joshua Roysa2f37222011-11-14 13:00:12 +00002139 /* Find the Super I/O in the probed list */
2140 for (sio = 0; sio < superio_count; sio++) {
2141 int i;
2142 if (superios[sio].vendor != SUPERIO_VENDOR_ITE)
2143 continue;
2144
2145 /* Is this device in our list? */
2146 for (i = 0; it87_gpio_table[i].id; i++)
2147 if (superios[sio].model == it87_gpio_table[i].id) {
2148 cfg = &it87_gpio_table[i];
2149 goto found;
2150 }
2151 }
2152
2153 if (cfg == NULL) {
2154 msg_perr("\nERROR: No IT87 Super I/O GPIO configuration "
2155 "found.\n");
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002156 return -1;
Luc Verhaegen72272912009-09-01 21:22:23 +00002157 }
2158
Joshua Roysa2f37222011-11-14 13:00:12 +00002159found:
2160 /* Check whether the gpio is allowed. */
2161 if (gpio < 32)
2162 allowed = (cfg->bank0 >> gpio) & 0x01;
2163 else if (gpio < 64)
2164 allowed = (cfg->bank1 >> (gpio - 32)) & 0x01;
2165 else if (gpio < 96)
2166 allowed = (cfg->bank2 >> (gpio - 64)) & 0x01;
2167 else
2168 allowed = 0;
Luc Verhaegen72272912009-09-01 21:22:23 +00002169
Joshua Roysa2f37222011-11-14 13:00:12 +00002170 if (!allowed) {
2171 msg_perr("\nERROR: IT%02X does not allow setting GPIO%02u.\n",
2172 cfg->id, gpio);
Luc Verhaegen72272912009-09-01 21:22:23 +00002173 return -1;
2174 }
2175
Joshua Roysa2f37222011-11-14 13:00:12 +00002176 /* Read the Simple I/O Base Address Register */
2177 sioport = superios[sio].port;
2178 enter_conf_mode_ite(sioport);
2179 sio_write(sioport, 0x07, 0x07);
2180 base = (sio_read(sioport, cfg->base_reg) << 8) |
2181 sio_read(sioport, cfg->base_reg + 1);
2182 exit_conf_mode_ite(sioport);
Luc Verhaegen72272912009-09-01 21:22:23 +00002183
2184 if (!base) {
Joshua Roysa2f37222011-11-14 13:00:12 +00002185 msg_perr("\nERROR: Failed to read IT87 Super I/O GPIO Base.\n");
Luc Verhaegen72272912009-09-01 21:22:23 +00002186 return -1;
2187 }
2188
Joshua Roysa2f37222011-11-14 13:00:12 +00002189 msg_pdbg("Using IT87 GPIO base 0x%04x\n", base);
2190
2191 port = gpio / 10 - 1;
2192 gpio %= 10;
2193
2194 /* set GPIO. */
Luc Verhaegen72272912009-09-01 21:22:23 +00002195 tmp = INB(base + port);
2196 if (raise)
Joshua Roysa2f37222011-11-14 13:00:12 +00002197 tmp |= 1 << gpio;
Luc Verhaegen72272912009-09-01 21:22:23 +00002198 else
Joshua Roysa2f37222011-11-14 13:00:12 +00002199 tmp &= ~(1 << gpio);
Luc Verhaegen72272912009-09-01 21:22:23 +00002200 OUTB(tmp, base + port);
2201
2202 return 0;
2203}
2204
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002205/*
Russ Dillbd622d12010-03-09 16:57:06 +00002206 * Suited for:
Joshua Roys8ca42552011-11-19 19:31:17 +00002207 * - ASUS A7N8X-VM/400: NVIDIA nForce2 IGP2 + IT8712F
2208 */
2209static int it8712f_gpio12_raise(void)
2210{
2211 return it87_gpio_set(12, 1);
2212}
2213
2214/*
2215 * Suited for:
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00002216 * - ASUS A7V600-X: VIA KT600 + VT8237 + IT8712F
2217 * - ASUS A7V8X-X: VIA KT400 + VT8235 + IT8712F
Luc Verhaegen72272912009-09-01 21:22:23 +00002218 */
Joshua Roysa2f37222011-11-14 13:00:12 +00002219static int it8712f_gpio31_raise(void)
Luc Verhaegen72272912009-09-01 21:22:23 +00002220{
Joshua Roysa2f37222011-11-14 13:00:12 +00002221 return it87_gpio_set(32, 1);
2222}
2223
2224/*
2225 * Suited for:
2226 * - ASUS P5N-D: NVIDIA MCP51 + IT8718F
2227 * - ASUS P5N-E SLI: NVIDIA MCP51 + IT8718F
2228 */
2229static int it8718f_gpio63_raise(void)
2230{
2231 return it87_gpio_set(63, 1);
Luc Verhaegen72272912009-09-01 21:22:23 +00002232}
2233
Ingo Feldschmid8a0f9b02012-01-31 06:51:56 +00002234/*
2235 * Suited for all boards with ambiguous DMI chassis information, which should be
2236 * whitelisted because they are known to work:
Stefan Tauner463dd692013-08-08 12:00:19 +00002237 * - ASRock IMB-A180(-H)
Stefan Taunerdbac46c2013-08-13 22:10:41 +00002238 * - Intel D945GCNL
Ingo Feldschmid8a0f9b02012-01-31 06:51:56 +00002239 * - MSC Q7 Tunnel Creek Module (Q7-TCTC)
2240 */
2241static int p2_not_a_laptop(void)
2242{
2243 /* label this board as not a laptop */
2244 is_laptop = 0;
2245 msg_pdbg("Laptop detection overridden by P2 board enable.\n");
2246 return 0;
2247}
2248
Stefan Tauner98feaa52012-09-25 21:08:41 +00002249/*
2250 * Suited for all laptops, which are known to *not* have interfering embedded controllers.
2251 */
2252static int p2_whitelist_laptop(void)
2253{
2254 is_laptop = 1;
2255 laptop_ok = 1;
2256 msg_pdbg("Whitelisted laptop detected.\n");
2257 return 0;
2258}
2259
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00002260#endif
2261
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002262/*
Uwe Hermannd0e347d2009-10-06 13:00:00 +00002263 * Below is the list of boards which need a special "board enable" code in
2264 * flashrom before their ROM chip can be accessed/written to.
2265 *
2266 * NOTE: Please add boards that _don't_ need such enables or don't work yet
2267 * to the respective tables in print.c. Thanks!
2268 *
Stefan Tauner2c5b65e2013-10-26 17:02:03 +00002269 * We use 2 sets of PCI IDs here, you're free to choose which is which. This
Uwe Hermannffec5f32007-08-23 16:08:21 +00002270 * is to provide a very high degree of certainty when matching a board on
2271 * the basis of subsystem/card IDs. As not every vendor handles
2272 * subsystem/card IDs in a sane manner.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002273 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00002274 * Keep the second set NULLed if it should be ignored. Keep the subsystem IDs
Stefan Tauner2c5b65e2013-10-26 17:02:03 +00002275 * and the dmi identifier NULLed if they don't identify the board fully to disable autodetection.
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00002276 * But please take care to provide an as complete set of pci ids as possible;
2277 * autodetection is the preferred behaviour and we would like to make sure that
2278 * matches are unique.
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00002279 *
Michael Karcher6701ee82010-01-20 14:14:11 +00002280 * If PCI IDs are not sufficient for board matching, the match can be further
2281 * constrained by a string that has to be present in the DMI database for
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00002282 * the baseboard or the system entry. The pattern is matched by case sensitive
Michael Karcher6701ee82010-01-20 14:14:11 +00002283 * substring match, unless it is anchored to the beginning (with a ^ in front)
2284 * or the end (with a $ at the end). Both anchors may be specified at the
2285 * same time to match the full field.
2286 *
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00002287 * When a board is matched through DMI, the first and second main PCI IDs
2288 * and the first subsystem PCI ID have to match as well. If you specify the
2289 * first subsystem ID as 0x0:0x0, the DMI matching code expects that the
2290 * subsystem ID of that device is indeed zero.
2291 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00002292 * The coreboot ids are used two fold. When running with a coreboot firmware,
2293 * the ids uniquely matches the coreboot board identification string. When a
2294 * legacy bios is installed and when autodetection is not possible, these ids
Carl-Daniel Hailfinger2d927fb2012-01-04 00:48:27 +00002295 * can be used to identify the board through the -p internal:mainboard=
2296 * programmer parameter.
Luc Verhaegenc5210162009-04-20 12:38:17 +00002297 *
2298 * When a board is identified through its coreboot ids (in both cases), the
2299 * main pci ids are still required to match, as a safeguard.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002300 */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002301
Uwe Hermanndeeebe22009-05-08 16:23:34 +00002302/* Please keep this list alphabetically ordered by vendor/board name. */
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002303const struct board_match board_matches[] = {
Uwe Hermann5ab88892009-06-21 20:50:22 +00002304
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002305 /* first pci-id set [4], second pci-id set [4], dmi identifier, coreboot id [2], phase, vendor name, board name max_rom_... OK? flash enable */
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00002306#if defined(__i386__) || defined(__x86_64__)
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002307 {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, P3, "abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise},
Christoph Grenzd13a3942011-10-21 13:20:11 +00002308 {0x1106, 0x0282, 0x147B, 0x1415, 0x1106, 0x3227, 0x147B, 0x1415, "^AV8 ", NULL, NULL, P3, "abit", "AV8", 0, OK, board_abit_av8},
Stefan Tauner2c5b65e2013-10-26 17:02:03 +00002309 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, NULL /* "^I440BX-W977$" */, "abit", "bf6", P3, "abit", "BF6", 0, OK, intel_piix4_gpo26_lower},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002310 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^i440BX-W977 (BM6)$", NULL, NULL, P3, "abit", "BM6", 0, OK, intel_piix4_gpo26_lower},
2311 {0x8086, 0x24d3, 0x147b, 0x1014, 0x8086, 0x2578, 0x147b, 0x1014, NULL, NULL, NULL, P3, "abit", "IC7", 0, NT, intel_ich_gpio23_raise},
2312 {0x8086, 0x2930, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, P3, "abit", "IP35", 0, OK, intel_ich_gpio16_raise},
2313 {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, P3, "abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise},
Stefan Tauner24c38df2012-08-11 02:33:20 +00002314 {0x10de, 0x0050, 0x147b, 0x1c1a, 0x10de, 0x0052, 0x147b, 0x1c1a, NULL, NULL, NULL, P3, "abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002315 {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, P3, "abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise},
Paul Menzelac427b22012-02-16 21:07:07 +00002316 {0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0260, 0x147b, 0x1c26, NULL, NULL, NULL, P3, "abit", "NF-M2 nView", 0, OK, nvidia_mcp_gpio4_lower},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002317 {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, "(VA6)$", NULL, NULL, P3, "abit", "VA6", 0, OK, via_apollo_gpo4_lower},
2318 {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", P3, "abit", "VT6X4", 0, OK, via_apollo_gpo4_lower},
2319 {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, P3, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd},
Stefan Tauner24c38df2012-08-11 02:33:20 +00002320 {0x1022, 0x746B, 0, 0, 0x1022, 0x7460, 0, 0, NULL, "AGAMI", "ARUMA", P3, "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002321 {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, P3, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e},
2322 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", P3, "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x},
2323 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", P3, "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x},
Stefan Taunerc6782182012-01-19 17:50:32 +00002324 {0x8086, 0x27b9, 0xa0a0, 0x0632, 0x8086, 0x27da, 0xa0a0, 0x0632, NULL, NULL, NULL, P3, "AOpen", "i945GMx-VFX", 0, OK, intel_ich_gpio38_raise},
Joshua Roys7225ccd2011-05-18 01:32:16 +00002325 {0x8086, 0x277c, 0xa0a0, 0x060b, 0x8086, 0x27da, 0xa0a0, 0x060b, NULL, NULL, NULL, P3, "AOpen", "i975Xa-YDG", 0, OK, board_aopen_i975xa_ydg},
Stefan Taunerc2eec2c2014-05-03 21:33:01 +00002326 {0x8086, 0x27A0, 0x8086, 0x7270, 0x8086, 0x27B9, 0x8086, 0x7270, "^MacBook2,1$", NULL, NULL, P2, "Apple", "MacBook2,1", 0, OK, p2_whitelist_laptop},
Joshua Roysea3aed02011-11-16 22:08:11 +00002327 {0x8086, 0x27b8, 0x1849, 0x27b8, 0x8086, 0x27da, 0x1849, 0x27da, "^ConRoeXFire-eSATA2", NULL, NULL, P3, "ASRock", "ConRoeXFire-eSATA2", 0, OK, intel_ich_gpio16_raise},
Stefan Tauner463dd692013-08-08 12:00:19 +00002328 {0x1022, 0x1536, 0x1849, 0x1536, 0x1022, 0x780e, 0x1849, 0x780e, "^Kabini CRB$", NULL, NULL, P2, "ASRock", "IMB-A180(-H)", 0, OK, p2_not_a_laptop},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002329 {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41 $", NULL, NULL, P3, "ASRock", "K7S41", 0, OK, w836xx_memw_enable_2e},
Pawel Rozanski1d233072011-06-19 16:52:48 +00002330 {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41GX$", NULL, NULL, P3, "ASRock", "K7S41GX", 0, OK, w836xx_memw_enable_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002331 {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, P3, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise},
2332 {0x8086, 0x2570, 0x1849, 0x2570, 0x8086, 0x24d3, 0x1849, 0x24d0, NULL, NULL, NULL, P3, "ASRock", "775i65G", 0, OK, intel_ich_gpio23_raise},
Joshua Roys8ca42552011-11-19 19:31:17 +00002333 {0x10DE, 0x0060, 0x1043, 0x80AD, 0x10DE, 0x01E0, 0x1043, 0x80C0, NULL, NULL, NULL, P3, "ASUS", "A7N8X-VM/400", 0, OK, it8712f_gpio12_raise},
Joshua Roysa2f37222011-11-14 13:00:12 +00002334 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, P3, "ASUS", "A7V600-X", 0, OK, it8712f_gpio31_raise},
François Revol495fc2c2014-03-14 08:10:02 +00002335 {0x1106, 0x3177, 0x1043, 0x80F9, 0x1106, 0x3205, 0x1043, 0x80F9, NULL, NULL, NULL, P3, "ASUS", "A7V8X-MX", 0, OK, w836xx_memw_enable_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002336 {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, P3, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e},
2337 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V8X", 0, OK, it8703f_gpio51_raise},
2338 {0x1106, 0x3099, 0x1043, 0x807F, 0x1106, 0x3147, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V333", 0, OK, it8703f_gpio51_raise},
Joshua Roysa2f37222011-11-14 13:00:12 +00002339 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, P3, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio31_raise},
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00002340 {0x1002, 0x4372, 0x103c, 0x2a26, 0x1002, 0x4377, 0x103c, 0x2a26, NULL, NULL, NULL, P3, "ASUS", "A8AE-LE", 0, OK, amd_sbxxx_gpio9_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002341 {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, P3, "ASUS", "A8Jm", 0, NT, intel_ich_gpio34_raise},
Stefan Taunera9cbbac2011-08-07 13:17:20 +00002342 {0x10DE, 0x0260, 0x103C, 0x2A34, 0x10DE, 0x0264, 0x103C, 0x2A34, "NODUSM3", NULL, NULL, P3, "ASUS", "A8M2N-LA (NodusM3-GL8E)", 0, OK, nvidia_mcp_gpio0_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002343 {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI2L", NULL, NULL, P3, "ASUS", "A8N-LA (Nagami-GL8E)", 0, OK, nvidia_mcp_gpio0_raise},
Stefan Taunerff80e682011-07-20 16:34:18 +00002344 {0x10de, 0x0264, 0x1043, 0x81bc, 0x10de, 0x02f0, 0x1043, 0x81cd, NULL, NULL, NULL, P3, "ASUS", "A8N-VM CSM", 0, OK, w83627ehf_gpio22_raise_2e},
Stefan Tauner98546c92012-11-05 12:20:29 +00002345 {0x8086, 0x65c0, 0x1043, 0x8301, 0x8086, 0x2916, 0x1043, 0x82a6, "^DSAN-DX$", NULL, NULL, P3, "ASUS", "DSAN-DX", 0, NT, intel_ich_gpio32_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002346 {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, P3, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise},
2347 {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, P3, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise},
Joshua Roysc73e2812011-07-09 19:46:53 +00002348 {0x8086, 0x24cc, 0, 0, 0x8086, 0x24c3, 0x1043, 0x1869, "^M6Ne$", NULL, NULL, P3, "ASUS", "M6Ne", 0, NT, intel_ich_gpio43_raise},
Joshua Roysd708fad2012-02-17 14:51:15 +00002349 {0x8086, 0x7180, 0, 0, 0x8086, 0x7110, 0, 0, "^OPLX-M$", NULL, NULL, P3, "ASUS", "OPLX-M", 0, NT, intel_piix4_gpo18_lower},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002350 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^P2B-N$", NULL, NULL, P3, "ASUS", "P2B-N", 0, OK, intel_piix4_gpo18_lower},
2351 {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, P3, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise},
2352 {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, P3, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise},
2353 {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, P3, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise},
Joshua Roysa5f5a152011-11-15 08:08:15 +00002354 {0x8086, 0x2560, 0x103C, 0x2A00, 0x8086, 0x24C3, 0x103C, 0x2A01, "^Guppy", NULL, NULL, P3, "ASUS", "P4GV-LA (Guppy)", 0, OK, intel_ich_gpio21_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002355 {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, P3, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
2356 {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D5, 0x1043, 0x80F3, NULL, NULL, NULL, P3, "ASUS", "P4P800", 0, NT, intel_ich_gpio21_raise},
Stefan Taunereb582572012-09-21 12:52:50 +00002357 {0x8086, 0x2570, 0x1043, 0x80f2, 0x8086, 0x24d3, 0x1043, 0x80a6, "^P4P800-E$", NULL, NULL, P3, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
2358 {0x8086, 0x2570, 0x1043, 0x80a5, 0x8086, 0x24d3, 0x1043, 0x80a6, "^P4P800-VM$", NULL, NULL, P3, "ASUS", "P4P800-VM", 0, OK, intel_ich_gpio21_raise},
2359 {0x8086, 0x2570, 0x1043, 0x80f2, 0x8086, 0x24d3, 0x1043, 0x80a6, "^P4P800-X$", NULL, NULL, P3, "ASUS", "P4P800-X", 0, OK, intel_ich_gpio21_raise},
Stefan Taunerd3b98fb2013-03-04 01:41:56 +00002360 {0x8086, 0x2570, 0x1043, 0x80b2, 0x8086, 0x24c3, 0x1043, 0x8089, "^P4PE-X/TE$",NULL, NULL, P3, "ASUS", "P4PE-X/TE", 0, NT, intel_ich_gpio21_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002361 {0x1039, 0x0651, 0x1043, 0x8081, 0x1039, 0x0962, 0, 0, NULL, NULL, NULL, P3, "ASUS", "P4SC-E", 0, OK, it8707f_write_enable_2e},
2362 {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, P3, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise},
2363 {0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x5513, 0x1043, 0x8087, NULL, NULL, NULL, P3, "ASUS", "P4S800-MX", 512, OK, w836xx_memw_enable_2e},
2364 {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", P3, "ASUS", "P5A", 0, OK, board_asus_p5a},
Stefan Tauner027e0182012-05-02 19:48:21 +00002365 {0x8086, 0x27b8, 0x1043, 0x819e, 0x8086, 0x29f0, 0x1043, 0x82a5, "^P5BV-R$", NULL, NULL, P3, "ASUS", "P5BV-R", 0, OK, intel_ich_gpio20_raise},
Stefan Taunera4f14472011-10-22 22:01:09 +00002366 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, "^P5GD1 PRO$", NULL, NULL, P3, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise},
2367 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, "^P5GD1-VM$", NULL, NULL, P3, "ASUS", "P5GD1-VM/S", 0, OK, intel_ich_gpio21_raise},
2368 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, P3, "ASUS", "P5GD1(-VM)", 0, NT, intel_ich_gpio21_raise},
Joshua Roys1fd4f9e2011-08-11 05:47:32 +00002369 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GD2-Premium$", NULL, NULL, P3, "ASUS", "P5GD2 Premium", 0, OK, intel_ich_gpio21_raise},
Stefan Taunerd94d25d2012-07-28 03:17:15 +00002370 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x81a6, "^P5GD2-X$", NULL, NULL, P3, "ASUS", "P5GD2-X", 0, OK, intel_ich_gpio21_raise},
Stefan Taunera4f14472011-10-22 22:01:09 +00002371 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GDC-V$", NULL, NULL, P3, "ASUS", "P5GDC-V Deluxe", 0, OK, intel_ich_gpio21_raise},
2372 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GDC$", NULL, NULL, P3, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise},
2373 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, P3, "ASUS", "P5GD2/C variants", 0, NT, intel_ich_gpio21_raise},
Michael Karcher14ab8d42011-08-25 14:06:50 +00002374 {0x8086, 0x27b8, 0x103c, 0x2a22, 0x8086, 0x2770, 0x103c, 0x2a22, "^LITHIUM$", NULL, NULL, P3, "ASUS", "P5LP-LE (Lithium-UL8E)",0, OK, intel_ich_gpio34_raise},
2375 {0x8086, 0x27b8, 0x1043, 0x2a22, 0x8086, 0x2770, 0x1043, 0x2a22, "^P5LP-LE$", NULL, NULL, P3, "ASUS", "P5LP-LE (Epson OEM)", 0, OK, intel_ich_gpio34_raise},
Joshua Roys1fd4f9e2011-08-11 05:47:32 +00002376 {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, NT, intel_ich_gpio16_raise},
Idwer Vollering4d0cde12012-09-07 08:27:46 +00002377 {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2-VM$", NULL, NULL, P3, "ASUS", "P5LD2-VM", 0, NT, intel_ich_gpio16_raise},
Stefan Tauner309dd2c2013-11-21 15:59:52 +00002378 {0x8086, 0x27b0, 0x1043, 0x8179, 0x8086, 0x2770, 0x1043, 0x817a, "^P5LD2-VM DH$", NULL, NULL, P3, "ASUS", "P5LD2-VM DH", 0, OK, intel_ich_gpio16_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002379 {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, P3, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise},
Joshua Roysa2f37222011-11-14 13:00:12 +00002380 {0x10DE, 0x0260, 0x1043, 0x81BC, 0x10DE, 0x026C, 0x1043, 0x829E, "^P5N-D$", NULL, NULL, P3, "ASUS", "P5N-D", 0, OK, it8718f_gpio63_raise},
2381 {0x10DE, 0x0260, 0x1043, 0x81BC, 0x10DE, 0x026C, 0x1043, 0x8249, "^P5N-E SLI$",NULL, NULL, P3, "ASUS", "P5N-E SLI", 0, NT, it8718f_gpio63_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002382 {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, P3, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise},
Stefan Taunereb582572012-09-21 12:52:50 +00002383 {0x8086, 0x2443, 0x1043, 0x8027, 0x8086, 0x1130, 0x1043, 0x8027, "^CUSL2-C", NULL, NULL, P3, "ASUS", "CUSL2-C", 0, OK, intel_ich_gpio21_raise},
2384 {0x8086, 0x2443, 0x1043, 0x8027, 0x8086, 0x1130, 0x1043, 0x8027, "^TUSL2-C", NULL, NULL, P3, "ASUS", "TUSL2-C", 0, NT, intel_ich_gpio21_raise},
Corey Osgoodcbd56652013-09-10 10:42:48 +00002385 {0x1106, 0x3059, 0x1106, 0x4161, 0x1106, 0x3065, 0x1106, 0x0102, NULL, NULL, NULL, P3, "Bcom/Clientron", "WinNET P680", 0, OK, w836xx_memw_enable_2e},
Stefan Taunereb582572012-09-21 12:52:50 +00002386 {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3116, 0x1106, 0x3116, "^KM266-8235$", "biostar", "m7viq", P3, "Biostar", "M7VIQ", 0, NT, w83697xx_memw_enable_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002387 {0x10b7, 0x9055, 0x1028, 0x0082, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Dell", "OptiPlex GX1", 0, OK, intel_piix4_gpo30_lower},
2388 {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, P3, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise},
Tadas Slotkus3dcdc032012-08-25 03:53:12 +00002389 {0x1106, 0x3189, 0x1106, 0x3189, 0x1106, 0x3177, 0x1106, 0x3177, "^AD77", "dfi", "ad77", P3, "DFI", "AD77", 0, NT, w836xx_memw_enable_2e},
Stefan Taunere34e3e82013-01-01 00:06:51 +00002390 {0x1039, 0x6325, 0x1019, 0x0f05, 0x1039, 0x0016, 0, 0, NULL, NULL, NULL, P2, "Elitegroup", "A928", 0, OK, p2_whitelist_laptop},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002391 {0x10de, 0x03ea, 0x1019, 0x2602, 0x10de, 0x03e0, 0x1019, 0x2602, NULL, NULL, NULL, P3, "Elitegroup", "GeForce6100SM-M", 0, OK, board_ecs_geforce6100sm_m},
2392 {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, P3, "Elitegroup", "K7VTA3", 256, OK, NULL},
2393 {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, P3, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e},
Stefan Tauneraf4b1582011-08-06 16:16:33 +00002394 {0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, "8NPA7I", NULL, NULL, P3, "EPoX", "EP-8NPA7I", 0, OK, nvidia_mcp_gpio4_raise},
2395 {0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, "9NPA7I", NULL, NULL, P3, "EPoX", "EP-9NPA7I", 0, OK, nvidia_mcp_gpio4_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002396 {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, P3, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise},
2397 {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", P3, "EPoX", "EP-BX3", 0, NT, intel_piix4_gpo22_raise},
2398 {0x10de, 0x02f0, 0x105b, 0x0d01, 0x10de, 0x0264, 0x105b, 0x0d01, NULL, NULL, NULL, P3, "Foxconn", "6150K8MD-8EKRSH", 0, NT, nvidia_mcp_gpio2_raise},
2399 {0x8086, 0x2443, 0x8086, 0x2442, 0x8086, 0x1130, 0x8086, 0x1130, "^6IEM ", NULL, NULL, P3, "GIGABYTE", "GA-6IEM", 0, NT, intel_ich_gpio25_raise},
2400 {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-7ZM", 512, OK, NULL},
Joshua Roys9d9a1042011-06-13 16:59:01 +00002401 {0x8086, 0x2570, 0x1458, 0x2570, 0x8086, 0x24d0, 0, 0, "^8IP775/-G$",NULL, NULL, P3, "GIGABYTE", "GA-8IP775", 0, OK, intel_ich_gpio32_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002402 {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise},
2403 {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise},
Stefan Tauner716e0982011-07-25 20:38:52 +00002404 {0x1039, 0x0651, 0x1039, 0x0651, 0x1039, 0x7002, 0x1458, 0x5004, "^GA-8SIMLH$",NULL, NULL, P3, "GIGABYTE", "GA-8SIMLH", 0, OK, sis_gpio0_raise_and_w836xx_memw},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002405 {0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise},
2406 {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise},
Idwer Volleringd8a00a02011-06-13 16:58:54 +00002407 {0x10de, 0x00e4, 0x1458, 0x0c11, 0x10de, 0x00e0, 0x1458, 0x0c11, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8NS Pro-939", 0, NT, nvidia_mcp_gpio0a_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002408 {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise},
Idwer Volleringd8a00a02011-06-13 16:58:54 +00002409 {0x8086, 0x2415, 0x103c, 0x1250, 0x10b7, 0x9200, 0x103c, 0x1247, NULL, NULL, NULL, P3, "HP", "e-Vectra P2706T", 0, OK, board_hp_p2706t},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002410 {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", P3, "HP", "ProLiant DL145 G3", 0, OK, board_hp_dl145_g3_enable},
2411 {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", P3, "HP", "ProLiant DL165 G6", 0, OK, board_hp_dl165_g6_enable},
2412 {0x8086, 0x2580, 0x103c, 0x2a08, 0x8086, 0x2640, 0x103c, 0x2a0a, NULL, NULL, NULL, P3, "HP", "Puffer2-UL8E", 0, OK, intel_ich_gpio18_raise},
Idwer Volleringd8a00a02011-06-13 16:58:54 +00002413 {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, P3, "HP", "Vectra VL400", 0, OK, board_hp_vl400},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002414 {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, P3, "HP", "Vectra VL420 SFF", 0, OK, intel_ich_gpio22_raise},
2415 {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, "hp", "xw9400", P3, "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise},
2416 {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", P3, "IBASE", "MB899", 0, OK, intel_ich_gpio26_raise},
2417 {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, P3, "IBM", "x3455", 0, OK, board_ibm_x3455},
2418 {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, P3, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi},
Stefan Taunere34e3e82013-01-01 00:06:51 +00002419 {0x8086, 0x27b8, 0x8086, 0xd606, 0x8086, 0x2770, 0x8086, 0xd606, "^D945GCNL$", NULL, NULL, P2, "Intel", "D945GCNL", 0, OK, p2_not_a_laptop},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002420 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, P3, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower},
Stefan Tauner24c38df2012-08-11 02:33:20 +00002421 {0x1022, 0x7468, 0, 0, 0x1022, 0x7460, 0, 0, NULL, "iwill", "dk8_htx", P3, "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002422 {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", P3, "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m},
Stefan Taunerd7d423b2012-10-20 09:13:16 +00002423 {0x8086, 0x27a0, 0x17aa, 0x2015, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "Lenovo", "T60", 0, OK, p2_whitelist_laptop},
Stefan Tauner98feaa52012-09-25 21:08:41 +00002424 {0x8086, 0x27a0, 0x17aa, 0x2017, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "Lenovo", "T60(s)", 0, OK, p2_whitelist_laptop},
2425 {0x8086, 0x27a0, 0x17aa, 0x2017, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad X60", NULL, NULL, P2, "Lenovo", "X60(s)", 0, OK, p2_whitelist_laptop},
Stefan Tauner0554ca52013-07-25 22:54:25 +00002426 {0x8086, 0x3B07, 0x17AA, 0x2166, 0x8086, 0x3B30, 0x17AA, 0x2167, "^Lenovo X201", NULL, NULL, P2, "Lenovo", "X201", 0, OK, p2_whitelist_laptop},
Stefan Taunerc2eec2c2014-05-03 21:33:01 +00002427 {0x8086, 0x1E22, 0x17AA, 0x21FA, 0x8086, 0x1E55, 0x17AA, 0x21FA, "^ThinkPad X230", NULL, NULL, P2, "Lenovo", "X230", 0, OK, p2_whitelist_laptop},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002428 {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, P3, "Mitac", "6513WU", 0, OK, board_mitac_6513wu},
Stefan Taunerd7d423b2012-10-20 09:13:16 +00002429 {0x8086, 0x8186, 0x8086, 0x8186, 0x8086, 0x8800, 0, 0, "^MSC Vertriebs GmbH$", NULL, NULL, P2, "MSC", "Q7-TCTC", 0, OK, p2_not_a_laptop},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002430 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^MS-6163 (i440BX)$", NULL, NULL, P3, "MSI", "MS-6163 (MS-6163 Pro)", 0, OK, intel_piix4_gpo14_raise},
Stefan Taunerc2eec2c2014-05-03 21:33:01 +00002431 {0x8086, 0x244b, 0x1462, 0x3910, 0x8086, 0x2442, 0x1462, 0x3910, NULL, NULL, NULL, P3, "MSI", "MS-6391 (845 Pro4)", 0, OK, intel_ich_gpio23_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002432 {0x1039, 0x0745, 0, 0, 0x1039, 0x0018, 0, 0, "^MS-6561", NULL, NULL, P3, "MSI", "MS-6561 (745 Ultra)", 0, OK, w836xx_memw_enable_2e},
2433 {0x8086, 0x2560, 0x1462, 0x5770, 0x8086, 0x2562, 0x1462, 0x5778, NULL, NULL, NULL, P3, "MSI", "MS-6577 (Xenon)", 0, OK, w83627hf_gpio25_raise_2e},
2434 {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, P3, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v},
Stefan Taunerc2eec2c2014-05-03 21:33:01 +00002435 {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, "^MS-7094$", NULL, NULL, P3, "MSI", "MS-7094 (K8T Neo2-F V2.0)", 0, OK, w83627thf_gpio44_raise_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002436 {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, P3, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v},
2437 {0x1106, 0x3148, 0 , 0 , 0x1106, 0x3177, 0 , 0 , NULL, "msi", "ms6787", P3, "MSI", "MS-6787 (P4MAM-V/P4MAM-L)", 0, OK, w836xx_memw_enable_2e},
Maciej Pijanka6add0942011-06-09 20:59:30 +00002438 {0x8086, 0x24d3, 0x1462, 0x7880, 0x8086, 0x2570, 0, 0, NULL, NULL, NULL, P3, "MSI", "MS-6788-040 (848P NeoV)", 0, OK, intel_ich_gpio32_raise},
Michael Karchera08d0f22011-07-25 17:25:24 +00002439 {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, P3, "MSI", "MS-7005 (651M-L)", 0, OK, sis_gpio0_raise_and_w836xx_memw},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002440 {0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, P3, "MSI", "MS-7025 (K8N Neo2 Platinum)", 0, OK, nvidia_mcp_gpio0c_raise},
Stefan Tauner33366a02012-09-15 15:51:09 +00002441 {0x10DE, 0x00E0, 0x1462, 0x0300, 0x10DE, 0x00E1, 0x1462, 0x0300, NULL, NULL, NULL, P3, "MSI", "MS-7030 (K8N Neo Platinum)", 0, OK, nvidia_mcp_gpio0c_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002442 {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, P3, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002443 {0x1106, 0x3149, 0x1462, 0x7061, 0x1106, 0x3227, 0, 0, NULL, NULL, NULL, P3, "MSI", "MS-7061 (KM4M-V/KM4AM-V)", 0, OK, w836xx_memw_enable_2e},
Stefan Taunerc2eec2c2014-05-03 21:33:01 +00002444 {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, P3, "MSI", "MS-7125 (K8N Neo4(-F/-FI/-FX/Platinum))", 0, OK, nvidia_mcp_gpio2_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002445 {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", P3, "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio44_raise_4e},
2446 {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, P3, "MSI", "MS-7207 (K8NGM2-L)", 0, NT, nvidia_mcp_gpio2_raise},
Joshua Roys6e48a022012-06-29 23:07:14 +00002447 {0x10DE, 0x0360, 0x1462, 0x7250, 0x10DE, 0x0368, 0x1462, 0x7250, NULL, NULL, NULL, P3, "MSI", "MS-7250 (K9N SLI)", 0, OK, nvidia_mcp_gpio2_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002448 {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0},
Stefan Taunerc2eec2c2014-05-03 21:33:01 +00002449 {0x8086, 0x3B30, 0x1025, 0x0379, 0x8086, 0x3B09, 0x1025, 0x0379, "^EasyNote LM85$", NULL, NULL, P2, "Packard Bell","EasyNote LM85", 0, OK, p2_whitelist_laptop},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002450 {0x8086, 0x24d3, 0x144d, 0xb025, 0x8086, 0x1050, 0x144d, 0xb025, NULL, NULL, NULL, P3, "Samsung", "Polaris 32", 0, OK, intel_ich_gpio21_raise},
2451 {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", P3, "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e},
2452 {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, P3, "Shuttle", "AK38N", 256, OK, NULL},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002453 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, P3, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower},
Joshua Roysb992d342011-11-02 14:31:18 +00002454 {0x10de, 0x0364, 0x108e, 0x6676, 0x10de, 0x0369, 0x108e, 0x6676, "^Sun Ultra 40 M2", NULL, NULL, P3, "Sun", "Ultra 40 M2", 0, OK, board_sun_ultra_40_m2},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002455 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, P3, "Tekram", "P6Pro-A5", 256, OK, NULL},
2456 {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, P3, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e},
Michael Karcherbfd89a52012-02-12 00:13:14 +00002457 {0x8086, 0x7120, 0x109f, 0x3157, 0x8086, 0x2410, 0, 0, NULL, NULL, NULL, P3, "TriGem", "Anaheim-3", 0, OK, intel_ich_gpio22_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002458 {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, P3, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e},
2459 {0x1106, 0x0259, 0x1106, 0xAA07, 0x1106, 0x3227, 0x1106, 0xAA07, NULL, NULL, NULL, P3, "VIA", "EPIA EK", 0, NT, via_vt823x_gpio9_raise},
2460 {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, P3, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise},
2461 {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, P3, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise},
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00002462#endif
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002463 { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, P3, NULL, NULL, 0, NT, NULL}, /* end marker */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002464};
2465
Stefan Tauner600576b2014-06-12 22:57:36 +00002466int selfcheck_board_enables(void)
2467{
2468 if (board_matches[ARRAY_SIZE(board_matches) - 1].vendor_name != NULL) {
2469 msg_gerr("Board enables table miscompilation!\n");
2470 return 1;
2471 }
2472
2473 int ret = 0;
2474 unsigned int i;
2475 for (i = 0; i < ARRAY_SIZE(board_matches) - 1; i++) {
2476 const struct board_match *b = &board_matches[i];
2477 if (b->vendor_name == NULL || b->board_name == NULL) {
2478 msg_gerr("ERROR: Board enable #%d does not define a vendor and board name.\n"
2479 "Please report a bug at flashrom@flashrom.org\n", i);
2480 ret = 1;
2481 continue;
2482 }
2483 if ((b->first_vendor == 0 || b->first_device == 0 ||
2484 b->second_vendor == 0 || b->second_device == 0) ||
2485 ((b->lb_vendor == NULL) ^ (b->lb_part == NULL)) ||
2486 (b->max_rom_decode_parallel == 0 && b->enable == NULL)) {
2487 msg_gerr("ERROR: Board enable for %s %s is misdefined.\n"
2488 "Please report a bug at flashrom@flashrom.org\n",
2489 b->vendor_name, b->board_name);
2490 ret = 1;
2491 }
2492 }
2493 return ret;
2494}
2495
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002496/* Parse the <vendor>:<board> string specified by the user as part of -p internal:mainboard=<vendor>:<board>.
2497 * Parameters vendor and model will be overwritten. Returns 0 on success.
2498 * Note: strtok modifies the original string, so we work on a copy and allocate memory for the results.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002499 */
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002500int board_parse_parameter(const char *boardstring, const char **vendor, const char **model)
2501{
2502 /* strtok may modify the original string. */
2503 char *tempstr = strdup(boardstring);
2504 char *tempstr2 = NULL;
2505 strtok(tempstr, ":");
2506 tempstr2 = strtok(NULL, ":");
2507 if (tempstr == NULL || tempstr2 == NULL) {
2508 free(tempstr);
2509 msg_pinfo("Please supply the board vendor and model name with the "
2510 "-p internal:mainboard=<vendor>:<model> option.\n");
2511 return 1;
2512 }
2513 *vendor = strdup(tempstr);
2514 *model = strdup(tempstr2);
2515 msg_pspew("-p internal:mainboard: vendor=\"%s\", model=\"%s\"\n", tempstr, tempstr2);
2516 free(tempstr);
2517 return 0;
2518}
2519
2520/*
2521 * Match boards on vendor and model name.
2522 * Hint: the parameters can come either from the coreboot table or the command line (i.e. the user).
2523 * Require main PCI IDs to match too as extra safety.
2524 * vendor and model must be non-NULL!
2525 */
2526static const struct board_match *board_match_name(const char *vendor, const char *model)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002527{
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002528 const struct board_match *board = board_matches;
2529 const struct board_match *partmatch = NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002530
Uwe Hermanna93045c2009-05-09 00:47:04 +00002531 for (; board->vendor_name; board++) {
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002532 if (!board->lb_vendor || strcasecmp(board->lb_vendor, vendor))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002533 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002534
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002535 if (!board->lb_part || strcasecmp(board->lb_part, model))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002536 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002537
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002538 if (!pci_dev_find(board->first_vendor, board->first_device)) {
2539 msg_pdbg("Odd. Board name \"%s\":\"%s\" matches, but first PCI device %04x:%04x "
2540 "doesn't.\n", vendor, model, board->first_vendor, board->first_device);
Uwe Hermanna7e05482007-05-09 10:17:44 +00002541 continue;
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002542 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002543
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002544 if (!pci_dev_find(board->second_vendor, board->second_device)) {
2545 msg_pdbg("Odd. Board name \"%s\":\"%s\" matches, but second PCI device %04x:%04x "
2546 "doesn't.\n", vendor, model, board->second_vendor, board->second_device);
Uwe Hermanna7e05482007-05-09 10:17:44 +00002547 continue;
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002548 }
Peter Stuge6b53fed2008-01-27 16:21:21 +00002549
2550 if (partmatch) {
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002551 /* More than one entry has a matching name. */
2552 msg_perr("Board name \"%s\":\"%s\" and PCI IDs matched more than one board enable "
2553 "entry. Please report a bug at flashrom@flashrom.org\n", vendor, model);
Peter Stuge6b53fed2008-01-27 16:21:21 +00002554 return NULL;
2555 }
2556 partmatch = board;
Uwe Hermanna7e05482007-05-09 10:17:44 +00002557 }
Uwe Hermann372eeb52007-12-04 21:49:06 +00002558
Peter Stuge6b53fed2008-01-27 16:21:21 +00002559 if (partmatch)
2560 return partmatch;
2561
Uwe Hermanna7e05482007-05-09 10:17:44 +00002562 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002563}
2564
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002565/*
Uwe Hermannffec5f32007-08-23 16:08:21 +00002566 * Match boards on PCI IDs and subsystem IDs.
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002567 * Second set of IDs can be either main+subsystem IDs, main IDs or no IDs.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002568 */
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002569const static struct board_match *board_match_pci_ids(enum board_match_phase phase)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002570{
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002571 const struct board_match *board = board_matches;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002572
Uwe Hermanna93045c2009-05-09 00:47:04 +00002573 for (; board->vendor_name; board++) {
Michael Karcher2eab70d2010-02-04 10:58:50 +00002574 if ((!board->first_card_vendor || !board->first_card_device) &&
2575 !board->dmi_pattern)
Uwe Hermanna7e05482007-05-09 10:17:44 +00002576 continue;
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002577 if (board->phase != phase)
2578 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002579
Uwe Hermanna7e05482007-05-09 10:17:44 +00002580 if (!pci_card_find(board->first_vendor, board->first_device,
Uwe Hermann394131e2008-10-18 21:14:13 +00002581 board->first_card_vendor,
2582 board->first_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002583 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002584
Uwe Hermanna7e05482007-05-09 10:17:44 +00002585 if (board->second_vendor) {
2586 if (board->second_card_vendor) {
2587 if (!pci_card_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00002588 board->second_device,
2589 board->second_card_vendor,
2590 board->second_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002591 continue;
2592 } else {
2593 if (!pci_dev_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00002594 board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002595 continue;
2596 }
2597 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002598
Sean Nelson4c6d3a42013-09-11 23:35:03 +00002599#if defined(__i386__) || defined(__x86_64__)
Michael Karcher6701ee82010-01-20 14:14:11 +00002600 if (board->dmi_pattern) {
2601 if (!has_dmi_support) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00002602 msg_pwarn("Warning: Can't autodetect %s %s, DMI info unavailable.\n",
2603 board->vendor_name, board->board_name);
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002604 msg_pinfo("Please supply the board vendor and model name with the "
2605 "-p internal:mainboard=<vendor>:<model> option.\n");
Michael Karcher6701ee82010-01-20 14:14:11 +00002606 continue;
2607 } else {
2608 if (!dmi_match(board->dmi_pattern))
2609 continue;
2610 }
2611 }
Sean Nelson4c6d3a42013-09-11 23:35:03 +00002612#endif // defined(__i386__) || defined(__x86_64__)
Uwe Hermanna7e05482007-05-09 10:17:44 +00002613 return board;
2614 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002615
Uwe Hermanna7e05482007-05-09 10:17:44 +00002616 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002617}
2618
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002619static int board_enable_safetycheck(const struct board_match *board)
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002620{
2621 if (!board)
2622 return 1;
2623
2624 if (board->status == OK)
2625 return 0;
2626
2627 if (!force_boardenable) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00002628 msg_pwarn("Warning: The mainboard-specific code for %s %s has not been tested,\n"
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002629 "and thus will not be executed by default. Depending on your hardware,\n"
2630 "erasing, writing or even probing can fail without running this code.\n\n"
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002631 "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n"
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002632 "\"internal programmer\") for details.\n", board->vendor_name, board->board_name);
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002633 return 1;
2634 }
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00002635 msg_pwarn("NOTE: Running an untested board enable procedure.\n"
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002636 "Please report success/failure to flashrom@flashrom.org.\n");
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002637 return 0;
2638}
2639
2640/* FIXME: Should this be identical to board_flash_enable? */
2641static int board_handle_phase(enum board_match_phase phase)
2642{
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002643 const struct board_match *board = NULL;
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002644
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002645 board = board_match_pci_ids(phase);
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002646
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002647 if (!board)
2648 return 0;
2649
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002650 if (board_enable_safetycheck(board))
2651 return 0;
2652
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002653 if (!board->enable) {
2654 /* Not sure if there is a valid case for this. */
2655 msg_perr("Board match found, but nothing to do?\n");
2656 return 0;
2657 }
2658
2659 return board->enable();
2660}
2661
2662void board_handle_before_superio(void)
2663{
2664 board_handle_phase(P1);
2665}
2666
2667void board_handle_before_laptop(void)
2668{
2669 board_handle_phase(P2);
2670}
2671
Stefan Taunerfa9fa712012-09-24 21:29:29 +00002672int board_flash_enable(const char *vendor, const char *model, const char *cb_vendor, const char *cb_model)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002673{
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002674 const struct board_match *board = NULL;
Uwe Hermanna7e05482007-05-09 10:17:44 +00002675 int ret = 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002676
Stefan Taunerfa9fa712012-09-24 21:29:29 +00002677 if (vendor != NULL && model != NULL) {
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002678 board = board_match_name(vendor, model);
Stefan Taunerfa9fa712012-09-24 21:29:29 +00002679 if (!board) { /* If a board was given by the user it has to match, else we abort here. */
2680 msg_perr("No suitable board enable found for vendor=\"%s\", model=\"%s\".\n",
2681 vendor, model);
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002682 return 1;
Stefan Taunerfa9fa712012-09-24 21:29:29 +00002683 }
2684 }
2685 if (board == NULL && cb_vendor != NULL && cb_model != NULL) {
2686 board = board_match_name(cb_vendor, cb_model);
2687 if (!board) { /* Failure is an option here, because many cb boards don't require an enable. */
2688 msg_pdbg2("No board enable found matching coreboot IDs vendor=\"%s\", model=\"%s\".\n",
2689 cb_vendor, cb_model);
2690 }
2691 }
2692 if (board == NULL) {
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002693 board = board_match_pci_ids(P3);
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002694 if (!board) /* i.e. there is just no board enable available for this board */
2695 return 0;
2696 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002697
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002698 if (board_enable_safetycheck(board))
2699 return 1;
Michael Karcher7f0c3ec2010-03-07 22:29:28 +00002700
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002701 /* limit the maximum size of the parallel bus */
2702 if (board->max_rom_decode_parallel)
2703 max_rom_decode.parallel = board->max_rom_decode_parallel * 1024;
Luc Verhaegen93938c32010-01-20 14:45:03 +00002704
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002705 if (board->enable != NULL) {
2706 msg_pinfo("Enabling full flash access for board \"%s %s\"... ",
2707 board->vendor_name, board->board_name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002708
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002709 ret = board->enable();
2710 if (ret)
2711 msg_pinfo("FAILED!\n");
2712 else
2713 msg_pinfo("OK.\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +00002714 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002715
Uwe Hermanna7e05482007-05-09 10:17:44 +00002716 return ret;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002717}