blob: 7f3018090a8c63aaa30f284ae3ffc13d7dce198b [file] [log] [blame]
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
5 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +00006 * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
Carl-Daniel Hailfinger92242622007-09-27 14:29:57 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00008 *
Uwe Hermannd1107642007-08-29 17:52:32 +00009 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000012 *
Uwe Hermannd1107642007-08-29 17:52:32 +000013 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000021 */
22
23/*
24 * Contains the board specific flash enables.
25 */
26
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000027#include <strings.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000028#include <string.h>
Stefan Taunerb4e06bd2012-08-20 00:24:22 +000029#include <stdlib.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000030#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000031#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000032#include "hwaccess.h"
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000033
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000034#if defined(__i386__) || defined(__x86_64__)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000035/*
Uwe Hermannffec5f32007-08-23 16:08:21 +000036 * Helper functions for many Winbond Super I/Os of the W836xx range.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000037 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000038/* Enter extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000039void w836xx_ext_enter(uint16_t port)
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000040{
Andriy Gapon65c1b862008-05-22 13:22:45 +000041 OUTB(0x87, port);
42 OUTB(0x87, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000043}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000044
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000045/* Leave extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000046void w836xx_ext_leave(uint16_t port)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000047{
Andriy Gapon65c1b862008-05-22 13:22:45 +000048 OUTB(0xAA, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000049}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000050
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000051/* Generic Super I/O helper functions */
52uint8_t sio_read(uint16_t port, uint8_t reg)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000053{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000054 OUTB(reg, port);
55 return INB(port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000056}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000057
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000058void sio_write(uint16_t port, uint8_t reg, uint8_t data)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000059{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000060 OUTB(reg, port);
61 OUTB(data, port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000062}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000063
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000064void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000065{
Ronald G. Minnichfa496922007-10-12 21:22:40 +000066 uint8_t tmp;
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000067
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000068 OUTB(reg, port);
69 tmp = INB(port + 1) & ~mask;
70 OUTB(tmp | (data & mask), port + 1);
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000071}
72
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +000073/* Winbond W83697 documentation indicates that the index register has to be written for each access. */
74void sio_mask_alzheimer(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
75{
76 uint8_t tmp;
77
78 OUTB(reg, port);
79 tmp = INB(port + 1) & ~mask;
80 OUTB(reg, port);
81 OUTB(tmp | (data & mask), port + 1);
82}
83
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000084/* Not used yet. */
85#if 0
86static int enable_flash_decode_superio(void)
87{
88 int ret;
89 uint8_t tmp;
90
91 switch (superio.vendor) {
92 case SUPERIO_VENDOR_NONE:
93 ret = -1;
94 break;
95 case SUPERIO_VENDOR_ITE:
96 enter_conf_mode_ite(superio.port);
Uwe Hermann43959702010-03-13 17:28:29 +000097 /* Enable flash mapping. Works for most old ITE style Super I/O. */
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000098 tmp = sio_read(superio.port, 0x24);
99 tmp |= 0xfc;
100 sio_write(superio.port, 0x24, tmp);
101 exit_conf_mode_ite(superio.port);
102 ret = 0;
103 break;
104 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000105 msg_pdbg("Unhandled Super I/O type!\n");
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +0000106 ret = -1;
107 break;
108 }
109 return ret;
110}
111#endif
112
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000113/*
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000114 * SMSC FDC37B787: Raise GPIO50
115 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000116static int fdc37b787_gpio50_raise(uint16_t port)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000117{
118 uint8_t id, val;
119
120 OUTB(0x55, port); /* enter conf mode */
121 id = sio_read(port, 0x20);
122 if (id != 0x44) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000123 msg_perr("\nERROR: FDC37B787: Wrong ID 0x%02X.\n", id);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000124 OUTB(0xAA, port); /* leave conf mode */
125 return -1;
126 }
127
128 sio_write(port, 0x07, 0x08); /* Select Aux I/O subdevice */
129
130 val = sio_read(port, 0xC8); /* GP50 */
131 if ((val & 0x1B) != 0x10) /* output, no invert, GPIO */
132 {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000133 msg_perr("\nERROR: GPIO50 mode 0x%02X unexpected.\n", val);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000134 OUTB(0xAA, port);
135 return -1;
136 }
137
138 sio_mask(port, 0xF9, 0x01, 0x01);
139
140 OUTB(0xAA, port); /* Leave conf mode */
141 return 0;
142}
143
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000144/*
145 * Suited for:
146 * - Nokia IP530: Intel 440BX + PIIX4 + FDC37B787
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000147 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000148static int fdc37b787_gpio50_raise_3f0(void)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000149{
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000150 return fdc37b787_gpio50_raise(0x3f0);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000151}
152
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000153struct winbond_mux {
154 uint8_t reg; /* 0 if the corresponding pin is not muxed */
155 uint8_t data; /* reg/data/mask may be directly ... */
156 uint8_t mask; /* ... passed to sio_mask */
157};
158
159struct winbond_port {
160 const struct winbond_mux *mux; /* NULL or pointer to mux info for the 8 bits */
161 uint8_t ldn; /* LDN this GPIO register is located in */
162 uint8_t enable_bit; /* bit in 0x30 of that LDN to enable
163 the GPIO port */
164 uint8_t base; /* base register in that LDN for the port */
165};
166
167struct winbond_chip {
168 uint8_t device_id; /* reg 0x20 of the expected w83626x */
169 uint8_t gpio_port_count;
170 const struct winbond_port *port;
171};
172
173
174#define UNIMPLEMENTED_PORT {NULL, 0, 0, 0}
175
176enum winbond_id {
177 WINBOND_W83627HF_ID = 0x52,
Michael Karcherea36c9c2010-06-27 15:07:52 +0000178 WINBOND_W83627EHF_ID = 0x88,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000179 WINBOND_W83627THF_ID = 0x82,
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000180 WINBOND_W83697HF_ID = 0x60,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000181};
182
183static const struct winbond_mux w83627hf_port2_mux[8] = {
184 {0x2A, 0x01, 0x01}, /* or MIDI */
185 {0x2B, 0x80, 0x80}, /* or SPI */
186 {0x2B, 0x40, 0x40}, /* or SPI */
187 {0x2B, 0x20, 0x20}, /* or power LED */
188 {0x2B, 0x10, 0x10}, /* or watchdog */
189 {0x2B, 0x08, 0x08}, /* or infra red */
190 {0x2B, 0x04, 0x04}, /* or infra red */
191 {0x2B, 0x03, 0x03} /* or IRQ1 input */
192};
193
194static const struct winbond_port w83627hf[3] = {
195 UNIMPLEMENTED_PORT,
196 {w83627hf_port2_mux, 0x08, 0, 0xF0},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000197 UNIMPLEMENTED_PORT,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000198};
199
Michael Karcherea36c9c2010-06-27 15:07:52 +0000200static const struct winbond_mux w83627ehf_port2_mux[8] = {
201 {0x29, 0x06, 0x02}, /* or MIDI */
202 {0x29, 0x06, 0x02},
203 {0x24, 0x02, 0x00}, /* or SPI ROM interface */
204 {0x24, 0x02, 0x00},
205 {0x2A, 0x01, 0x01}, /* or keyboard/mouse interface */
206 {0x2A, 0x01, 0x01},
207 {0x2A, 0x01, 0x01},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000208 {0x2A, 0x01, 0x01},
Michael Karcherea36c9c2010-06-27 15:07:52 +0000209};
210
211static const struct winbond_port w83627ehf[6] = {
212 UNIMPLEMENTED_PORT,
213 {w83627ehf_port2_mux, 0x09, 0, 0xE3},
214 UNIMPLEMENTED_PORT,
215 UNIMPLEMENTED_PORT,
216 UNIMPLEMENTED_PORT,
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000217 UNIMPLEMENTED_PORT,
Michael Karcherea36c9c2010-06-27 15:07:52 +0000218};
219
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000220static const struct winbond_mux w83627thf_port4_mux[8] = {
221 {0x2D, 0x01, 0x01}, /* or watchdog or VID level strap */
222 {0x2D, 0x02, 0x02}, /* or resume reset */
223 {0x2D, 0x04, 0x04}, /* or S3 input */
224 {0x2D, 0x08, 0x08}, /* or PSON# */
225 {0x2D, 0x10, 0x10}, /* or PWROK */
226 {0x2D, 0x20, 0x20}, /* or suspend LED */
227 {0x2D, 0x40, 0x40}, /* or panel switch input */
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000228 {0x2D, 0x80, 0x80}, /* or panel switch output */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000229};
230
231static const struct winbond_port w83627thf[5] = {
232 UNIMPLEMENTED_PORT, /* GPIO1 */
233 UNIMPLEMENTED_PORT, /* GPIO2 */
234 UNIMPLEMENTED_PORT, /* GPIO3 */
235 {w83627thf_port4_mux, 0x09, 1, 0xF4},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000236 UNIMPLEMENTED_PORT, /* GPIO5 */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000237};
238
239static const struct winbond_chip winbond_chips[] = {
240 {WINBOND_W83627HF_ID, ARRAY_SIZE(w83627hf), w83627hf },
Michael Karcherea36c9c2010-06-27 15:07:52 +0000241 {WINBOND_W83627EHF_ID, ARRAY_SIZE(w83627ehf), w83627ehf},
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000242 {WINBOND_W83627THF_ID, ARRAY_SIZE(w83627thf), w83627thf},
243};
244
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000245#define WINBOND_SUPERIO_PORT1 0x2e
246#define WINBOND_SUPERIO_PORT2 0x4e
247
248/* We don't really care about the hardware monitor, but it offers better (more specific) device ID info than
249 * the simple device ID in the normal configuration registers.
250 * Note: This function expects to be called while the Super I/O is in config mode.
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000251 */
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000252static uint8_t w836xx_deviceid_hwmon(uint16_t sio_port)
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000253{
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000254 uint16_t hwmport;
255 uint16_t hwm_vendorid;
256 uint8_t hwm_deviceid;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000257
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000258 sio_write(sio_port, 0x07, 0x0b); /* Select LDN 0xb (HWM). */
259 if ((sio_read(sio_port, 0x30) & (1 << 0)) != (1 << 0)) {
260 msg_pinfo("W836xx hardware monitor disabled or does not exist.\n");
261 return 0;
262 }
263 /* Get HWM base address (stored in LDN 0xb, index 0x60/0x61). */
264 hwmport = sio_read(sio_port, 0x60) << 8;
265 hwmport |= sio_read(sio_port, 0x61);
266 /* HWM address register = HWM base address + 5. */
267 hwmport += 5;
268 msg_pdbg2("W836xx Hardware Monitor at port %04x\n", hwmport);
269 /* FIXME: This busy check should happen before each HWM access. */
270 if (INB(hwmport) & 0x80) {
271 msg_pinfo("W836xx hardware monitor busy, ignoring it.\n");
272 return 0;
273 }
274 /* Set HBACS=1. */
275 sio_mask_alzheimer(hwmport, 0x4e, 0x80, 0x80);
276 /* Read upper byte of vendor ID. */
277 hwm_vendorid = sio_read(hwmport, 0x4f) << 8;
278 /* Set HBACS=0. */
279 sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x80);
280 /* Read lower byte of vendor ID. */
281 hwm_vendorid |= sio_read(hwmport, 0x4f);
282 if (hwm_vendorid != 0x5ca3) {
283 msg_pinfo("W836xx hardware monitor vendor ID weirdness: expected 0x5ca3, got %04x\n",
284 hwm_vendorid);
285 return 0;
286 }
287 /* Set Bank=0. */
288 sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x07);
289 /* Read "chip" ID. We call this one the device ID. */
290 hwm_deviceid = sio_read(hwmport, 0x58);
291 return hwm_deviceid;
292}
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000293
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000294void probe_superio_winbond(void)
295{
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +0000296 struct superio s = {0};
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000297 uint16_t winbond_ports[] = {WINBOND_SUPERIO_PORT1, WINBOND_SUPERIO_PORT2, 0};
298 uint16_t *i = winbond_ports;
299 uint8_t model;
300 uint8_t tmp;
301
302 s.vendor = SUPERIO_VENDOR_WINBOND;
303 for (; *i; i++) {
304 s.port = *i;
305 /* If we're already in Super I/O config more, the W836xx enter sequence won't hurt. */
306 w836xx_ext_enter(s.port);
307 model = sio_read(s.port, 0x20);
308 /* No response, no point leaving the config mode. */
309 if (model == 0xff)
310 continue;
311 /* Try to leave config mode. If the ID register is still readable, it's not a Winbond chip. */
312 w836xx_ext_leave(s.port);
313 if (model == sio_read(s.port, 0x20)) {
314 msg_pdbg("W836xx enter config mode worked or we were already in config mode. W836xx "
315 "leave config mode had no effect.\n");
316 if (model == 0x87) {
317 /* ITE IT8707F and IT8710F are special: They need the W837xx enter sequence,
318 * but they want the ITE exit sequence. Handle them here.
319 */
320 tmp = sio_read(s.port, 0x21);
321 switch (tmp) {
322 case 0x07:
323 case 0x10:
324 s.vendor = SUPERIO_VENDOR_ITE;
325 s.model = (0x87 << 8) | tmp ;
326 msg_pdbg("Found ITE Super I/O, ID 0x%04hx on port "
327 "0x%x\n", s.model, s.port);
328 register_superio(s);
329 /* Exit ITE config mode. */
330 exit_conf_mode_ite(s.port);
331 /* Restore vendor for next loop iteration. */
332 s.vendor = SUPERIO_VENDOR_WINBOND;
333 continue;
334 }
335 }
336 msg_pinfo("Active config mode, unknown reg 0x20 ID: %02x.\n", model);
337 msg_pinfo("Please send the output of \"flashrom -V\" to \n"
338 "flashrom@flashrom.org with W836xx: your board name: flashrom -V\n"
339 "as the subject to help us finish support for your Super I/O. Thanks.\n");
340 continue;
341 }
342 /* The Super I/O reacts to W836xx enter and exit config mode, it's probably Winbond. */
343 w836xx_ext_enter(s.port);
344 s.model = sio_read(s.port, 0x20);
345 switch (s.model) {
346 case WINBOND_W83627HF_ID:
347 case WINBOND_W83627EHF_ID:
348 case WINBOND_W83627THF_ID:
Stefan Taunereb582572012-09-21 12:52:50 +0000349 msg_pdbg("Found Winbond Super I/O, id 0x%02hx\n", s.model);
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000350 register_superio(s);
351 break;
352 case WINBOND_W83697HF_ID:
353 /* This code is extremely paranoid. */
354 tmp = sio_read(s.port, 0x26) & 0x40;
355 if (((tmp == 0x00) && (s.port != WINBOND_SUPERIO_PORT1)) ||
356 ((tmp == 0x40) && (s.port != WINBOND_SUPERIO_PORT2))) {
357 msg_pdbg("Winbond Super I/O probe weirdness: Port mismatch for ID "
Stefan Taunereb582572012-09-21 12:52:50 +0000358 "0x%02x at port 0x%04x\n", s.model, s.port);
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000359 break;
360 }
361 tmp = w836xx_deviceid_hwmon(s.port);
362 /* FIXME: This might be too paranoid... */
363 if (!tmp) {
364 msg_pdbg("Probably not a Winbond Super I/O\n");
365 break;
366 }
367 if (tmp != s.model) {
Stefan Taunereb582572012-09-21 12:52:50 +0000368 msg_pinfo("W83 series hardware monitor device ID weirdness: expected 0x%02x, "
369 "got 0x%02x\n", WINBOND_W83697HF_ID, tmp);
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000370 break;
371 }
Stefan Taunereb582572012-09-21 12:52:50 +0000372 msg_pinfo("Found Winbond Super I/O, id 0x%02hx\n", s.model);
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000373 register_superio(s);
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000374 break;
375 }
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000376 w836xx_ext_leave(s.port);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000377 }
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000378 return;
379}
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000380
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000381static const struct winbond_chip *winbond_superio_chipdef(void)
382{
383 int i, j;
384
385 for (i = 0; i < superio_count; i++) {
386 if (superios[i].vendor != SUPERIO_VENDOR_WINBOND)
387 continue;
388 for (j = 0; j < ARRAY_SIZE(winbond_chips); j++)
389 if (winbond_chips[j].device_id == superios[i].model)
390 return &winbond_chips[j];
391 }
392 return NULL;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000393}
394
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000395/*
396 * The chipid parameter goes away as soon as we have Super I/O matching in the
397 * board enable table. The call to winbond_superio_detect() goes away as
398 * soon as we have generic Super I/O detection code.
399 */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000400static int winbond_gpio_set(uint16_t base, enum winbond_id chipid,
401 int pin, int raise)
402{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000403 const struct winbond_chip *chip = NULL;
404 const struct winbond_port *gpio;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000405 int port = pin / 10;
406 int bit = pin % 10;
407
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000408 chip = winbond_superio_chipdef();
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000409 if (!chip) {
410 msg_perr("\nERROR: No supported Winbond Super I/O found\n");
411 return -1;
412 }
Michael Karcher979d9252010-06-29 14:44:40 +0000413 if (chip->device_id != chipid) {
414 msg_perr("\nERROR: Found Winbond chip with ID 0x%x, "
415 "expected %x\n", chip->device_id, chipid);
416 return -1;
417 }
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000418 if (bit >= 8 || port == 0 || port > chip->gpio_port_count) {
419 msg_perr("\nERROR: winbond_gpio_set: Invalid GPIO number %d\n",
420 pin);
421 return -1;
422 }
423
424 gpio = &chip->port[port - 1];
425
426 if (gpio->ldn == 0) {
427 msg_perr("\nERROR: GPIO%d is not supported yet on this"
428 " winbond chip\n", port);
429 return -1;
430 }
431
432 w836xx_ext_enter(base);
433
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000434 /* Select logical device. */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000435 sio_write(base, 0x07, gpio->ldn);
436
437 /* Activate logical device. */
438 sio_mask(base, 0x30, 1 << gpio->enable_bit, 1 << gpio->enable_bit);
439
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000440 /* Select GPIO function of that pin. */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000441 if (gpio->mux && gpio->mux[bit].reg)
442 sio_mask(base, gpio->mux[bit].reg,
443 gpio->mux[bit].data, gpio->mux[bit].mask);
444
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000445 sio_mask(base, gpio->base + 0, 0, 1 << bit); /* Make pin output */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000446 sio_mask(base, gpio->base + 2, 0, 1 << bit); /* Clear inversion */
447 sio_mask(base, gpio->base + 1, raise << bit, 1 << bit);
448
449 w836xx_ext_leave(base);
450
451 return 0;
452}
453
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000454/*
Uwe Hermannffec5f32007-08-23 16:08:21 +0000455 * Winbond W83627HF: Raise GPIO24.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000456 *
457 * Suited for:
Uwe Hermannffec5f32007-08-23 16:08:21 +0000458 * - Agami Aruma
459 * - IWILL DK8-HTX
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000460 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000461static int w83627hf_gpio24_raise_2e(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000462{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000463 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 24, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000464}
465
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000466/*
Joshua Roysf280a382010-08-07 21:49:11 +0000467 * Winbond W83627HF: Raise GPIO25.
468 *
469 * Suited for:
470 * - MSI MS-6577
471 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000472static int w83627hf_gpio25_raise_2e(void)
Joshua Roysf280a382010-08-07 21:49:11 +0000473{
474 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 25, 1);
475}
476
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000477/*
Stefan Taunerff80e682011-07-20 16:34:18 +0000478 * Winbond W83627EHF: Raise GPIO22.
Michael Karcherea36c9c2010-06-27 15:07:52 +0000479 *
480 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000481 * - ASUS A8N-VM CSM: AMD Socket 939 + GeForce 6150 (C51) + MCP51
Michael Karcherea36c9c2010-06-27 15:07:52 +0000482 */
Stefan Taunerff80e682011-07-20 16:34:18 +0000483static int w83627ehf_gpio22_raise_2e(void)
Michael Karcherea36c9c2010-06-27 15:07:52 +0000484{
Stefan Taunerff80e682011-07-20 16:34:18 +0000485 return winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, 22, 1);
Michael Karcherea36c9c2010-06-27 15:07:52 +0000486}
487
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000488/*
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000489 * Winbond W83627THF: Raise GPIO 44.
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000490 *
491 * Suited for:
Peter Stugecce26822008-07-21 17:48:40 +0000492 * - MSI K8T Neo2-F
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000493 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000494static int w83627thf_gpio44_raise_2e(void)
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000495{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000496 return winbond_gpio_set(0x2e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000497}
498
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000499/*
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000500 * Winbond W83627THF: Raise GPIO 44.
501 *
502 * Suited for:
503 * - MSI K8N Neo3
504 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000505static int w83627thf_gpio44_raise_4e(void)
Peter Stugecce26822008-07-21 17:48:40 +0000506{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000507 return winbond_gpio_set(0x4e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000508}
Uwe Hermann372eeb52007-12-04 21:49:06 +0000509
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000510/*
David Borgb6417a62010-08-02 08:29:34 +0000511 * Enable MEMW# and set ROM size to max.
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000512 * Supported chips: W83L517D, W83697HF/F/HG, W83697SF/UF/UG
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000513 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000514static void w836xx_memw_enable(uint16_t port)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000515{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000516 w836xx_ext_enter(port);
517 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000518 /* Enable MEMW# and set ROM size select to max. (4M). */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000519 sio_mask(port, 0x24, 0x28, 0x28);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000520 }
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000521 w836xx_ext_leave(port);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000522}
523
David Borgb02c62b2012-05-05 20:43:42 +0000524/**
525 * Enable MEMW# and set ROM size to max.
526 * Supported chips:
527 * W83697HF/F/HG, W83697SF/UF/UG
528 */
529void w83697xx_memw_enable(uint16_t port)
530{
531 w836xx_ext_enter(port);
532 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
533 if((sio_read(port, 0x2A) & 0xF0) == 0xF0) {
534
535 /* CR24 Bits 7 & 2 must be set to 0 enable the flash ROM */
536 /* address segments 000E0000h ~ 000FFFFFh on W83697SF/UF/UG */
537 /* These bits are reserved on W83697HF/F/HG */
538 /* Shouldn't be needed though. */
539
540 /* CR28 Bit3 must be set to 1 to enable flash access to */
541 /* FFE80000h ~ FFEFFFFFh on W83697SF/UF/UG. */
542 /* This bit is reserved on W83697HF/F/HG which default to 0 */
543 sio_mask(port, 0x28, 0x08, 0x08);
544
545 /* Enable MEMW# and set ROM size select to max. (4M)*/
546 sio_mask(port, 0x24, 0x28, 0x38);
547
548 } else {
549 msg_perr("WARNING: Flash interface in use by GPIO!\n");
550 }
551 } else {
552 msg_pinfo("BIOS ROM is disabled\n");
553 }
554 w836xx_ext_leave(port);
555}
556
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000557/*
Luc Verhaegen73d21192009-12-23 00:54:26 +0000558 * Suited for:
Stefan Taunerb6304c12012-08-09 23:25:27 +0000559 * - Biostar M7VIQ: VIA KM266 + VT8235
560 */
561static int w83697xx_memw_enable_2e(void)
562{
563 w83697xx_memw_enable(0x2E);
564
565 return 0;
566}
567
568
569/*
570 * Suited for:
Tadas Slotkus3dcdc032012-08-25 03:53:12 +0000571 * - DFI AD77: VIA KT400 + VT8235 + W83697HF
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000572 * - EPoX EP-8K5A2: VIA KT333 + VT8235
573 * - Albatron PM266A Pro: VIA P4M266A + VT8235
574 * - Shuttle AK31 (all versions): VIA KT266 + VT8233
575 * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
576 * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237
Mattias Mattssone295eee2010-08-15 10:21:29 +0000577 * - MSI KM4M-V and KM4AM-V: VIA KM400/KM400A + VT8237
Mattias Mattssone8388242010-09-11 15:25:48 +0000578 * - MSI MS-6561 (745 Ultra): SiS 745 + W83697HF
Sergey A Lichackf3a4bff2010-09-07 18:14:53 +0000579 * - MSI MS-6787 (P4MAM-V/P4MAM-L): VIA P4M266 + VT8235
Uwe Hermann17da61e2010-10-05 21:48:43 +0000580 * - ASRock K7S41: SiS 741 + SiS 963 + W83697HF
Pawel Rozanski1d233072011-06-19 16:52:48 +0000581 * - ASRock K7S41GX: SiS 741GX + SiS 963L + W83697HF
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000582 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000583static int w836xx_memw_enable_2e(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000584{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000585 w836xx_memw_enable(0x2E);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000586
Luc Verhaegen73d21192009-12-23 00:54:26 +0000587 return 0;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000588}
589
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000590/*
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000591 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000592 * - Termtek TK-3370 (rev. 2.5b)
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000593 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000594static int w836xx_memw_enable_4e(void)
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000595{
596 w836xx_memw_enable(0x4E);
597
598 return 0;
599}
600
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000601/*
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000602 * Suited for all boards with ITE IT8705F.
603 * The SIS950 Super I/O probably requires a similar flash write enable.
Luc Verhaegen21f54962010-01-20 14:45:07 +0000604 */
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000605int it8705f_write_enable(uint8_t port)
Luc Verhaegen21f54962010-01-20 14:45:07 +0000606{
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000607 uint8_t tmp;
608 int ret = 0;
609
Luc Verhaegen21f54962010-01-20 14:45:07 +0000610 enter_conf_mode_ite(port);
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000611 tmp = sio_read(port, 0x24);
612 /* Check if at least one flash segment is enabled. */
613 if (tmp & 0xf0) {
614 /* The IT8705F will respond to LPC cycles and translate them. */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000615 internal_buses_supported = BUS_PARALLEL;
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000616 /* Flash ROM I/F Writes Enable */
617 tmp |= 0x04;
618 msg_pdbg("Enabling IT8705F flash ROM interface write.\n");
619 if (tmp & 0x02) {
620 /* The data sheet contradicts itself about max size. */
621 max_rom_decode.parallel = 1024 * 1024;
622 msg_pinfo("IT8705F with very unusual settings. Please "
623 "send the output of \"flashrom -V\" to \n"
Paul Menzelab6328f2010-10-08 11:03:02 +0000624 "flashrom@flashrom.org with "
625 "IT8705: your board name: flashrom -V\n"
626 "as the subject to help us finish "
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000627 "support for your Super I/O. Thanks.\n");
628 ret = 1;
629 } else if (tmp & 0x08) {
630 max_rom_decode.parallel = 512 * 1024;
631 } else {
632 max_rom_decode.parallel = 256 * 1024;
633 }
634 /* Safety checks. The data sheet is unclear here: Segments 1+3
635 * overlap, no segment seems to cover top - 1MB to top - 512kB.
636 * We assume that certain combinations make no sense.
637 */
638 if (((tmp & 0x02) && !(tmp & 0x08)) || /* 1 MB en, 512 kB dis */
639 (!(tmp & 0x10)) || /* 128 kB dis */
640 (!(tmp & 0x40))) { /* 256/512 kB dis */
641 msg_perr("Inconsistent IT8705F decode size!\n");
642 ret = 1;
643 }
644 if (sio_read(port, 0x25) != 0) {
645 msg_perr("IT8705F flash data pins disabled!\n");
646 ret = 1;
647 }
648 if (sio_read(port, 0x26) != 0) {
649 msg_perr("IT8705F flash address pins 0-7 disabled!\n");
650 ret = 1;
651 }
652 if (sio_read(port, 0x27) != 0) {
653 msg_perr("IT8705F flash address pins 8-15 disabled!\n");
654 ret = 1;
655 }
656 if ((sio_read(port, 0x29) & 0x10) != 0) {
657 msg_perr("IT8705F flash write enable pin disabled!\n");
658 ret = 1;
659 }
660 if ((sio_read(port, 0x29) & 0x08) != 0) {
661 msg_perr("IT8705F flash chip select pin disabled!\n");
662 ret = 1;
663 }
664 if ((sio_read(port, 0x29) & 0x04) != 0) {
665 msg_perr("IT8705F flash read strobe pin disabled!\n");
666 ret = 1;
667 }
668 if ((sio_read(port, 0x29) & 0x03) != 0) {
669 msg_perr("IT8705F flash address pins 16-17 disabled!\n");
670 /* Not really an error if you use flash chips smaller
671 * than 256 kByte, but such a configuration is unlikely.
672 */
673 ret = 1;
674 }
675 msg_pdbg("Maximum IT8705F parallel flash decode size is %u.\n",
676 max_rom_decode.parallel);
677 if (ret) {
678 msg_pinfo("Not enabling IT8705F flash write.\n");
679 } else {
680 sio_write(port, 0x24, tmp);
681 }
682 } else {
683 msg_pdbg("No IT8705F flash segment enabled.\n");
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000684 ret = 0;
685 }
Luc Verhaegen21f54962010-01-20 14:45:07 +0000686 exit_conf_mode_ite(port);
687
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000688 return ret;
Luc Verhaegen21f54962010-01-20 14:45:07 +0000689}
Luc Verhaegen73d21192009-12-23 00:54:26 +0000690
Mattias Mattssonfb60cec2010-09-13 19:39:25 +0000691/*
692 * The ITE IT8707F is a custom chip made by ITE exclusively for ASUS.
693 * It uses the Winbond command sequence to enter extended configuration
694 * mode and the ITE sequence to exit.
695 *
696 * Registers seems similar to the ones on ITE IT8710F.
697 */
698static int it8707f_write_enable(uint8_t port)
699{
700 uint8_t tmp;
701
702 w836xx_ext_enter(port);
703
704 /* Set bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A rw */
705 tmp = sio_read(port, 0x23);
706 tmp |= (1 << 3);
707 sio_write(port, 0x23, tmp);
708
709 /* Set bit 2 (FLASH_WE) and bit 3 (FLASH_IF_EN) of reg 0x24 */
710 tmp = sio_read(port, 0x24);
711 tmp |= (1 << 2) | (1 << 3);
712 sio_write(port, 0x24, tmp);
713
714 /* Clear bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A ro */
715 tmp = sio_read(port, 0x23);
716 tmp &= ~(1 << 3);
717 sio_write(port, 0x23, tmp);
718
719 exit_conf_mode_ite(port);
720
721 return 0;
722}
723
724/*
725 * Suited for:
726 * - ASUS P4SC-E: SiS 651 + 962 + ITE IT8707F
727 */
728static int it8707f_write_enable_2e(void)
729{
730 return it8707f_write_enable(0x2e);
731}
732
Michael Karchercba52de2011-03-06 12:07:19 +0000733#define PC87360_ID 0xE1
734#define PC87364_ID 0xE4
735
736static int pc8736x_gpio_set(uint8_t chipid, uint8_t gpio, int raise)
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000737{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000738 static const int bankbase[] = {0, 4, 8, 10, 12};
739 int gpio_bank = gpio / 8;
740 int gpio_pin = gpio % 8;
741 uint16_t baseport;
742 uint8_t id, val;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000743
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000744 if (gpio_bank > 4) {
Michael Karchercba52de2011-03-06 12:07:19 +0000745 msg_perr("PC8736x: Invalid GPIO %d\n", gpio);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000746 return -1;
747 }
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000748
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000749 id = sio_read(0x2E, 0x20);
Michael Karchercba52de2011-03-06 12:07:19 +0000750 if (id != chipid) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000751 msg_perr("PC8736x: unexpected ID %02x (expected %02x)\n",
752 id, chipid);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000753 return -1;
754 }
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000755
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000756 sio_write(0x2E, 0x07, 0x07); /* Select GPIO device. */
757 baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
758 if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) {
759 msg_perr("PC87360: invalid GPIO base address %04x\n",
760 baseport);
761 return -1;
762 }
763 sio_mask (0x2E, 0x30, 0x01, 0x01); /* Enable logical device. */
764 sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin);
765 sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output. */
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000766
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000767 val = INB(baseport + bankbase[gpio_bank]);
768 if (raise)
769 val |= 1 << gpio_pin;
770 else
771 val &= ~(1 << gpio_pin);
772 OUTB(val, baseport + bankbase[gpio_bank]);
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000773
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000774 return 0;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000775}
776
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000777/*
778 * VIA VT823x: Set one of the GPIO pins.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000779 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000780static int via_vt823x_gpio_set(uint8_t gpio, int raise)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000781{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000782 struct pci_dev *dev;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000783 uint16_t base;
David Bartleyf58d3642009-12-09 07:53:01 +0000784 uint8_t val, bit, offset;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000785
Luc Verhaegen73d21192009-12-23 00:54:26 +0000786 dev = pci_dev_find_vendorclass(0x1106, 0x0601);
787 switch (dev->device_id) {
788 case 0x3177: /* VT8235 */
Helge Wagnerdd73d832012-08-24 23:03:46 +0000789 case 0x3227: /* VT8237/VT8237R */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000790 case 0x3337: /* VT8237A */
791 break;
792 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000793 msg_perr("\nERROR: VT823x ISA bridge not found.\n");
Luc Verhaegen73d21192009-12-23 00:54:26 +0000794 return -1;
795 }
796
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000797 if ((gpio >= 12) && (gpio <= 15)) {
798 /* GPIO12-15 -> output */
799 val = pci_read_byte(dev, 0xE4);
800 val |= 0x10;
801 pci_write_byte(dev, 0xE4, val);
802 } else if (gpio == 9) {
803 /* GPIO9 -> Output */
804 val = pci_read_byte(dev, 0xE4);
805 val |= 0x20;
806 pci_write_byte(dev, 0xE4, val);
David Bartleyf58d3642009-12-09 07:53:01 +0000807 } else if (gpio == 5) {
808 val = pci_read_byte(dev, 0xE4);
809 val |= 0x01;
810 pci_write_byte(dev, 0xE4, val);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000811 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000812 msg_perr("\nERROR: "
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000813 "VT823x GPIO%02d is not implemented.\n", gpio);
Luc Verhaegen73d21192009-12-23 00:54:26 +0000814 return -1;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000815 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000816
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000817 /* We need the I/O Base Address for this board's flash enable. */
818 base = pci_read_word(dev, 0x88) & 0xff80;
819
David Bartleyf58d3642009-12-09 07:53:01 +0000820 offset = 0x4C + gpio / 8;
821 bit = 0x01 << (gpio % 8);
822
823 val = INB(base + offset);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000824 if (raise)
825 val |= bit;
826 else
827 val &= ~bit;
David Bartleyf58d3642009-12-09 07:53:01 +0000828 OUTB(val, base + offset);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000829
Uwe Hermanna7e05482007-05-09 10:17:44 +0000830 return 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000831}
832
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000833/*
834 * Suited for:
835 * - ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000836 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000837static int via_vt823x_gpio5_raise(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000838{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000839 /* On M2V-MX: GPO5 is connected to WP# and TBL#. */
840 return via_vt823x_gpio_set(5, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000841}
842
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000843/*
844 * Suited for:
845 * - VIA EPIA EK & N & NL
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000846 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000847static int via_vt823x_gpio9_raise(void)
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000848{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000849 return via_vt823x_gpio_set(9, 1);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000850}
851
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000852/*
853 * Suited for:
854 * - VIA EPIA M and MII (and maybe other CLE266 based EPIAs)
Luc Verhaegen73d21192009-12-23 00:54:26 +0000855 *
856 * We don't need to do this for EPIA M when using coreboot, GPIO15 is never
857 * lowered there.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000858 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000859static int via_vt823x_gpio15_raise(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000860{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000861 return via_vt823x_gpio_set(15, 1);
862}
863
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000864/*
Luc Verhaegen73d21192009-12-23 00:54:26 +0000865 * Winbond W83697HF Super I/O + VIA VT8235 southbridge
866 *
867 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000868 * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
869 * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
Luc Verhaegen73d21192009-12-23 00:54:26 +0000870 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000871static int board_msi_kt4v(void)
Luc Verhaegen73d21192009-12-23 00:54:26 +0000872{
873 int ret;
874
875 ret = via_vt823x_gpio_set(12, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000876 w836xx_memw_enable(0x2E);
Luc Verhaegen97866082008-02-09 02:03:06 +0000877
Luc Verhaegen73d21192009-12-23 00:54:26 +0000878 return ret;
Luc Verhaegen97866082008-02-09 02:03:06 +0000879}
880
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000881/*
882 * Suited for:
883 * - ASUS P5A
Luc Verhaegen6b141752007-05-20 16:16:13 +0000884 *
885 * This is rather nasty code, but there's no way to do this cleanly.
886 * We're basically talking to some unknown device on SMBus, my guess
887 * is that it is the Winbond W83781D that lives near the DIP BIOS.
888 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000889static int board_asus_p5a(void)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000890{
891 uint8_t tmp;
892 int i;
893
894#define ASUSP5A_LOOP 5000
895
Andriy Gapon65c1b862008-05-22 13:22:45 +0000896 OUTB(0x00, 0xE807);
897 OUTB(0xEF, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000898
Andriy Gapon65c1b862008-05-22 13:22:45 +0000899 OUTB(0xFF, 0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000900
901 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000902 OUTB(0xE1, 0xFF);
903 if (INB(0xE800) & 0x04)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000904 break;
905 }
906
907 if (i == ASUSP5A_LOOP) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000908 msg_perr("Unable to contact device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000909 return -1;
910 }
911
Andriy Gapon65c1b862008-05-22 13:22:45 +0000912 OUTB(0x20, 0xE801);
913 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000914
Andriy Gapon65c1b862008-05-22 13:22:45 +0000915 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000916
917 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000918 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000919 if (tmp & 0x70)
920 break;
921 }
922
923 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000924 msg_perr("Failed to read device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000925 return -1;
926 }
927
Andriy Gapon65c1b862008-05-22 13:22:45 +0000928 tmp = INB(0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000929 tmp &= ~0x02;
930
Andriy Gapon65c1b862008-05-22 13:22:45 +0000931 OUTB(0x00, 0xE807);
932 OUTB(0xEE, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000933
Andriy Gapon65c1b862008-05-22 13:22:45 +0000934 OUTB(tmp, 0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000935
Andriy Gapon65c1b862008-05-22 13:22:45 +0000936 OUTB(0xFF, 0xE800);
937 OUTB(0xE1, 0xFF);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000938
Andriy Gapon65c1b862008-05-22 13:22:45 +0000939 OUTB(0x20, 0xE801);
940 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000941
Andriy Gapon65c1b862008-05-22 13:22:45 +0000942 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000943
944 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000945 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000946 if (tmp & 0x70)
947 break;
948 }
949
950 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000951 msg_perr("Failed to write to device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000952 return -1;
953 }
954
955 return 0;
956}
957
Luc Verhaegena7e30502009-12-09 11:39:02 +0000958/*
959 * Set GPIO lines in the Broadcom HT-1000 southbridge.
960 *
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000961 * It's not a Super I/O but it uses the same index/data port method.
Luc Verhaegena7e30502009-12-09 11:39:02 +0000962 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000963static int board_hp_dl145_g3_enable(void)
Luc Verhaegena7e30502009-12-09 11:39:02 +0000964{
965 /* GPIO 0 reg from PM regs */
966 /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
967 sio_mask(0xcd6, 0x44, 0x24, 0x24);
968
969 return 0;
970}
971
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +0000972/*
973 * Set GPIO lines in the Broadcom HT-1000 southbridge.
974 *
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000975 * It's not a Super I/O but it uses the same index/data port method.
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +0000976 */
977static int board_hp_dl165_g6_enable(void)
978{
979 /* Variant of DL145, with slightly different pin placement. */
980 sio_mask(0xcd6, 0x44, 0x80, 0x80); /* TBL# */
981 sio_mask(0xcd6, 0x46, 0x04, 0x04); /* WP# */
982
983 return 0;
984}
985
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000986static int board_ibm_x3455(void)
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000987{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000988 /* Raise GPIO13. */
Carl-Daniel Hailfinger500b4232009-06-01 21:30:42 +0000989 sio_mask(0xcd6, 0x45, 0x20, 0x20);
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000990
991 return 0;
992}
993
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000994/*
995 * Suited for:
Mattias Mattssonf4925162010-09-16 22:09:18 +0000996 * - Elitegroup GeForce6100SM-M: NVIDIA MCP61 + ITE IT8726F
997 */
Mattias Mattssonf4925162010-09-16 22:09:18 +0000998static int board_ecs_geforce6100sm_m(void)
999{
1000 struct pci_dev *dev;
1001 uint32_t tmp;
1002
1003 dev = pci_dev_find(0x10DE, 0x03EB); /* NVIDIA MCP61 SMBus. */
1004 if (!dev) {
1005 msg_perr("\nERROR: NVIDIA MCP61 SMBus not found.\n");
1006 return -1;
1007 }
1008
1009 tmp = pci_read_byte(dev, 0xE0);
1010 tmp &= ~(1 << 3);
1011 pci_write_byte(dev, 0xE0, tmp);
1012
1013 return 0;
1014}
1015
1016/*
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001017 * Very similar to AMD 8111 IO Hub.
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001018 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001019static int nvidia_mcp_gpio_set(int gpio, int raise)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001020{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001021 struct pci_dev *dev;
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001022 uint16_t base, devclass;
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001023 uint8_t tmp;
1024
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001025 if ((gpio < 0) || (gpio >= 0x40)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001026 msg_perr("\nERROR: unsupported GPIO: %d.\n", gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +00001027 return -1;
1028 }
1029
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001030 /* Check for the ISA bridge first. */
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001031 dev = pci_dev_find_vendorclass(0x10DE, 0x0601);
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001032 switch (dev->device_id) {
1033 case 0x0030: /* CK804 */
1034 case 0x0050: /* MCP04 */
1035 case 0x0060: /* MCP2 */
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001036 case 0x00E0: /* CK8 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001037 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +00001038 case 0x0260: /* MCP51 */
Michael Karcher242efd42011-03-06 12:09:05 +00001039 case 0x0261: /* MCP51 */
Joshua Roys6e48a022012-06-29 23:07:14 +00001040 case 0x0360: /* MCP55 */
Michael Karcher2ead2e22010-06-01 16:09:06 +00001041 case 0x0364: /* MCP55 */
1042 /* find SMBus controller on *this* southbridge */
1043 /* The infamous Tyan S2915-E has two south bridges; they are
1044 easily told apart from each other by the class of the
1045 LPC bridge, but have the same SMBus bridge IDs */
1046 if (dev->func != 0) {
1047 msg_perr("MCP LPC bridge at unexpected function"
1048 " number %d\n", dev->func);
1049 return -1;
1050 }
1051
Carl-Daniel Hailfinger44cd9ab2010-07-17 22:28:05 +00001052#if PCI_LIB_VERSION >= 0x020200
Michael Karcher2ead2e22010-06-01 16:09:06 +00001053 dev = pci_get_dev(pacc, dev->domain, dev->bus, dev->dev, 1);
Carl-Daniel Hailfinger44cd9ab2010-07-17 22:28:05 +00001054#else
1055 /* pciutils/libpci before version 2.2 is too old to support
1056 * PCI domains. Such old machines usually don't have domains
1057 * besides domain 0, so this is not a problem.
1058 */
1059 dev = pci_get_dev(pacc, dev->bus, dev->dev, 1);
1060#endif
Michael Karcher2ead2e22010-06-01 16:09:06 +00001061 if (!dev) {
1062 msg_perr("MCP SMBus controller could not be found\n");
1063 return -1;
1064 }
1065 devclass = pci_read_word(dev, PCI_CLASS_DEVICE);
1066 if (devclass != 0x0C05) {
1067 msg_perr("Unexpected device class %04x for SMBus"
1068 " controller\n", devclass);
1069 return -1;
1070 }
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001071 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +00001072 default:
Sean Nelson316a29f2010-05-07 20:09:04 +00001073 msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n");
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001074 return -1;
1075 }
1076
1077 base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */
1078 base += 0xC0;
1079
1080 tmp = INB(base + gpio);
1081 tmp &= ~0x0F; /* null lower nibble */
1082 tmp |= 0x04; /* gpio -> output. */
1083 if (raise)
1084 tmp |= 0x01;
1085 OUTB(tmp, base + gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +00001086
1087 return 0;
1088}
1089
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001090/*
1091 * Suited for:
Stefan Taunera9cbbac2011-08-07 13:17:20 +00001092 * - ASUS A8M2N-LA (HP OEM "NodusM3-GL8E"): NVIDIA MCP51
Sean Nelson0a247512010-08-15 14:36:18 +00001093 * - ASUS A8N-LA (HP OEM "Nagami-GL8E"): NVIDIA MCP51
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001094 * - ASUS M2NBP-VM CSM: NVIDIA MCP51
Michael Karcherb2184c12010-03-07 16:42:55 +00001095 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001096static int nvidia_mcp_gpio0_raise(void)
Michael Karcherb2184c12010-03-07 16:42:55 +00001097{
1098 return nvidia_mcp_gpio_set(0x00, 1);
1099}
1100
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001101/*
1102 * Suited for:
1103 * - abit KN8 Ultra: NVIDIA CK804
Sean Nelson92bc6bd2010-03-19 22:37:29 +00001104 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001105static int nvidia_mcp_gpio2_lower(void)
Sean Nelson92bc6bd2010-03-19 22:37:29 +00001106{
1107 return nvidia_mcp_gpio_set(0x02, 0);
1108}
1109
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001110/*
1111 * Suited for:
Michael Karcher2842db32011-04-14 23:14:27 +00001112 * - Foxconn 6150K8MD-8EKRSH: Socket 939 + NVIDIA MCP51
Uwe Hermannead705f2010-08-15 15:26:30 +00001113 * - MSI K8N Neo4: NVIDIA CK804. TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html.
1114 * - MSI K8NGM2-L: NVIDIA MCP51
Joshua Roys6e48a022012-06-29 23:07:14 +00001115 * - MSI K9N SLI: NVIDIA MCP55
Luc Verhaegen6c5f7332009-12-23 03:01:36 +00001116 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001117static int nvidia_mcp_gpio2_raise(void)
Luc Verhaegen6c5f7332009-12-23 03:01:36 +00001118{
1119 return nvidia_mcp_gpio_set(0x02, 1);
1120}
1121
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001122/*
1123 * Suited for:
Uwe Hermann83d349a2010-10-18 22:32:03 +00001124 * - EPoX EP-8NPA7I: Socket 754 + NVIDIA nForce4 4X
Jonathan Kollaschf8db9592010-10-15 23:02:15 +00001125 */
1126static int nvidia_mcp_gpio4_raise(void)
1127{
1128 return nvidia_mcp_gpio_set(0x04, 1);
1129}
1130
1131/*
1132 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001133 * - HP xw9400 (Tyan S2915-E OEM): Dual(!) NVIDIA MCP55
1134 *
1135 * Notes: a) There are two MCP55 chips, so also two SMBus bridges on that
1136 * board. We can't tell the SMBus logical devices apart, but we
1137 * can tell the LPC bridge functions apart.
1138 * We need to choose the SMBus bridge next to the LPC bridge with
1139 * ID 0x364 and the "LPC bridge" class.
1140 * b) #TBL is hardwired on that board to a pull-down. It can be
1141 * overridden by connecting the two solder points next to F2.
Michael Karcher2ead2e22010-06-01 16:09:06 +00001142 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001143static int nvidia_mcp_gpio5_raise(void)
Michael Karcher2ead2e22010-06-01 16:09:06 +00001144{
1145 return nvidia_mcp_gpio_set(0x05, 1);
1146}
1147
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001148/*
1149 * Suited for:
1150 * - abit NF7-S: NVIDIA CK804
Michael Karcher8f10d242010-04-11 21:01:06 +00001151 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001152static int nvidia_mcp_gpio8_raise(void)
Michael Karcher8f10d242010-04-11 21:01:06 +00001153{
1154 return nvidia_mcp_gpio_set(0x08, 1);
1155}
1156
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001157/*
1158 * Suited for:
Cristian Măgherușan-Stanciu9932c7b2011-07-07 19:56:58 +00001159 * - GIGABYTE GA-K8NS Pro-939: Socket 939 + NVIDIA nForce3 + CK8
Idwer Volleringd8a00a02011-06-13 16:58:54 +00001160 */
1161static int nvidia_mcp_gpio0a_raise(void)
1162{
1163 return nvidia_mcp_gpio_set(0x0a, 1);
1164}
1165
1166/*
1167 * Suited for:
Stefan Tauner33366a02012-09-15 15:51:09 +00001168 * - MSI K8N Neo Platinum: Socket 754 + nForce3 Ultra + CK8
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001169 * - MSI K8N Neo2 Platinum: Socket 939 + nForce3 Ultra + CK8
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001170 */
Michael Karcher51825082010-06-12 23:14:03 +00001171static int nvidia_mcp_gpio0c_raise(void)
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001172{
1173 return nvidia_mcp_gpio_set(0x0c, 1);
1174}
1175
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001176/*
1177 * Suited for:
1178 * - abit NF-M2 nView: Socket AM2 + NVIDIA MCP51
Michael Karcherefd8af32010-07-24 22:50:54 +00001179 */
1180static int nvidia_mcp_gpio4_lower(void)
1181{
1182 return nvidia_mcp_gpio_set(0x04, 0);
1183}
1184
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001185/*
1186 * Suited for:
1187 * - ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001188 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001189static int nvidia_mcp_gpio10_raise(void)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001190{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001191 return nvidia_mcp_gpio_set(0x10, 1);
1192}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001193
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001194/*
1195 * Suited for:
1196 * - GIGABYTE GA-K8N-SLI: AMD socket 939 + NVIDIA CK804 + ITE IT8712F
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001197 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001198static int nvidia_mcp_gpio21_raise(void)
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001199{
1200 return nvidia_mcp_gpio_set(0x21, 0x01);
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001201}
1202
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001203/*
1204 * Suited for:
1205 * - EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001206 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001207static int nvidia_mcp_gpio31_raise(void)
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001208{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001209 return nvidia_mcp_gpio_set(0x31, 0x01);
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001210}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001211
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001212/*
1213 * Suited for:
Michael Karcher242efd42011-03-06 12:09:05 +00001214 * - GIGABYTE GA-K8N51GMF: Socket 754 + Geforce 6100 + MCP51
1215 * - GIGABYTE GA-K8N51GMF-9: Socket 939 + Geforce 6100 + MCP51
Joshua Roys2ee137f2010-09-07 17:52:09 +00001216 */
1217static int nvidia_mcp_gpio3b_raise(void)
1218{
1219 return nvidia_mcp_gpio_set(0x3b, 1);
1220}
1221
1222/*
1223 * Suited for:
Joshua Roysb992d342011-11-02 14:31:18 +00001224 * - Sun Ultra 40 M2: Dual Socket F (1207) + MCP55
1225 */
1226static int board_sun_ultra_40_m2(void)
1227{
1228 int ret;
1229 uint8_t reg;
1230 uint16_t base;
1231 struct pci_dev *dev;
1232
1233 ret = nvidia_mcp_gpio4_lower();
1234 if (ret)
1235 return ret;
1236
1237 dev = pci_dev_find(0x10de, 0x0364); /* NVIDIA MCP55 LPC bridge */
1238 if (!dev) {
1239 msg_perr("\nERROR: NVIDIA MCP55 LPC bridge not found.\n");
1240 return -1;
1241 }
1242
1243 base = pci_read_word(dev, 0xb4); /* some IO BAR? */
1244 if (!base)
1245 return -1;
1246
1247 reg = INB(base + 0x4b);
1248 reg |= 0x10;
1249 OUTB(reg, base + 0x4b);
1250
1251 return 0;
1252}
1253
1254/*
1255 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001256 * - Artec Group DBE61 and DBE62
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001257 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001258static int board_artecgroup_dbe6x(void)
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001259{
1260#define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001261#define DBE6x_PRI_BOOT_LOC_SHIFT 2
1262#define DBE6x_BOOT_OP_LATCHED_SHIFT 8
1263#define DBE6x_SEC_BOOT_LOC_SHIFT 10
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001264#define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT)
1265#define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT)
1266#define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT)
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001267#define DBE6x_BOOT_LOC_FLASH 2
1268#define DBE6x_BOOT_LOC_FWHUB 3
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001269
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001270 msr_t msr;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001271 unsigned long boot_loc;
1272
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001273 /* Geode only has a single core */
1274 if (setup_cpu_msr(0))
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001275 return -1;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001276
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001277 msr = rdmsr(DBE6x_MSR_DIVIL_BALL_OPTS);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001278
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001279 if ((msr.lo & (DBE6x_BOOT_OP_LATCHED)) ==
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001280 (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT))
1281 boot_loc = DBE6x_BOOT_LOC_FWHUB;
1282 else
1283 boot_loc = DBE6x_BOOT_LOC_FLASH;
1284
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001285 msr.lo &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC);
1286 msr.lo |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) |
Uwe Hermann394131e2008-10-18 21:14:13 +00001287 (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001288
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001289 wrmsr(DBE6x_MSR_DIVIL_BALL_OPTS, msr);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001290
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001291 cleanup_cpu_msr();
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001292
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001293 return 0;
1294}
1295
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001296/*
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001297 * Suited for:
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001298 * - ASUS A8AE-LE (Codename AmberineM; used in Compaq Presario 061)
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001299 * Datasheet(s) used:
1300 * - AMD document 43009 "AMD SB700/710/750 Register Reference Guide" rev. 1.00
1301 */
1302static int amd_sbxxx_gpio9_raise(void)
1303{
1304 struct pci_dev *dev;
1305 uint32_t reg;
1306
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001307 dev = pci_dev_find(0x1002, 0x4372); /* AMD SMBus controller */
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001308 if (!dev) {
1309 msg_perr("\nERROR: AMD SMBus Controller (0x4372) not found.\n");
1310 return -1;
1311 }
1312
1313 reg = pci_read_long(dev, 0xA8); /* GPIO_12_to_4_Cntrl CI_Reg: A8h-ABh */
1314 /* enable output (0: enable, 1: tristate):
1315 GPIO9 output enable is at bit 5 in 0xA9 */
1316 reg &= ~((uint32_t)1<<(8+5));
1317 /* raise:
1318 GPIO9 output register is at bit 5 in 0xA8 */
1319 reg |= (1<<5);
1320 pci_write_long(dev, 0xA8, reg);
1321
1322 return 0;
1323}
1324
1325/*
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001326 * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}.
Luc Verhaegenf5226912009-12-14 10:41:58 +00001327 */
1328static int intel_piix4_gpo_set(unsigned int gpo, int raise)
1329{
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001330 unsigned int gpo_byte, gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001331 struct pci_dev *dev;
1332 uint32_t tmp, base;
1333
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001334 /* GPO{0,8,27,28,30} are always available. */
1335 static const uint32_t nonmuxed_gpos = 0x58000101;
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001336
1337 static const struct {unsigned int reg, mask, value; } piix4_gpo[] = {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001338 {0},
1339 {0xB0, 0x0001, 0x0000}, /* GPO1... */
1340 {0xB0, 0x0001, 0x0000},
1341 {0xB0, 0x0001, 0x0000},
1342 {0xB0, 0x0001, 0x0000},
1343 {0xB0, 0x0001, 0x0000},
1344 {0xB0, 0x0001, 0x0000},
1345 {0xB0, 0x0001, 0x0000}, /* ...GPO7: GENCFG bit 0 */
1346 {0},
1347 {0xB0, 0x0100, 0x0000}, /* GPO9: GENCFG bit 8 */
1348 {0xB0, 0x0200, 0x0000}, /* GPO10: GENCFG bit 9 */
1349 {0xB0, 0x0400, 0x0000}, /* GPO11: GENCFG bit 10 */
1350 {0x4E, 0x0100, 0x0000}, /* GPO12... */
1351 {0x4E, 0x0100, 0x0000},
1352 {0x4E, 0x0100, 0x0000}, /* ...GPO14: XBCS bit 8 */
1353 {0xB2, 0x0002, 0x0002}, /* GPO15... */
1354 {0xB2, 0x0002, 0x0002}, /* ...GPO16: GENCFG bit 17 */
1355 {0xB2, 0x0004, 0x0004}, /* GPO17: GENCFG bit 18 */
1356 {0xB2, 0x0008, 0x0008}, /* GPO18: GENCFG bit 19 */
1357 {0xB2, 0x0010, 0x0010}, /* GPO19: GENCFG bit 20 */
1358 {0xB2, 0x0020, 0x0020}, /* GPO20: GENCFG bit 21 */
1359 {0xB2, 0x0040, 0x0040}, /* GPO21: GENCFG bit 22 */
1360 {0xB2, 0x1000, 0x1000}, /* GPO22... */
1361 {0xB2, 0x1000, 0x1000}, /* ...GPO23: GENCFG bit 28 */
1362 {0xB2, 0x2000, 0x2000}, /* GPO24: GENCFG bit 29 */
1363 {0xB2, 0x4000, 0x4000}, /* GPO25: GENCFG bit 30 */
1364 {0xB2, 0x8000, 0x8000}, /* GPO26: GENCFG bit 31 */
1365 {0},
1366 {0},
1367 {0x4E, 0x0100, 0x0000}, /* ...GPO29: XBCS bit 8 */
1368 {0}
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001369 };
1370
Luc Verhaegenf5226912009-12-14 10:41:58 +00001371 dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */
1372 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001373 msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +00001374 return -1;
1375 }
1376
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001377 /* Sanity check. */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001378 if (gpo > 30) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001379 msg_perr("\nERROR: Intel PIIX4 has no GPO%d.\n", gpo);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001380 return -1;
1381 }
1382
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001383 if ((((1 << gpo) & nonmuxed_gpos) == 0) &&
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001384 ((pci_read_word(dev, piix4_gpo[gpo].reg) & piix4_gpo[gpo].mask) !=
1385 piix4_gpo[gpo].value)) {
1386 msg_perr("\nERROR: PIIX4 GPO%d not programmed for output.\n", gpo);
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001387 return -1;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001388 }
1389
Luc Verhaegenf5226912009-12-14 10:41:58 +00001390 dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */
1391 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001392 msg_perr("\nERROR: Intel PIIX4 PM not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +00001393 return -1;
1394 }
1395
1396 /* PM IO base */
1397 base = pci_read_long(dev, 0x40) & 0x0000FFC0;
1398
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001399 gpo_byte = gpo >> 3;
1400 gpo_bit = gpo & 7;
1401 tmp = INB(base + 0x34 + gpo_byte); /* GPO register */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001402 if (raise)
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001403 tmp |= 0x01 << gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001404 else
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001405 tmp &= ~(0x01 << gpo_bit);
1406 OUTB(tmp, base + 0x34 + gpo_byte);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001407
1408 return 0;
1409}
1410
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001411/*
1412 * Suited for:
Joshua Roysd708fad2012-02-17 14:51:15 +00001413 * - ASUS OPLX-M
Mattias Mattsson85016b92010-09-01 01:21:34 +00001414 * - ASUS P2B-N
1415 */
1416static int intel_piix4_gpo18_lower(void)
1417{
1418 return intel_piix4_gpo_set(18, 0);
1419}
1420
1421/*
1422 * Suited for:
Mattias Mattssonc8ca3de2010-09-13 18:22:36 +00001423 * - MSI MS-6163 v2 (MS-6163 Pro): Intel 440BX + PIIX4E + Winbond W83977EF
1424 */
1425static int intel_piix4_gpo14_raise(void)
1426{
1427 return intel_piix4_gpo_set(14, 1);
1428}
1429
1430/*
1431 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001432 * - EPoX EP-BX3
Luc Verhaegenf5226912009-12-14 10:41:58 +00001433 */
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001434static int intel_piix4_gpo22_raise(void)
Luc Verhaegenf5226912009-12-14 10:41:58 +00001435{
1436 return intel_piix4_gpo_set(22, 1);
1437}
1438
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001439/*
1440 * Suited for:
Tim ter Laak4b933f02010-09-13 23:00:57 +00001441 * - abit BM6
1442 */
1443static int intel_piix4_gpo26_lower(void)
1444{
1445 return intel_piix4_gpo_set(26, 0);
1446}
1447
1448/*
1449 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001450 * - Intel SE440BX-2
Michael Karcher51cd0c92010-03-19 22:35:21 +00001451 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001452static int intel_piix4_gpo27_lower(void)
Michael Karcher51cd0c92010-03-19 22:35:21 +00001453{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001454 return intel_piix4_gpo_set(27, 0);
Michael Karcher51cd0c92010-03-19 22:35:21 +00001455}
1456
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001457/*
Mattias Mattsson2eaad632010-10-05 21:32:29 +00001458 * Suited for:
1459 * - Dell OptiPlex GX1
1460 */
1461static int intel_piix4_gpo30_lower(void)
1462{
1463 return intel_piix4_gpo_set(30, 0);
1464}
1465
1466/*
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001467 * Set a GPIO line on a given Intel ICH LPC controller.
Uwe Hermann93f66db2008-05-22 21:19:38 +00001468 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001469static int intel_ich_gpio_set(int gpio, int raise)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001470{
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001471 /* Table mapping the different Intel ICH LPC chipsets. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001472 static struct {
1473 uint16_t id;
1474 uint8_t base_reg;
1475 uint32_t bank0;
1476 uint32_t bank1;
1477 uint32_t bank2;
1478 } intel_ich_gpio_table[] = {
1479 {0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */
1480 {0x2420, 0x58, 0x0FE30000, 0, 0}, /* 82801AB (ICH0) */
1481 {0x2440, 0x58, 0x1BFF391B, 0, 0}, /* 82801BA (ICH2) */
1482 {0x244C, 0x58, 0x1A23399B, 0, 0}, /* 82801BAM (ICH2M) */
1483 {0x2450, 0x58, 0x1BFF0000, 0, 0}, /* 82801E (C-ICH) */
1484 {0x2480, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801CA (ICH3-S) */
1485 {0x248C, 0x58, 0x1A230000, 0x00000FFF, 0}, /* 82801CAM (ICH3-M) */
1486 {0x24C0, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801DB/DBL (ICH4/ICH4-L) */
1487 {0x24CC, 0x58, 0x1A030000, 0x00000FFF, 0}, /* 82801DBM (ICH4-M) */
1488 {0x24D0, 0x58, 0x1BFF0000, 0x00030305, 0}, /* 82801EB/ER (ICH5/ICH5R) */
1489 {0x2640, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FB/FR (ICH6/ICH6R) */
1490 {0x2641, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FBM (ICH6M) */
1491 {0x27B8, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GB/GR (ICH7 Family) */
1492 {0x27B9, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GBM (ICH7-M) */
1493 {0x27BD, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GHM (ICH7-M DH) */
1494 {0x2810, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HB/HR (ICH8/R) */
1495 {0x2811, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HBM (ICH8M-E) */
1496 {0x2812, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HH (ICH8DH) */
1497 {0x2814, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HO (ICH8DO) */
1498 {0x2815, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HEM (ICH8M) */
1499 {0x2912, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IH (ICH9DH) */
1500 {0x2914, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IO (ICH9DO) */
1501 {0x2916, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IR (ICH9R) */
1502 {0x2917, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IEM (ICH9M-E) */
1503 {0x2918, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IB (ICH9) */
1504 {0x2919, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IBM (ICH9M) */
1505 {0x3A14, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JDO (ICH10DO) */
1506 {0x3A16, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIR (ICH10R) */
1507 {0x3A18, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIB (ICH10) */
1508 {0x3A1A, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JD (ICH10D) */
1509 {0, 0, 0, 0, 0} /* end marker */
1510 };
Uwe Hermann93f66db2008-05-22 21:19:38 +00001511
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001512 struct pci_dev *dev;
1513 uint16_t base;
1514 uint32_t tmp;
1515 int i, allowed;
1516
1517 /* First, look for a known LPC bridge */
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001518 for (dev = pacc->devices; dev; dev = dev->next) {
Carl-Daniel Hailfingerd175e062010-05-21 23:00:56 +00001519 uint16_t device_class;
1520 /* libpci before version 2.2.4 does not store class info. */
1521 device_class = pci_read_word(dev, PCI_CLASS_DEVICE);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001522 if ((dev->vendor_id == 0x8086) &&
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001523 (device_class == 0x0601)) { /* ISA bridge */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001524 /* Is this device in our list? */
1525 for (i = 0; intel_ich_gpio_table[i].id; i++)
1526 if (dev->device_id == intel_ich_gpio_table[i].id)
1527 break;
1528
1529 if (intel_ich_gpio_table[i].id)
1530 break;
1531 }
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001532 }
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001533
Uwe Hermann93f66db2008-05-22 21:19:38 +00001534 if (!dev) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001535 msg_perr("\nERROR: No known Intel LPC bridge found.\n");
Uwe Hermann93f66db2008-05-22 21:19:38 +00001536 return -1;
1537 }
1538
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001539 /*
1540 * According to the datasheets, all Intel ICHs have the GPIO bar 5:1
1541 * strapped to zero. From some mobile ICH9 version on, this becomes
1542 * 6:1. The mask below catches all.
1543 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001544 base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0;
Uwe Hermann93f66db2008-05-22 21:19:38 +00001545
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001546 /* Check whether the line is allowed. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001547 if (gpio < 32)
1548 allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01;
1549 else if (gpio < 64)
1550 allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01;
1551 else
1552 allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01;
1553
1554 if (!allowed) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001555 msg_perr("\nERROR: This Intel LPC bridge does not allow"
1556 " setting GPIO%02d\n", gpio);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001557 return -1;
1558 }
1559
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001560 msg_pdbg("\nIntel ICH LPC bridge: %sing GPIO%02d.\n",
1561 raise ? "Rais" : "Dropp", gpio);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001562
1563 if (gpio < 32) {
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001564 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001565 tmp = INL(base);
1566 /* ICH/ICH0 multiplexes 27/28 on the line set. */
1567 if ((gpio == 28) &&
1568 ((dev->device_id == 0x2410) || (dev->device_id == 0x2420)))
1569 tmp |= 1 << 27;
1570 else
1571 tmp |= 1 << gpio;
1572 OUTL(tmp, base);
1573
1574 /* As soon as we are talking to ICH8 and above, this register
1575 decides whether we can set the gpio or not. */
1576 if (dev->device_id > 0x2800) {
1577 tmp = INL(base);
1578 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001579 msg_perr("\nERROR: This Intel LPC bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001580 " does not allow setting GPIO%02d\n",
1581 gpio);
1582 return -1;
1583 }
1584 }
1585
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001586 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001587 tmp = INL(base + 0x04);
1588 tmp &= ~(1 << gpio);
1589 OUTL(tmp, base + 0x04);
1590
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001591 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001592 tmp = INL(base + 0x0C);
1593 if (raise)
1594 tmp |= 1 << gpio;
1595 else
1596 tmp &= ~(1 << gpio);
1597 OUTL(tmp, base + 0x0C);
1598 } else if (gpio < 64) {
1599 gpio -= 32;
1600
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001601 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001602 tmp = INL(base + 0x30);
1603 tmp |= 1 << gpio;
1604 OUTL(tmp, base + 0x30);
1605
1606 /* As soon as we are talking to ICH8 and above, this register
1607 decides whether we can set the gpio or not. */
1608 if (dev->device_id > 0x2800) {
1609 tmp = INL(base + 30);
1610 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001611 msg_perr("\nERROR: This Intel LPC bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001612 " does not allow setting GPIO%02d\n",
1613 gpio + 32);
1614 return -1;
1615 }
1616 }
1617
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001618 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001619 tmp = INL(base + 0x34);
1620 tmp &= ~(1 << gpio);
1621 OUTL(tmp, base + 0x34);
1622
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001623 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001624 tmp = INL(base + 0x38);
1625 if (raise)
1626 tmp |= 1 << gpio;
1627 else
1628 tmp &= ~(1 << gpio);
1629 OUTL(tmp, base + 0x38);
1630 } else {
1631 gpio -= 64;
1632
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001633 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001634 tmp = INL(base + 0x40);
1635 tmp |= 1 << gpio;
1636 OUTL(tmp, base + 0x40);
1637
1638 tmp = INL(base + 40);
1639 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001640 msg_perr("\nERROR: This Intel LPC bridge does "
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001641 "not allow setting GPIO%02d\n", gpio + 64);
1642 return -1;
1643 }
1644
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001645 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001646 tmp = INL(base + 0x44);
1647 tmp &= ~(1 << gpio);
1648 OUTL(tmp, base + 0x44);
1649
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001650 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001651 tmp = INL(base + 0x48);
1652 if (raise)
1653 tmp |= 1 << gpio;
1654 else
1655 tmp &= ~(1 << gpio);
1656 OUTL(tmp, base + 0x48);
1657 }
Uwe Hermann93f66db2008-05-22 21:19:38 +00001658
1659 return 0;
1660}
1661
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001662/*
1663 * Suited for:
1664 * - abit IP35: Intel P35 + ICH9R
1665 * - abit IP35 Pro: Intel P35 + ICH9R
Joshua Roysac8b2a12011-08-11 04:21:34 +00001666 * - ASUS P5LD2
Idwer Vollering4d0cde12012-09-07 08:27:46 +00001667 * - ASUS P5LD2-VM
Uwe Hermann93f66db2008-05-22 21:19:38 +00001668 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001669static int intel_ich_gpio16_raise(void)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001670{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001671 return intel_ich_gpio_set(16, 1);
Uwe Hermann93f66db2008-05-22 21:19:38 +00001672}
1673
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001674/*
1675 * Suited for:
1676 * - HP Puffer2-UL8E (ASUS PTGD-LA OEM): LGA775 + 915 + ICH6
Michael Karchere57957c2010-07-24 11:14:37 +00001677 */
1678static int intel_ich_gpio18_raise(void)
1679{
1680 return intel_ich_gpio_set(18, 1);
1681}
1682
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001683/*
1684 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001685 * - MSI MS-7046: LGA775 + 915P + ICH6
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001686 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001687static int intel_ich_gpio19_raise(void)
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001688{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001689 return intel_ich_gpio_set(19, 1);
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001690}
1691
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001692/*
Luc Verhaegen6c5d4cc2009-11-28 18:26:21 +00001693 * Suited for:
Stefan Tauner027e0182012-05-02 19:48:21 +00001694 * - ASUS P5BV-R: LGA775 + 3200 + ICH7
1695 */
1696static int intel_ich_gpio20_raise(void)
1697{
1698 return intel_ich_gpio_set(20, 1);
1699}
1700
1701/*
1702 * Suited for:
Stefan Taunereb582572012-09-21 12:52:50 +00001703 * - ASUS CUSL2-C: Intel socket370 + 815 + ICH2
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001704 * - ASUS P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2
1705 * - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5
Michael Karcherf4b58792010-09-10 14:54:18 +00001706 * - ASUS P4P800: Intel socket478 + 865PE + ICH5R
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001707 * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R
Diego Elio Pettenòc6f71462011-03-06 22:52:55 +00001708 * - ASUS P4P800-VM: Intel socket478 + 865PE + ICH5R
Stefan Taunereb582572012-09-21 12:52:50 +00001709 * - ASUS P4P800-X: Intel socket478 + 865PE + ICH5R
Michael Karcher4a23e442010-09-10 14:46:46 +00001710 * - ASUS P5GD1 Pro: Intel LGA 775 + 915P + ICH6R
Joshua Roys1fd4f9e2011-08-11 05:47:32 +00001711 * - ASUS P5GD2 Premium: Intel LGA775 + 915G + ICH6R
Joshua Roysb1d980f2010-09-13 14:02:22 +00001712 * - ASUS P5GDC Deluxe: Intel socket775 + 915P + ICH6R
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001713 * - ASUS P5PE-VM: Intel LGA775 + 865G + ICH5
Stefan Taunerded71e52012-03-10 19:22:13 +00001714 * - ASUS TUSL2-C: Intel socket370 + 815 + ICH2
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001715 * - Samsung Polaris 32: socket478 + 865P + ICH5
Peter Stuge09c13332009-02-02 22:55:26 +00001716 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001717static int intel_ich_gpio21_raise(void)
Peter Stuge09c13332009-02-02 22:55:26 +00001718{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001719 return intel_ich_gpio_set(21, 1);
Peter Stuge09c13332009-02-02 22:55:26 +00001720}
1721
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001722/*
Michael Karcher03b80e92010-03-07 16:32:32 +00001723 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001724 * - ASUS P4B266: socket478 + Intel 845D + ICH2
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001725 * - ASUS P4B533-E: socket478 + 845E + ICH4
1726 * - ASUS P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2
Michael Karcherbfd89a52012-02-12 00:13:14 +00001727 * - TriGem Anaheim-3: socket370 + Intel 810 + ICH
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001728 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001729static int intel_ich_gpio22_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001730{
1731 return intel_ich_gpio_set(22, 1);
1732}
1733
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001734/*
1735 * Suited for:
Stefan Tauner716e0982011-07-25 20:38:52 +00001736 * - ASUS A8Jm (laptop): Intel 945 + ICH7
Michael Karcher14ab8d42011-08-25 14:06:50 +00001737 * - ASUS P5LP-LE used in ...
1738 * - HP Media Center m7270.fr Desktop PC as "Lithium-UL8E"
1739 * - Epson Endeavor MT7700
Stefan Tauner716e0982011-07-25 20:38:52 +00001740 */
1741static int intel_ich_gpio34_raise(void)
1742{
1743 return intel_ich_gpio_set(34, 1);
1744}
1745
1746/*
1747 * Suited for:
Stefan Taunerc6782182012-01-19 17:50:32 +00001748 * - AOpen i945GMx-VFX: Intel 945GM + ICH7-M used in ...
Paul Menzelac427b22012-02-16 21:07:07 +00001749 * - FSC ESPRIMO Q5010 (SMBIOS: D2544-B1)
Stefan Taunerc6782182012-01-19 17:50:32 +00001750 */
1751static int intel_ich_gpio38_raise(void)
1752{
1753 return intel_ich_gpio_set(38, 1);
1754}
1755
1756/*
1757 * Suited for:
Joshua Roysc73e2812011-07-09 19:46:53 +00001758 * - ASUS M6Ne (laptop): socket 479M (guessed) + Intel 855PM + ICH4-M
1759 */
1760static int intel_ich_gpio43_raise(void)
1761{
1762 return intel_ich_gpio_set(43, 1);
1763}
1764
1765/*
1766 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001767 * - HP Vectra VL400: 815 + ICH + PC87360
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001768 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001769static int board_hp_vl400(void)
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001770{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001771 int ret;
1772 ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */
1773 if (!ret)
Michael Karchercba52de2011-03-06 12:07:19 +00001774 ret = pc8736x_gpio_set(PC87360_ID, 0x09, 1); /* #WP ? */
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001775 if (!ret)
Michael Karchercba52de2011-03-06 12:07:19 +00001776 ret = pc8736x_gpio_set(PC87360_ID, 0x27, 1); /* #TBL */
1777 return ret;
1778}
1779
1780/*
1781 * Suited for:
1782 * - HP e-Vectra P2706T: 810E + ICH + PC87364
1783 */
1784static int board_hp_p2706t(void)
1785{
1786 int ret;
1787 ret = pc8736x_gpio_set(PC87364_ID, 0x25, 1);
1788 if (!ret)
1789 ret = pc8736x_gpio_set(PC87364_ID, 0x26, 1);
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001790 return ret;
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001791}
1792
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001793/*
Luc Verhaegen1265d8d2009-11-28 18:16:31 +00001794 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001795 * - Dell PowerEdge 1850: Intel PPGA604 + E7520 + ICH5R
1796 * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R
1797 * - ASRock 775i65G: Intel LGA 775 + 865G + ICH5
Uwe Hermann742999c2010-12-02 21:57:42 +00001798 * - MSI MS-6391 (845 Pro4): Intel Socket478 + 845 + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001799 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001800static int intel_ich_gpio23_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001801{
1802 return intel_ich_gpio_set(23, 1);
1803}
1804
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001805/*
1806 * Suited for:
Michael Karcher39dcdec2010-10-05 17:29:35 +00001807 * - GIGABYTE GA-6IEM: Intel Socket370 + i815 + ICH2
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001808 * - GIGABYTE GA-8IRML: Intel Socket478 + i845 + ICH2
Michael Karcherc7a1ffb2010-07-24 22:27:29 +00001809 */
1810static int intel_ich_gpio25_raise(void)
1811{
1812 return intel_ich_gpio_set(25, 1);
1813}
1814
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001815/*
1816 * Suited for:
1817 * - IBASE MB899: i945GM + ICH7
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001818 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001819static int intel_ich_gpio26_raise(void)
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001820{
1821 return intel_ich_gpio_set(26, 1);
1822}
1823
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001824/*
1825 * Suited for:
1826 * - P4SD-LA (HP OEM): i865 + ICH5
Joshua Roys9d9a1042011-06-13 16:59:01 +00001827 * - GIGABYTE GA-8IP775: 865P + ICH5
Michael Karcherc8613242010-08-13 12:49:01 +00001828 * - GIGABYTE GA-8PE667 Ultra 2: socket 478 + i845PE + ICH4
Maciej Pijanka6add0942011-06-09 20:59:30 +00001829 * - MSI MS-6788-40 (aka 848P Neo-V)
Michael Karcher87c90992010-07-24 11:03:48 +00001830 */
Idwer Vollering19dceac2010-07-24 18:47:45 +00001831static int intel_ich_gpio32_raise(void)
Michael Karcher87c90992010-07-24 11:03:48 +00001832{
1833 return intel_ich_gpio_set(32, 1);
1834}
1835
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001836/*
1837 * Suited for:
Joshua Roys7225ccd2011-05-18 01:32:16 +00001838 * - AOpen i975Xa-YDG: i975X + ICH7 + W83627EHF
1839 */
1840static int board_aopen_i975xa_ydg(void)
1841{
1842 int ret;
1843
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001844 /* Vendor BIOS ends up in LDN6... maybe the board enable is wrong,
Joshua Roys7225ccd2011-05-18 01:32:16 +00001845 * or perhaps it's not needed at all?
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001846 * The regs it tries to touch are 0xF0, 0xF1, 0xF2 which means if it
1847 * were in the right LDN, it would have to be GPIO1 or GPIO3.
Joshua Roys7225ccd2011-05-18 01:32:16 +00001848 */
1849/*
1850 ret = winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, x, 0)
1851 if (!ret)
1852*/
1853 ret = intel_ich_gpio_set(33, 1);
1854
1855 return ret;
1856}
1857
1858/*
1859 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001860 * - Acorp 6A815EPD: socket 370 + intel 815 + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001861 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001862static int board_acorp_6a815epd(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001863{
1864 int ret;
1865
1866 /* Lower Blocks Lock -- pin 7 of PLCC32 */
1867 ret = intel_ich_gpio_set(22, 1);
1868 if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */
1869 ret = intel_ich_gpio_set(23, 1);
1870
1871 return ret;
1872}
1873
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001874/*
1875 * Suited for:
1876 * - Kontron 986LCD-M: Socket478 + 915GM + ICH7R
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001877 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001878static int board_kontron_986lcd_m(void)
Stefan Reinauerac378972008-03-17 22:59:40 +00001879{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001880 int ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001881
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001882 ret = intel_ich_gpio_set(34, 1); /* #TBL */
1883 if (!ret)
1884 ret = intel_ich_gpio_set(35, 1); /* #WP */
Stefan Reinauerac378972008-03-17 22:59:40 +00001885
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001886 return ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001887}
1888
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001889/*
1890 * Suited for:
1891 * - Soyo SY-7VCA: Pro133A + VT82C686
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001892 */
Michael Karcher06477332010-03-19 22:49:09 +00001893static int via_apollo_gpo_set(int gpio, int raise)
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001894{
Michael Karcher06477332010-03-19 22:49:09 +00001895 struct pci_dev *dev;
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001896 uint32_t base, tmp;
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001897
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001898 /* VT82C686 power management */
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001899 dev = pci_dev_find(0x1106, 0x3057);
1900 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001901 msg_perr("\nERROR: VT82C686 PM device not found.\n");
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001902 return -1;
1903 }
1904
Sean Nelson316a29f2010-05-07 20:09:04 +00001905 msg_pdbg("\nVIA Apollo ACPI: %sing GPIO%02d.\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001906 raise ? "Rais" : "Dropp", gpio);
Michael Karcher06477332010-03-19 22:49:09 +00001907
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001908 /* Select GPO function on multiplexed pins. */
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001909 tmp = pci_read_byte(dev, 0x54);
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001910 switch (gpio) {
1911 case 0:
1912 tmp &= ~0x03;
1913 break;
1914 case 1:
1915 tmp |= 0x04;
1916 break;
1917 case 2:
1918 tmp |= 0x08;
1919 break;
1920 case 3:
1921 tmp |= 0x10;
1922 break;
Michael Karcher06477332010-03-19 22:49:09 +00001923 }
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001924 pci_write_byte(dev, 0x54, tmp);
1925
1926 /* PM IO base */
1927 base = pci_read_long(dev, 0x48) & 0x0000FF00;
1928
1929 /* Drop GPO0 */
Michael Karcher06477332010-03-19 22:49:09 +00001930 tmp = INL(base + 0x4C);
1931 if (raise)
1932 tmp |= 1U << gpio;
1933 else
1934 tmp &= ~(1U << gpio);
1935 OUTL(tmp, base + 0x4C);
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001936
1937 return 0;
1938}
1939
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001940/*
1941 * Suited for:
1942 * - abit VT6X4: Pro133x + VT82C686A
Mattias Mattssone3df96e2010-08-15 22:43:23 +00001943 * - abit VA6: Pro133x + VT82C686A
Michael Karcher187a46a2010-03-19 22:30:49 +00001944 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001945static int via_apollo_gpo4_lower(void)
Michael Karcher187a46a2010-03-19 22:30:49 +00001946{
1947 return via_apollo_gpo_set(4, 0);
1948}
1949
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001950/*
1951 * Suited for:
1952 * - Soyo SY-7VCA: Pro133A + VT82C686
Michael Karcher06477332010-03-19 22:49:09 +00001953 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001954static int via_apollo_gpo0_lower(void)
Michael Karcher06477332010-03-19 22:49:09 +00001955{
1956 return via_apollo_gpo_set(0, 0);
1957}
1958
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001959/*
Michael Karchera08d0f22011-07-25 17:25:24 +00001960 * Enable some GPIO pin on SiS southbridge and enables SIO flash writes.
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001961 *
1962 * Suited for:
1963 * - MSI 651M-L: SiS651 / SiS962
Michael Karchera08d0f22011-07-25 17:25:24 +00001964 * - GIGABYTE GA-8SIMLH
Michael Karcher9f9e6132010-01-09 17:36:06 +00001965 */
Michael Karchera08d0f22011-07-25 17:25:24 +00001966static int sis_gpio0_raise_and_w836xx_memw(void)
Michael Karcher9f9e6132010-01-09 17:36:06 +00001967{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001968 struct pci_dev *dev;
Uwe Hermann43959702010-03-13 17:28:29 +00001969 uint16_t base, temp;
Michael Karcher9f9e6132010-01-09 17:36:06 +00001970
1971 dev = pci_dev_find(0x1039, 0x0962);
1972 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001973 msg_perr("Expected south bridge not found\n");
Michael Karcher9f9e6132010-01-09 17:36:06 +00001974 return 1;
1975 }
1976
Michael Karcher9f9e6132010-01-09 17:36:06 +00001977 base = pci_read_word(dev, 0x74);
1978 temp = INW(base + 0x68);
1979 temp &= ~(1 << 0); /* Make pin output? */
Michael Karcher0435dfd2010-01-09 23:31:13 +00001980 OUTW(temp, base + 0x68);
Michael Karcher9f9e6132010-01-09 17:36:06 +00001981
1982 temp = INW(base + 0x64);
1983 temp |= (1 << 0); /* Raise output? */
1984 OUTW(temp, base + 0x64);
1985
1986 w836xx_memw_enable(0x2E);
1987
1988 return 0;
1989}
1990
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001991/*
Michael Gold6d52e472009-06-19 13:00:24 +00001992 * Find the runtime registers of an SMSC Super I/O, after verifying its
1993 * chip ID.
1994 *
1995 * Returns the base port of the runtime register block, or 0 on error.
1996 */
1997static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id,
1998 uint8_t logical_device)
1999{
2000 uint16_t rt_port = 0;
2001
2002 /* Verify the chip ID. */
Uwe Hermann1432a602009-06-28 23:26:37 +00002003 OUTB(0x55, sio_port); /* Enable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00002004 if (sio_read(sio_port, 0x20) != chip_id) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002005 msg_perr("\nERROR: SMSC Super I/O not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +00002006 goto out;
2007 }
2008
2009 /* If the runtime block is active, get its address. */
2010 sio_write(sio_port, 0x07, logical_device);
2011 if (sio_read(sio_port, 0x30) & 1) {
2012 rt_port = (sio_read(sio_port, 0x60) << 8)
2013 | sio_read(sio_port, 0x61);
2014 }
2015
2016 if (rt_port == 0) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002017 msg_perr("\nERROR: "
Michael Gold6d52e472009-06-19 13:00:24 +00002018 "Super I/O runtime interface not available.\n");
2019 }
2020out:
Uwe Hermann1432a602009-06-28 23:26:37 +00002021 OUTB(0xaa, sio_port); /* Disable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00002022 return rt_port;
2023}
2024
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002025/*
2026 * Disable write protection on the Mitac 6513WU. WP# on the FWH is
Michael Gold6d52e472009-06-19 13:00:24 +00002027 * connected to GP30 on the Super I/O, and TBL# is always high.
2028 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00002029static int board_mitac_6513wu(void)
Michael Gold6d52e472009-06-19 13:00:24 +00002030{
2031 struct pci_dev *dev;
2032 uint16_t rt_port;
2033 uint8_t val;
2034
2035 dev = pci_dev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */
2036 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002037 msg_perr("\nERROR: Intel 82801AA ISA bridge not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +00002038 return -1;
2039 }
2040
Uwe Hermann1432a602009-06-28 23:26:37 +00002041 rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa);
Michael Gold6d52e472009-06-19 13:00:24 +00002042 if (rt_port == 0)
2043 return -1;
2044
2045 /* Configure the GPIO pin. */
2046 val = INB(rt_port + 0x33); /* GP30 config */
Uwe Hermann1432a602009-06-28 23:26:37 +00002047 val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */
Michael Gold6d52e472009-06-19 13:00:24 +00002048 OUTB(val, rt_port + 0x33);
2049
2050 /* Disable write protection. */
2051 val = INB(rt_port + 0x4d); /* GP3 values */
Uwe Hermann1432a602009-06-28 23:26:37 +00002052 val |= 0x01; /* Set GP30 high. */
Michael Gold6d52e472009-06-19 13:00:24 +00002053 OUTB(val, rt_port + 0x4d);
2054
2055 return 0;
2056}
2057
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002058/*
2059 * Suited for:
Christoph Grenzd13a3942011-10-21 13:20:11 +00002060 * - abit AV8: Socket939 + K8T800Pro + VT8237
2061 */
2062static int board_abit_av8(void)
2063{
2064 uint8_t val;
2065
2066 /* Raise GPO pins GP22 & GP23 */
2067 val = INB(0x404E);
2068 val |= 0xC0;
2069 OUTB(val, 0x404E);
2070
2071 return 0;
2072}
2073
2074/*
2075 * Suited for:
Uwe Hermann45bd1442010-09-14 23:20:35 +00002076 * - ASUS A7V333: VIA KT333 + VT8233A + IT8703F
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002077 * - ASUS A7V8X: VIA KT400 + VT8235 + IT8703F
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002078 */
Uwe Hermann45bd1442010-09-14 23:20:35 +00002079static int it8703f_gpio51_raise(void)
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002080{
2081 uint16_t id, base;
2082 uint8_t tmp;
2083
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002084 /* Find the IT8703F. */
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002085 w836xx_ext_enter(0x2E);
2086 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
2087 w836xx_ext_leave(0x2E);
2088
2089 if (id != 0x8701) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002090 msg_perr("\nERROR: IT8703F Super I/O not found.\n");
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002091 return -1;
2092 }
2093
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002094 /* Get the GP567 I/O base. */
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002095 w836xx_ext_enter(0x2E);
2096 sio_write(0x2E, 0x07, 0x0C);
2097 base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
2098 w836xx_ext_leave(0x2E);
2099
2100 if (!base) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002101 msg_perr("\nERROR: Failed to read IT8703F Super I/O GPIO"
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002102 " Base.\n");
2103 return -1;
2104 }
2105
2106 /* Raise GP51. */
2107 tmp = INB(base);
2108 tmp |= 0x02;
2109 OUTB(tmp, base);
2110
2111 return 0;
2112}
2113
Luc Verhaegen72272912009-09-01 21:22:23 +00002114/*
Joshua Roysa2f37222011-11-14 13:00:12 +00002115 * General routine for raising/dropping GPIO lines on the ITE IT87xx.
Luc Verhaegen72272912009-09-01 21:22:23 +00002116 */
Joshua Roysa2f37222011-11-14 13:00:12 +00002117static int it87_gpio_set(unsigned int gpio, int raise)
Luc Verhaegen72272912009-09-01 21:22:23 +00002118{
Joshua Roysa2f37222011-11-14 13:00:12 +00002119 int allowed, sio;
Luc Verhaegen72272912009-09-01 21:22:23 +00002120 unsigned int port;
Joshua Roysa2f37222011-11-14 13:00:12 +00002121 uint16_t base, sioport;
Luc Verhaegen72272912009-09-01 21:22:23 +00002122 uint8_t tmp;
2123
Joshua Roysa2f37222011-11-14 13:00:12 +00002124 /* IT87 GPIO configuration table */
2125 static const struct it87cfg {
2126 uint16_t id;
2127 uint8_t base_reg;
2128 uint32_t bank0;
2129 uint32_t bank1;
2130 uint32_t bank2;
2131 } it87_gpio_table[] = {
2132 {0x8712, 0x62, 0xCFF3FC00, 0x00FCFF3F, 0},
2133 {0x8718, 0x62, 0xCFF37C00, 0xF3FCDF3F, 0x0000000F},
2134 {0, 0, 0, 0, 0} /* end marker */
2135 };
2136 const struct it87cfg *cfg = NULL;
Luc Verhaegen72272912009-09-01 21:22:23 +00002137
Joshua Roysa2f37222011-11-14 13:00:12 +00002138 /* Find the Super I/O in the probed list */
2139 for (sio = 0; sio < superio_count; sio++) {
2140 int i;
2141 if (superios[sio].vendor != SUPERIO_VENDOR_ITE)
2142 continue;
2143
2144 /* Is this device in our list? */
2145 for (i = 0; it87_gpio_table[i].id; i++)
2146 if (superios[sio].model == it87_gpio_table[i].id) {
2147 cfg = &it87_gpio_table[i];
2148 goto found;
2149 }
2150 }
2151
2152 if (cfg == NULL) {
2153 msg_perr("\nERROR: No IT87 Super I/O GPIO configuration "
2154 "found.\n");
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002155 return -1;
Luc Verhaegen72272912009-09-01 21:22:23 +00002156 }
2157
Joshua Roysa2f37222011-11-14 13:00:12 +00002158found:
2159 /* Check whether the gpio is allowed. */
2160 if (gpio < 32)
2161 allowed = (cfg->bank0 >> gpio) & 0x01;
2162 else if (gpio < 64)
2163 allowed = (cfg->bank1 >> (gpio - 32)) & 0x01;
2164 else if (gpio < 96)
2165 allowed = (cfg->bank2 >> (gpio - 64)) & 0x01;
2166 else
2167 allowed = 0;
Luc Verhaegen72272912009-09-01 21:22:23 +00002168
Joshua Roysa2f37222011-11-14 13:00:12 +00002169 if (!allowed) {
2170 msg_perr("\nERROR: IT%02X does not allow setting GPIO%02u.\n",
2171 cfg->id, gpio);
Luc Verhaegen72272912009-09-01 21:22:23 +00002172 return -1;
2173 }
2174
Joshua Roysa2f37222011-11-14 13:00:12 +00002175 /* Read the Simple I/O Base Address Register */
2176 sioport = superios[sio].port;
2177 enter_conf_mode_ite(sioport);
2178 sio_write(sioport, 0x07, 0x07);
2179 base = (sio_read(sioport, cfg->base_reg) << 8) |
2180 sio_read(sioport, cfg->base_reg + 1);
2181 exit_conf_mode_ite(sioport);
Luc Verhaegen72272912009-09-01 21:22:23 +00002182
2183 if (!base) {
Joshua Roysa2f37222011-11-14 13:00:12 +00002184 msg_perr("\nERROR: Failed to read IT87 Super I/O GPIO Base.\n");
Luc Verhaegen72272912009-09-01 21:22:23 +00002185 return -1;
2186 }
2187
Joshua Roysa2f37222011-11-14 13:00:12 +00002188 msg_pdbg("Using IT87 GPIO base 0x%04x\n", base);
2189
2190 port = gpio / 10 - 1;
2191 gpio %= 10;
2192
2193 /* set GPIO. */
Luc Verhaegen72272912009-09-01 21:22:23 +00002194 tmp = INB(base + port);
2195 if (raise)
Joshua Roysa2f37222011-11-14 13:00:12 +00002196 tmp |= 1 << gpio;
Luc Verhaegen72272912009-09-01 21:22:23 +00002197 else
Joshua Roysa2f37222011-11-14 13:00:12 +00002198 tmp &= ~(1 << gpio);
Luc Verhaegen72272912009-09-01 21:22:23 +00002199 OUTB(tmp, base + port);
2200
2201 return 0;
2202}
2203
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002204/*
Russ Dillbd622d12010-03-09 16:57:06 +00002205 * Suited for:
Joshua Roys8ca42552011-11-19 19:31:17 +00002206 * - ASUS A7N8X-VM/400: NVIDIA nForce2 IGP2 + IT8712F
2207 */
2208static int it8712f_gpio12_raise(void)
2209{
2210 return it87_gpio_set(12, 1);
2211}
2212
2213/*
2214 * Suited for:
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00002215 * - ASUS A7V600-X: VIA KT600 + VT8237 + IT8712F
2216 * - ASUS A7V8X-X: VIA KT400 + VT8235 + IT8712F
Luc Verhaegen72272912009-09-01 21:22:23 +00002217 */
Joshua Roysa2f37222011-11-14 13:00:12 +00002218static int it8712f_gpio31_raise(void)
Luc Verhaegen72272912009-09-01 21:22:23 +00002219{
Joshua Roysa2f37222011-11-14 13:00:12 +00002220 return it87_gpio_set(32, 1);
2221}
2222
2223/*
2224 * Suited for:
2225 * - ASUS P5N-D: NVIDIA MCP51 + IT8718F
2226 * - ASUS P5N-E SLI: NVIDIA MCP51 + IT8718F
2227 */
2228static int it8718f_gpio63_raise(void)
2229{
2230 return it87_gpio_set(63, 1);
Luc Verhaegen72272912009-09-01 21:22:23 +00002231}
2232
Ingo Feldschmid8a0f9b02012-01-31 06:51:56 +00002233/*
2234 * Suited for all boards with ambiguous DMI chassis information, which should be
2235 * whitelisted because they are known to work:
2236 * - MSC Q7 Tunnel Creek Module (Q7-TCTC)
2237 */
2238static int p2_not_a_laptop(void)
2239{
2240 /* label this board as not a laptop */
2241 is_laptop = 0;
2242 msg_pdbg("Laptop detection overridden by P2 board enable.\n");
2243 return 0;
2244}
2245
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00002246#endif
2247
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002248/*
Uwe Hermannd0e347d2009-10-06 13:00:00 +00002249 * Below is the list of boards which need a special "board enable" code in
2250 * flashrom before their ROM chip can be accessed/written to.
2251 *
2252 * NOTE: Please add boards that _don't_ need such enables or don't work yet
2253 * to the respective tables in print.c. Thanks!
2254 *
Uwe Hermannffec5f32007-08-23 16:08:21 +00002255 * We use 2 sets of IDs here, you're free to choose which is which. This
2256 * is to provide a very high degree of certainty when matching a board on
2257 * the basis of subsystem/card IDs. As not every vendor handles
2258 * subsystem/card IDs in a sane manner.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002259 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00002260 * Keep the second set NULLed if it should be ignored. Keep the subsystem IDs
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00002261 * NULLed if they don't identify the board fully and if you can't use DMI.
2262 * But please take care to provide an as complete set of pci ids as possible;
2263 * autodetection is the preferred behaviour and we would like to make sure that
2264 * matches are unique.
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00002265 *
Michael Karcher6701ee82010-01-20 14:14:11 +00002266 * If PCI IDs are not sufficient for board matching, the match can be further
2267 * constrained by a string that has to be present in the DMI database for
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00002268 * the baseboard or the system entry. The pattern is matched by case sensitive
Michael Karcher6701ee82010-01-20 14:14:11 +00002269 * substring match, unless it is anchored to the beginning (with a ^ in front)
2270 * or the end (with a $ at the end). Both anchors may be specified at the
2271 * same time to match the full field.
2272 *
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00002273 * When a board is matched through DMI, the first and second main PCI IDs
2274 * and the first subsystem PCI ID have to match as well. If you specify the
2275 * first subsystem ID as 0x0:0x0, the DMI matching code expects that the
2276 * subsystem ID of that device is indeed zero.
2277 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00002278 * The coreboot ids are used two fold. When running with a coreboot firmware,
2279 * the ids uniquely matches the coreboot board identification string. When a
2280 * legacy bios is installed and when autodetection is not possible, these ids
Carl-Daniel Hailfinger2d927fb2012-01-04 00:48:27 +00002281 * can be used to identify the board through the -p internal:mainboard=
2282 * programmer parameter.
Luc Verhaegenc5210162009-04-20 12:38:17 +00002283 *
2284 * When a board is identified through its coreboot ids (in both cases), the
2285 * main pci ids are still required to match, as a safeguard.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002286 */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002287
Uwe Hermanndeeebe22009-05-08 16:23:34 +00002288/* Please keep this list alphabetically ordered by vendor/board name. */
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002289const struct board_match board_matches[] = {
Uwe Hermann5ab88892009-06-21 20:50:22 +00002290
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002291 /* first pci-id set [4], second pci-id set [4], dmi identifier, coreboot id [2], phase, vendor name, board name max_rom_... OK? flash enable */
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00002292#if defined(__i386__) || defined(__x86_64__)
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002293 {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, P3, "abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise},
Christoph Grenzd13a3942011-10-21 13:20:11 +00002294 {0x1106, 0x0282, 0x147B, 0x1415, 0x1106, 0x3227, 0x147B, 0x1415, "^AV8 ", NULL, NULL, P3, "abit", "AV8", 0, OK, board_abit_av8},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002295 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^i440BX-W977 (BM6)$", NULL, NULL, P3, "abit", "BM6", 0, OK, intel_piix4_gpo26_lower},
2296 {0x8086, 0x24d3, 0x147b, 0x1014, 0x8086, 0x2578, 0x147b, 0x1014, NULL, NULL, NULL, P3, "abit", "IC7", 0, NT, intel_ich_gpio23_raise},
2297 {0x8086, 0x2930, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, P3, "abit", "IP35", 0, OK, intel_ich_gpio16_raise},
2298 {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, P3, "abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise},
Stefan Tauner24c38df2012-08-11 02:33:20 +00002299 {0x10de, 0x0050, 0x147b, 0x1c1a, 0x10de, 0x0052, 0x147b, 0x1c1a, NULL, NULL, NULL, P3, "abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002300 {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, P3, "abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise},
Paul Menzelac427b22012-02-16 21:07:07 +00002301 {0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0260, 0x147b, 0x1c26, NULL, NULL, NULL, P3, "abit", "NF-M2 nView", 0, OK, nvidia_mcp_gpio4_lower},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002302 {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, "(VA6)$", NULL, NULL, P3, "abit", "VA6", 0, OK, via_apollo_gpo4_lower},
2303 {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", P3, "abit", "VT6X4", 0, OK, via_apollo_gpo4_lower},
2304 {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, P3, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd},
Stefan Tauner24c38df2012-08-11 02:33:20 +00002305 {0x1022, 0x746B, 0, 0, 0x1022, 0x7460, 0, 0, NULL, "AGAMI", "ARUMA", P3, "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002306 {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, P3, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e},
2307 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", P3, "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x},
2308 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", P3, "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x},
Stefan Taunerc6782182012-01-19 17:50:32 +00002309 {0x8086, 0x27b9, 0xa0a0, 0x0632, 0x8086, 0x27da, 0xa0a0, 0x0632, NULL, NULL, NULL, P3, "AOpen", "i945GMx-VFX", 0, OK, intel_ich_gpio38_raise},
Joshua Roys7225ccd2011-05-18 01:32:16 +00002310 {0x8086, 0x277c, 0xa0a0, 0x060b, 0x8086, 0x27da, 0xa0a0, 0x060b, NULL, NULL, NULL, P3, "AOpen", "i975Xa-YDG", 0, OK, board_aopen_i975xa_ydg},
Joshua Roysea3aed02011-11-16 22:08:11 +00002311 {0x8086, 0x27b8, 0x1849, 0x27b8, 0x8086, 0x27da, 0x1849, 0x27da, "^ConRoeXFire-eSATA2", NULL, NULL, P3, "ASRock", "ConRoeXFire-eSATA2", 0, OK, intel_ich_gpio16_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002312 {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41 $", NULL, NULL, P3, "ASRock", "K7S41", 0, OK, w836xx_memw_enable_2e},
Pawel Rozanski1d233072011-06-19 16:52:48 +00002313 {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41GX$", NULL, NULL, P3, "ASRock", "K7S41GX", 0, OK, w836xx_memw_enable_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002314 {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, P3, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise},
2315 {0x8086, 0x2570, 0x1849, 0x2570, 0x8086, 0x24d3, 0x1849, 0x24d0, NULL, NULL, NULL, P3, "ASRock", "775i65G", 0, OK, intel_ich_gpio23_raise},
Joshua Roys8ca42552011-11-19 19:31:17 +00002316 {0x10DE, 0x0060, 0x1043, 0x80AD, 0x10DE, 0x01E0, 0x1043, 0x80C0, NULL, NULL, NULL, P3, "ASUS", "A7N8X-VM/400", 0, OK, it8712f_gpio12_raise},
Joshua Roysa2f37222011-11-14 13:00:12 +00002317 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, P3, "ASUS", "A7V600-X", 0, OK, it8712f_gpio31_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002318 {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, P3, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e},
2319 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V8X", 0, OK, it8703f_gpio51_raise},
2320 {0x1106, 0x3099, 0x1043, 0x807F, 0x1106, 0x3147, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V333", 0, OK, it8703f_gpio51_raise},
Joshua Roysa2f37222011-11-14 13:00:12 +00002321 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, P3, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio31_raise},
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00002322 {0x1002, 0x4372, 0x103c, 0x2a26, 0x1002, 0x4377, 0x103c, 0x2a26, NULL, NULL, NULL, P3, "ASUS", "A8AE-LE", 0, OK, amd_sbxxx_gpio9_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002323 {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, P3, "ASUS", "A8Jm", 0, NT, intel_ich_gpio34_raise},
Stefan Taunera9cbbac2011-08-07 13:17:20 +00002324 {0x10DE, 0x0260, 0x103C, 0x2A34, 0x10DE, 0x0264, 0x103C, 0x2A34, "NODUSM3", NULL, NULL, P3, "ASUS", "A8M2N-LA (NodusM3-GL8E)", 0, OK, nvidia_mcp_gpio0_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002325 {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI2L", NULL, NULL, P3, "ASUS", "A8N-LA (Nagami-GL8E)", 0, OK, nvidia_mcp_gpio0_raise},
Stefan Taunerff80e682011-07-20 16:34:18 +00002326 {0x10de, 0x0264, 0x1043, 0x81bc, 0x10de, 0x02f0, 0x1043, 0x81cd, NULL, NULL, NULL, P3, "ASUS", "A8N-VM CSM", 0, OK, w83627ehf_gpio22_raise_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002327 {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, P3, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise},
2328 {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, P3, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise},
Joshua Roysc73e2812011-07-09 19:46:53 +00002329 {0x8086, 0x24cc, 0, 0, 0x8086, 0x24c3, 0x1043, 0x1869, "^M6Ne$", NULL, NULL, P3, "ASUS", "M6Ne", 0, NT, intel_ich_gpio43_raise},
Joshua Roysd708fad2012-02-17 14:51:15 +00002330 {0x8086, 0x7180, 0, 0, 0x8086, 0x7110, 0, 0, "^OPLX-M$", NULL, NULL, P3, "ASUS", "OPLX-M", 0, NT, intel_piix4_gpo18_lower},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002331 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^P2B-N$", NULL, NULL, P3, "ASUS", "P2B-N", 0, OK, intel_piix4_gpo18_lower},
2332 {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, P3, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise},
2333 {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, P3, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise},
2334 {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, P3, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise},
Joshua Roysa5f5a152011-11-15 08:08:15 +00002335 {0x8086, 0x2560, 0x103C, 0x2A00, 0x8086, 0x24C3, 0x103C, 0x2A01, "^Guppy", NULL, NULL, P3, "ASUS", "P4GV-LA (Guppy)", 0, OK, intel_ich_gpio21_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002336 {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, P3, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
2337 {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D5, 0x1043, 0x80F3, NULL, NULL, NULL, P3, "ASUS", "P4P800", 0, NT, intel_ich_gpio21_raise},
Stefan Taunereb582572012-09-21 12:52:50 +00002338 {0x8086, 0x2570, 0x1043, 0x80f2, 0x8086, 0x24d3, 0x1043, 0x80a6, "^P4P800-E$", NULL, NULL, P3, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
2339 {0x8086, 0x2570, 0x1043, 0x80a5, 0x8086, 0x24d3, 0x1043, 0x80a6, "^P4P800-VM$", NULL, NULL, P3, "ASUS", "P4P800-VM", 0, OK, intel_ich_gpio21_raise},
2340 {0x8086, 0x2570, 0x1043, 0x80f2, 0x8086, 0x24d3, 0x1043, 0x80a6, "^P4P800-X$", NULL, NULL, P3, "ASUS", "P4P800-X", 0, OK, intel_ich_gpio21_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002341 {0x1039, 0x0651, 0x1043, 0x8081, 0x1039, 0x0962, 0, 0, NULL, NULL, NULL, P3, "ASUS", "P4SC-E", 0, OK, it8707f_write_enable_2e},
2342 {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, P3, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise},
2343 {0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x5513, 0x1043, 0x8087, NULL, NULL, NULL, P3, "ASUS", "P4S800-MX", 512, OK, w836xx_memw_enable_2e},
2344 {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", P3, "ASUS", "P5A", 0, OK, board_asus_p5a},
Stefan Tauner027e0182012-05-02 19:48:21 +00002345 {0x8086, 0x27b8, 0x1043, 0x819e, 0x8086, 0x29f0, 0x1043, 0x82a5, "^P5BV-R$", NULL, NULL, P3, "ASUS", "P5BV-R", 0, OK, intel_ich_gpio20_raise},
Stefan Taunera4f14472011-10-22 22:01:09 +00002346 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, "^P5GD1 PRO$", NULL, NULL, P3, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise},
2347 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, "^P5GD1-VM$", NULL, NULL, P3, "ASUS", "P5GD1-VM/S", 0, OK, intel_ich_gpio21_raise},
2348 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, P3, "ASUS", "P5GD1(-VM)", 0, NT, intel_ich_gpio21_raise},
Joshua Roys1fd4f9e2011-08-11 05:47:32 +00002349 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GD2-Premium$", NULL, NULL, P3, "ASUS", "P5GD2 Premium", 0, OK, intel_ich_gpio21_raise},
Stefan Taunerd94d25d2012-07-28 03:17:15 +00002350 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x81a6, "^P5GD2-X$", NULL, NULL, P3, "ASUS", "P5GD2-X", 0, OK, intel_ich_gpio21_raise},
Stefan Taunera4f14472011-10-22 22:01:09 +00002351 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GDC-V$", NULL, NULL, P3, "ASUS", "P5GDC-V Deluxe", 0, OK, intel_ich_gpio21_raise},
2352 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GDC$", NULL, NULL, P3, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise},
2353 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, P3, "ASUS", "P5GD2/C variants", 0, NT, intel_ich_gpio21_raise},
Michael Karcher14ab8d42011-08-25 14:06:50 +00002354 {0x8086, 0x27b8, 0x103c, 0x2a22, 0x8086, 0x2770, 0x103c, 0x2a22, "^LITHIUM$", NULL, NULL, P3, "ASUS", "P5LP-LE (Lithium-UL8E)",0, OK, intel_ich_gpio34_raise},
2355 {0x8086, 0x27b8, 0x1043, 0x2a22, 0x8086, 0x2770, 0x1043, 0x2a22, "^P5LP-LE$", NULL, NULL, P3, "ASUS", "P5LP-LE (Epson OEM)", 0, OK, intel_ich_gpio34_raise},
Joshua Roys1fd4f9e2011-08-11 05:47:32 +00002356 {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, NT, intel_ich_gpio16_raise},
Idwer Vollering4d0cde12012-09-07 08:27:46 +00002357 {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2-VM$", NULL, NULL, P3, "ASUS", "P5LD2-VM", 0, NT, intel_ich_gpio16_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002358 {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, P3, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise},
Joshua Roysa2f37222011-11-14 13:00:12 +00002359 {0x10DE, 0x0260, 0x1043, 0x81BC, 0x10DE, 0x026C, 0x1043, 0x829E, "^P5N-D$", NULL, NULL, P3, "ASUS", "P5N-D", 0, OK, it8718f_gpio63_raise},
2360 {0x10DE, 0x0260, 0x1043, 0x81BC, 0x10DE, 0x026C, 0x1043, 0x8249, "^P5N-E SLI$",NULL, NULL, P3, "ASUS", "P5N-E SLI", 0, NT, it8718f_gpio63_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002361 {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, P3, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise},
Stefan Taunereb582572012-09-21 12:52:50 +00002362 {0x8086, 0x2443, 0x1043, 0x8027, 0x8086, 0x1130, 0x1043, 0x8027, "^CUSL2-C", NULL, NULL, P3, "ASUS", "CUSL2-C", 0, OK, intel_ich_gpio21_raise},
2363 {0x8086, 0x2443, 0x1043, 0x8027, 0x8086, 0x1130, 0x1043, 0x8027, "^TUSL2-C", NULL, NULL, P3, "ASUS", "TUSL2-C", 0, NT, intel_ich_gpio21_raise},
2364 {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3116, 0x1106, 0x3116, "^KM266-8235$", "biostar", "m7viq", P3, "Biostar", "M7VIQ", 0, NT, w83697xx_memw_enable_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002365 {0x10b7, 0x9055, 0x1028, 0x0082, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Dell", "OptiPlex GX1", 0, OK, intel_piix4_gpo30_lower},
2366 {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, P3, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise},
Tadas Slotkus3dcdc032012-08-25 03:53:12 +00002367 {0x1106, 0x3189, 0x1106, 0x3189, 0x1106, 0x3177, 0x1106, 0x3177, "^AD77", "dfi", "ad77", P3, "DFI", "AD77", 0, NT, w836xx_memw_enable_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002368 {0x10de, 0x03ea, 0x1019, 0x2602, 0x10de, 0x03e0, 0x1019, 0x2602, NULL, NULL, NULL, P3, "Elitegroup", "GeForce6100SM-M", 0, OK, board_ecs_geforce6100sm_m},
2369 {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, P3, "Elitegroup", "K7VTA3", 256, OK, NULL},
2370 {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, P3, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e},
Stefan Tauneraf4b1582011-08-06 16:16:33 +00002371 {0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, "8NPA7I", NULL, NULL, P3, "EPoX", "EP-8NPA7I", 0, OK, nvidia_mcp_gpio4_raise},
2372 {0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, "9NPA7I", NULL, NULL, P3, "EPoX", "EP-9NPA7I", 0, OK, nvidia_mcp_gpio4_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002373 {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, P3, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise},
2374 {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", P3, "EPoX", "EP-BX3", 0, NT, intel_piix4_gpo22_raise},
2375 {0x10de, 0x02f0, 0x105b, 0x0d01, 0x10de, 0x0264, 0x105b, 0x0d01, NULL, NULL, NULL, P3, "Foxconn", "6150K8MD-8EKRSH", 0, NT, nvidia_mcp_gpio2_raise},
2376 {0x8086, 0x2443, 0x8086, 0x2442, 0x8086, 0x1130, 0x8086, 0x1130, "^6IEM ", NULL, NULL, P3, "GIGABYTE", "GA-6IEM", 0, NT, intel_ich_gpio25_raise},
2377 {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-7ZM", 512, OK, NULL},
Joshua Roys9d9a1042011-06-13 16:59:01 +00002378 {0x8086, 0x2570, 0x1458, 0x2570, 0x8086, 0x24d0, 0, 0, "^8IP775/-G$",NULL, NULL, P3, "GIGABYTE", "GA-8IP775", 0, OK, intel_ich_gpio32_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002379 {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise},
2380 {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise},
Stefan Tauner716e0982011-07-25 20:38:52 +00002381 {0x1039, 0x0651, 0x1039, 0x0651, 0x1039, 0x7002, 0x1458, 0x5004, "^GA-8SIMLH$",NULL, NULL, P3, "GIGABYTE", "GA-8SIMLH", 0, OK, sis_gpio0_raise_and_w836xx_memw},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002382 {0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise},
2383 {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise},
Idwer Volleringd8a00a02011-06-13 16:58:54 +00002384 {0x10de, 0x00e4, 0x1458, 0x0c11, 0x10de, 0x00e0, 0x1458, 0x0c11, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8NS Pro-939", 0, NT, nvidia_mcp_gpio0a_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002385 {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise},
Idwer Volleringd8a00a02011-06-13 16:58:54 +00002386 {0x8086, 0x2415, 0x103c, 0x1250, 0x10b7, 0x9200, 0x103c, 0x1247, NULL, NULL, NULL, P3, "HP", "e-Vectra P2706T", 0, OK, board_hp_p2706t},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002387 {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", P3, "HP", "ProLiant DL145 G3", 0, OK, board_hp_dl145_g3_enable},
2388 {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", P3, "HP", "ProLiant DL165 G6", 0, OK, board_hp_dl165_g6_enable},
2389 {0x8086, 0x2580, 0x103c, 0x2a08, 0x8086, 0x2640, 0x103c, 0x2a0a, NULL, NULL, NULL, P3, "HP", "Puffer2-UL8E", 0, OK, intel_ich_gpio18_raise},
Idwer Volleringd8a00a02011-06-13 16:58:54 +00002390 {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, P3, "HP", "Vectra VL400", 0, OK, board_hp_vl400},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002391 {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, P3, "HP", "Vectra VL420 SFF", 0, OK, intel_ich_gpio22_raise},
2392 {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, "hp", "xw9400", P3, "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise},
2393 {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", P3, "IBASE", "MB899", 0, OK, intel_ich_gpio26_raise},
2394 {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, P3, "IBM", "x3455", 0, OK, board_ibm_x3455},
2395 {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, P3, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi},
2396 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, P3, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower},
Stefan Tauner24c38df2012-08-11 02:33:20 +00002397 {0x1022, 0x7468, 0, 0, 0x1022, 0x7460, 0, 0, NULL, "iwill", "dk8_htx", P3, "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002398 {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", P3, "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m},
2399 {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, P3, "Mitac", "6513WU", 0, OK, board_mitac_6513wu},
Ingo Feldschmid8a0f9b02012-01-31 06:51:56 +00002400 {0x8086, 0x8186, 0x8086, 0x8186, 0x8086, 0x8800, 0x0000, 0x0000, "^MSC Vertriebs GmbH$", NULL, NULL, P2, "MSC", "Q7-TCTC", 0, OK, p2_not_a_laptop},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002401 {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, P3, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, /* TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html. */
2402 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^MS-6163 (i440BX)$", NULL, NULL, P3, "MSI", "MS-6163 (MS-6163 Pro)", 0, OK, intel_piix4_gpo14_raise},
2403 {0x1039, 0x0745, 0, 0, 0x1039, 0x0018, 0, 0, "^MS-6561", NULL, NULL, P3, "MSI", "MS-6561 (745 Ultra)", 0, OK, w836xx_memw_enable_2e},
2404 {0x8086, 0x2560, 0x1462, 0x5770, 0x8086, 0x2562, 0x1462, 0x5778, NULL, NULL, NULL, P3, "MSI", "MS-6577 (Xenon)", 0, OK, w83627hf_gpio25_raise_2e},
2405 {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, P3, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v},
2406 {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, P3, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio44_raise_2e},
2407 {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, P3, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v},
2408 {0x1106, 0x3148, 0 , 0 , 0x1106, 0x3177, 0 , 0 , NULL, "msi", "ms6787", P3, "MSI", "MS-6787 (P4MAM-V/P4MAM-L)", 0, OK, w836xx_memw_enable_2e},
Maciej Pijanka6add0942011-06-09 20:59:30 +00002409 {0x8086, 0x24d3, 0x1462, 0x7880, 0x8086, 0x2570, 0, 0, NULL, NULL, NULL, P3, "MSI", "MS-6788-040 (848P NeoV)", 0, OK, intel_ich_gpio32_raise},
Michael Karchera08d0f22011-07-25 17:25:24 +00002410 {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, P3, "MSI", "MS-7005 (651M-L)", 0, OK, sis_gpio0_raise_and_w836xx_memw},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002411 {0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, P3, "MSI", "MS-7025 (K8N Neo2 Platinum)", 0, OK, nvidia_mcp_gpio0c_raise},
Stefan Tauner33366a02012-09-15 15:51:09 +00002412 {0x10DE, 0x00E0, 0x1462, 0x0300, 0x10DE, 0x00E1, 0x1462, 0x0300, NULL, NULL, NULL, P3, "MSI", "MS-7030 (K8N Neo Platinum)", 0, OK, nvidia_mcp_gpio0c_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002413 {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, P3, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise},
2414 {0x8086, 0x244b, 0x1462, 0x3910, 0x8086, 0x2442, 0x1462, 0x3910, NULL, NULL, NULL, P3, "MSI", "MS-6391 (845 Pro4)", 0, OK, intel_ich_gpio23_raise},
2415 {0x1106, 0x3149, 0x1462, 0x7061, 0x1106, 0x3227, 0, 0, NULL, NULL, NULL, P3, "MSI", "MS-7061 (KM4M-V/KM4AM-V)", 0, OK, w836xx_memw_enable_2e},
2416 {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", P3, "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio44_raise_4e},
2417 {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, P3, "MSI", "MS-7207 (K8NGM2-L)", 0, NT, nvidia_mcp_gpio2_raise},
Joshua Roys6e48a022012-06-29 23:07:14 +00002418 {0x10DE, 0x0360, 0x1462, 0x7250, 0x10DE, 0x0368, 0x1462, 0x7250, NULL, NULL, NULL, P3, "MSI", "MS-7250 (K9N SLI)", 0, OK, nvidia_mcp_gpio2_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002419 {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0},
2420 {0x8086, 0x24d3, 0x144d, 0xb025, 0x8086, 0x1050, 0x144d, 0xb025, NULL, NULL, NULL, P3, "Samsung", "Polaris 32", 0, OK, intel_ich_gpio21_raise},
2421 {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", P3, "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e},
2422 {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, P3, "Shuttle", "AK38N", 256, OK, NULL},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002423 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, P3, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower},
Joshua Roysb992d342011-11-02 14:31:18 +00002424 {0x10de, 0x0364, 0x108e, 0x6676, 0x10de, 0x0369, 0x108e, 0x6676, "^Sun Ultra 40 M2", NULL, NULL, P3, "Sun", "Ultra 40 M2", 0, OK, board_sun_ultra_40_m2},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002425 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, P3, "Tekram", "P6Pro-A5", 256, OK, NULL},
2426 {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, P3, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e},
Michael Karcherbfd89a52012-02-12 00:13:14 +00002427 {0x8086, 0x7120, 0x109f, 0x3157, 0x8086, 0x2410, 0, 0, NULL, NULL, NULL, P3, "TriGem", "Anaheim-3", 0, OK, intel_ich_gpio22_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002428 {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, P3, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e},
2429 {0x1106, 0x0259, 0x1106, 0xAA07, 0x1106, 0x3227, 0x1106, 0xAA07, NULL, NULL, NULL, P3, "VIA", "EPIA EK", 0, NT, via_vt823x_gpio9_raise},
2430 {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, P3, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise},
2431 {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, P3, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise},
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00002432#endif
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002433 { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, P3, NULL, NULL, 0, NT, NULL}, /* end marker */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002434};
2435
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002436/* Parse the <vendor>:<board> string specified by the user as part of -p internal:mainboard=<vendor>:<board>.
2437 * Parameters vendor and model will be overwritten. Returns 0 on success.
2438 * Note: strtok modifies the original string, so we work on a copy and allocate memory for the results.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002439 */
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002440int board_parse_parameter(const char *boardstring, const char **vendor, const char **model)
2441{
2442 /* strtok may modify the original string. */
2443 char *tempstr = strdup(boardstring);
2444 char *tempstr2 = NULL;
2445 strtok(tempstr, ":");
2446 tempstr2 = strtok(NULL, ":");
2447 if (tempstr == NULL || tempstr2 == NULL) {
2448 free(tempstr);
2449 msg_pinfo("Please supply the board vendor and model name with the "
2450 "-p internal:mainboard=<vendor>:<model> option.\n");
2451 return 1;
2452 }
2453 *vendor = strdup(tempstr);
2454 *model = strdup(tempstr2);
2455 msg_pspew("-p internal:mainboard: vendor=\"%s\", model=\"%s\"\n", tempstr, tempstr2);
2456 free(tempstr);
2457 return 0;
2458}
2459
2460/*
2461 * Match boards on vendor and model name.
2462 * Hint: the parameters can come either from the coreboot table or the command line (i.e. the user).
2463 * Require main PCI IDs to match too as extra safety.
2464 * vendor and model must be non-NULL!
2465 */
2466static const struct board_match *board_match_name(const char *vendor, const char *model)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002467{
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002468 const struct board_match *board = board_matches;
2469 const struct board_match *partmatch = NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002470
Uwe Hermanna93045c2009-05-09 00:47:04 +00002471 for (; board->vendor_name; board++) {
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002472 if (!board->lb_vendor || strcasecmp(board->lb_vendor, vendor))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002473 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002474
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002475 if (!board->lb_part || strcasecmp(board->lb_part, model))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002476 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002477
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002478 if (!pci_dev_find(board->first_vendor, board->first_device)) {
2479 msg_pdbg("Odd. Board name \"%s\":\"%s\" matches, but first PCI device %04x:%04x "
2480 "doesn't.\n", vendor, model, board->first_vendor, board->first_device);
Uwe Hermanna7e05482007-05-09 10:17:44 +00002481 continue;
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002482 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002483
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002484 if (!pci_dev_find(board->second_vendor, board->second_device)) {
2485 msg_pdbg("Odd. Board name \"%s\":\"%s\" matches, but second PCI device %04x:%04x "
2486 "doesn't.\n", vendor, model, board->second_vendor, board->second_device);
Uwe Hermanna7e05482007-05-09 10:17:44 +00002487 continue;
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002488 }
Peter Stuge6b53fed2008-01-27 16:21:21 +00002489
2490 if (partmatch) {
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002491 /* More than one entry has a matching name. */
2492 msg_perr("Board name \"%s\":\"%s\" and PCI IDs matched more than one board enable "
2493 "entry. Please report a bug at flashrom@flashrom.org\n", vendor, model);
Peter Stuge6b53fed2008-01-27 16:21:21 +00002494 return NULL;
2495 }
2496 partmatch = board;
Uwe Hermanna7e05482007-05-09 10:17:44 +00002497 }
Uwe Hermann372eeb52007-12-04 21:49:06 +00002498
Peter Stuge6b53fed2008-01-27 16:21:21 +00002499 if (partmatch)
2500 return partmatch;
2501
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002502 msg_perr("No suitable board enable found for vendor=\"%s\", model=\"%s\".\n", vendor, model);
Uwe Hermanna7e05482007-05-09 10:17:44 +00002503 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002504}
2505
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002506/*
Uwe Hermannffec5f32007-08-23 16:08:21 +00002507 * Match boards on PCI IDs and subsystem IDs.
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002508 * Second set of IDs can be either main+subsystem IDs, main IDs or no IDs.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002509 */
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002510const static struct board_match *board_match_pci_ids(enum board_match_phase phase)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002511{
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002512 const struct board_match *board = board_matches;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002513
Uwe Hermanna93045c2009-05-09 00:47:04 +00002514 for (; board->vendor_name; board++) {
Michael Karcher2eab70d2010-02-04 10:58:50 +00002515 if ((!board->first_card_vendor || !board->first_card_device) &&
2516 !board->dmi_pattern)
Uwe Hermanna7e05482007-05-09 10:17:44 +00002517 continue;
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002518 if (board->phase != phase)
2519 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002520
Uwe Hermanna7e05482007-05-09 10:17:44 +00002521 if (!pci_card_find(board->first_vendor, board->first_device,
Uwe Hermann394131e2008-10-18 21:14:13 +00002522 board->first_card_vendor,
2523 board->first_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002524 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002525
Uwe Hermanna7e05482007-05-09 10:17:44 +00002526 if (board->second_vendor) {
2527 if (board->second_card_vendor) {
2528 if (!pci_card_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00002529 board->second_device,
2530 board->second_card_vendor,
2531 board->second_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002532 continue;
2533 } else {
2534 if (!pci_dev_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00002535 board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002536 continue;
2537 }
2538 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002539
Michael Karcher6701ee82010-01-20 14:14:11 +00002540 if (board->dmi_pattern) {
2541 if (!has_dmi_support) {
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002542 msg_perr("WARNING: Can't autodetect %s %s, DMI info unavailable.\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002543 board->vendor_name, board->board_name);
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002544 msg_pinfo("Please supply the board vendor and model name with the "
2545 "-p internal:mainboard=<vendor>:<model> option.\n");
Michael Karcher6701ee82010-01-20 14:14:11 +00002546 continue;
2547 } else {
2548 if (!dmi_match(board->dmi_pattern))
2549 continue;
2550 }
2551 }
2552
Uwe Hermanna7e05482007-05-09 10:17:44 +00002553 return board;
2554 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002555
Uwe Hermanna7e05482007-05-09 10:17:44 +00002556 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002557}
2558
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002559static int board_enable_safetycheck(const struct board_match *board)
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002560{
2561 if (!board)
2562 return 1;
2563
2564 if (board->status == OK)
2565 return 0;
2566
2567 if (!force_boardenable) {
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002568 msg_pinfo("WARNING: The mainboard-specific code for %s %s has not been tested,\n"
2569 "and thus will not be executed by default. Depending on your hardware,\n"
2570 "erasing, writing or even probing can fail without running this code.\n\n"
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002571 "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n"
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002572 "\"internal programmer\") for details.\n", board->vendor_name, board->board_name);
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002573 return 1;
2574 }
2575 msg_pinfo("NOTE: Running an untested board enable procedure.\n"
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002576 "Please report success/failure to flashrom@flashrom.org.\n");
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002577 return 0;
2578}
2579
2580/* FIXME: Should this be identical to board_flash_enable? */
2581static int board_handle_phase(enum board_match_phase phase)
2582{
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002583 const struct board_match *board = NULL;
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002584
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002585 board = board_match_pci_ids(phase);
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002586
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002587 if (!board)
2588 return 0;
2589
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002590 if (board_enable_safetycheck(board))
2591 return 0;
2592
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002593 if (!board->enable) {
2594 /* Not sure if there is a valid case for this. */
2595 msg_perr("Board match found, but nothing to do?\n");
2596 return 0;
2597 }
2598
2599 return board->enable();
2600}
2601
2602void board_handle_before_superio(void)
2603{
2604 board_handle_phase(P1);
2605}
2606
2607void board_handle_before_laptop(void)
2608{
2609 board_handle_phase(P2);
2610}
2611
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002612int board_flash_enable(const char *vendor, const char *model)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002613{
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002614 const struct board_match *board = NULL;
Uwe Hermanna7e05482007-05-09 10:17:44 +00002615 int ret = 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002616
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002617 if (vendor && model) {
2618 board = board_match_name(vendor, model);
2619 if (!board) /* if a board was given it has to match, else we abort here. */
2620 return 1;
2621 } else {
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002622 board = board_match_pci_ids(P3);
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002623 if (!board) /* i.e. there is just no board enable available for this board */
2624 return 0;
2625 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002626
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002627 if (board_enable_safetycheck(board))
2628 return 1;
Michael Karcher7f0c3ec2010-03-07 22:29:28 +00002629
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002630 /* limit the maximum size of the parallel bus */
2631 if (board->max_rom_decode_parallel)
2632 max_rom_decode.parallel = board->max_rom_decode_parallel * 1024;
Luc Verhaegen93938c32010-01-20 14:45:03 +00002633
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002634 if (board->enable != NULL) {
2635 msg_pinfo("Enabling full flash access for board \"%s %s\"... ",
2636 board->vendor_name, board->board_name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002637
Stefan Taunerb4e06bd2012-08-20 00:24:22 +00002638 ret = board->enable();
2639 if (ret)
2640 msg_pinfo("FAILED!\n");
2641 else
2642 msg_pinfo("OK.\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +00002643 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002644
Uwe Hermanna7e05482007-05-09 10:17:44 +00002645 return ret;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002646}