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Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
5 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +00006 * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
Carl-Daniel Hailfinger92242622007-09-27 14:29:57 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00008 *
Uwe Hermannd1107642007-08-29 17:52:32 +00009 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000012 *
Uwe Hermannd1107642007-08-29 17:52:32 +000013 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000021 */
22
23/*
24 * Contains the board specific flash enables.
25 */
26
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000027#include <string.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000028#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000029#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000030#include "hwaccess.h"
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000031
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000032#if defined(__i386__) || defined(__x86_64__)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000033/*
Uwe Hermannffec5f32007-08-23 16:08:21 +000034 * Helper functions for many Winbond Super I/Os of the W836xx range.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000035 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000036/* Enter extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000037void w836xx_ext_enter(uint16_t port)
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000038{
Andriy Gapon65c1b862008-05-22 13:22:45 +000039 OUTB(0x87, port);
40 OUTB(0x87, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000041}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000042
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000043/* Leave extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000044void w836xx_ext_leave(uint16_t port)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000045{
Andriy Gapon65c1b862008-05-22 13:22:45 +000046 OUTB(0xAA, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000047}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000048
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000049/* Generic Super I/O helper functions */
50uint8_t sio_read(uint16_t port, uint8_t reg)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000051{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000052 OUTB(reg, port);
53 return INB(port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000054}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000055
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000056void sio_write(uint16_t port, uint8_t reg, uint8_t data)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000057{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000058 OUTB(reg, port);
59 OUTB(data, port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000060}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000061
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000062void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000063{
Ronald G. Minnichfa496922007-10-12 21:22:40 +000064 uint8_t tmp;
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000065
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000066 OUTB(reg, port);
67 tmp = INB(port + 1) & ~mask;
68 OUTB(tmp | (data & mask), port + 1);
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000069}
70
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +000071/* Winbond W83697 documentation indicates that the index register has to be written for each access. */
72void sio_mask_alzheimer(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
73{
74 uint8_t tmp;
75
76 OUTB(reg, port);
77 tmp = INB(port + 1) & ~mask;
78 OUTB(reg, port);
79 OUTB(tmp | (data & mask), port + 1);
80}
81
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000082/* Not used yet. */
83#if 0
84static int enable_flash_decode_superio(void)
85{
86 int ret;
87 uint8_t tmp;
88
89 switch (superio.vendor) {
90 case SUPERIO_VENDOR_NONE:
91 ret = -1;
92 break;
93 case SUPERIO_VENDOR_ITE:
94 enter_conf_mode_ite(superio.port);
Uwe Hermann43959702010-03-13 17:28:29 +000095 /* Enable flash mapping. Works for most old ITE style Super I/O. */
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000096 tmp = sio_read(superio.port, 0x24);
97 tmp |= 0xfc;
98 sio_write(superio.port, 0x24, tmp);
99 exit_conf_mode_ite(superio.port);
100 ret = 0;
101 break;
102 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000103 msg_pdbg("Unhandled Super I/O type!\n");
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +0000104 ret = -1;
105 break;
106 }
107 return ret;
108}
109#endif
110
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000111/*
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000112 * SMSC FDC37B787: Raise GPIO50
113 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000114static int fdc37b787_gpio50_raise(uint16_t port)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000115{
116 uint8_t id, val;
117
118 OUTB(0x55, port); /* enter conf mode */
119 id = sio_read(port, 0x20);
120 if (id != 0x44) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000121 msg_perr("\nERROR: FDC37B787: Wrong ID 0x%02X.\n", id);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000122 OUTB(0xAA, port); /* leave conf mode */
123 return -1;
124 }
125
126 sio_write(port, 0x07, 0x08); /* Select Aux I/O subdevice */
127
128 val = sio_read(port, 0xC8); /* GP50 */
129 if ((val & 0x1B) != 0x10) /* output, no invert, GPIO */
130 {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000131 msg_perr("\nERROR: GPIO50 mode 0x%02X unexpected.\n", val);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000132 OUTB(0xAA, port);
133 return -1;
134 }
135
136 sio_mask(port, 0xF9, 0x01, 0x01);
137
138 OUTB(0xAA, port); /* Leave conf mode */
139 return 0;
140}
141
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000142/*
143 * Suited for:
144 * - Nokia IP530: Intel 440BX + PIIX4 + FDC37B787
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000145 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000146static int fdc37b787_gpio50_raise_3f0(void)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000147{
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000148 return fdc37b787_gpio50_raise(0x3f0);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000149}
150
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000151struct winbond_mux {
152 uint8_t reg; /* 0 if the corresponding pin is not muxed */
153 uint8_t data; /* reg/data/mask may be directly ... */
154 uint8_t mask; /* ... passed to sio_mask */
155};
156
157struct winbond_port {
158 const struct winbond_mux *mux; /* NULL or pointer to mux info for the 8 bits */
159 uint8_t ldn; /* LDN this GPIO register is located in */
160 uint8_t enable_bit; /* bit in 0x30 of that LDN to enable
161 the GPIO port */
162 uint8_t base; /* base register in that LDN for the port */
163};
164
165struct winbond_chip {
166 uint8_t device_id; /* reg 0x20 of the expected w83626x */
167 uint8_t gpio_port_count;
168 const struct winbond_port *port;
169};
170
171
172#define UNIMPLEMENTED_PORT {NULL, 0, 0, 0}
173
174enum winbond_id {
175 WINBOND_W83627HF_ID = 0x52,
Michael Karcherea36c9c2010-06-27 15:07:52 +0000176 WINBOND_W83627EHF_ID = 0x88,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000177 WINBOND_W83627THF_ID = 0x82,
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000178 WINBOND_W83697HF_ID = 0x60,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000179};
180
181static const struct winbond_mux w83627hf_port2_mux[8] = {
182 {0x2A, 0x01, 0x01}, /* or MIDI */
183 {0x2B, 0x80, 0x80}, /* or SPI */
184 {0x2B, 0x40, 0x40}, /* or SPI */
185 {0x2B, 0x20, 0x20}, /* or power LED */
186 {0x2B, 0x10, 0x10}, /* or watchdog */
187 {0x2B, 0x08, 0x08}, /* or infra red */
188 {0x2B, 0x04, 0x04}, /* or infra red */
189 {0x2B, 0x03, 0x03} /* or IRQ1 input */
190};
191
192static const struct winbond_port w83627hf[3] = {
193 UNIMPLEMENTED_PORT,
194 {w83627hf_port2_mux, 0x08, 0, 0xF0},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000195 UNIMPLEMENTED_PORT,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000196};
197
Michael Karcherea36c9c2010-06-27 15:07:52 +0000198static const struct winbond_mux w83627ehf_port2_mux[8] = {
199 {0x29, 0x06, 0x02}, /* or MIDI */
200 {0x29, 0x06, 0x02},
201 {0x24, 0x02, 0x00}, /* or SPI ROM interface */
202 {0x24, 0x02, 0x00},
203 {0x2A, 0x01, 0x01}, /* or keyboard/mouse interface */
204 {0x2A, 0x01, 0x01},
205 {0x2A, 0x01, 0x01},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000206 {0x2A, 0x01, 0x01},
Michael Karcherea36c9c2010-06-27 15:07:52 +0000207};
208
209static const struct winbond_port w83627ehf[6] = {
210 UNIMPLEMENTED_PORT,
211 {w83627ehf_port2_mux, 0x09, 0, 0xE3},
212 UNIMPLEMENTED_PORT,
213 UNIMPLEMENTED_PORT,
214 UNIMPLEMENTED_PORT,
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000215 UNIMPLEMENTED_PORT,
Michael Karcherea36c9c2010-06-27 15:07:52 +0000216};
217
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000218static const struct winbond_mux w83627thf_port4_mux[8] = {
219 {0x2D, 0x01, 0x01}, /* or watchdog or VID level strap */
220 {0x2D, 0x02, 0x02}, /* or resume reset */
221 {0x2D, 0x04, 0x04}, /* or S3 input */
222 {0x2D, 0x08, 0x08}, /* or PSON# */
223 {0x2D, 0x10, 0x10}, /* or PWROK */
224 {0x2D, 0x20, 0x20}, /* or suspend LED */
225 {0x2D, 0x40, 0x40}, /* or panel switch input */
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000226 {0x2D, 0x80, 0x80}, /* or panel switch output */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000227};
228
229static const struct winbond_port w83627thf[5] = {
230 UNIMPLEMENTED_PORT, /* GPIO1 */
231 UNIMPLEMENTED_PORT, /* GPIO2 */
232 UNIMPLEMENTED_PORT, /* GPIO3 */
233 {w83627thf_port4_mux, 0x09, 1, 0xF4},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000234 UNIMPLEMENTED_PORT, /* GPIO5 */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000235};
236
237static const struct winbond_chip winbond_chips[] = {
238 {WINBOND_W83627HF_ID, ARRAY_SIZE(w83627hf), w83627hf },
Michael Karcherea36c9c2010-06-27 15:07:52 +0000239 {WINBOND_W83627EHF_ID, ARRAY_SIZE(w83627ehf), w83627ehf},
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000240 {WINBOND_W83627THF_ID, ARRAY_SIZE(w83627thf), w83627thf},
241};
242
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000243#define WINBOND_SUPERIO_PORT1 0x2e
244#define WINBOND_SUPERIO_PORT2 0x4e
245
246/* We don't really care about the hardware monitor, but it offers better (more specific) device ID info than
247 * the simple device ID in the normal configuration registers.
248 * Note: This function expects to be called while the Super I/O is in config mode.
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000249 */
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000250static uint8_t w836xx_deviceid_hwmon(uint16_t sio_port)
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000251{
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000252 uint16_t hwmport;
253 uint16_t hwm_vendorid;
254 uint8_t hwm_deviceid;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000255
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000256 sio_write(sio_port, 0x07, 0x0b); /* Select LDN 0xb (HWM). */
257 if ((sio_read(sio_port, 0x30) & (1 << 0)) != (1 << 0)) {
258 msg_pinfo("W836xx hardware monitor disabled or does not exist.\n");
259 return 0;
260 }
261 /* Get HWM base address (stored in LDN 0xb, index 0x60/0x61). */
262 hwmport = sio_read(sio_port, 0x60) << 8;
263 hwmport |= sio_read(sio_port, 0x61);
264 /* HWM address register = HWM base address + 5. */
265 hwmport += 5;
266 msg_pdbg2("W836xx Hardware Monitor at port %04x\n", hwmport);
267 /* FIXME: This busy check should happen before each HWM access. */
268 if (INB(hwmport) & 0x80) {
269 msg_pinfo("W836xx hardware monitor busy, ignoring it.\n");
270 return 0;
271 }
272 /* Set HBACS=1. */
273 sio_mask_alzheimer(hwmport, 0x4e, 0x80, 0x80);
274 /* Read upper byte of vendor ID. */
275 hwm_vendorid = sio_read(hwmport, 0x4f) << 8;
276 /* Set HBACS=0. */
277 sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x80);
278 /* Read lower byte of vendor ID. */
279 hwm_vendorid |= sio_read(hwmport, 0x4f);
280 if (hwm_vendorid != 0x5ca3) {
281 msg_pinfo("W836xx hardware monitor vendor ID weirdness: expected 0x5ca3, got %04x\n",
282 hwm_vendorid);
283 return 0;
284 }
285 /* Set Bank=0. */
286 sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x07);
287 /* Read "chip" ID. We call this one the device ID. */
288 hwm_deviceid = sio_read(hwmport, 0x58);
289 return hwm_deviceid;
290}
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000291
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000292void probe_superio_winbond(void)
293{
294 struct superio s = {};
295 uint16_t winbond_ports[] = {WINBOND_SUPERIO_PORT1, WINBOND_SUPERIO_PORT2, 0};
296 uint16_t *i = winbond_ports;
297 uint8_t model;
298 uint8_t tmp;
299
300 s.vendor = SUPERIO_VENDOR_WINBOND;
301 for (; *i; i++) {
302 s.port = *i;
303 /* If we're already in Super I/O config more, the W836xx enter sequence won't hurt. */
304 w836xx_ext_enter(s.port);
305 model = sio_read(s.port, 0x20);
306 /* No response, no point leaving the config mode. */
307 if (model == 0xff)
308 continue;
309 /* Try to leave config mode. If the ID register is still readable, it's not a Winbond chip. */
310 w836xx_ext_leave(s.port);
311 if (model == sio_read(s.port, 0x20)) {
312 msg_pdbg("W836xx enter config mode worked or we were already in config mode. W836xx "
313 "leave config mode had no effect.\n");
314 if (model == 0x87) {
315 /* ITE IT8707F and IT8710F are special: They need the W837xx enter sequence,
316 * but they want the ITE exit sequence. Handle them here.
317 */
318 tmp = sio_read(s.port, 0x21);
319 switch (tmp) {
320 case 0x07:
321 case 0x10:
322 s.vendor = SUPERIO_VENDOR_ITE;
323 s.model = (0x87 << 8) | tmp ;
324 msg_pdbg("Found ITE Super I/O, ID 0x%04hx on port "
325 "0x%x\n", s.model, s.port);
326 register_superio(s);
327 /* Exit ITE config mode. */
328 exit_conf_mode_ite(s.port);
329 /* Restore vendor for next loop iteration. */
330 s.vendor = SUPERIO_VENDOR_WINBOND;
331 continue;
332 }
333 }
334 msg_pinfo("Active config mode, unknown reg 0x20 ID: %02x.\n", model);
335 msg_pinfo("Please send the output of \"flashrom -V\" to \n"
336 "flashrom@flashrom.org with W836xx: your board name: flashrom -V\n"
337 "as the subject to help us finish support for your Super I/O. Thanks.\n");
338 continue;
339 }
340 /* The Super I/O reacts to W836xx enter and exit config mode, it's probably Winbond. */
341 w836xx_ext_enter(s.port);
342 s.model = sio_read(s.port, 0x20);
343 switch (s.model) {
344 case WINBOND_W83627HF_ID:
345 case WINBOND_W83627EHF_ID:
346 case WINBOND_W83627THF_ID:
347 msg_pdbg("Found Winbond Super I/O, id %02hx\n", s.model);
348 register_superio(s);
349 break;
350 case WINBOND_W83697HF_ID:
351 /* This code is extremely paranoid. */
352 tmp = sio_read(s.port, 0x26) & 0x40;
353 if (((tmp == 0x00) && (s.port != WINBOND_SUPERIO_PORT1)) ||
354 ((tmp == 0x40) && (s.port != WINBOND_SUPERIO_PORT2))) {
355 msg_pdbg("Winbond Super I/O probe weirdness: Port mismatch for ID "
356 "%02x at port %04x\n", s.model, s.port);
357 break;
358 }
359 tmp = w836xx_deviceid_hwmon(s.port);
360 /* FIXME: This might be too paranoid... */
361 if (!tmp) {
362 msg_pdbg("Probably not a Winbond Super I/O\n");
363 break;
364 }
365 if (tmp != s.model) {
366 msg_pinfo("W83 series hardware monitor device ID weirdness: expected %02x, "
367 "got %02x\n", WINBOND_W83697HF_ID, tmp);
368 break;
369 }
370 msg_pinfo("Found Winbond Super I/O, id %02hx\n", s.model);
371 register_superio(s);
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000372 break;
373 }
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000374 w836xx_ext_leave(s.port);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000375 }
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000376 return;
377}
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000378
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000379static const struct winbond_chip *winbond_superio_chipdef(void)
380{
381 int i, j;
382
383 for (i = 0; i < superio_count; i++) {
384 if (superios[i].vendor != SUPERIO_VENDOR_WINBOND)
385 continue;
386 for (j = 0; j < ARRAY_SIZE(winbond_chips); j++)
387 if (winbond_chips[j].device_id == superios[i].model)
388 return &winbond_chips[j];
389 }
390 return NULL;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000391}
392
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000393/*
394 * The chipid parameter goes away as soon as we have Super I/O matching in the
395 * board enable table. The call to winbond_superio_detect() goes away as
396 * soon as we have generic Super I/O detection code.
397 */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000398static int winbond_gpio_set(uint16_t base, enum winbond_id chipid,
399 int pin, int raise)
400{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000401 const struct winbond_chip *chip = NULL;
402 const struct winbond_port *gpio;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000403 int port = pin / 10;
404 int bit = pin % 10;
405
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000406 chip = winbond_superio_chipdef();
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000407 if (!chip) {
408 msg_perr("\nERROR: No supported Winbond Super I/O found\n");
409 return -1;
410 }
Michael Karcher979d9252010-06-29 14:44:40 +0000411 if (chip->device_id != chipid) {
412 msg_perr("\nERROR: Found Winbond chip with ID 0x%x, "
413 "expected %x\n", chip->device_id, chipid);
414 return -1;
415 }
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000416 if (bit >= 8 || port == 0 || port > chip->gpio_port_count) {
417 msg_perr("\nERROR: winbond_gpio_set: Invalid GPIO number %d\n",
418 pin);
419 return -1;
420 }
421
422 gpio = &chip->port[port - 1];
423
424 if (gpio->ldn == 0) {
425 msg_perr("\nERROR: GPIO%d is not supported yet on this"
426 " winbond chip\n", port);
427 return -1;
428 }
429
430 w836xx_ext_enter(base);
431
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000432 /* Select logical device. */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000433 sio_write(base, 0x07, gpio->ldn);
434
435 /* Activate logical device. */
436 sio_mask(base, 0x30, 1 << gpio->enable_bit, 1 << gpio->enable_bit);
437
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000438 /* Select GPIO function of that pin. */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000439 if (gpio->mux && gpio->mux[bit].reg)
440 sio_mask(base, gpio->mux[bit].reg,
441 gpio->mux[bit].data, gpio->mux[bit].mask);
442
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000443 sio_mask(base, gpio->base + 0, 0, 1 << bit); /* Make pin output */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000444 sio_mask(base, gpio->base + 2, 0, 1 << bit); /* Clear inversion */
445 sio_mask(base, gpio->base + 1, raise << bit, 1 << bit);
446
447 w836xx_ext_leave(base);
448
449 return 0;
450}
451
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000452/*
Uwe Hermannffec5f32007-08-23 16:08:21 +0000453 * Winbond W83627HF: Raise GPIO24.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000454 *
455 * Suited for:
Uwe Hermannffec5f32007-08-23 16:08:21 +0000456 * - Agami Aruma
457 * - IWILL DK8-HTX
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000458 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000459static int w83627hf_gpio24_raise_2e(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000460{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000461 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 24, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000462}
463
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000464/*
Joshua Roysf280a382010-08-07 21:49:11 +0000465 * Winbond W83627HF: Raise GPIO25.
466 *
467 * Suited for:
468 * - MSI MS-6577
469 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000470static int w83627hf_gpio25_raise_2e(void)
Joshua Roysf280a382010-08-07 21:49:11 +0000471{
472 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 25, 1);
473}
474
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000475/*
Stefan Taunerff80e682011-07-20 16:34:18 +0000476 * Winbond W83627EHF: Raise GPIO22.
Michael Karcherea36c9c2010-06-27 15:07:52 +0000477 *
478 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000479 * - ASUS A8N-VM CSM: AMD Socket 939 + GeForce 6150 (C51) + MCP51
Michael Karcherea36c9c2010-06-27 15:07:52 +0000480 */
Stefan Taunerff80e682011-07-20 16:34:18 +0000481static int w83627ehf_gpio22_raise_2e(void)
Michael Karcherea36c9c2010-06-27 15:07:52 +0000482{
Stefan Taunerff80e682011-07-20 16:34:18 +0000483 return winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, 22, 1);
Michael Karcherea36c9c2010-06-27 15:07:52 +0000484}
485
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000486/*
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000487 * Winbond W83627THF: Raise GPIO 44.
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000488 *
489 * Suited for:
Peter Stugecce26822008-07-21 17:48:40 +0000490 * - MSI K8T Neo2-F
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000491 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000492static int w83627thf_gpio44_raise_2e(void)
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000493{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000494 return winbond_gpio_set(0x2e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000495}
496
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000497/*
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000498 * Winbond W83627THF: Raise GPIO 44.
499 *
500 * Suited for:
501 * - MSI K8N Neo3
502 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000503static int w83627thf_gpio44_raise_4e(void)
Peter Stugecce26822008-07-21 17:48:40 +0000504{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000505 return winbond_gpio_set(0x4e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000506}
Uwe Hermann372eeb52007-12-04 21:49:06 +0000507
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000508/*
David Borgb6417a62010-08-02 08:29:34 +0000509 * Enable MEMW# and set ROM size to max.
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000510 * Supported chips: W83L517D, W83697HF/F/HG, W83697SF/UF/UG
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000511 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000512static void w836xx_memw_enable(uint16_t port)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000513{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000514 w836xx_ext_enter(port);
515 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000516 /* Enable MEMW# and set ROM size select to max. (4M). */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000517 sio_mask(port, 0x24, 0x28, 0x28);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000518 }
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000519 w836xx_ext_leave(port);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000520}
521
David Borgb02c62b2012-05-05 20:43:42 +0000522/**
523 * Enable MEMW# and set ROM size to max.
524 * Supported chips:
525 * W83697HF/F/HG, W83697SF/UF/UG
526 */
527void w83697xx_memw_enable(uint16_t port)
528{
529 w836xx_ext_enter(port);
530 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
531 if((sio_read(port, 0x2A) & 0xF0) == 0xF0) {
532
533 /* CR24 Bits 7 & 2 must be set to 0 enable the flash ROM */
534 /* address segments 000E0000h ~ 000FFFFFh on W83697SF/UF/UG */
535 /* These bits are reserved on W83697HF/F/HG */
536 /* Shouldn't be needed though. */
537
538 /* CR28 Bit3 must be set to 1 to enable flash access to */
539 /* FFE80000h ~ FFEFFFFFh on W83697SF/UF/UG. */
540 /* This bit is reserved on W83697HF/F/HG which default to 0 */
541 sio_mask(port, 0x28, 0x08, 0x08);
542
543 /* Enable MEMW# and set ROM size select to max. (4M)*/
544 sio_mask(port, 0x24, 0x28, 0x38);
545
546 } else {
547 msg_perr("WARNING: Flash interface in use by GPIO!\n");
548 }
549 } else {
550 msg_pinfo("BIOS ROM is disabled\n");
551 }
552 w836xx_ext_leave(port);
553}
554
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000555/*
Luc Verhaegen73d21192009-12-23 00:54:26 +0000556 * Suited for:
Stefan Taunerb6304c12012-08-09 23:25:27 +0000557 * - Biostar M7VIQ: VIA KM266 + VT8235
558 */
559static int w83697xx_memw_enable_2e(void)
560{
561 w83697xx_memw_enable(0x2E);
562
563 return 0;
564}
565
566
567/*
568 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000569 * - EPoX EP-8K5A2: VIA KT333 + VT8235
570 * - Albatron PM266A Pro: VIA P4M266A + VT8235
571 * - Shuttle AK31 (all versions): VIA KT266 + VT8233
572 * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
573 * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237
Mattias Mattssone295eee2010-08-15 10:21:29 +0000574 * - MSI KM4M-V and KM4AM-V: VIA KM400/KM400A + VT8237
Mattias Mattssone8388242010-09-11 15:25:48 +0000575 * - MSI MS-6561 (745 Ultra): SiS 745 + W83697HF
Sergey A Lichackf3a4bff2010-09-07 18:14:53 +0000576 * - MSI MS-6787 (P4MAM-V/P4MAM-L): VIA P4M266 + VT8235
Uwe Hermann17da61e2010-10-05 21:48:43 +0000577 * - ASRock K7S41: SiS 741 + SiS 963 + W83697HF
Pawel Rozanski1d233072011-06-19 16:52:48 +0000578 * - ASRock K7S41GX: SiS 741GX + SiS 963L + W83697HF
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000579 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000580static int w836xx_memw_enable_2e(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000581{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000582 w836xx_memw_enable(0x2E);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000583
Luc Verhaegen73d21192009-12-23 00:54:26 +0000584 return 0;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000585}
586
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000587/*
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000588 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000589 * - Termtek TK-3370 (rev. 2.5b)
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000590 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000591static int w836xx_memw_enable_4e(void)
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000592{
593 w836xx_memw_enable(0x4E);
594
595 return 0;
596}
597
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000598/*
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000599 * Suited for all boards with ITE IT8705F.
600 * The SIS950 Super I/O probably requires a similar flash write enable.
Luc Verhaegen21f54962010-01-20 14:45:07 +0000601 */
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000602int it8705f_write_enable(uint8_t port)
Luc Verhaegen21f54962010-01-20 14:45:07 +0000603{
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000604 uint8_t tmp;
605 int ret = 0;
606
Luc Verhaegen21f54962010-01-20 14:45:07 +0000607 enter_conf_mode_ite(port);
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000608 tmp = sio_read(port, 0x24);
609 /* Check if at least one flash segment is enabled. */
610 if (tmp & 0xf0) {
611 /* The IT8705F will respond to LPC cycles and translate them. */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000612 internal_buses_supported = BUS_PARALLEL;
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000613 /* Flash ROM I/F Writes Enable */
614 tmp |= 0x04;
615 msg_pdbg("Enabling IT8705F flash ROM interface write.\n");
616 if (tmp & 0x02) {
617 /* The data sheet contradicts itself about max size. */
618 max_rom_decode.parallel = 1024 * 1024;
619 msg_pinfo("IT8705F with very unusual settings. Please "
620 "send the output of \"flashrom -V\" to \n"
Paul Menzelab6328f2010-10-08 11:03:02 +0000621 "flashrom@flashrom.org with "
622 "IT8705: your board name: flashrom -V\n"
623 "as the subject to help us finish "
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000624 "support for your Super I/O. Thanks.\n");
625 ret = 1;
626 } else if (tmp & 0x08) {
627 max_rom_decode.parallel = 512 * 1024;
628 } else {
629 max_rom_decode.parallel = 256 * 1024;
630 }
631 /* Safety checks. The data sheet is unclear here: Segments 1+3
632 * overlap, no segment seems to cover top - 1MB to top - 512kB.
633 * We assume that certain combinations make no sense.
634 */
635 if (((tmp & 0x02) && !(tmp & 0x08)) || /* 1 MB en, 512 kB dis */
636 (!(tmp & 0x10)) || /* 128 kB dis */
637 (!(tmp & 0x40))) { /* 256/512 kB dis */
638 msg_perr("Inconsistent IT8705F decode size!\n");
639 ret = 1;
640 }
641 if (sio_read(port, 0x25) != 0) {
642 msg_perr("IT8705F flash data pins disabled!\n");
643 ret = 1;
644 }
645 if (sio_read(port, 0x26) != 0) {
646 msg_perr("IT8705F flash address pins 0-7 disabled!\n");
647 ret = 1;
648 }
649 if (sio_read(port, 0x27) != 0) {
650 msg_perr("IT8705F flash address pins 8-15 disabled!\n");
651 ret = 1;
652 }
653 if ((sio_read(port, 0x29) & 0x10) != 0) {
654 msg_perr("IT8705F flash write enable pin disabled!\n");
655 ret = 1;
656 }
657 if ((sio_read(port, 0x29) & 0x08) != 0) {
658 msg_perr("IT8705F flash chip select pin disabled!\n");
659 ret = 1;
660 }
661 if ((sio_read(port, 0x29) & 0x04) != 0) {
662 msg_perr("IT8705F flash read strobe pin disabled!\n");
663 ret = 1;
664 }
665 if ((sio_read(port, 0x29) & 0x03) != 0) {
666 msg_perr("IT8705F flash address pins 16-17 disabled!\n");
667 /* Not really an error if you use flash chips smaller
668 * than 256 kByte, but such a configuration is unlikely.
669 */
670 ret = 1;
671 }
672 msg_pdbg("Maximum IT8705F parallel flash decode size is %u.\n",
673 max_rom_decode.parallel);
674 if (ret) {
675 msg_pinfo("Not enabling IT8705F flash write.\n");
676 } else {
677 sio_write(port, 0x24, tmp);
678 }
679 } else {
680 msg_pdbg("No IT8705F flash segment enabled.\n");
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000681 ret = 0;
682 }
Luc Verhaegen21f54962010-01-20 14:45:07 +0000683 exit_conf_mode_ite(port);
684
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000685 return ret;
Luc Verhaegen21f54962010-01-20 14:45:07 +0000686}
Luc Verhaegen73d21192009-12-23 00:54:26 +0000687
Mattias Mattssonfb60cec2010-09-13 19:39:25 +0000688/*
689 * The ITE IT8707F is a custom chip made by ITE exclusively for ASUS.
690 * It uses the Winbond command sequence to enter extended configuration
691 * mode and the ITE sequence to exit.
692 *
693 * Registers seems similar to the ones on ITE IT8710F.
694 */
695static int it8707f_write_enable(uint8_t port)
696{
697 uint8_t tmp;
698
699 w836xx_ext_enter(port);
700
701 /* Set bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A rw */
702 tmp = sio_read(port, 0x23);
703 tmp |= (1 << 3);
704 sio_write(port, 0x23, tmp);
705
706 /* Set bit 2 (FLASH_WE) and bit 3 (FLASH_IF_EN) of reg 0x24 */
707 tmp = sio_read(port, 0x24);
708 tmp |= (1 << 2) | (1 << 3);
709 sio_write(port, 0x24, tmp);
710
711 /* Clear bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A ro */
712 tmp = sio_read(port, 0x23);
713 tmp &= ~(1 << 3);
714 sio_write(port, 0x23, tmp);
715
716 exit_conf_mode_ite(port);
717
718 return 0;
719}
720
721/*
722 * Suited for:
723 * - ASUS P4SC-E: SiS 651 + 962 + ITE IT8707F
724 */
725static int it8707f_write_enable_2e(void)
726{
727 return it8707f_write_enable(0x2e);
728}
729
Michael Karchercba52de2011-03-06 12:07:19 +0000730#define PC87360_ID 0xE1
731#define PC87364_ID 0xE4
732
733static int pc8736x_gpio_set(uint8_t chipid, uint8_t gpio, int raise)
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000734{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000735 static const int bankbase[] = {0, 4, 8, 10, 12};
736 int gpio_bank = gpio / 8;
737 int gpio_pin = gpio % 8;
738 uint16_t baseport;
739 uint8_t id, val;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000740
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000741 if (gpio_bank > 4) {
Michael Karchercba52de2011-03-06 12:07:19 +0000742 msg_perr("PC8736x: Invalid GPIO %d\n", gpio);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000743 return -1;
744 }
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000745
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000746 id = sio_read(0x2E, 0x20);
Michael Karchercba52de2011-03-06 12:07:19 +0000747 if (id != chipid) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000748 msg_perr("PC8736x: unexpected ID %02x (expected %02x)\n",
749 id, chipid);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000750 return -1;
751 }
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000752
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000753 sio_write(0x2E, 0x07, 0x07); /* Select GPIO device. */
754 baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
755 if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) {
756 msg_perr("PC87360: invalid GPIO base address %04x\n",
757 baseport);
758 return -1;
759 }
760 sio_mask (0x2E, 0x30, 0x01, 0x01); /* Enable logical device. */
761 sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin);
762 sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output. */
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000763
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000764 val = INB(baseport + bankbase[gpio_bank]);
765 if (raise)
766 val |= 1 << gpio_pin;
767 else
768 val &= ~(1 << gpio_pin);
769 OUTB(val, baseport + bankbase[gpio_bank]);
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000770
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000771 return 0;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000772}
773
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000774/*
775 * VIA VT823x: Set one of the GPIO pins.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000776 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000777static int via_vt823x_gpio_set(uint8_t gpio, int raise)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000778{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000779 struct pci_dev *dev;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000780 uint16_t base;
David Bartleyf58d3642009-12-09 07:53:01 +0000781 uint8_t val, bit, offset;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000782
Luc Verhaegen73d21192009-12-23 00:54:26 +0000783 dev = pci_dev_find_vendorclass(0x1106, 0x0601);
784 switch (dev->device_id) {
785 case 0x3177: /* VT8235 */
786 case 0x3227: /* VT8237R */
787 case 0x3337: /* VT8237A */
788 break;
789 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000790 msg_perr("\nERROR: VT823x ISA bridge not found.\n");
Luc Verhaegen73d21192009-12-23 00:54:26 +0000791 return -1;
792 }
793
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000794 if ((gpio >= 12) && (gpio <= 15)) {
795 /* GPIO12-15 -> output */
796 val = pci_read_byte(dev, 0xE4);
797 val |= 0x10;
798 pci_write_byte(dev, 0xE4, val);
799 } else if (gpio == 9) {
800 /* GPIO9 -> Output */
801 val = pci_read_byte(dev, 0xE4);
802 val |= 0x20;
803 pci_write_byte(dev, 0xE4, val);
David Bartleyf58d3642009-12-09 07:53:01 +0000804 } else if (gpio == 5) {
805 val = pci_read_byte(dev, 0xE4);
806 val |= 0x01;
807 pci_write_byte(dev, 0xE4, val);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000808 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000809 msg_perr("\nERROR: "
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000810 "VT823x GPIO%02d is not implemented.\n", gpio);
Luc Verhaegen73d21192009-12-23 00:54:26 +0000811 return -1;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000812 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000813
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000814 /* We need the I/O Base Address for this board's flash enable. */
815 base = pci_read_word(dev, 0x88) & 0xff80;
816
David Bartleyf58d3642009-12-09 07:53:01 +0000817 offset = 0x4C + gpio / 8;
818 bit = 0x01 << (gpio % 8);
819
820 val = INB(base + offset);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000821 if (raise)
822 val |= bit;
823 else
824 val &= ~bit;
David Bartleyf58d3642009-12-09 07:53:01 +0000825 OUTB(val, base + offset);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000826
Uwe Hermanna7e05482007-05-09 10:17:44 +0000827 return 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000828}
829
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000830/*
831 * Suited for:
832 * - ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000833 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000834static int via_vt823x_gpio5_raise(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000835{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000836 /* On M2V-MX: GPO5 is connected to WP# and TBL#. */
837 return via_vt823x_gpio_set(5, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000838}
839
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000840/*
841 * Suited for:
842 * - VIA EPIA EK & N & NL
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000843 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000844static int via_vt823x_gpio9_raise(void)
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000845{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000846 return via_vt823x_gpio_set(9, 1);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000847}
848
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000849/*
850 * Suited for:
851 * - VIA EPIA M and MII (and maybe other CLE266 based EPIAs)
Luc Verhaegen73d21192009-12-23 00:54:26 +0000852 *
853 * We don't need to do this for EPIA M when using coreboot, GPIO15 is never
854 * lowered there.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000855 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000856static int via_vt823x_gpio15_raise(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000857{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000858 return via_vt823x_gpio_set(15, 1);
859}
860
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000861/*
Luc Verhaegen73d21192009-12-23 00:54:26 +0000862 * Winbond W83697HF Super I/O + VIA VT8235 southbridge
863 *
864 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000865 * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
866 * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
Luc Verhaegen73d21192009-12-23 00:54:26 +0000867 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000868static int board_msi_kt4v(void)
Luc Verhaegen73d21192009-12-23 00:54:26 +0000869{
870 int ret;
871
872 ret = via_vt823x_gpio_set(12, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000873 w836xx_memw_enable(0x2E);
Luc Verhaegen97866082008-02-09 02:03:06 +0000874
Luc Verhaegen73d21192009-12-23 00:54:26 +0000875 return ret;
Luc Verhaegen97866082008-02-09 02:03:06 +0000876}
877
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000878/*
879 * Suited for:
880 * - ASUS P5A
Luc Verhaegen6b141752007-05-20 16:16:13 +0000881 *
882 * This is rather nasty code, but there's no way to do this cleanly.
883 * We're basically talking to some unknown device on SMBus, my guess
884 * is that it is the Winbond W83781D that lives near the DIP BIOS.
885 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000886static int board_asus_p5a(void)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000887{
888 uint8_t tmp;
889 int i;
890
891#define ASUSP5A_LOOP 5000
892
Andriy Gapon65c1b862008-05-22 13:22:45 +0000893 OUTB(0x00, 0xE807);
894 OUTB(0xEF, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000895
Andriy Gapon65c1b862008-05-22 13:22:45 +0000896 OUTB(0xFF, 0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000897
898 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000899 OUTB(0xE1, 0xFF);
900 if (INB(0xE800) & 0x04)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000901 break;
902 }
903
904 if (i == ASUSP5A_LOOP) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000905 msg_perr("Unable to contact device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000906 return -1;
907 }
908
Andriy Gapon65c1b862008-05-22 13:22:45 +0000909 OUTB(0x20, 0xE801);
910 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000911
Andriy Gapon65c1b862008-05-22 13:22:45 +0000912 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000913
914 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000915 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000916 if (tmp & 0x70)
917 break;
918 }
919
920 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000921 msg_perr("Failed to read device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000922 return -1;
923 }
924
Andriy Gapon65c1b862008-05-22 13:22:45 +0000925 tmp = INB(0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000926 tmp &= ~0x02;
927
Andriy Gapon65c1b862008-05-22 13:22:45 +0000928 OUTB(0x00, 0xE807);
929 OUTB(0xEE, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000930
Andriy Gapon65c1b862008-05-22 13:22:45 +0000931 OUTB(tmp, 0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000932
Andriy Gapon65c1b862008-05-22 13:22:45 +0000933 OUTB(0xFF, 0xE800);
934 OUTB(0xE1, 0xFF);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000935
Andriy Gapon65c1b862008-05-22 13:22:45 +0000936 OUTB(0x20, 0xE801);
937 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000938
Andriy Gapon65c1b862008-05-22 13:22:45 +0000939 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000940
941 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000942 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000943 if (tmp & 0x70)
944 break;
945 }
946
947 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000948 msg_perr("Failed to write to device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000949 return -1;
950 }
951
952 return 0;
953}
954
Luc Verhaegena7e30502009-12-09 11:39:02 +0000955/*
956 * Set GPIO lines in the Broadcom HT-1000 southbridge.
957 *
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000958 * It's not a Super I/O but it uses the same index/data port method.
Luc Verhaegena7e30502009-12-09 11:39:02 +0000959 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000960static int board_hp_dl145_g3_enable(void)
Luc Verhaegena7e30502009-12-09 11:39:02 +0000961{
962 /* GPIO 0 reg from PM regs */
963 /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
964 sio_mask(0xcd6, 0x44, 0x24, 0x24);
965
966 return 0;
967}
968
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +0000969/*
970 * Set GPIO lines in the Broadcom HT-1000 southbridge.
971 *
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000972 * It's not a Super I/O but it uses the same index/data port method.
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +0000973 */
974static int board_hp_dl165_g6_enable(void)
975{
976 /* Variant of DL145, with slightly different pin placement. */
977 sio_mask(0xcd6, 0x44, 0x80, 0x80); /* TBL# */
978 sio_mask(0xcd6, 0x46, 0x04, 0x04); /* WP# */
979
980 return 0;
981}
982
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000983static int board_ibm_x3455(void)
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000984{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000985 /* Raise GPIO13. */
Carl-Daniel Hailfinger500b4232009-06-01 21:30:42 +0000986 sio_mask(0xcd6, 0x45, 0x20, 0x20);
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000987
988 return 0;
989}
990
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000991/*
992 * Suited for:
993 * - Shuttle FN25 (SN25P): AMD S939 + NVIDIA CK804 (nForce4)
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000994 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000995static int board_shuttle_fn25(void)
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000996{
997 struct pci_dev *dev;
998
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000999 dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA bridge. */
Luc Verhaegen20fdce12009-10-21 12:05:50 +00001000 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001001 msg_perr("\nERROR: NVIDIA nForce4 ISA bridge not found.\n");
Luc Verhaegen20fdce12009-10-21 12:05:50 +00001002 return -1;
1003 }
1004
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001005 /* One of those bits seems to be connected to TBL#, but -ENOINFO. */
Luc Verhaegen20fdce12009-10-21 12:05:50 +00001006 pci_write_byte(dev, 0x92, 0);
1007
1008 return 0;
1009}
1010
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001011/*
Mattias Mattssonf4925162010-09-16 22:09:18 +00001012 * Suited for:
1013 * - Elitegroup GeForce6100SM-M: NVIDIA MCP61 + ITE IT8726F
1014 */
Mattias Mattssonf4925162010-09-16 22:09:18 +00001015static int board_ecs_geforce6100sm_m(void)
1016{
1017 struct pci_dev *dev;
1018 uint32_t tmp;
1019
1020 dev = pci_dev_find(0x10DE, 0x03EB); /* NVIDIA MCP61 SMBus. */
1021 if (!dev) {
1022 msg_perr("\nERROR: NVIDIA MCP61 SMBus not found.\n");
1023 return -1;
1024 }
1025
1026 tmp = pci_read_byte(dev, 0xE0);
1027 tmp &= ~(1 << 3);
1028 pci_write_byte(dev, 0xE0, tmp);
1029
1030 return 0;
1031}
1032
1033/*
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001034 * Very similar to AMD 8111 IO Hub.
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001035 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001036static int nvidia_mcp_gpio_set(int gpio, int raise)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001037{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001038 struct pci_dev *dev;
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001039 uint16_t base, devclass;
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001040 uint8_t tmp;
1041
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001042 if ((gpio < 0) || (gpio >= 0x40)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001043 msg_perr("\nERROR: unsupported GPIO: %d.\n", gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +00001044 return -1;
1045 }
1046
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001047 /* Check for the ISA bridge first. */
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001048 dev = pci_dev_find_vendorclass(0x10DE, 0x0601);
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001049 switch (dev->device_id) {
1050 case 0x0030: /* CK804 */
1051 case 0x0050: /* MCP04 */
1052 case 0x0060: /* MCP2 */
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001053 case 0x00E0: /* CK8 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001054 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +00001055 case 0x0260: /* MCP51 */
Michael Karcher242efd42011-03-06 12:09:05 +00001056 case 0x0261: /* MCP51 */
Joshua Roys6e48a022012-06-29 23:07:14 +00001057 case 0x0360: /* MCP55 */
Michael Karcher2ead2e22010-06-01 16:09:06 +00001058 case 0x0364: /* MCP55 */
1059 /* find SMBus controller on *this* southbridge */
1060 /* The infamous Tyan S2915-E has two south bridges; they are
1061 easily told apart from each other by the class of the
1062 LPC bridge, but have the same SMBus bridge IDs */
1063 if (dev->func != 0) {
1064 msg_perr("MCP LPC bridge at unexpected function"
1065 " number %d\n", dev->func);
1066 return -1;
1067 }
1068
Carl-Daniel Hailfinger44cd9ab2010-07-17 22:28:05 +00001069#if PCI_LIB_VERSION >= 0x020200
Michael Karcher2ead2e22010-06-01 16:09:06 +00001070 dev = pci_get_dev(pacc, dev->domain, dev->bus, dev->dev, 1);
Carl-Daniel Hailfinger44cd9ab2010-07-17 22:28:05 +00001071#else
1072 /* pciutils/libpci before version 2.2 is too old to support
1073 * PCI domains. Such old machines usually don't have domains
1074 * besides domain 0, so this is not a problem.
1075 */
1076 dev = pci_get_dev(pacc, dev->bus, dev->dev, 1);
1077#endif
Michael Karcher2ead2e22010-06-01 16:09:06 +00001078 if (!dev) {
1079 msg_perr("MCP SMBus controller could not be found\n");
1080 return -1;
1081 }
1082 devclass = pci_read_word(dev, PCI_CLASS_DEVICE);
1083 if (devclass != 0x0C05) {
1084 msg_perr("Unexpected device class %04x for SMBus"
1085 " controller\n", devclass);
1086 return -1;
1087 }
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001088 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +00001089 default:
Sean Nelson316a29f2010-05-07 20:09:04 +00001090 msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n");
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001091 return -1;
1092 }
1093
1094 base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */
1095 base += 0xC0;
1096
1097 tmp = INB(base + gpio);
1098 tmp &= ~0x0F; /* null lower nibble */
1099 tmp |= 0x04; /* gpio -> output. */
1100 if (raise)
1101 tmp |= 0x01;
1102 OUTB(tmp, base + gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +00001103
1104 return 0;
1105}
1106
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001107/*
1108 * Suited for:
Stefan Taunera9cbbac2011-08-07 13:17:20 +00001109 * - ASUS A8M2N-LA (HP OEM "NodusM3-GL8E"): NVIDIA MCP51
Sean Nelson0a247512010-08-15 14:36:18 +00001110 * - ASUS A8N-LA (HP OEM "Nagami-GL8E"): NVIDIA MCP51
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001111 * - ASUS M2NBP-VM CSM: NVIDIA MCP51
Michael Karcherb2184c12010-03-07 16:42:55 +00001112 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001113static int nvidia_mcp_gpio0_raise(void)
Michael Karcherb2184c12010-03-07 16:42:55 +00001114{
1115 return nvidia_mcp_gpio_set(0x00, 1);
1116}
1117
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001118/*
1119 * Suited for:
1120 * - abit KN8 Ultra: NVIDIA CK804
Sean Nelson92bc6bd2010-03-19 22:37:29 +00001121 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001122static int nvidia_mcp_gpio2_lower(void)
Sean Nelson92bc6bd2010-03-19 22:37:29 +00001123{
1124 return nvidia_mcp_gpio_set(0x02, 0);
1125}
1126
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001127/*
1128 * Suited for:
Michael Karcher2842db32011-04-14 23:14:27 +00001129 * - Foxconn 6150K8MD-8EKRSH: Socket 939 + NVIDIA MCP51
Uwe Hermannead705f2010-08-15 15:26:30 +00001130 * - MSI K8N Neo4: NVIDIA CK804. TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html.
1131 * - MSI K8NGM2-L: NVIDIA MCP51
Joshua Roys6e48a022012-06-29 23:07:14 +00001132 * - MSI K9N SLI: NVIDIA MCP55
Luc Verhaegen6c5f7332009-12-23 03:01:36 +00001133 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001134static int nvidia_mcp_gpio2_raise(void)
Luc Verhaegen6c5f7332009-12-23 03:01:36 +00001135{
1136 return nvidia_mcp_gpio_set(0x02, 1);
1137}
1138
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001139/*
1140 * Suited for:
Uwe Hermann83d349a2010-10-18 22:32:03 +00001141 * - EPoX EP-8NPA7I: Socket 754 + NVIDIA nForce4 4X
Jonathan Kollaschf8db9592010-10-15 23:02:15 +00001142 */
1143static int nvidia_mcp_gpio4_raise(void)
1144{
1145 return nvidia_mcp_gpio_set(0x04, 1);
1146}
1147
1148/*
1149 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001150 * - HP xw9400 (Tyan S2915-E OEM): Dual(!) NVIDIA MCP55
1151 *
1152 * Notes: a) There are two MCP55 chips, so also two SMBus bridges on that
1153 * board. We can't tell the SMBus logical devices apart, but we
1154 * can tell the LPC bridge functions apart.
1155 * We need to choose the SMBus bridge next to the LPC bridge with
1156 * ID 0x364 and the "LPC bridge" class.
1157 * b) #TBL is hardwired on that board to a pull-down. It can be
1158 * overridden by connecting the two solder points next to F2.
Michael Karcher2ead2e22010-06-01 16:09:06 +00001159 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001160static int nvidia_mcp_gpio5_raise(void)
Michael Karcher2ead2e22010-06-01 16:09:06 +00001161{
1162 return nvidia_mcp_gpio_set(0x05, 1);
1163}
1164
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001165/*
1166 * Suited for:
1167 * - abit NF7-S: NVIDIA CK804
Michael Karcher8f10d242010-04-11 21:01:06 +00001168 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001169static int nvidia_mcp_gpio8_raise(void)
Michael Karcher8f10d242010-04-11 21:01:06 +00001170{
1171 return nvidia_mcp_gpio_set(0x08, 1);
1172}
1173
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001174/*
1175 * Suited for:
Cristian Măgherușan-Stanciu9932c7b2011-07-07 19:56:58 +00001176 * - GIGABYTE GA-K8NS Pro-939: Socket 939 + NVIDIA nForce3 + CK8
Idwer Volleringd8a00a02011-06-13 16:58:54 +00001177 */
1178static int nvidia_mcp_gpio0a_raise(void)
1179{
1180 return nvidia_mcp_gpio_set(0x0a, 1);
1181}
1182
1183/*
1184 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001185 * - MSI K8N Neo2 Platinum: Socket 939 + nForce3 Ultra + CK8
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001186 */
Michael Karcher51825082010-06-12 23:14:03 +00001187static int nvidia_mcp_gpio0c_raise(void)
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001188{
1189 return nvidia_mcp_gpio_set(0x0c, 1);
1190}
1191
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001192/*
1193 * Suited for:
1194 * - abit NF-M2 nView: Socket AM2 + NVIDIA MCP51
Michael Karcherefd8af32010-07-24 22:50:54 +00001195 */
1196static int nvidia_mcp_gpio4_lower(void)
1197{
1198 return nvidia_mcp_gpio_set(0x04, 0);
1199}
1200
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001201/*
1202 * Suited for:
1203 * - ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001204 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001205static int nvidia_mcp_gpio10_raise(void)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001206{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001207 return nvidia_mcp_gpio_set(0x10, 1);
1208}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001209
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001210/*
1211 * Suited for:
1212 * - GIGABYTE GA-K8N-SLI: AMD socket 939 + NVIDIA CK804 + ITE IT8712F
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001213 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001214static int nvidia_mcp_gpio21_raise(void)
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001215{
1216 return nvidia_mcp_gpio_set(0x21, 0x01);
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001217}
1218
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001219/*
1220 * Suited for:
1221 * - EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001222 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001223static int nvidia_mcp_gpio31_raise(void)
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001224{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001225 return nvidia_mcp_gpio_set(0x31, 0x01);
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001226}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001227
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001228/*
1229 * Suited for:
Michael Karcher242efd42011-03-06 12:09:05 +00001230 * - GIGABYTE GA-K8N51GMF: Socket 754 + Geforce 6100 + MCP51
1231 * - GIGABYTE GA-K8N51GMF-9: Socket 939 + Geforce 6100 + MCP51
Joshua Roys2ee137f2010-09-07 17:52:09 +00001232 */
1233static int nvidia_mcp_gpio3b_raise(void)
1234{
1235 return nvidia_mcp_gpio_set(0x3b, 1);
1236}
1237
1238/*
1239 * Suited for:
Joshua Roysb992d342011-11-02 14:31:18 +00001240 * - Sun Ultra 40 M2: Dual Socket F (1207) + MCP55
1241 */
1242static int board_sun_ultra_40_m2(void)
1243{
1244 int ret;
1245 uint8_t reg;
1246 uint16_t base;
1247 struct pci_dev *dev;
1248
1249 ret = nvidia_mcp_gpio4_lower();
1250 if (ret)
1251 return ret;
1252
1253 dev = pci_dev_find(0x10de, 0x0364); /* NVIDIA MCP55 LPC bridge */
1254 if (!dev) {
1255 msg_perr("\nERROR: NVIDIA MCP55 LPC bridge not found.\n");
1256 return -1;
1257 }
1258
1259 base = pci_read_word(dev, 0xb4); /* some IO BAR? */
1260 if (!base)
1261 return -1;
1262
1263 reg = INB(base + 0x4b);
1264 reg |= 0x10;
1265 OUTB(reg, base + 0x4b);
1266
1267 return 0;
1268}
1269
1270/*
1271 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001272 * - Artec Group DBE61 and DBE62
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001273 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001274static int board_artecgroup_dbe6x(void)
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001275{
1276#define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001277#define DBE6x_PRI_BOOT_LOC_SHIFT 2
1278#define DBE6x_BOOT_OP_LATCHED_SHIFT 8
1279#define DBE6x_SEC_BOOT_LOC_SHIFT 10
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001280#define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT)
1281#define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT)
1282#define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT)
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001283#define DBE6x_BOOT_LOC_FLASH 2
1284#define DBE6x_BOOT_LOC_FWHUB 3
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001285
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001286 msr_t msr;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001287 unsigned long boot_loc;
1288
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001289 /* Geode only has a single core */
1290 if (setup_cpu_msr(0))
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001291 return -1;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001292
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001293 msr = rdmsr(DBE6x_MSR_DIVIL_BALL_OPTS);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001294
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001295 if ((msr.lo & (DBE6x_BOOT_OP_LATCHED)) ==
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001296 (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT))
1297 boot_loc = DBE6x_BOOT_LOC_FWHUB;
1298 else
1299 boot_loc = DBE6x_BOOT_LOC_FLASH;
1300
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001301 msr.lo &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC);
1302 msr.lo |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) |
Uwe Hermann394131e2008-10-18 21:14:13 +00001303 (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001304
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001305 wrmsr(DBE6x_MSR_DIVIL_BALL_OPTS, msr);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001306
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001307 cleanup_cpu_msr();
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001308
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001309 return 0;
1310}
1311
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001312/*
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001313 * Suited for:
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001314 * - ASUS A8AE-LE (Codename AmberineM; used in Compaq Presario 061)
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001315 * Datasheet(s) used:
1316 * - AMD document 43009 "AMD SB700/710/750 Register Reference Guide" rev. 1.00
1317 */
1318static int amd_sbxxx_gpio9_raise(void)
1319{
1320 struct pci_dev *dev;
1321 uint32_t reg;
1322
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001323 dev = pci_dev_find(0x1002, 0x4372); /* AMD SMBus controller */
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001324 if (!dev) {
1325 msg_perr("\nERROR: AMD SMBus Controller (0x4372) not found.\n");
1326 return -1;
1327 }
1328
1329 reg = pci_read_long(dev, 0xA8); /* GPIO_12_to_4_Cntrl CI_Reg: A8h-ABh */
1330 /* enable output (0: enable, 1: tristate):
1331 GPIO9 output enable is at bit 5 in 0xA9 */
1332 reg &= ~((uint32_t)1<<(8+5));
1333 /* raise:
1334 GPIO9 output register is at bit 5 in 0xA8 */
1335 reg |= (1<<5);
1336 pci_write_long(dev, 0xA8, reg);
1337
1338 return 0;
1339}
1340
1341/*
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001342 * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}.
Luc Verhaegenf5226912009-12-14 10:41:58 +00001343 */
1344static int intel_piix4_gpo_set(unsigned int gpo, int raise)
1345{
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001346 unsigned int gpo_byte, gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001347 struct pci_dev *dev;
1348 uint32_t tmp, base;
1349
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001350 /* GPO{0,8,27,28,30} are always available. */
1351 static const uint32_t nonmuxed_gpos = 0x58000101;
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001352
1353 static const struct {unsigned int reg, mask, value; } piix4_gpo[] = {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001354 {0},
1355 {0xB0, 0x0001, 0x0000}, /* GPO1... */
1356 {0xB0, 0x0001, 0x0000},
1357 {0xB0, 0x0001, 0x0000},
1358 {0xB0, 0x0001, 0x0000},
1359 {0xB0, 0x0001, 0x0000},
1360 {0xB0, 0x0001, 0x0000},
1361 {0xB0, 0x0001, 0x0000}, /* ...GPO7: GENCFG bit 0 */
1362 {0},
1363 {0xB0, 0x0100, 0x0000}, /* GPO9: GENCFG bit 8 */
1364 {0xB0, 0x0200, 0x0000}, /* GPO10: GENCFG bit 9 */
1365 {0xB0, 0x0400, 0x0000}, /* GPO11: GENCFG bit 10 */
1366 {0x4E, 0x0100, 0x0000}, /* GPO12... */
1367 {0x4E, 0x0100, 0x0000},
1368 {0x4E, 0x0100, 0x0000}, /* ...GPO14: XBCS bit 8 */
1369 {0xB2, 0x0002, 0x0002}, /* GPO15... */
1370 {0xB2, 0x0002, 0x0002}, /* ...GPO16: GENCFG bit 17 */
1371 {0xB2, 0x0004, 0x0004}, /* GPO17: GENCFG bit 18 */
1372 {0xB2, 0x0008, 0x0008}, /* GPO18: GENCFG bit 19 */
1373 {0xB2, 0x0010, 0x0010}, /* GPO19: GENCFG bit 20 */
1374 {0xB2, 0x0020, 0x0020}, /* GPO20: GENCFG bit 21 */
1375 {0xB2, 0x0040, 0x0040}, /* GPO21: GENCFG bit 22 */
1376 {0xB2, 0x1000, 0x1000}, /* GPO22... */
1377 {0xB2, 0x1000, 0x1000}, /* ...GPO23: GENCFG bit 28 */
1378 {0xB2, 0x2000, 0x2000}, /* GPO24: GENCFG bit 29 */
1379 {0xB2, 0x4000, 0x4000}, /* GPO25: GENCFG bit 30 */
1380 {0xB2, 0x8000, 0x8000}, /* GPO26: GENCFG bit 31 */
1381 {0},
1382 {0},
1383 {0x4E, 0x0100, 0x0000}, /* ...GPO29: XBCS bit 8 */
1384 {0}
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001385 };
1386
Luc Verhaegenf5226912009-12-14 10:41:58 +00001387 dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */
1388 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001389 msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +00001390 return -1;
1391 }
1392
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001393 /* Sanity check. */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001394 if (gpo > 30) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001395 msg_perr("\nERROR: Intel PIIX4 has no GPO%d.\n", gpo);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001396 return -1;
1397 }
1398
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001399 if ((((1 << gpo) & nonmuxed_gpos) == 0) &&
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001400 ((pci_read_word(dev, piix4_gpo[gpo].reg) & piix4_gpo[gpo].mask) !=
1401 piix4_gpo[gpo].value)) {
1402 msg_perr("\nERROR: PIIX4 GPO%d not programmed for output.\n", gpo);
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001403 return -1;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001404 }
1405
Luc Verhaegenf5226912009-12-14 10:41:58 +00001406 dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */
1407 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001408 msg_perr("\nERROR: Intel PIIX4 PM not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +00001409 return -1;
1410 }
1411
1412 /* PM IO base */
1413 base = pci_read_long(dev, 0x40) & 0x0000FFC0;
1414
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001415 gpo_byte = gpo >> 3;
1416 gpo_bit = gpo & 7;
1417 tmp = INB(base + 0x34 + gpo_byte); /* GPO register */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001418 if (raise)
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001419 tmp |= 0x01 << gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001420 else
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001421 tmp &= ~(0x01 << gpo_bit);
1422 OUTB(tmp, base + 0x34 + gpo_byte);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001423
1424 return 0;
1425}
1426
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001427/*
1428 * Suited for:
Joshua Roysd708fad2012-02-17 14:51:15 +00001429 * - ASUS OPLX-M
Mattias Mattsson85016b92010-09-01 01:21:34 +00001430 * - ASUS P2B-N
1431 */
1432static int intel_piix4_gpo18_lower(void)
1433{
1434 return intel_piix4_gpo_set(18, 0);
1435}
1436
1437/*
1438 * Suited for:
Mattias Mattssonc8ca3de2010-09-13 18:22:36 +00001439 * - MSI MS-6163 v2 (MS-6163 Pro): Intel 440BX + PIIX4E + Winbond W83977EF
1440 */
1441static int intel_piix4_gpo14_raise(void)
1442{
1443 return intel_piix4_gpo_set(14, 1);
1444}
1445
1446/*
1447 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001448 * - EPoX EP-BX3
Luc Verhaegenf5226912009-12-14 10:41:58 +00001449 */
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001450static int intel_piix4_gpo22_raise(void)
Luc Verhaegenf5226912009-12-14 10:41:58 +00001451{
1452 return intel_piix4_gpo_set(22, 1);
1453}
1454
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001455/*
1456 * Suited for:
Tim ter Laak4b933f02010-09-13 23:00:57 +00001457 * - abit BM6
1458 */
1459static int intel_piix4_gpo26_lower(void)
1460{
1461 return intel_piix4_gpo_set(26, 0);
1462}
1463
1464/*
1465 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001466 * - Intel SE440BX-2
Michael Karcher51cd0c92010-03-19 22:35:21 +00001467 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001468static int intel_piix4_gpo27_lower(void)
Michael Karcher51cd0c92010-03-19 22:35:21 +00001469{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001470 return intel_piix4_gpo_set(27, 0);
Michael Karcher51cd0c92010-03-19 22:35:21 +00001471}
1472
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001473/*
Mattias Mattsson2eaad632010-10-05 21:32:29 +00001474 * Suited for:
1475 * - Dell OptiPlex GX1
1476 */
1477static int intel_piix4_gpo30_lower(void)
1478{
1479 return intel_piix4_gpo_set(30, 0);
1480}
1481
1482/*
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001483 * Set a GPIO line on a given Intel ICH LPC controller.
Uwe Hermann93f66db2008-05-22 21:19:38 +00001484 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001485static int intel_ich_gpio_set(int gpio, int raise)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001486{
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001487 /* Table mapping the different Intel ICH LPC chipsets. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001488 static struct {
1489 uint16_t id;
1490 uint8_t base_reg;
1491 uint32_t bank0;
1492 uint32_t bank1;
1493 uint32_t bank2;
1494 } intel_ich_gpio_table[] = {
1495 {0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */
1496 {0x2420, 0x58, 0x0FE30000, 0, 0}, /* 82801AB (ICH0) */
1497 {0x2440, 0x58, 0x1BFF391B, 0, 0}, /* 82801BA (ICH2) */
1498 {0x244C, 0x58, 0x1A23399B, 0, 0}, /* 82801BAM (ICH2M) */
1499 {0x2450, 0x58, 0x1BFF0000, 0, 0}, /* 82801E (C-ICH) */
1500 {0x2480, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801CA (ICH3-S) */
1501 {0x248C, 0x58, 0x1A230000, 0x00000FFF, 0}, /* 82801CAM (ICH3-M) */
1502 {0x24C0, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801DB/DBL (ICH4/ICH4-L) */
1503 {0x24CC, 0x58, 0x1A030000, 0x00000FFF, 0}, /* 82801DBM (ICH4-M) */
1504 {0x24D0, 0x58, 0x1BFF0000, 0x00030305, 0}, /* 82801EB/ER (ICH5/ICH5R) */
1505 {0x2640, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FB/FR (ICH6/ICH6R) */
1506 {0x2641, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FBM (ICH6M) */
1507 {0x27B8, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GB/GR (ICH7 Family) */
1508 {0x27B9, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GBM (ICH7-M) */
1509 {0x27BD, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GHM (ICH7-M DH) */
1510 {0x2810, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HB/HR (ICH8/R) */
1511 {0x2811, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HBM (ICH8M-E) */
1512 {0x2812, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HH (ICH8DH) */
1513 {0x2814, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HO (ICH8DO) */
1514 {0x2815, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HEM (ICH8M) */
1515 {0x2912, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IH (ICH9DH) */
1516 {0x2914, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IO (ICH9DO) */
1517 {0x2916, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IR (ICH9R) */
1518 {0x2917, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IEM (ICH9M-E) */
1519 {0x2918, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IB (ICH9) */
1520 {0x2919, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IBM (ICH9M) */
1521 {0x3A14, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JDO (ICH10DO) */
1522 {0x3A16, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIR (ICH10R) */
1523 {0x3A18, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIB (ICH10) */
1524 {0x3A1A, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JD (ICH10D) */
1525 {0, 0, 0, 0, 0} /* end marker */
1526 };
Uwe Hermann93f66db2008-05-22 21:19:38 +00001527
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001528 struct pci_dev *dev;
1529 uint16_t base;
1530 uint32_t tmp;
1531 int i, allowed;
1532
1533 /* First, look for a known LPC bridge */
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001534 for (dev = pacc->devices; dev; dev = dev->next) {
Carl-Daniel Hailfingerd175e062010-05-21 23:00:56 +00001535 uint16_t device_class;
1536 /* libpci before version 2.2.4 does not store class info. */
1537 device_class = pci_read_word(dev, PCI_CLASS_DEVICE);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001538 if ((dev->vendor_id == 0x8086) &&
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001539 (device_class == 0x0601)) { /* ISA bridge */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001540 /* Is this device in our list? */
1541 for (i = 0; intel_ich_gpio_table[i].id; i++)
1542 if (dev->device_id == intel_ich_gpio_table[i].id)
1543 break;
1544
1545 if (intel_ich_gpio_table[i].id)
1546 break;
1547 }
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001548 }
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001549
Uwe Hermann93f66db2008-05-22 21:19:38 +00001550 if (!dev) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001551 msg_perr("\nERROR: No known Intel LPC bridge found.\n");
Uwe Hermann93f66db2008-05-22 21:19:38 +00001552 return -1;
1553 }
1554
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001555 /*
1556 * According to the datasheets, all Intel ICHs have the GPIO bar 5:1
1557 * strapped to zero. From some mobile ICH9 version on, this becomes
1558 * 6:1. The mask below catches all.
1559 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001560 base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0;
Uwe Hermann93f66db2008-05-22 21:19:38 +00001561
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001562 /* Check whether the line is allowed. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001563 if (gpio < 32)
1564 allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01;
1565 else if (gpio < 64)
1566 allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01;
1567 else
1568 allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01;
1569
1570 if (!allowed) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001571 msg_perr("\nERROR: This Intel LPC bridge does not allow"
1572 " setting GPIO%02d\n", gpio);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001573 return -1;
1574 }
1575
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001576 msg_pdbg("\nIntel ICH LPC bridge: %sing GPIO%02d.\n",
1577 raise ? "Rais" : "Dropp", gpio);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001578
1579 if (gpio < 32) {
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001580 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001581 tmp = INL(base);
1582 /* ICH/ICH0 multiplexes 27/28 on the line set. */
1583 if ((gpio == 28) &&
1584 ((dev->device_id == 0x2410) || (dev->device_id == 0x2420)))
1585 tmp |= 1 << 27;
1586 else
1587 tmp |= 1 << gpio;
1588 OUTL(tmp, base);
1589
1590 /* As soon as we are talking to ICH8 and above, this register
1591 decides whether we can set the gpio or not. */
1592 if (dev->device_id > 0x2800) {
1593 tmp = INL(base);
1594 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001595 msg_perr("\nERROR: This Intel LPC bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001596 " does not allow setting GPIO%02d\n",
1597 gpio);
1598 return -1;
1599 }
1600 }
1601
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001602 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001603 tmp = INL(base + 0x04);
1604 tmp &= ~(1 << gpio);
1605 OUTL(tmp, base + 0x04);
1606
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001607 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001608 tmp = INL(base + 0x0C);
1609 if (raise)
1610 tmp |= 1 << gpio;
1611 else
1612 tmp &= ~(1 << gpio);
1613 OUTL(tmp, base + 0x0C);
1614 } else if (gpio < 64) {
1615 gpio -= 32;
1616
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001617 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001618 tmp = INL(base + 0x30);
1619 tmp |= 1 << gpio;
1620 OUTL(tmp, base + 0x30);
1621
1622 /* As soon as we are talking to ICH8 and above, this register
1623 decides whether we can set the gpio or not. */
1624 if (dev->device_id > 0x2800) {
1625 tmp = INL(base + 30);
1626 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001627 msg_perr("\nERROR: This Intel LPC bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001628 " does not allow setting GPIO%02d\n",
1629 gpio + 32);
1630 return -1;
1631 }
1632 }
1633
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001634 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001635 tmp = INL(base + 0x34);
1636 tmp &= ~(1 << gpio);
1637 OUTL(tmp, base + 0x34);
1638
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001639 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001640 tmp = INL(base + 0x38);
1641 if (raise)
1642 tmp |= 1 << gpio;
1643 else
1644 tmp &= ~(1 << gpio);
1645 OUTL(tmp, base + 0x38);
1646 } else {
1647 gpio -= 64;
1648
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001649 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001650 tmp = INL(base + 0x40);
1651 tmp |= 1 << gpio;
1652 OUTL(tmp, base + 0x40);
1653
1654 tmp = INL(base + 40);
1655 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001656 msg_perr("\nERROR: This Intel LPC bridge does "
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001657 "not allow setting GPIO%02d\n", gpio + 64);
1658 return -1;
1659 }
1660
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001661 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001662 tmp = INL(base + 0x44);
1663 tmp &= ~(1 << gpio);
1664 OUTL(tmp, base + 0x44);
1665
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001666 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001667 tmp = INL(base + 0x48);
1668 if (raise)
1669 tmp |= 1 << gpio;
1670 else
1671 tmp &= ~(1 << gpio);
1672 OUTL(tmp, base + 0x48);
1673 }
Uwe Hermann93f66db2008-05-22 21:19:38 +00001674
1675 return 0;
1676}
1677
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001678/*
1679 * Suited for:
1680 * - abit IP35: Intel P35 + ICH9R
1681 * - abit IP35 Pro: Intel P35 + ICH9R
Joshua Roysac8b2a12011-08-11 04:21:34 +00001682 * - ASUS P5LD2
Uwe Hermann93f66db2008-05-22 21:19:38 +00001683 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001684static int intel_ich_gpio16_raise(void)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001685{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001686 return intel_ich_gpio_set(16, 1);
Uwe Hermann93f66db2008-05-22 21:19:38 +00001687}
1688
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001689/*
1690 * Suited for:
1691 * - HP Puffer2-UL8E (ASUS PTGD-LA OEM): LGA775 + 915 + ICH6
Michael Karchere57957c2010-07-24 11:14:37 +00001692 */
1693static int intel_ich_gpio18_raise(void)
1694{
1695 return intel_ich_gpio_set(18, 1);
1696}
1697
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001698/*
1699 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001700 * - MSI MS-7046: LGA775 + 915P + ICH6
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001701 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001702static int intel_ich_gpio19_raise(void)
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001703{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001704 return intel_ich_gpio_set(19, 1);
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001705}
1706
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001707/*
Luc Verhaegen6c5d4cc2009-11-28 18:26:21 +00001708 * Suited for:
Stefan Tauner027e0182012-05-02 19:48:21 +00001709 * - ASUS P5BV-R: LGA775 + 3200 + ICH7
1710 */
1711static int intel_ich_gpio20_raise(void)
1712{
1713 return intel_ich_gpio_set(20, 1);
1714}
1715
1716/*
1717 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001718 * - ASUS P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2
1719 * - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5
Michael Karcherf4b58792010-09-10 14:54:18 +00001720 * - ASUS P4P800: Intel socket478 + 865PE + ICH5R
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001721 * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R
Diego Elio Pettenòc6f71462011-03-06 22:52:55 +00001722 * - ASUS P4P800-VM: Intel socket478 + 865PE + ICH5R
Michael Karcher4a23e442010-09-10 14:46:46 +00001723 * - ASUS P5GD1 Pro: Intel LGA 775 + 915P + ICH6R
Joshua Roys1fd4f9e2011-08-11 05:47:32 +00001724 * - ASUS P5GD2 Premium: Intel LGA775 + 915G + ICH6R
Joshua Roysb1d980f2010-09-13 14:02:22 +00001725 * - ASUS P5GDC Deluxe: Intel socket775 + 915P + ICH6R
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001726 * - ASUS P5PE-VM: Intel LGA775 + 865G + ICH5
Stefan Taunerded71e52012-03-10 19:22:13 +00001727 * - ASUS TUSL2-C: Intel socket370 + 815 + ICH2
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001728 * - Samsung Polaris 32: socket478 + 865P + ICH5
Peter Stuge09c13332009-02-02 22:55:26 +00001729 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001730static int intel_ich_gpio21_raise(void)
Peter Stuge09c13332009-02-02 22:55:26 +00001731{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001732 return intel_ich_gpio_set(21, 1);
Peter Stuge09c13332009-02-02 22:55:26 +00001733}
1734
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001735/*
Michael Karcher03b80e92010-03-07 16:32:32 +00001736 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001737 * - ASUS P4B266: socket478 + Intel 845D + ICH2
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001738 * - ASUS P4B533-E: socket478 + 845E + ICH4
1739 * - ASUS P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2
Michael Karcherbfd89a52012-02-12 00:13:14 +00001740 * - TriGem Anaheim-3: socket370 + Intel 810 + ICH
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001741 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001742static int intel_ich_gpio22_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001743{
1744 return intel_ich_gpio_set(22, 1);
1745}
1746
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001747/*
1748 * Suited for:
Stefan Tauner716e0982011-07-25 20:38:52 +00001749 * - ASUS A8Jm (laptop): Intel 945 + ICH7
Michael Karcher14ab8d42011-08-25 14:06:50 +00001750 * - ASUS P5LP-LE used in ...
1751 * - HP Media Center m7270.fr Desktop PC as "Lithium-UL8E"
1752 * - Epson Endeavor MT7700
Stefan Tauner716e0982011-07-25 20:38:52 +00001753 */
1754static int intel_ich_gpio34_raise(void)
1755{
1756 return intel_ich_gpio_set(34, 1);
1757}
1758
1759/*
1760 * Suited for:
Stefan Taunerc6782182012-01-19 17:50:32 +00001761 * - AOpen i945GMx-VFX: Intel 945GM + ICH7-M used in ...
Paul Menzelac427b22012-02-16 21:07:07 +00001762 * - FSC ESPRIMO Q5010 (SMBIOS: D2544-B1)
Stefan Taunerc6782182012-01-19 17:50:32 +00001763 */
1764static int intel_ich_gpio38_raise(void)
1765{
1766 return intel_ich_gpio_set(38, 1);
1767}
1768
1769/*
1770 * Suited for:
Joshua Roysc73e2812011-07-09 19:46:53 +00001771 * - ASUS M6Ne (laptop): socket 479M (guessed) + Intel 855PM + ICH4-M
1772 */
1773static int intel_ich_gpio43_raise(void)
1774{
1775 return intel_ich_gpio_set(43, 1);
1776}
1777
1778/*
1779 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001780 * - HP Vectra VL400: 815 + ICH + PC87360
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001781 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001782static int board_hp_vl400(void)
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001783{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001784 int ret;
1785 ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */
1786 if (!ret)
Michael Karchercba52de2011-03-06 12:07:19 +00001787 ret = pc8736x_gpio_set(PC87360_ID, 0x09, 1); /* #WP ? */
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001788 if (!ret)
Michael Karchercba52de2011-03-06 12:07:19 +00001789 ret = pc8736x_gpio_set(PC87360_ID, 0x27, 1); /* #TBL */
1790 return ret;
1791}
1792
1793/*
1794 * Suited for:
1795 * - HP e-Vectra P2706T: 810E + ICH + PC87364
1796 */
1797static int board_hp_p2706t(void)
1798{
1799 int ret;
1800 ret = pc8736x_gpio_set(PC87364_ID, 0x25, 1);
1801 if (!ret)
1802 ret = pc8736x_gpio_set(PC87364_ID, 0x26, 1);
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001803 return ret;
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001804}
1805
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001806/*
Luc Verhaegen1265d8d2009-11-28 18:16:31 +00001807 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001808 * - Dell PowerEdge 1850: Intel PPGA604 + E7520 + ICH5R
1809 * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R
1810 * - ASRock 775i65G: Intel LGA 775 + 865G + ICH5
Uwe Hermann742999c2010-12-02 21:57:42 +00001811 * - MSI MS-6391 (845 Pro4): Intel Socket478 + 845 + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001812 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001813static int intel_ich_gpio23_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001814{
1815 return intel_ich_gpio_set(23, 1);
1816}
1817
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001818/*
1819 * Suited for:
Michael Karcher39dcdec2010-10-05 17:29:35 +00001820 * - GIGABYTE GA-6IEM: Intel Socket370 + i815 + ICH2
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001821 * - GIGABYTE GA-8IRML: Intel Socket478 + i845 + ICH2
Michael Karcherc7a1ffb2010-07-24 22:27:29 +00001822 */
1823static int intel_ich_gpio25_raise(void)
1824{
1825 return intel_ich_gpio_set(25, 1);
1826}
1827
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001828/*
1829 * Suited for:
1830 * - IBASE MB899: i945GM + ICH7
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001831 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001832static int intel_ich_gpio26_raise(void)
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001833{
1834 return intel_ich_gpio_set(26, 1);
1835}
1836
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001837/*
1838 * Suited for:
1839 * - P4SD-LA (HP OEM): i865 + ICH5
Joshua Roys9d9a1042011-06-13 16:59:01 +00001840 * - GIGABYTE GA-8IP775: 865P + ICH5
Michael Karcherc8613242010-08-13 12:49:01 +00001841 * - GIGABYTE GA-8PE667 Ultra 2: socket 478 + i845PE + ICH4
Maciej Pijanka6add0942011-06-09 20:59:30 +00001842 * - MSI MS-6788-40 (aka 848P Neo-V)
Michael Karcher87c90992010-07-24 11:03:48 +00001843 */
Idwer Vollering19dceac2010-07-24 18:47:45 +00001844static int intel_ich_gpio32_raise(void)
Michael Karcher87c90992010-07-24 11:03:48 +00001845{
1846 return intel_ich_gpio_set(32, 1);
1847}
1848
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001849/*
1850 * Suited for:
Joshua Roys7225ccd2011-05-18 01:32:16 +00001851 * - AOpen i975Xa-YDG: i975X + ICH7 + W83627EHF
1852 */
1853static int board_aopen_i975xa_ydg(void)
1854{
1855 int ret;
1856
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001857 /* Vendor BIOS ends up in LDN6... maybe the board enable is wrong,
Joshua Roys7225ccd2011-05-18 01:32:16 +00001858 * or perhaps it's not needed at all?
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001859 * The regs it tries to touch are 0xF0, 0xF1, 0xF2 which means if it
1860 * were in the right LDN, it would have to be GPIO1 or GPIO3.
Joshua Roys7225ccd2011-05-18 01:32:16 +00001861 */
1862/*
1863 ret = winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, x, 0)
1864 if (!ret)
1865*/
1866 ret = intel_ich_gpio_set(33, 1);
1867
1868 return ret;
1869}
1870
1871/*
1872 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001873 * - Acorp 6A815EPD: socket 370 + intel 815 + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001874 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001875static int board_acorp_6a815epd(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001876{
1877 int ret;
1878
1879 /* Lower Blocks Lock -- pin 7 of PLCC32 */
1880 ret = intel_ich_gpio_set(22, 1);
1881 if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */
1882 ret = intel_ich_gpio_set(23, 1);
1883
1884 return ret;
1885}
1886
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001887/*
1888 * Suited for:
1889 * - Kontron 986LCD-M: Socket478 + 915GM + ICH7R
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001890 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001891static int board_kontron_986lcd_m(void)
Stefan Reinauerac378972008-03-17 22:59:40 +00001892{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001893 int ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001894
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001895 ret = intel_ich_gpio_set(34, 1); /* #TBL */
1896 if (!ret)
1897 ret = intel_ich_gpio_set(35, 1); /* #WP */
Stefan Reinauerac378972008-03-17 22:59:40 +00001898
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001899 return ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001900}
1901
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001902/*
1903 * Suited for:
1904 * - Soyo SY-7VCA: Pro133A + VT82C686
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001905 */
Michael Karcher06477332010-03-19 22:49:09 +00001906static int via_apollo_gpo_set(int gpio, int raise)
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001907{
Michael Karcher06477332010-03-19 22:49:09 +00001908 struct pci_dev *dev;
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001909 uint32_t base, tmp;
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001910
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001911 /* VT82C686 power management */
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001912 dev = pci_dev_find(0x1106, 0x3057);
1913 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001914 msg_perr("\nERROR: VT82C686 PM device not found.\n");
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001915 return -1;
1916 }
1917
Sean Nelson316a29f2010-05-07 20:09:04 +00001918 msg_pdbg("\nVIA Apollo ACPI: %sing GPIO%02d.\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001919 raise ? "Rais" : "Dropp", gpio);
Michael Karcher06477332010-03-19 22:49:09 +00001920
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001921 /* Select GPO function on multiplexed pins. */
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001922 tmp = pci_read_byte(dev, 0x54);
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001923 switch (gpio) {
1924 case 0:
1925 tmp &= ~0x03;
1926 break;
1927 case 1:
1928 tmp |= 0x04;
1929 break;
1930 case 2:
1931 tmp |= 0x08;
1932 break;
1933 case 3:
1934 tmp |= 0x10;
1935 break;
Michael Karcher06477332010-03-19 22:49:09 +00001936 }
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001937 pci_write_byte(dev, 0x54, tmp);
1938
1939 /* PM IO base */
1940 base = pci_read_long(dev, 0x48) & 0x0000FF00;
1941
1942 /* Drop GPO0 */
Michael Karcher06477332010-03-19 22:49:09 +00001943 tmp = INL(base + 0x4C);
1944 if (raise)
1945 tmp |= 1U << gpio;
1946 else
1947 tmp &= ~(1U << gpio);
1948 OUTL(tmp, base + 0x4C);
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001949
1950 return 0;
1951}
1952
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001953/*
1954 * Suited for:
1955 * - abit VT6X4: Pro133x + VT82C686A
Mattias Mattssone3df96e2010-08-15 22:43:23 +00001956 * - abit VA6: Pro133x + VT82C686A
Michael Karcher187a46a2010-03-19 22:30:49 +00001957 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001958static int via_apollo_gpo4_lower(void)
Michael Karcher187a46a2010-03-19 22:30:49 +00001959{
1960 return via_apollo_gpo_set(4, 0);
1961}
1962
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001963/*
1964 * Suited for:
1965 * - Soyo SY-7VCA: Pro133A + VT82C686
Michael Karcher06477332010-03-19 22:49:09 +00001966 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001967static int via_apollo_gpo0_lower(void)
Michael Karcher06477332010-03-19 22:49:09 +00001968{
1969 return via_apollo_gpo_set(0, 0);
1970}
1971
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001972/*
Michael Karchera08d0f22011-07-25 17:25:24 +00001973 * Enable some GPIO pin on SiS southbridge and enables SIO flash writes.
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001974 *
1975 * Suited for:
1976 * - MSI 651M-L: SiS651 / SiS962
Michael Karchera08d0f22011-07-25 17:25:24 +00001977 * - GIGABYTE GA-8SIMLH
Michael Karcher9f9e6132010-01-09 17:36:06 +00001978 */
Michael Karchera08d0f22011-07-25 17:25:24 +00001979static int sis_gpio0_raise_and_w836xx_memw(void)
Michael Karcher9f9e6132010-01-09 17:36:06 +00001980{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001981 struct pci_dev *dev;
Uwe Hermann43959702010-03-13 17:28:29 +00001982 uint16_t base, temp;
Michael Karcher9f9e6132010-01-09 17:36:06 +00001983
1984 dev = pci_dev_find(0x1039, 0x0962);
1985 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001986 msg_perr("Expected south bridge not found\n");
Michael Karcher9f9e6132010-01-09 17:36:06 +00001987 return 1;
1988 }
1989
Michael Karcher9f9e6132010-01-09 17:36:06 +00001990 base = pci_read_word(dev, 0x74);
1991 temp = INW(base + 0x68);
1992 temp &= ~(1 << 0); /* Make pin output? */
Michael Karcher0435dfd2010-01-09 23:31:13 +00001993 OUTW(temp, base + 0x68);
Michael Karcher9f9e6132010-01-09 17:36:06 +00001994
1995 temp = INW(base + 0x64);
1996 temp |= (1 << 0); /* Raise output? */
1997 OUTW(temp, base + 0x64);
1998
1999 w836xx_memw_enable(0x2E);
2000
2001 return 0;
2002}
2003
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002004/*
Michael Gold6d52e472009-06-19 13:00:24 +00002005 * Find the runtime registers of an SMSC Super I/O, after verifying its
2006 * chip ID.
2007 *
2008 * Returns the base port of the runtime register block, or 0 on error.
2009 */
2010static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id,
2011 uint8_t logical_device)
2012{
2013 uint16_t rt_port = 0;
2014
2015 /* Verify the chip ID. */
Uwe Hermann1432a602009-06-28 23:26:37 +00002016 OUTB(0x55, sio_port); /* Enable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00002017 if (sio_read(sio_port, 0x20) != chip_id) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002018 msg_perr("\nERROR: SMSC Super I/O not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +00002019 goto out;
2020 }
2021
2022 /* If the runtime block is active, get its address. */
2023 sio_write(sio_port, 0x07, logical_device);
2024 if (sio_read(sio_port, 0x30) & 1) {
2025 rt_port = (sio_read(sio_port, 0x60) << 8)
2026 | sio_read(sio_port, 0x61);
2027 }
2028
2029 if (rt_port == 0) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002030 msg_perr("\nERROR: "
Michael Gold6d52e472009-06-19 13:00:24 +00002031 "Super I/O runtime interface not available.\n");
2032 }
2033out:
Uwe Hermann1432a602009-06-28 23:26:37 +00002034 OUTB(0xaa, sio_port); /* Disable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00002035 return rt_port;
2036}
2037
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002038/*
2039 * Disable write protection on the Mitac 6513WU. WP# on the FWH is
Michael Gold6d52e472009-06-19 13:00:24 +00002040 * connected to GP30 on the Super I/O, and TBL# is always high.
2041 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00002042static int board_mitac_6513wu(void)
Michael Gold6d52e472009-06-19 13:00:24 +00002043{
2044 struct pci_dev *dev;
2045 uint16_t rt_port;
2046 uint8_t val;
2047
2048 dev = pci_dev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */
2049 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002050 msg_perr("\nERROR: Intel 82801AA ISA bridge not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +00002051 return -1;
2052 }
2053
Uwe Hermann1432a602009-06-28 23:26:37 +00002054 rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa);
Michael Gold6d52e472009-06-19 13:00:24 +00002055 if (rt_port == 0)
2056 return -1;
2057
2058 /* Configure the GPIO pin. */
2059 val = INB(rt_port + 0x33); /* GP30 config */
Uwe Hermann1432a602009-06-28 23:26:37 +00002060 val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */
Michael Gold6d52e472009-06-19 13:00:24 +00002061 OUTB(val, rt_port + 0x33);
2062
2063 /* Disable write protection. */
2064 val = INB(rt_port + 0x4d); /* GP3 values */
Uwe Hermann1432a602009-06-28 23:26:37 +00002065 val |= 0x01; /* Set GP30 high. */
Michael Gold6d52e472009-06-19 13:00:24 +00002066 OUTB(val, rt_port + 0x4d);
2067
2068 return 0;
2069}
2070
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002071/*
2072 * Suited for:
Christoph Grenzd13a3942011-10-21 13:20:11 +00002073 * - abit AV8: Socket939 + K8T800Pro + VT8237
2074 */
2075static int board_abit_av8(void)
2076{
2077 uint8_t val;
2078
2079 /* Raise GPO pins GP22 & GP23 */
2080 val = INB(0x404E);
2081 val |= 0xC0;
2082 OUTB(val, 0x404E);
2083
2084 return 0;
2085}
2086
2087/*
2088 * Suited for:
Uwe Hermann45bd1442010-09-14 23:20:35 +00002089 * - ASUS A7V333: VIA KT333 + VT8233A + IT8703F
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002090 * - ASUS A7V8X: VIA KT400 + VT8235 + IT8703F
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002091 */
Uwe Hermann45bd1442010-09-14 23:20:35 +00002092static int it8703f_gpio51_raise(void)
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002093{
2094 uint16_t id, base;
2095 uint8_t tmp;
2096
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002097 /* Find the IT8703F. */
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002098 w836xx_ext_enter(0x2E);
2099 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
2100 w836xx_ext_leave(0x2E);
2101
2102 if (id != 0x8701) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002103 msg_perr("\nERROR: IT8703F Super I/O not found.\n");
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002104 return -1;
2105 }
2106
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002107 /* Get the GP567 I/O base. */
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002108 w836xx_ext_enter(0x2E);
2109 sio_write(0x2E, 0x07, 0x0C);
2110 base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
2111 w836xx_ext_leave(0x2E);
2112
2113 if (!base) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002114 msg_perr("\nERROR: Failed to read IT8703F Super I/O GPIO"
Luc Verhaegen78e4e122009-07-13 12:40:17 +00002115 " Base.\n");
2116 return -1;
2117 }
2118
2119 /* Raise GP51. */
2120 tmp = INB(base);
2121 tmp |= 0x02;
2122 OUTB(tmp, base);
2123
2124 return 0;
2125}
2126
Luc Verhaegen72272912009-09-01 21:22:23 +00002127/*
Joshua Roysa2f37222011-11-14 13:00:12 +00002128 * General routine for raising/dropping GPIO lines on the ITE IT87xx.
Luc Verhaegen72272912009-09-01 21:22:23 +00002129 */
Joshua Roysa2f37222011-11-14 13:00:12 +00002130static int it87_gpio_set(unsigned int gpio, int raise)
Luc Verhaegen72272912009-09-01 21:22:23 +00002131{
Joshua Roysa2f37222011-11-14 13:00:12 +00002132 int allowed, sio;
Luc Verhaegen72272912009-09-01 21:22:23 +00002133 unsigned int port;
Joshua Roysa2f37222011-11-14 13:00:12 +00002134 uint16_t base, sioport;
Luc Verhaegen72272912009-09-01 21:22:23 +00002135 uint8_t tmp;
2136
Joshua Roysa2f37222011-11-14 13:00:12 +00002137 /* IT87 GPIO configuration table */
2138 static const struct it87cfg {
2139 uint16_t id;
2140 uint8_t base_reg;
2141 uint32_t bank0;
2142 uint32_t bank1;
2143 uint32_t bank2;
2144 } it87_gpio_table[] = {
2145 {0x8712, 0x62, 0xCFF3FC00, 0x00FCFF3F, 0},
2146 {0x8718, 0x62, 0xCFF37C00, 0xF3FCDF3F, 0x0000000F},
2147 {0, 0, 0, 0, 0} /* end marker */
2148 };
2149 const struct it87cfg *cfg = NULL;
Luc Verhaegen72272912009-09-01 21:22:23 +00002150
Joshua Roysa2f37222011-11-14 13:00:12 +00002151 /* Find the Super I/O in the probed list */
2152 for (sio = 0; sio < superio_count; sio++) {
2153 int i;
2154 if (superios[sio].vendor != SUPERIO_VENDOR_ITE)
2155 continue;
2156
2157 /* Is this device in our list? */
2158 for (i = 0; it87_gpio_table[i].id; i++)
2159 if (superios[sio].model == it87_gpio_table[i].id) {
2160 cfg = &it87_gpio_table[i];
2161 goto found;
2162 }
2163 }
2164
2165 if (cfg == NULL) {
2166 msg_perr("\nERROR: No IT87 Super I/O GPIO configuration "
2167 "found.\n");
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002168 return -1;
Luc Verhaegen72272912009-09-01 21:22:23 +00002169 }
2170
Joshua Roysa2f37222011-11-14 13:00:12 +00002171found:
2172 /* Check whether the gpio is allowed. */
2173 if (gpio < 32)
2174 allowed = (cfg->bank0 >> gpio) & 0x01;
2175 else if (gpio < 64)
2176 allowed = (cfg->bank1 >> (gpio - 32)) & 0x01;
2177 else if (gpio < 96)
2178 allowed = (cfg->bank2 >> (gpio - 64)) & 0x01;
2179 else
2180 allowed = 0;
Luc Verhaegen72272912009-09-01 21:22:23 +00002181
Joshua Roysa2f37222011-11-14 13:00:12 +00002182 if (!allowed) {
2183 msg_perr("\nERROR: IT%02X does not allow setting GPIO%02u.\n",
2184 cfg->id, gpio);
Luc Verhaegen72272912009-09-01 21:22:23 +00002185 return -1;
2186 }
2187
Joshua Roysa2f37222011-11-14 13:00:12 +00002188 /* Read the Simple I/O Base Address Register */
2189 sioport = superios[sio].port;
2190 enter_conf_mode_ite(sioport);
2191 sio_write(sioport, 0x07, 0x07);
2192 base = (sio_read(sioport, cfg->base_reg) << 8) |
2193 sio_read(sioport, cfg->base_reg + 1);
2194 exit_conf_mode_ite(sioport);
Luc Verhaegen72272912009-09-01 21:22:23 +00002195
2196 if (!base) {
Joshua Roysa2f37222011-11-14 13:00:12 +00002197 msg_perr("\nERROR: Failed to read IT87 Super I/O GPIO Base.\n");
Luc Verhaegen72272912009-09-01 21:22:23 +00002198 return -1;
2199 }
2200
Joshua Roysa2f37222011-11-14 13:00:12 +00002201 msg_pdbg("Using IT87 GPIO base 0x%04x\n", base);
2202
2203 port = gpio / 10 - 1;
2204 gpio %= 10;
2205
2206 /* set GPIO. */
Luc Verhaegen72272912009-09-01 21:22:23 +00002207 tmp = INB(base + port);
2208 if (raise)
Joshua Roysa2f37222011-11-14 13:00:12 +00002209 tmp |= 1 << gpio;
Luc Verhaegen72272912009-09-01 21:22:23 +00002210 else
Joshua Roysa2f37222011-11-14 13:00:12 +00002211 tmp &= ~(1 << gpio);
Luc Verhaegen72272912009-09-01 21:22:23 +00002212 OUTB(tmp, base + port);
2213
2214 return 0;
2215}
2216
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002217/*
Russ Dillbd622d12010-03-09 16:57:06 +00002218 * Suited for:
Joshua Roys8ca42552011-11-19 19:31:17 +00002219 * - ASUS A7N8X-VM/400: NVIDIA nForce2 IGP2 + IT8712F
2220 */
2221static int it8712f_gpio12_raise(void)
2222{
2223 return it87_gpio_set(12, 1);
2224}
2225
2226/*
2227 * Suited for:
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00002228 * - ASUS A7V600-X: VIA KT600 + VT8237 + IT8712F
2229 * - ASUS A7V8X-X: VIA KT400 + VT8235 + IT8712F
Luc Verhaegen72272912009-09-01 21:22:23 +00002230 */
Joshua Roysa2f37222011-11-14 13:00:12 +00002231static int it8712f_gpio31_raise(void)
Luc Verhaegen72272912009-09-01 21:22:23 +00002232{
Joshua Roysa2f37222011-11-14 13:00:12 +00002233 return it87_gpio_set(32, 1);
2234}
2235
2236/*
2237 * Suited for:
2238 * - ASUS P5N-D: NVIDIA MCP51 + IT8718F
2239 * - ASUS P5N-E SLI: NVIDIA MCP51 + IT8718F
2240 */
2241static int it8718f_gpio63_raise(void)
2242{
2243 return it87_gpio_set(63, 1);
Luc Verhaegen72272912009-09-01 21:22:23 +00002244}
2245
Ingo Feldschmid8a0f9b02012-01-31 06:51:56 +00002246/*
2247 * Suited for all boards with ambiguous DMI chassis information, which should be
2248 * whitelisted because they are known to work:
2249 * - MSC Q7 Tunnel Creek Module (Q7-TCTC)
2250 */
2251static int p2_not_a_laptop(void)
2252{
2253 /* label this board as not a laptop */
2254 is_laptop = 0;
2255 msg_pdbg("Laptop detection overridden by P2 board enable.\n");
2256 return 0;
2257}
2258
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00002259#endif
2260
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002261/*
Uwe Hermannd0e347d2009-10-06 13:00:00 +00002262 * Below is the list of boards which need a special "board enable" code in
2263 * flashrom before their ROM chip can be accessed/written to.
2264 *
2265 * NOTE: Please add boards that _don't_ need such enables or don't work yet
2266 * to the respective tables in print.c. Thanks!
2267 *
Uwe Hermannffec5f32007-08-23 16:08:21 +00002268 * We use 2 sets of IDs here, you're free to choose which is which. This
2269 * is to provide a very high degree of certainty when matching a board on
2270 * the basis of subsystem/card IDs. As not every vendor handles
2271 * subsystem/card IDs in a sane manner.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002272 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00002273 * Keep the second set NULLed if it should be ignored. Keep the subsystem IDs
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00002274 * NULLed if they don't identify the board fully and if you can't use DMI.
2275 * But please take care to provide an as complete set of pci ids as possible;
2276 * autodetection is the preferred behaviour and we would like to make sure that
2277 * matches are unique.
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00002278 *
Michael Karcher6701ee82010-01-20 14:14:11 +00002279 * If PCI IDs are not sufficient for board matching, the match can be further
2280 * constrained by a string that has to be present in the DMI database for
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00002281 * the baseboard or the system entry. The pattern is matched by case sensitive
Michael Karcher6701ee82010-01-20 14:14:11 +00002282 * substring match, unless it is anchored to the beginning (with a ^ in front)
2283 * or the end (with a $ at the end). Both anchors may be specified at the
2284 * same time to match the full field.
2285 *
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00002286 * When a board is matched through DMI, the first and second main PCI IDs
2287 * and the first subsystem PCI ID have to match as well. If you specify the
2288 * first subsystem ID as 0x0:0x0, the DMI matching code expects that the
2289 * subsystem ID of that device is indeed zero.
2290 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00002291 * The coreboot ids are used two fold. When running with a coreboot firmware,
2292 * the ids uniquely matches the coreboot board identification string. When a
2293 * legacy bios is installed and when autodetection is not possible, these ids
Carl-Daniel Hailfinger2d927fb2012-01-04 00:48:27 +00002294 * can be used to identify the board through the -p internal:mainboard=
2295 * programmer parameter.
Luc Verhaegenc5210162009-04-20 12:38:17 +00002296 *
2297 * When a board is identified through its coreboot ids (in both cases), the
2298 * main pci ids are still required to match, as a safeguard.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002299 */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002300
Uwe Hermanndeeebe22009-05-08 16:23:34 +00002301/* Please keep this list alphabetically ordered by vendor/board name. */
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002302const struct board_match board_matches[] = {
Uwe Hermann5ab88892009-06-21 20:50:22 +00002303
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002304 /* first pci-id set [4], second pci-id set [4], dmi identifier, coreboot id [2], phase, vendor name, board name max_rom_... OK? flash enable */
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00002305#if defined(__i386__) || defined(__x86_64__)
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002306 {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, P3, "abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise},
Christoph Grenzd13a3942011-10-21 13:20:11 +00002307 {0x1106, 0x0282, 0x147B, 0x1415, 0x1106, 0x3227, 0x147B, 0x1415, "^AV8 ", NULL, NULL, P3, "abit", "AV8", 0, OK, board_abit_av8},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002308 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^i440BX-W977 (BM6)$", NULL, NULL, P3, "abit", "BM6", 0, OK, intel_piix4_gpo26_lower},
2309 {0x8086, 0x24d3, 0x147b, 0x1014, 0x8086, 0x2578, 0x147b, 0x1014, NULL, NULL, NULL, P3, "abit", "IC7", 0, NT, intel_ich_gpio23_raise},
2310 {0x8086, 0x2930, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, P3, "abit", "IP35", 0, OK, intel_ich_gpio16_raise},
2311 {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, P3, "abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise},
Stefan Tauner24c38df2012-08-11 02:33:20 +00002312 {0x10de, 0x0050, 0x147b, 0x1c1a, 0x10de, 0x0052, 0x147b, 0x1c1a, NULL, NULL, NULL, P3, "abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002313 {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, P3, "abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise},
Paul Menzelac427b22012-02-16 21:07:07 +00002314 {0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0260, 0x147b, 0x1c26, NULL, NULL, NULL, P3, "abit", "NF-M2 nView", 0, OK, nvidia_mcp_gpio4_lower},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002315 {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, "(VA6)$", NULL, NULL, P3, "abit", "VA6", 0, OK, via_apollo_gpo4_lower},
2316 {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", P3, "abit", "VT6X4", 0, OK, via_apollo_gpo4_lower},
2317 {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, P3, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd},
Stefan Tauner24c38df2012-08-11 02:33:20 +00002318 {0x1022, 0x746B, 0, 0, 0x1022, 0x7460, 0, 0, NULL, "AGAMI", "ARUMA", P3, "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002319 {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, P3, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e},
2320 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", P3, "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x},
2321 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", P3, "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x},
Stefan Taunerc6782182012-01-19 17:50:32 +00002322 {0x8086, 0x27b9, 0xa0a0, 0x0632, 0x8086, 0x27da, 0xa0a0, 0x0632, NULL, NULL, NULL, P3, "AOpen", "i945GMx-VFX", 0, OK, intel_ich_gpio38_raise},
Joshua Roys7225ccd2011-05-18 01:32:16 +00002323 {0x8086, 0x277c, 0xa0a0, 0x060b, 0x8086, 0x27da, 0xa0a0, 0x060b, NULL, NULL, NULL, P3, "AOpen", "i975Xa-YDG", 0, OK, board_aopen_i975xa_ydg},
Joshua Roysea3aed02011-11-16 22:08:11 +00002324 {0x8086, 0x27b8, 0x1849, 0x27b8, 0x8086, 0x27da, 0x1849, 0x27da, "^ConRoeXFire-eSATA2", NULL, NULL, P3, "ASRock", "ConRoeXFire-eSATA2", 0, OK, intel_ich_gpio16_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002325 {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41 $", NULL, NULL, P3, "ASRock", "K7S41", 0, OK, w836xx_memw_enable_2e},
Pawel Rozanski1d233072011-06-19 16:52:48 +00002326 {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41GX$", NULL, NULL, P3, "ASRock", "K7S41GX", 0, OK, w836xx_memw_enable_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002327 {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, P3, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise},
2328 {0x8086, 0x2570, 0x1849, 0x2570, 0x8086, 0x24d3, 0x1849, 0x24d0, NULL, NULL, NULL, P3, "ASRock", "775i65G", 0, OK, intel_ich_gpio23_raise},
Joshua Roys8ca42552011-11-19 19:31:17 +00002329 {0x10DE, 0x0060, 0x1043, 0x80AD, 0x10DE, 0x01E0, 0x1043, 0x80C0, NULL, NULL, NULL, P3, "ASUS", "A7N8X-VM/400", 0, OK, it8712f_gpio12_raise},
Joshua Roysa2f37222011-11-14 13:00:12 +00002330 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, P3, "ASUS", "A7V600-X", 0, OK, it8712f_gpio31_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002331 {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, P3, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e},
2332 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V8X", 0, OK, it8703f_gpio51_raise},
2333 {0x1106, 0x3099, 0x1043, 0x807F, 0x1106, 0x3147, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V333", 0, OK, it8703f_gpio51_raise},
Joshua Roysa2f37222011-11-14 13:00:12 +00002334 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, P3, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio31_raise},
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00002335 {0x1002, 0x4372, 0x103c, 0x2a26, 0x1002, 0x4377, 0x103c, 0x2a26, NULL, NULL, NULL, P3, "ASUS", "A8AE-LE", 0, OK, amd_sbxxx_gpio9_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002336 {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, P3, "ASUS", "A8Jm", 0, NT, intel_ich_gpio34_raise},
Stefan Taunera9cbbac2011-08-07 13:17:20 +00002337 {0x10DE, 0x0260, 0x103C, 0x2A34, 0x10DE, 0x0264, 0x103C, 0x2A34, "NODUSM3", NULL, NULL, P3, "ASUS", "A8M2N-LA (NodusM3-GL8E)", 0, OK, nvidia_mcp_gpio0_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002338 {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI2L", NULL, NULL, P3, "ASUS", "A8N-LA (Nagami-GL8E)", 0, OK, nvidia_mcp_gpio0_raise},
Stefan Tauner2414e092011-08-06 16:16:45 +00002339 {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, "^A8N-SLI DELUXE", NULL, NULL, P3, "ASUS", "A8N-SLI Deluxe", 0, NT, board_shuttle_fn25},
Stefan Taunerff80e682011-07-20 16:34:18 +00002340 {0x10de, 0x0264, 0x1043, 0x81bc, 0x10de, 0x02f0, 0x1043, 0x81cd, NULL, NULL, NULL, P3, "ASUS", "A8N-VM CSM", 0, OK, w83627ehf_gpio22_raise_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002341 {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, P3, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise},
2342 {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, P3, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise},
Joshua Roysc73e2812011-07-09 19:46:53 +00002343 {0x8086, 0x24cc, 0, 0, 0x8086, 0x24c3, 0x1043, 0x1869, "^M6Ne$", NULL, NULL, P3, "ASUS", "M6Ne", 0, NT, intel_ich_gpio43_raise},
Joshua Roysd708fad2012-02-17 14:51:15 +00002344 {0x8086, 0x7180, 0, 0, 0x8086, 0x7110, 0, 0, "^OPLX-M$", NULL, NULL, P3, "ASUS", "OPLX-M", 0, NT, intel_piix4_gpo18_lower},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002345 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^P2B-N$", NULL, NULL, P3, "ASUS", "P2B-N", 0, OK, intel_piix4_gpo18_lower},
2346 {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, P3, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise},
2347 {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, P3, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise},
2348 {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, P3, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise},
Joshua Roysa5f5a152011-11-15 08:08:15 +00002349 {0x8086, 0x2560, 0x103C, 0x2A00, 0x8086, 0x24C3, 0x103C, 0x2A01, "^Guppy", NULL, NULL, P3, "ASUS", "P4GV-LA (Guppy)", 0, OK, intel_ich_gpio21_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002350 {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, P3, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
2351 {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D5, 0x1043, 0x80F3, NULL, NULL, NULL, P3, "ASUS", "P4P800", 0, NT, intel_ich_gpio21_raise},
Sylvain "ythier" Hitier3093f8f2011-09-03 11:22:27 +00002352 {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D3, 0x1043, 0x80A6, "^P4P800-E$", NULL, NULL, P3, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002353 {0x8086, 0x2570, 0x1043, 0x80A5, 0x8086, 0x24d0, 0, 0, NULL, NULL, NULL, P3, "ASUS", "P4P800-VM", 0, OK, intel_ich_gpio21_raise},
2354 {0x1039, 0x0651, 0x1043, 0x8081, 0x1039, 0x0962, 0, 0, NULL, NULL, NULL, P3, "ASUS", "P4SC-E", 0, OK, it8707f_write_enable_2e},
2355 {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, P3, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise},
2356 {0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x5513, 0x1043, 0x8087, NULL, NULL, NULL, P3, "ASUS", "P4S800-MX", 512, OK, w836xx_memw_enable_2e},
2357 {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", P3, "ASUS", "P5A", 0, OK, board_asus_p5a},
Stefan Tauner027e0182012-05-02 19:48:21 +00002358 {0x8086, 0x27b8, 0x1043, 0x819e, 0x8086, 0x29f0, 0x1043, 0x82a5, "^P5BV-R$", NULL, NULL, P3, "ASUS", "P5BV-R", 0, OK, intel_ich_gpio20_raise},
Stefan Taunera4f14472011-10-22 22:01:09 +00002359 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, "^P5GD1 PRO$", NULL, NULL, P3, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise},
2360 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, "^P5GD1-VM$", NULL, NULL, P3, "ASUS", "P5GD1-VM/S", 0, OK, intel_ich_gpio21_raise},
2361 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, P3, "ASUS", "P5GD1(-VM)", 0, NT, intel_ich_gpio21_raise},
Joshua Roys1fd4f9e2011-08-11 05:47:32 +00002362 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GD2-Premium$", NULL, NULL, P3, "ASUS", "P5GD2 Premium", 0, OK, intel_ich_gpio21_raise},
Stefan Taunerd94d25d2012-07-28 03:17:15 +00002363 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x81a6, "^P5GD2-X$", NULL, NULL, P3, "ASUS", "P5GD2-X", 0, OK, intel_ich_gpio21_raise},
Stefan Taunera4f14472011-10-22 22:01:09 +00002364 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GDC-V$", NULL, NULL, P3, "ASUS", "P5GDC-V Deluxe", 0, OK, intel_ich_gpio21_raise},
2365 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GDC$", NULL, NULL, P3, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise},
2366 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, P3, "ASUS", "P5GD2/C variants", 0, NT, intel_ich_gpio21_raise},
Michael Karcher14ab8d42011-08-25 14:06:50 +00002367 {0x8086, 0x27b8, 0x103c, 0x2a22, 0x8086, 0x2770, 0x103c, 0x2a22, "^LITHIUM$", NULL, NULL, P3, "ASUS", "P5LP-LE (Lithium-UL8E)",0, OK, intel_ich_gpio34_raise},
2368 {0x8086, 0x27b8, 0x1043, 0x2a22, 0x8086, 0x2770, 0x1043, 0x2a22, "^P5LP-LE$", NULL, NULL, P3, "ASUS", "P5LP-LE (Epson OEM)", 0, OK, intel_ich_gpio34_raise},
Joshua Roys1fd4f9e2011-08-11 05:47:32 +00002369 {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, NT, intel_ich_gpio16_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002370 {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, P3, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise},
Joshua Roysa2f37222011-11-14 13:00:12 +00002371 {0x10DE, 0x0260, 0x1043, 0x81BC, 0x10DE, 0x026C, 0x1043, 0x829E, "^P5N-D$", NULL, NULL, P3, "ASUS", "P5N-D", 0, OK, it8718f_gpio63_raise},
2372 {0x10DE, 0x0260, 0x1043, 0x81BC, 0x10DE, 0x026C, 0x1043, 0x8249, "^P5N-E SLI$",NULL, NULL, P3, "ASUS", "P5N-E SLI", 0, NT, it8718f_gpio63_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002373 {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, P3, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise},
Stefan Taunerded71e52012-03-10 19:22:13 +00002374 {0x8086, 0x2443, 0x1043, 0x8027, 0x8086, 0x1130, 0x1043, 0x8027, NULL, NULL, NULL, P3, "ASUS", "TUSL2-C", 0, NT, intel_ich_gpio21_raise},
Stefan Taunerb6304c12012-08-09 23:25:27 +00002375 {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3116, 0x1106, 0x3116, "^KM266-8235$", "biostar", "m7viq", P3, "Biostar", "M7VIQ", 0, NT, w83697xx_memw_enable_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002376 {0x10b7, 0x9055, 0x1028, 0x0082, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Dell", "OptiPlex GX1", 0, OK, intel_piix4_gpo30_lower},
2377 {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, P3, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise},
2378 {0x10de, 0x03ea, 0x1019, 0x2602, 0x10de, 0x03e0, 0x1019, 0x2602, NULL, NULL, NULL, P3, "Elitegroup", "GeForce6100SM-M", 0, OK, board_ecs_geforce6100sm_m},
2379 {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, P3, "Elitegroup", "K7VTA3", 256, OK, NULL},
2380 {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, P3, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e},
Stefan Tauneraf4b1582011-08-06 16:16:33 +00002381 {0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, "8NPA7I", NULL, NULL, P3, "EPoX", "EP-8NPA7I", 0, OK, nvidia_mcp_gpio4_raise},
2382 {0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, "9NPA7I", NULL, NULL, P3, "EPoX", "EP-9NPA7I", 0, OK, nvidia_mcp_gpio4_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002383 {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, P3, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise},
2384 {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", P3, "EPoX", "EP-BX3", 0, NT, intel_piix4_gpo22_raise},
2385 {0x10de, 0x02f0, 0x105b, 0x0d01, 0x10de, 0x0264, 0x105b, 0x0d01, NULL, NULL, NULL, P3, "Foxconn", "6150K8MD-8EKRSH", 0, NT, nvidia_mcp_gpio2_raise},
2386 {0x8086, 0x2443, 0x8086, 0x2442, 0x8086, 0x1130, 0x8086, 0x1130, "^6IEM ", NULL, NULL, P3, "GIGABYTE", "GA-6IEM", 0, NT, intel_ich_gpio25_raise},
2387 {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-7ZM", 512, OK, NULL},
Joshua Roys9d9a1042011-06-13 16:59:01 +00002388 {0x8086, 0x2570, 0x1458, 0x2570, 0x8086, 0x24d0, 0, 0, "^8IP775/-G$",NULL, NULL, P3, "GIGABYTE", "GA-8IP775", 0, OK, intel_ich_gpio32_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002389 {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise},
2390 {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise},
Stefan Tauner716e0982011-07-25 20:38:52 +00002391 {0x1039, 0x0651, 0x1039, 0x0651, 0x1039, 0x7002, 0x1458, 0x5004, "^GA-8SIMLH$",NULL, NULL, P3, "GIGABYTE", "GA-8SIMLH", 0, OK, sis_gpio0_raise_and_w836xx_memw},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002392 {0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise},
2393 {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise},
Idwer Volleringd8a00a02011-06-13 16:58:54 +00002394 {0x10de, 0x00e4, 0x1458, 0x0c11, 0x10de, 0x00e0, 0x1458, 0x0c11, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8NS Pro-939", 0, NT, nvidia_mcp_gpio0a_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002395 {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise},
Idwer Volleringd8a00a02011-06-13 16:58:54 +00002396 {0x8086, 0x2415, 0x103c, 0x1250, 0x10b7, 0x9200, 0x103c, 0x1247, NULL, NULL, NULL, P3, "HP", "e-Vectra P2706T", 0, OK, board_hp_p2706t},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002397 {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", P3, "HP", "ProLiant DL145 G3", 0, OK, board_hp_dl145_g3_enable},
2398 {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", P3, "HP", "ProLiant DL165 G6", 0, OK, board_hp_dl165_g6_enable},
2399 {0x8086, 0x2580, 0x103c, 0x2a08, 0x8086, 0x2640, 0x103c, 0x2a0a, NULL, NULL, NULL, P3, "HP", "Puffer2-UL8E", 0, OK, intel_ich_gpio18_raise},
Idwer Volleringd8a00a02011-06-13 16:58:54 +00002400 {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, P3, "HP", "Vectra VL400", 0, OK, board_hp_vl400},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002401 {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, P3, "HP", "Vectra VL420 SFF", 0, OK, intel_ich_gpio22_raise},
2402 {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, "hp", "xw9400", P3, "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise},
2403 {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", P3, "IBASE", "MB899", 0, OK, intel_ich_gpio26_raise},
2404 {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, P3, "IBM", "x3455", 0, OK, board_ibm_x3455},
2405 {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, P3, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi},
2406 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, P3, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower},
Stefan Tauner24c38df2012-08-11 02:33:20 +00002407 {0x1022, 0x7468, 0, 0, 0x1022, 0x7460, 0, 0, NULL, "iwill", "dk8_htx", P3, "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002408 {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", P3, "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m},
2409 {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, P3, "Mitac", "6513WU", 0, OK, board_mitac_6513wu},
Ingo Feldschmid8a0f9b02012-01-31 06:51:56 +00002410 {0x8086, 0x8186, 0x8086, 0x8186, 0x8086, 0x8800, 0x0000, 0x0000, "^MSC Vertriebs GmbH$", NULL, NULL, P2, "MSC", "Q7-TCTC", 0, OK, p2_not_a_laptop},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002411 {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, P3, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, /* TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html. */
2412 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^MS-6163 (i440BX)$", NULL, NULL, P3, "MSI", "MS-6163 (MS-6163 Pro)", 0, OK, intel_piix4_gpo14_raise},
2413 {0x1039, 0x0745, 0, 0, 0x1039, 0x0018, 0, 0, "^MS-6561", NULL, NULL, P3, "MSI", "MS-6561 (745 Ultra)", 0, OK, w836xx_memw_enable_2e},
2414 {0x8086, 0x2560, 0x1462, 0x5770, 0x8086, 0x2562, 0x1462, 0x5778, NULL, NULL, NULL, P3, "MSI", "MS-6577 (Xenon)", 0, OK, w83627hf_gpio25_raise_2e},
2415 {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, P3, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v},
2416 {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, P3, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio44_raise_2e},
2417 {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, P3, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v},
2418 {0x1106, 0x3148, 0 , 0 , 0x1106, 0x3177, 0 , 0 , NULL, "msi", "ms6787", P3, "MSI", "MS-6787 (P4MAM-V/P4MAM-L)", 0, OK, w836xx_memw_enable_2e},
Maciej Pijanka6add0942011-06-09 20:59:30 +00002419 {0x8086, 0x24d3, 0x1462, 0x7880, 0x8086, 0x2570, 0, 0, NULL, NULL, NULL, P3, "MSI", "MS-6788-040 (848P NeoV)", 0, OK, intel_ich_gpio32_raise},
Michael Karchera08d0f22011-07-25 17:25:24 +00002420 {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, P3, "MSI", "MS-7005 (651M-L)", 0, OK, sis_gpio0_raise_and_w836xx_memw},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002421 {0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, P3, "MSI", "MS-7025 (K8N Neo2 Platinum)", 0, OK, nvidia_mcp_gpio0c_raise},
2422 {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, P3, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise},
2423 {0x8086, 0x244b, 0x1462, 0x3910, 0x8086, 0x2442, 0x1462, 0x3910, NULL, NULL, NULL, P3, "MSI", "MS-6391 (845 Pro4)", 0, OK, intel_ich_gpio23_raise},
2424 {0x1106, 0x3149, 0x1462, 0x7061, 0x1106, 0x3227, 0, 0, NULL, NULL, NULL, P3, "MSI", "MS-7061 (KM4M-V/KM4AM-V)", 0, OK, w836xx_memw_enable_2e},
2425 {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", P3, "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio44_raise_4e},
2426 {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, P3, "MSI", "MS-7207 (K8NGM2-L)", 0, NT, nvidia_mcp_gpio2_raise},
Joshua Roys6e48a022012-06-29 23:07:14 +00002427 {0x10DE, 0x0360, 0x1462, 0x7250, 0x10DE, 0x0368, 0x1462, 0x7250, NULL, NULL, NULL, P3, "MSI", "MS-7250 (K9N SLI)", 0, OK, nvidia_mcp_gpio2_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002428 {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0},
2429 {0x8086, 0x24d3, 0x144d, 0xb025, 0x8086, 0x1050, 0x144d, 0xb025, NULL, NULL, NULL, P3, "Samsung", "Polaris 32", 0, OK, intel_ich_gpio21_raise},
2430 {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", P3, "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e},
2431 {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, P3, "Shuttle", "AK38N", 256, OK, NULL},
2432 {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, P3, "Shuttle", "FN25", 0, OK, board_shuttle_fn25},
2433 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, P3, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower},
Joshua Roysb992d342011-11-02 14:31:18 +00002434 {0x10de, 0x0364, 0x108e, 0x6676, 0x10de, 0x0369, 0x108e, 0x6676, "^Sun Ultra 40 M2", NULL, NULL, P3, "Sun", "Ultra 40 M2", 0, OK, board_sun_ultra_40_m2},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002435 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, P3, "Tekram", "P6Pro-A5", 256, OK, NULL},
2436 {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, P3, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e},
Michael Karcherbfd89a52012-02-12 00:13:14 +00002437 {0x8086, 0x7120, 0x109f, 0x3157, 0x8086, 0x2410, 0, 0, NULL, NULL, NULL, P3, "TriGem", "Anaheim-3", 0, OK, intel_ich_gpio22_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002438 {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, P3, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e},
2439 {0x1106, 0x0259, 0x1106, 0xAA07, 0x1106, 0x3227, 0x1106, 0xAA07, NULL, NULL, NULL, P3, "VIA", "EPIA EK", 0, NT, via_vt823x_gpio9_raise},
2440 {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, P3, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise},
2441 {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, P3, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise},
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00002442#endif
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002443 { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, P3, NULL, NULL, 0, NT, NULL}, /* end marker */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002444};
2445
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002446/*
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +00002447 * Match boards on coreboot table gathered vendor and part name.
Uwe Hermannffec5f32007-08-23 16:08:21 +00002448 * Require main PCI IDs to match too as extra safety.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002449 */
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002450static const struct board_match *board_match_cbname(const char *vendor,
2451 const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002452{
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002453 const struct board_match *board = board_matches;
2454 const struct board_match *partmatch = NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002455
Uwe Hermanna93045c2009-05-09 00:47:04 +00002456 for (; board->vendor_name; board++) {
Uwe Hermann394131e2008-10-18 21:14:13 +00002457 if (vendor && (!board->lb_vendor
2458 || strcasecmp(board->lb_vendor, vendor)))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002459 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002460
Peter Stuge0b9c5f32008-07-02 00:47:30 +00002461 if (!board->lb_part || strcasecmp(board->lb_part, part))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002462 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002463
Uwe Hermanna7e05482007-05-09 10:17:44 +00002464 if (!pci_dev_find(board->first_vendor, board->first_device))
2465 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002466
Uwe Hermanna7e05482007-05-09 10:17:44 +00002467 if (board->second_vendor &&
Uwe Hermann394131e2008-10-18 21:14:13 +00002468 !pci_dev_find(board->second_vendor, board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002469 continue;
Peter Stuge6b53fed2008-01-27 16:21:21 +00002470
2471 if (vendor)
2472 return board;
2473
2474 if (partmatch) {
2475 /* a second entry has a matching part name */
Sean Nelson316a29f2010-05-07 20:09:04 +00002476 msg_pinfo("AMBIGUOUS BOARD NAME: %s\n", part);
2477 msg_pinfo("At least vendors '%s' and '%s' match.\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002478 partmatch->lb_vendor, board->lb_vendor);
Carl-Daniel Hailfinger2d927fb2012-01-04 00:48:27 +00002479 msg_perr("Please use the full -p internal:mainboard="
2480 "vendor:part syntax.\n");
Peter Stuge6b53fed2008-01-27 16:21:21 +00002481 return NULL;
2482 }
2483 partmatch = board;
Uwe Hermanna7e05482007-05-09 10:17:44 +00002484 }
Uwe Hermann372eeb52007-12-04 21:49:06 +00002485
Peter Stuge6b53fed2008-01-27 16:21:21 +00002486 if (partmatch)
2487 return partmatch;
2488
Carl-Daniel Hailfingerbc25f942009-07-30 13:30:17 +00002489 if (!partvendor_from_cbtable) {
2490 /* Only warn if the mainboard type was not gathered from the
2491 * coreboot table. If it was, the coreboot implementor is
2492 * expected to fix flashrom, too.
2493 */
Carl-Daniel Hailfinger2d927fb2012-01-04 00:48:27 +00002494 msg_perr("\nUnknown vendor:board from -p internal:mainboard="
2495 " programmer parameter:\n%s:%s\n\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002496 vendor, part);
Carl-Daniel Hailfingerbc25f942009-07-30 13:30:17 +00002497 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00002498 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002499}
2500
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002501/*
Uwe Hermannffec5f32007-08-23 16:08:21 +00002502 * Match boards on PCI IDs and subsystem IDs.
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002503 * Second set of IDs can be either main+subsystem IDs, main IDs or no IDs.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002504 */
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002505const static struct board_match *board_match_pci_ids(enum board_match_phase phase)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002506{
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002507 const struct board_match *board = board_matches;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002508
Uwe Hermanna93045c2009-05-09 00:47:04 +00002509 for (; board->vendor_name; board++) {
Michael Karcher2eab70d2010-02-04 10:58:50 +00002510 if ((!board->first_card_vendor || !board->first_card_device) &&
2511 !board->dmi_pattern)
Uwe Hermanna7e05482007-05-09 10:17:44 +00002512 continue;
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002513 if (board->phase != phase)
2514 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002515
Uwe Hermanna7e05482007-05-09 10:17:44 +00002516 if (!pci_card_find(board->first_vendor, board->first_device,
Uwe Hermann394131e2008-10-18 21:14:13 +00002517 board->first_card_vendor,
2518 board->first_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002519 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002520
Uwe Hermanna7e05482007-05-09 10:17:44 +00002521 if (board->second_vendor) {
2522 if (board->second_card_vendor) {
2523 if (!pci_card_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00002524 board->second_device,
2525 board->second_card_vendor,
2526 board->second_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002527 continue;
2528 } else {
2529 if (!pci_dev_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00002530 board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002531 continue;
2532 }
2533 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002534
Michael Karcher6701ee82010-01-20 14:14:11 +00002535 if (board->dmi_pattern) {
2536 if (!has_dmi_support) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002537 msg_perr("WARNING: Can't autodetect %s %s,"
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002538 " DMI info unavailable.\n",
2539 board->vendor_name, board->board_name);
Michael Karcher6701ee82010-01-20 14:14:11 +00002540 continue;
2541 } else {
2542 if (!dmi_match(board->dmi_pattern))
2543 continue;
2544 }
2545 }
2546
Uwe Hermanna7e05482007-05-09 10:17:44 +00002547 return board;
2548 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002549
Uwe Hermanna7e05482007-05-09 10:17:44 +00002550 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002551}
2552
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002553static int unsafe_board_handler(const struct board_match *board)
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002554{
2555 if (!board)
2556 return 1;
2557
2558 if (board->status == OK)
2559 return 0;
2560
2561 if (!force_boardenable) {
2562 msg_pinfo("WARNING: Your mainboard is %s %s, but the mainboard-specific\n"
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002563 "code has not been tested, and thus will not be executed by default.\n"
2564 "Depending on your hardware environment, erasing, writing or even probing\n"
2565 "can fail without running the board specific code.\n\n"
2566 "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n"
2567 "\"internal programmer\") for details.\n",
2568 board->vendor_name, board->board_name);
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002569 return 1;
2570 }
2571 msg_pinfo("NOTE: Running an untested board enable procedure.\n"
2572 "Please report success/failure to flashrom@flashrom.org\n"
2573 "with your board name and SUCCESS or FAILURE in the subject.\n");
2574 return 0;
2575}
2576
2577/* FIXME: Should this be identical to board_flash_enable? */
2578static int board_handle_phase(enum board_match_phase phase)
2579{
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002580 const struct board_match *board = NULL;
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002581
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002582 board = board_match_pci_ids(phase);
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002583
2584 if (unsafe_board_handler(board))
2585 board = NULL;
2586
2587 if (!board)
2588 return 0;
2589
2590 if (!board->enable) {
2591 /* Not sure if there is a valid case for this. */
2592 msg_perr("Board match found, but nothing to do?\n");
2593 return 0;
2594 }
2595
2596 return board->enable();
2597}
2598
2599void board_handle_before_superio(void)
2600{
2601 board_handle_phase(P1);
2602}
2603
2604void board_handle_before_laptop(void)
2605{
2606 board_handle_phase(P2);
2607}
2608
Uwe Hermann372eeb52007-12-04 21:49:06 +00002609int board_flash_enable(const char *vendor, const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002610{
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002611 const struct board_match *board = NULL;
Uwe Hermanna7e05482007-05-09 10:17:44 +00002612 int ret = 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002613
Peter Stuge6b53fed2008-01-27 16:21:21 +00002614 if (part)
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002615 board = board_match_cbname(vendor, part);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002616
Uwe Hermanna7e05482007-05-09 10:17:44 +00002617 if (!board)
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +00002618 board = board_match_pci_ids(P3);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002619
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002620 if (unsafe_board_handler(board))
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002621 board = NULL;
Michael Karcher7f0c3ec2010-03-07 22:29:28 +00002622
Uwe Hermanna7e05482007-05-09 10:17:44 +00002623 if (board) {
Luc Verhaegen93938c32010-01-20 14:45:03 +00002624 if (board->max_rom_decode_parallel)
2625 max_rom_decode.parallel =
2626 board->max_rom_decode_parallel * 1024;
2627
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00002628 if (board->enable != NULL) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002629 msg_pinfo("Disabling flash write protection for "
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002630 "board \"%s %s\"... ", board->vendor_name,
2631 board->board_name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002632
Uwe Hermann36dec8b2010-06-07 19:06:26 +00002633 ret = board->enable();
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00002634 if (ret)
Sean Nelson316a29f2010-05-07 20:09:04 +00002635 msg_pinfo("FAILED!\n");
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00002636 else
Sean Nelson316a29f2010-05-07 20:09:04 +00002637 msg_pinfo("OK.\n");
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00002638 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00002639 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002640
Uwe Hermanna7e05482007-05-09 10:17:44 +00002641 return ret;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002642}