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review.sourcearcade.org / libgfxinit / 3f37cce66ef8b36932db08a1fb5e6486647da308 / . / common / hw-gfx-gma-registers.ads
blob: c9454c983a09a90c883fe2c899a8169498361284 [file] [log] [blame]
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1--
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]2-- Copyright (C) 2015-2017 secunet Security Networks AG
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
Nico Huber125a29e2016-10-18 00:23:54 +0200[diff] [blame]6-- the Free Software Foundation; either version 2 of the License, or
7-- (at your option) any later version.
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]8--
9-- This program is distributed in the hope that it will be useful,
10-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12-- GNU General Public License for more details.
13--
14
15with System;
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]16with HW.GFX.GMA.Config;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]17
18private package HW.GFX.GMA.Registers
19with
20 Abstract_State =>
21 ((Address_State with Part_Of => GMA.State),
22 (Register_State with External, Part_Of => GMA.Device_State),
23 (GTT_State with External, Part_Of => GMA.Device_State)),
24 Initializes => Address_State
25is
Nico Huber0b2329a2018-06-09 21:14:27 +0200[diff] [blame]26
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]27 type Registers_Invalid_Index is
28 (Invalid_Register, -- Allow a placeholder when access is not acceptable
29
30 RCS_RING_BUFFER_TAIL,
31 RCS_RING_BUFFER_HEAD,
32 RCS_RING_BUFFER_STRT,
33 RCS_RING_BUFFER_CTL,
34 QUIRK_02084,
35 QUIRK_02090,
36 HWSTAM,
37 MI_MODE,
38 INSTPM,
39 GT_MODE,
40 CACHE_MODE_0,
41 CTX_SIZE,
42 PP_DCLV_HIGH,
43 PP_DCLV_LOW,
44 GFX_MODE,
45 ARB_MODE,
46 HWS_PGA,
47 GAM_ECOCHK,
Arthur Heymans229ed1c2018-03-28 16:45:43 +0200[diff] [blame]48 GMCH_GMBUS0,
49 GMCH_GMBUS1,
50 GMCH_GMBUS2,
51 GMCH_GMBUS3,
52 GMCH_GMBUS4,
53 GMCH_GMBUS5,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]54 GMCH_DPLL_A,
55 GMCH_DPLL_B,
56 GMCH_FPA0,
57 GMCH_FPA1,
58 GMCH_FPB0,
59 GMCH_FPB1,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]60 MBCTL,
61 UCGCTL1,
62 UCGCTL2,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]63 GMCH_CLKCFG,
Nico Huberb47a5c42019-09-29 00:07:21 +0200[diff] [blame]64 GMCH_HPLLVCO_MOBILE,
65 GMCH_HPLLVCO,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]66 VCS_RING_BUFFER_TAIL,
67 VCS_RING_BUFFER_HEAD,
68 VCS_RING_BUFFER_STRT,
69 VCS_RING_BUFFER_CTL,
70 SLEEP_PSMI_CONTROL,
71 VCS_HWSTAM,
72 VCS_PP_DCLV_HIGH,
73 VCS_PP_DCLV_LOW,
74 GAC_ECO_BITS,
75 BCS_RING_BUFFER_TAIL,
76 BCS_RING_BUFFER_HEAD,
77 BCS_RING_BUFFER_STRT,
78 BCS_RING_BUFFER_CTL,
79 BCS_HWSTAM,
80 BCS_PP_DCLV_HIGH,
81 BCS_PP_DCLV_LOW,
82 GAB_CTL_REG,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]83 CPU_VGACNTRL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]84 FUSE_STATUS,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]85 ILK_DISPLAY_CHICKEN2,
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]86 FUSE_STRAP,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]87 DSPCLK_GATE_D,
88 FBA_CFB_BASE,
89 FBC_CTL,
90 IPS_CTL,
91 DEISR,
92 DEIMR,
93 DEIIR,
94 DEIER,
95 GTISR,
96 GTIMR,
97 GTIIR,
98 GTIER,
99 IIR,
100 HOTPLUG_CTL,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]101 TC_HOTPLUG_CTL,
102 DISPLAY_ERR_FATAL_MASK,
103 DBUF_CTL_S2,
104 DBUF_CTL_S3,
105 MBUS_CTL,
106 GEN11_DE_HPD_ISR,
107 DBUF_CTL_S1,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]108 ARB_CTL,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]109 DBUF_CTL_S0,
110 MBUS_ABOX_CTL,
111 MBUS_ABOX1_CTL,
112 MBUS_ABOX2_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]113 WM_PIPE_A,
114 WM_PIPE_B,
115 WM1_LP_ILK,
116 WM2_LP_ILK,
117 WM3_LP_ILK,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]118 BW_BUDDY1_CTL,
119 BW_BUDDY1_PAGE_MASK,
120 BW_BUDDY2_CTL,
121 BW_BUDDY2_PAGE_MASK,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]122 WM_PIPE_C,
123 WM_LINETIME_A,
124 WM_LINETIME_B,
125 WM_LINETIME_C,
126 PWR_WELL_CTL_BIOS,
127 PWR_WELL_CTL_DRIVER,
128 PWR_WELL_CTL_KVMR,
129 PWR_WELL_CTL_DEBUG,
130 PWR_WELL_CTL5,
131 PWR_WELL_CTL6,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]132 PWR_AUX_CTL_BIOS,
133 PWR_AUX_CTL_DRIVER,
134 PWR_DDI_CTL_BIOS,
135 PWR_DDI_CTL_DRIVER,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]136 CDCLK_CTL,
137 LCPLL1_CTL,
138 LCPLL2_CTL,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]139 DPLL_4_ENABLE,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]140 SPLL_CTL,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]141 MGPLL1_ENABLE,
142 MGPLL2_ENABLE,
143 MGPLL3_ENABLE,
144 MGPLL4_ENABLE,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]145 WRPLL_CTL_1,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]146 MGPLL6_ENABLE,
147 PORTTC3_PLL1_ENABLE,
148 PORTTC4_PLL0_ENABLE,
149 PORTTC4_PLL1_ENABLE,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]150 WRPLL_CTL_2,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]151 BXT_DE_PLL_ENABLE,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]152 BXT_PORT_PLL_ENABLE_A,
153 BXT_PORT_PLL_ENABLE_B,
154 BXT_PORT_PLL_ENABLE_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]155 PORT_CLK_SEL_DDIA,
156 PORT_CLK_SEL_DDIB,
157 PORT_CLK_SEL_DDIC,
158 PORT_CLK_SEL_DDID,
159 PORT_CLK_SEL_DDIE,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]160 DDI_CLK_SEL_USBC3,
161 DDI_CLK_SEL_USBC4,
162 DDI_CLK_SEL_USBC5,
163 DDI_CLK_SEL_USBC6,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]164 TRANSA_CLK_SEL,
165 TRANSB_CLK_SEL,
166 TRANSC_CLK_SEL,
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]167 CDCLK_FREQ,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]168 NDE_RSTWRN_OPT,
Angel Ponsae186bd2020-10-21 21:37:34 +0200[diff] [blame]169 GEN8_CHICKEN_DCPR_1,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]170 GEN11_CHICKEN_DCPR_2,
171 GEN9_CLKGATE_DIS_0,
172 GEN9_CHICKEN_DPCR_3,
173 GEN9_CLKGATE_DIS_5,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]174 BLC_PWM_CPU_CTL2,
175 BLC_PWM_CPU_CTL,
Nico Huber6b4678d2019-09-22 21:31:52 +0200[diff] [blame]176 DFSM,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]177 DSSM,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]178 HTOTAL_A,
179 HBLANK_A,
180 HSYNC_A,
181 VTOTAL_A,
182 VBLANK_A,
183 VSYNC_A,
184 PIPEASRC,
185 PIPE_VSYNCSHIFT_A,
186 PIPEA_DATA_M1,
187 PIPEA_DATA_N1,
188 PIPEA_LINK_M1,
189 PIPEA_LINK_N1,
190 FDI_TX_CTL_A,
191 PIPEA_DDI_FUNC_CTL,
192 PIPEA_MSA_MISC,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]193 TGL_DP_TP_CTL_A,
194 TGL_DP_TP_STATUS_A,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]195 SRD_CTL_A,
196 SRD_STATUS_A,
197 HTOTAL_B,
198 HBLANK_B,
199 HSYNC_B,
200 VTOTAL_B,
201 VBLANK_B,
202 VSYNC_B,
203 PIPEBSRC,
204 PIPE_VSYNCSHIFT_B,
205 PIPEB_DATA_M1,
206 PIPEB_DATA_N1,
207 PIPEB_LINK_M1,
208 PIPEB_LINK_N1,
209 FDI_TX_CTL_B,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]210 PORT_HOTPLUG_EN,
211 PORT_HOTPLUG_STAT,
212 GMCH_SDVOB,
213 GMCH_SDVOC,
214 GMCH_LVDS,
Arthur Heymanse87d0d12018-03-28 17:02:49 +0200[diff] [blame]215 GMCH_PP_STATUS,
216 GMCH_PP_CONTROL,
217 GMCH_PP_ON_DELAYS,
218 GMCH_PP_OFF_DELAYS,
219 GMCH_PP_DIVISOR,
Arthur Heymansd5198442018-03-28 17:05:12 +0200[diff] [blame]220 GMCH_PFIT_CONTROL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]221 PIPEB_DDI_FUNC_CTL,
222 PIPEB_MSA_MISC,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]223 TGL_DP_TP_CTL_B,
224 TGL_DP_TP_STATUS_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]225 SRD_CTL_B,
226 SRD_STATUS_B,
227 HTOTAL_C,
228 HBLANK_C,
229 HSYNC_C,
230 VTOTAL_C,
231 VBLANK_C,
232 VSYNC_C,
233 PIPECSRC,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]234 G4X_AUD_VID_DID,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]235 PIPE_VSYNCSHIFT_C,
236 PIPEC_DATA_M1,
237 PIPEC_DATA_N1,
238 PIPEC_LINK_M1,
239 PIPEC_LINK_N1,
240 FDI_TX_CTL_C,
241 PIPEC_DDI_FUNC_CTL,
242 PIPEC_MSA_MISC,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]243 TGL_DP_TP_CTL_C,
244 TGL_DP_TP_STATUS_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]245 SRD_CTL_C,
246 SRD_STATUS_C,
247 DDI_BUF_CTL_A,
248 DDI_AUX_CTL_A,
249 DDI_AUX_DATA_A_1,
250 DDI_AUX_DATA_A_2,
251 DDI_AUX_DATA_A_3,
252 DDI_AUX_DATA_A_4,
253 DDI_AUX_DATA_A_5,
254 DDI_AUX_MUTEX_A,
255 DP_TP_CTL_A,
256 DDI_BUF_CTL_B,
257 DDI_AUX_CTL_B,
258 DDI_AUX_DATA_B_1,
259 DDI_AUX_DATA_B_2,
260 DDI_AUX_DATA_B_3,
261 DDI_AUX_DATA_B_4,
262 DDI_AUX_DATA_B_5,
263 DDI_AUX_MUTEX_B,
264 DP_TP_CTL_B,
265 DP_TP_STATUS_B,
266 DDI_BUF_CTL_C,
267 DDI_AUX_CTL_C,
268 DDI_AUX_DATA_C_1,
269 DDI_AUX_DATA_C_2,
270 DDI_AUX_DATA_C_3,
271 DDI_AUX_DATA_C_4,
272 DDI_AUX_DATA_C_5,
273 DDI_AUX_MUTEX_C,
274 DP_TP_CTL_C,
275 DP_TP_STATUS_C,
276 DDI_BUF_CTL_D,
277 DDI_AUX_CTL_D,
278 DDI_AUX_DATA_D_1,
279 DDI_AUX_DATA_D_2,
280 DDI_AUX_DATA_D_3,
281 DDI_AUX_DATA_D_4,
282 DDI_AUX_DATA_D_5,
283 DDI_AUX_MUTEX_D,
284 DP_TP_CTL_D,
285 DP_TP_STATUS_D,
286 DDI_BUF_CTL_E,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]287 DDI_AUX_CTL_USBC2,
288 DDI_AUX_DATA_USBC2_1,
289 DDI_AUX_DATA_USBC2_2,
290 DDI_AUX_DATA_USBC2_3,
291 DDI_AUX_DATA_USBC2_4,
292 DDI_AUX_DATA_USBC2_5,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]293 DP_TP_CTL_E,
294 DP_TP_STATUS_E,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]295 DDI_BUF_CTL_USBC3,
296 DDI_AUX_CTL_USBC3,
297 DDI_AUX_DATA_USBC3_1,
298 DDI_AUX_DATA_USBC3_2,
299 DDI_AUX_DATA_USBC3_3,
300 DDI_AUX_DATA_USBC3_4,
301 DDI_AUX_DATA_USBC3_5,
302 DDI_BUF_CTL_USBC4,
303 DDI_AUX_CTL_USBC4,
304 DDI_AUX_DATA_USBC4_1,
305 DDI_AUX_DATA_USBC4_2,
306 DDI_AUX_DATA_USBC4_3,
307 DDI_AUX_DATA_USBC4_4,
308 DDI_AUX_DATA_USBC4_5,
309 DDI_BUF_CTL_USBC5,
310 DDI_AUX_CTL_USBC5,
311 DDI_AUX_DATA_USBC5_1,
312 DDI_AUX_DATA_USBC5_2,
313 DDI_AUX_DATA_USBC5_3,
314 DDI_AUX_DATA_USBC5_4,
315 DDI_AUX_DATA_USBC5_5,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]316 SRD_CTL,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]317 DDI_AUX_CTL_USBC6,
318 DDI_AUX_DATA_USBC6_1,
319 DDI_AUX_DATA_USBC6_2,
320 DDI_AUX_DATA_USBC6_3,
321 DDI_AUX_DATA_USBC6_4,
322 DDI_AUX_DATA_USBC6_5,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]323 SRD_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]324 BXT_PHY_CTL_A,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]325 PHY_MISC_B,
326 PHY_MISC_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]327 BXT_PHY_CTL_B,
328 BXT_PHY_CTL_C,
329 BXT_PHY_CTL_FAM_EDP,
330 BXT_PHY_CTL_FAM_DDI,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]331 DDI_BUF_TRANS_A_S0T1,
332 DDI_BUF_TRANS_A_S0T2,
333 DDI_BUF_TRANS_A_S1T1,
334 DDI_BUF_TRANS_A_S1T2,
335 DDI_BUF_TRANS_A_S2T1,
336 DDI_BUF_TRANS_A_S2T2,
337 DDI_BUF_TRANS_A_S3T1,
338 DDI_BUF_TRANS_A_S3T2,
339 DDI_BUF_TRANS_A_S4T1,
340 DDI_BUF_TRANS_A_S4T2,
341 DDI_BUF_TRANS_A_S5T1,
342 DDI_BUF_TRANS_A_S5T2,
343 DDI_BUF_TRANS_A_S6T1,
344 DDI_BUF_TRANS_A_S6T2,
345 DDI_BUF_TRANS_A_S7T1,
346 DDI_BUF_TRANS_A_S7T2,
347 DDI_BUF_TRANS_A_S8T1,
348 DDI_BUF_TRANS_A_S8T2,
349 DDI_BUF_TRANS_A_S9T1,
350 DDI_BUF_TRANS_A_S9T2,
351 DDI_BUF_TRANS_B_S0T1,
352 DDI_BUF_TRANS_B_S0T2,
353 DDI_BUF_TRANS_B_S1T1,
354 DDI_BUF_TRANS_B_S1T2,
355 DDI_BUF_TRANS_B_S2T1,
356 DDI_BUF_TRANS_B_S2T2,
357 DDI_BUF_TRANS_B_S3T1,
358 DDI_BUF_TRANS_B_S3T2,
359 DDI_BUF_TRANS_B_S4T1,
360 DDI_BUF_TRANS_B_S4T2,
361 DDI_BUF_TRANS_B_S5T1,
362 DDI_BUF_TRANS_B_S5T2,
363 DDI_BUF_TRANS_B_S6T1,
364 DDI_BUF_TRANS_B_S6T2,
365 DDI_BUF_TRANS_B_S7T1,
366 DDI_BUF_TRANS_B_S7T2,
367 DDI_BUF_TRANS_B_S8T1,
368 DDI_BUF_TRANS_B_S8T2,
369 DDI_BUF_TRANS_B_S9T1,
370 DDI_BUF_TRANS_B_S9T2,
371 DDI_BUF_TRANS_C_S0T1,
372 DDI_BUF_TRANS_C_S0T2,
373 DDI_BUF_TRANS_C_S1T1,
374 DDI_BUF_TRANS_C_S1T2,
375 DDI_BUF_TRANS_C_S2T1,
376 DDI_BUF_TRANS_C_S2T2,
377 DDI_BUF_TRANS_C_S3T1,
378 DDI_BUF_TRANS_C_S3T2,
379 DDI_BUF_TRANS_C_S4T1,
380 DDI_BUF_TRANS_C_S4T2,
381 DDI_BUF_TRANS_C_S5T1,
382 DDI_BUF_TRANS_C_S5T2,
383 DDI_BUF_TRANS_C_S6T1,
384 DDI_BUF_TRANS_C_S6T2,
385 DDI_BUF_TRANS_C_S7T1,
386 DDI_BUF_TRANS_C_S7T2,
387 DDI_BUF_TRANS_C_S8T1,
388 DDI_BUF_TRANS_C_S8T2,
389 DDI_BUF_TRANS_C_S9T1,
390 DDI_BUF_TRANS_C_S9T2,
391 DDI_BUF_TRANS_D_S0T1,
392 DDI_BUF_TRANS_D_S0T2,
393 DDI_BUF_TRANS_D_S1T1,
394 DDI_BUF_TRANS_D_S1T2,
395 DDI_BUF_TRANS_D_S2T1,
396 DDI_BUF_TRANS_D_S2T2,
397 DDI_BUF_TRANS_D_S3T1,
398 DDI_BUF_TRANS_D_S3T2,
399 DDI_BUF_TRANS_D_S4T1,
400 DDI_BUF_TRANS_D_S4T2,
401 DDI_BUF_TRANS_D_S5T1,
402 DDI_BUF_TRANS_D_S5T2,
403 DDI_BUF_TRANS_D_S6T1,
404 DDI_BUF_TRANS_D_S6T2,
405 DDI_BUF_TRANS_D_S7T1,
406 DDI_BUF_TRANS_D_S7T2,
407 DDI_BUF_TRANS_D_S8T1,
408 DDI_BUF_TRANS_D_S8T2,
409 DDI_BUF_TRANS_D_S9T1,
410 DDI_BUF_TRANS_D_S9T2,
411 DDI_BUF_TRANS_E_S0T1,
412 DDI_BUF_TRANS_E_S0T2,
413 DDI_BUF_TRANS_E_S1T1,
414 DDI_BUF_TRANS_E_S1T2,
415 DDI_BUF_TRANS_E_S2T1,
416 DDI_BUF_TRANS_E_S2T2,
417 DDI_BUF_TRANS_E_S3T1,
418 DDI_BUF_TRANS_E_S3T2,
419 DDI_BUF_TRANS_E_S4T1,
420 DDI_BUF_TRANS_E_S4T2,
421 DDI_BUF_TRANS_E_S5T1,
422 DDI_BUF_TRANS_E_S5T2,
423 DDI_BUF_TRANS_E_S6T1,
424 DDI_BUF_TRANS_E_S6T2,
425 DDI_BUF_TRANS_E_S7T1,
426 DDI_BUF_TRANS_E_S7T2,
427 DDI_BUF_TRANS_E_S8T1,
428 DDI_BUF_TRANS_E_S8T2,
429 DDI_BUF_TRANS_E_S9T1,
430 DDI_BUF_TRANS_E_S9T2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]431 AUD_VID_DID,
432 PFA_WIN_POS,
433 PFA_WIN_SZ,
434 PFA_CTL_1,
435 PS_WIN_POS_1_A,
436 PS_WIN_SZ_1_A,
437 PS_CTRL_1_A,
438 PS_WIN_POS_2_A,
439 PS_WIN_SZ_2_A,
440 PS_CTRL_2_A,
441 PFB_WIN_POS,
442 PFB_WIN_SZ,
443 PFB_CTL_1,
444 PS_WIN_POS_1_B,
445 PS_WIN_SZ_1_B,
446 PS_CTRL_1_B,
447 PS_WIN_POS_2_B,
448 PS_WIN_SZ_2_B,
449 PS_CTRL_2_B,
450 PFC_WIN_POS,
451 PFC_WIN_SZ,
452 PFC_CTL_1,
453 PS_WIN_POS_1_C,
454 PS_WIN_SZ_1_C,
455 PS_CTRL_1_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]456 BXT_PORT_CL1CM_DW0_BC,
Nico Huber58afc202017-06-12 21:34:55 +0200[diff] [blame]457 DISPIO_CR_TX_BMU_CR0,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]458 PORT_CL_DW5_B,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]459 BXT_PORT_CL1CM_DW9_BC,
460 BXT_PORT_CL1CM_DW10_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]461 BXT_PORT_PLL_EBB_0_B,
462 BXT_PORT_PLL_EBB_4_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]463 DPLL1_CFGR1,
464 DPLL1_CFGR2,
465 DPLL2_CFGR1,
466 DPLL2_CFGR2,
467 DPLL3_CFGR1,
468 DPLL3_CFGR2,
469 DPLL_CTRL1,
470 DPLL_CTRL2,
471 DPLL_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]472 BXT_PORT_CL1CM_DW28_BC,
473 BXT_PORT_CL1CM_DW30_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]474 BXT_PORT_PLL_0_B,
475 BXT_PORT_PLL_1_B,
476 BXT_PORT_PLL_2_B,
477 BXT_PORT_PLL_3_B,
478 BXT_PORT_PLL_6_B,
479 BXT_PORT_PLL_8_B,
480 BXT_PORT_PLL_9_B,
481 BXT_PORT_PLL_10_B,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]482 BXT_PORT_REF_DW3_BC,
483 BXT_PORT_REF_DW6_BC,
484 BXT_PORT_REF_DW8_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]485 BXT_PORT_PLL_EBB_0_C,
486 BXT_PORT_PLL_EBB_4_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]487 BXT_PORT_CL2CM_DW6_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]488 BXT_PORT_PLL_0_C,
489 BXT_PORT_PLL_1_C,
490 BXT_PORT_PLL_2_C,
491 BXT_PORT_PLL_3_C,
492 BXT_PORT_PLL_6_C,
493 BXT_PORT_PLL_8_C,
494 BXT_PORT_PLL_9_C,
495 BXT_PORT_PLL_10_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]496 BXT_PORT_PCS_DW10_01_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]497 BXT_PORT_PCS_DW12_01_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]498 BXT_PORT_TX_DW2_LN0_B,
499 BXT_PORT_TX_DW3_LN0_B,
500 BXT_PORT_TX_DW4_LN0_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]501 BXT_PORT_TX_DW14_LN0_B,
502 BXT_PORT_TX_DW14_LN1_B,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]503 PORT_PCS_DW1_GRP_B,
504 PORT_TX_DW2_GRP_B,
505 PORT_TX_DW4_GRP_B,
506 PORT_TX_DW5_GRP_B,
507 PORT_TX_DW7_GRP_B,
508 PORT_TX_DW8_GRP_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]509 BXT_PORT_TX_DW14_LN2_B,
510 BXT_PORT_TX_DW14_LN3_B,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]511 PORT_PCS_DW1_LN0_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]512 BXT_PORT_PCS_DW10_01_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]513 BXT_PORT_PCS_DW12_01_C,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]514 PORT_TX_DW2_LN0_B,
515 PORT_TX_DW4_LN0_B,
516 PORT_TX_DW5_LN0_B,
517 PORT_TX_DW7_LN0_B,
518 PORT_TX_DW8_LN0_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]519 BXT_PORT_TX_DW2_LN0_C,
520 BXT_PORT_TX_DW3_LN0_C,
521 BXT_PORT_TX_DW4_LN0_C,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]522 BXT_PORT_TX_DW14_LN0_C,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]523 PORT_TX_DW4_LN1_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]524 BXT_PORT_TX_DW14_LN1_C,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]525 PORT_TX_DW4_LN2_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]526 BXT_PORT_TX_DW14_LN2_C,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]527 PORT_TX_DW4_LN3_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]528 BXT_PORT_TX_DW14_LN3_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]529 BXT_PORT_PCS_DW10_GRP_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]530 BXT_PORT_PCS_DW12_GRP_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]531 BXT_PORT_TX_DW2_GRP_B,
532 BXT_PORT_TX_DW3_GRP_B,
533 BXT_PORT_TX_DW4_GRP_B,
534 BXT_PORT_PCS_DW10_GRP_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]535 BXT_PORT_PCS_DW12_GRP_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]536 BXT_PORT_TX_DW2_GRP_C,
537 BXT_PORT_TX_DW3_GRP_C,
538 BXT_PORT_TX_DW4_GRP_C,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]539 BXT_DE_PLL_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]540 HTOTAL_EDP,
541 HBLANK_EDP,
542 HSYNC_EDP,
543 VTOTAL_EDP,
544 VBLANK_EDP,
545 VSYNC_EDP,
546 PIPE_EDP_DATA_M1,
547 PIPE_EDP_DATA_N1,
548 PIPE_EDP_LINK_M1,
549 PIPE_EDP_LINK_N1,
550 PIPE_EDP_DDI_FUNC_CTL,
551 PIPE_EDP_MSA_MISC,
552 SRD_CTL_EDP,
553 SRD_STATUS_EDP,
554 PIPE_SCANLINE_A,
555 PIPEACONF,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]556 PIPEA_ARB_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]557 PIPEAMISC,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]558 PIPEA_CHICKEN,
559 PIPE_MBUS_DBOX_CTL_A,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]560 PIPE_FRMCNT_A,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]561 PIPEA_GMCH_DATA_M,
562 PIPEA_GMCH_DATA_N,
563 PIPEA_GMCH_LINK_M,
564 PIPEA_GMCH_LINK_N,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]565 CUR_CTL_A,
566 CUR_BASE_A,
567 CUR_POS_A,
568 CUR_FBC_CTL_A,
Nico Huber75a707f2018-06-18 16:28:33 +0200[diff] [blame]569 CURBCNTR,
570 CURBBASE,
571 CURBPOS,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]572 CUR_WM_A_0,
573 CUR_WM_A_1,
574 CUR_WM_A_2,
575 CUR_WM_A_3,
576 CUR_WM_A_4,
577 CUR_WM_A_5,
578 CUR_WM_A_6,
579 CUR_WM_A_7,
580 CUR_BUF_CFG_A,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]581 DSPACNTR,
582 DSPALINOFF,
583 DSPASTRIDE,
584 PLANE_POS_1_A,
585 PLANE_SIZE_1_A,
586 DSPASURF,
587 DSPATILEOFF,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]588 PLANE_AUX_DIST_1_A,
589 PLANE_COLOR_CTL_1_A,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]590 PLANE_WM_1_A_0,
591 PLANE_WM_1_A_1,
592 PLANE_WM_1_A_2,
593 PLANE_WM_1_A_3,
594 PLANE_WM_1_A_4,
595 PLANE_WM_1_A_5,
596 PLANE_WM_1_A_6,
597 PLANE_WM_1_A_7,
598 PLANE_BUF_CFG_1_A,
599 SPACNTR,
600 PIPE_SCANLINE_B,
601 PIPEBCONF,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]602 PIPEB_ARB_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]603 PIPEBMISC,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]604 PIPEB_CHICKEN,
605 PIPE_MBUS_DBOX_CTL_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]606 PIPE_FRMCNT_B,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]607 PIPEB_GMCH_DATA_M,
608 PIPEB_GMCH_DATA_N,
609 PIPEB_GMCH_LINK_M,
610 PIPEB_GMCH_LINK_N,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]611 CUR_CTL_B,
612 CUR_BASE_B,
613 CUR_POS_B,
614 CUR_FBC_CTL_B,
615 CUR_WM_B_0,
616 CUR_WM_B_1,
617 CUR_WM_B_2,
618 CUR_WM_B_3,
619 CUR_WM_B_4,
620 CUR_WM_B_5,
621 CUR_WM_B_6,
622 CUR_WM_B_7,
623 CUR_BUF_CFG_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]624 DSPBCNTR,
625 DSPBLINOFF,
626 DSPBSTRIDE,
627 PLANE_POS_1_B,
628 PLANE_SIZE_1_B,
629 DSPBSURF,
630 DSPBTILEOFF,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]631 PLANE_AUX_DIST_1_B,
632 PLANE_COLOR_CTL_1_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]633 PLANE_WM_1_B_0,
634 PLANE_WM_1_B_1,
635 PLANE_WM_1_B_2,
636 PLANE_WM_1_B_3,
637 PLANE_WM_1_B_4,
638 PLANE_WM_1_B_5,
639 PLANE_WM_1_B_6,
640 PLANE_WM_1_B_7,
641 PLANE_BUF_CFG_1_B,
642 SPBCNTR,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]643 GMCH_VGACNTRL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]644 PIPE_SCANLINE_C,
645 PIPECCONF,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]646 PIPEC_ARB_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]647 PIPECMISC,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]648 PIPEC_CHICKEN,
649 PIPE_MBUS_DBOX_CTL_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]650 PIPE_FRMCNT_C,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]651 CUR_CTL_C,
652 CUR_BASE_C,
653 CUR_POS_C,
654 CUR_FBC_CTL_C,
655 CUR_WM_C_0,
656 CUR_WM_C_1,
657 CUR_WM_C_2,
658 CUR_WM_C_3,
659 CUR_WM_C_4,
660 CUR_WM_C_5,
661 CUR_WM_C_6,
662 CUR_WM_C_7,
663 CUR_BUF_CFG_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]664 DSPCCNTR,
665 DSPCLINOFF,
666 DSPCSTRIDE,
667 PLANE_POS_1_C,
668 PLANE_SIZE_1_C,
669 DSPCSURF,
670 DSPCTILEOFF,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]671 PLANE_AUX_DIST_1_C,
672 PLANE_COLOR_CTL_1_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]673 PLANE_WM_1_C_0,
674 PLANE_WM_1_C_1,
675 PLANE_WM_1_C_2,
676 PLANE_WM_1_C_3,
677 PLANE_WM_1_C_4,
678 PLANE_WM_1_C_5,
679 PLANE_WM_1_C_6,
680 PLANE_WM_1_C_7,
681 PLANE_BUF_CFG_1_C,
682 SPCCNTR,
683 PIPE_EDP_CONF,
684 PCH_FDI_CHICKEN_B_C,
685 QUIRK_C2004,
686 SFUSE_STRAP,
687 PCH_DSPCLK_GATE_D,
688 SDEISR,
689 SDEIMR,
690 SDEIIR,
691 SDEIER,
692 SHOTPLUG_CTL,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]693 SHOTPLUG_CTL_TC,
694 SHPD_FILTER_CNT,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]695 PCH_GMBUS0,
696 PCH_GMBUS1,
697 PCH_GMBUS2,
698 PCH_GMBUS3,
699 PCH_GMBUS4,
700 PCH_GMBUS5,
701 SBI_ADDR,
702 SBI_DATA,
703 SBI_CTL_STAT,
704 PCH_DPLL_A,
705 PCH_DPLL_B,
706 PCH_PIXCLK_GATE,
707 PCH_FPA0,
708 PCH_FPA1,
709 PCH_FPB0,
710 PCH_FPB1,
711 PCH_DREF_CONTROL,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]712 PCH_RAWCLK_FREQ,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]713 PCH_DPLL_SEL,
714 PCH_PP_STATUS,
715 PCH_PP_CONTROL,
716 PCH_PP_ON_DELAYS,
717 PCH_PP_OFF_DELAYS,
718 PCH_PP_DIVISOR,
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]719 BXT_PP_STATUS_2,
720 BXT_PP_CONTROL_2,
721 BXT_PP_ON_DELAYS_2,
722 BXT_PP_OFF_DELAYS_2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]723 BLC_PWM_PCH_CTL1,
724 BLC_PWM_PCH_CTL2,
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]725 BXT_BLC_PWM_DUTY_1,
726 BXT_BLC_PWM_CTL_2,
727 BXT_BLC_PWM_FREQ_2,
728 BXT_BLC_PWM_DUTY_2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]729 TRANS_HTOTAL_A,
730 TRANS_HBLANK_A,
731 TRANS_HSYNC_A,
732 TRANS_VTOTAL_A,
733 TRANS_VBLANK_A,
734 TRANS_VSYNC_A,
735 TRANS_VSYNCSHIFT_A,
736 TRANSA_DATA_M1,
737 TRANSA_DATA_N1,
738 TRANSA_DP_LINK_M1,
739 TRANSA_DP_LINK_N1,
740 TRANS_DP_CTL_A,
741 TRANS_HTOTAL_B,
742 TRANS_HBLANK_B,
743 TRANS_HSYNC_B,
744 TRANS_VTOTAL_B,
745 TRANS_VBLANK_B,
746 TRANS_VSYNC_B,
747 TRANS_VSYNCSHIFT_B,
748 TRANSB_DATA_M1,
749 TRANSB_DATA_N1,
750 TRANSB_DP_LINK_M1,
751 TRANSB_DP_LINK_N1,
752 PCH_ADPA,
753 PCH_HDMIB,
754 PCH_HDMIC,
755 PCH_HDMID,
756 PCH_LVDS,
757 TRANS_DP_CTL_B,
758 TRANS_HTOTAL_C,
759 TRANS_HBLANK_C,
760 TRANS_HSYNC_C,
761 TRANS_VTOTAL_C,
762 TRANS_VBLANK_C,
763 TRANS_VSYNC_C,
764 TRANS_VSYNCSHIFT_C,
765 TRANSC_DATA_M1,
766 TRANSC_DATA_N1,
767 TRANSC_DP_LINK_M1,
768 TRANSC_DP_LINK_N1,
769 TRANS_DP_CTL_C,
770 PCH_DP_B,
771 PCH_DP_AUX_CTL_B,
772 PCH_DP_AUX_DATA_B_1,
773 PCH_DP_AUX_DATA_B_2,
774 PCH_DP_AUX_DATA_B_3,
775 PCH_DP_AUX_DATA_B_4,
776 PCH_DP_AUX_DATA_B_5,
777 PCH_DP_C,
778 PCH_DP_AUX_CTL_C,
779 PCH_DP_AUX_DATA_C_1,
780 PCH_DP_AUX_DATA_C_2,
781 PCH_DP_AUX_DATA_C_3,
782 PCH_DP_AUX_DATA_C_4,
783 PCH_DP_AUX_DATA_C_5,
784 PCH_DP_D,
785 PCH_DP_AUX_CTL_D,
786 PCH_DP_AUX_DATA_D_1,
787 PCH_DP_AUX_DATA_D_2,
788 PCH_DP_AUX_DATA_D_3,
789 PCH_DP_AUX_DATA_D_4,
790 PCH_DP_AUX_DATA_D_5,
791 AUD_CONFIG_A,
792 PCH_AUD_VID_DID,
793 AUD_HDMIW_HDMIEDID_A,
794 AUD_CNTL_ST_A,
795 AUD_CNTRL_ST2,
796 AUD_CONFIG_B,
797 AUD_HDMIW_HDMIEDID_B,
798 AUD_CNTL_ST_B,
799 AUD_CONFIG_C,
800 AUD_HDMIW_HDMIEDID_C,
801 AUD_CNTL_ST_C,
802 TRANSACONF,
803 FDI_RXA_CTL,
804 FDI_RX_MISC_A,
805 FDI_RXA_IIR,
806 FDI_RXA_IMR,
807 FDI_RXA_TUSIZE1,
808 QUIRK_F0060,
809 TRANSA_CHICKEN2,
810 TRANSBCONF,
811 FDI_RXB_CTL,
812 FDI_RX_MISC_B,
813 FDI_RXB_IIR,
814 FDI_RXB_IMR,
815 FDI_RXB_TUSIZE1,
816 QUIRK_F1060,
817 TRANSB_CHICKEN2,
818 TRANSCCONF,
819 FDI_RXC_CTL,
820 FDI_RX_MISC_C,
821 FDI_RXC_IIR,
822 FDI_RXC_IMR,
823 FDI_RXC_TUSIZE1,
824 QUIRK_F2060,
825 TRANSC_CHICKEN2,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]826 HIP_INDEX_REG0,
827 HIP_INDEX_REG1,
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]828 LCPLL_CTL,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]829 BXT_P_CR_GT_DISP_PWRON,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]830 GT_MAILBOX,
831 GT_MAILBOX_DATA,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]832 GT_MAILBOX_DATA_1,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]833 PORT_CL_DW5_C,
834 PORT_CL_DW10_C,
835 PORT_COMP_DW0_C,
836 PORT_COMP_DW1_C,
837 PORT_COMP_DW3_C,
838 PORT_COMP_DW8_C,
839 PORT_COMP_DW9_C,
840 PORT_COMP_DW10_C,
841 PORT_PCS_DW1_GRP_C,
842 PORT_TX_DW2_GRP_C,
843 PORT_TX_DW4_GRP_C,
844 PORT_TX_DW5_GRP_C,
845 PORT_TX_DW7_GRP_C,
846 PORT_TX_DW8_GRP_C,
847 PORT_PCS_DW1_LN0_C,
848 PORT_TX_DW2_LN0_C,
849 PORT_TX_DW4_LN0_C,
850 PORT_TX_DW5_LN0_C,
851 PORT_TX_DW7_LN0_C,
852 PORT_TX_DW8_LN0_C,
853 PORT_TX_DW4_LN1_C,
854 PORT_TX_DW4_LN2_C,
855 PORT_TX_DW4_LN3_C,
856 TCSS_DDI_STATUS_1,
857 TCSS_DDI_STATUS_2,
858 TCSS_DDI_STATUS_3,
859 TCSS_DDI_STATUS_4,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]860 BXT_PORT_CL1CM_DW0_A,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]861 PORT_CL_DW5_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]862 BXT_PORT_CL1CM_DW9_A,
863 BXT_PORT_CL1CM_DW10_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]864 BXT_PORT_PLL_EBB_0_A,
865 BXT_PORT_PLL_EBB_4_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]866 BXT_PORT_CL1CM_DW28_A,
867 BXT_PORT_CL1CM_DW30_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]868 BXT_PORT_PLL_0_A,
869 BXT_PORT_PLL_1_A,
870 BXT_PORT_PLL_2_A,
871 BXT_PORT_PLL_3_A,
872 BXT_PORT_PLL_6_A,
873 BXT_PORT_PLL_8_A,
874 BXT_PORT_PLL_9_A,
875 BXT_PORT_PLL_10_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]876 BXT_PORT_REF_DW3_A,
877 BXT_PORT_REF_DW6_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]878 BXT_PORT_REF_DW8_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]879 BXT_PORT_PCS_DW10_01_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]880 BXT_PORT_PCS_DW12_01_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]881 BXT_PORT_TX_DW2_LN0_A,
882 BXT_PORT_TX_DW3_LN0_A,
883 BXT_PORT_TX_DW4_LN0_A,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]884 BXT_PORT_TX_DW14_LN0_A,
885 BXT_PORT_TX_DW14_LN1_A,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]886 PORT_PCS_DW1_GRP_A,
887 PORT_TX_DW2_GRP_A,
888 PORT_TX_DW4_GRP_A,
889 PORT_TX_DW5_GRP_A,
890 PORT_TX_DW7_GRP_A,
891 PORT_TX_DW8_GRP_A,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]892 BXT_PORT_TX_DW14_LN2_A,
893 BXT_PORT_TX_DW14_LN3_A,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]894 PORT_PCS_DW1_LN0_A,
895 PORT_TX_DW2_LN0_A,
896 PORT_TX_DW4_LN0_A,
897 PORT_TX_DW5_LN0_A,
898 PORT_TX_DW7_LN0_A,
899 PORT_TX_DW8_LN0_A,
900 PORT_TX_DW4_LN1_A,
901 PORT_TX_DW4_LN2_A,
902 PORT_TX_DW4_LN3_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]903 BXT_PORT_PCS_DW10_GRP_A,
904 BXT_PORT_PCS_DW12_GRP_A,
905 BXT_PORT_TX_DW2_GRP_A,
906 BXT_PORT_TX_DW3_GRP_A,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]907 BXT_PORT_TX_DW4_GRP_A,
908 PORT_TX_DFLEXPA1_FIA1,
909 PORT_TX_DFLEXDPPMS_FIA1,
910 PORT_TX_DFLEXDPCSSS_FIA1,
911 PORT_TX_DFLEXDPSP_FIA1,
912 PORT_TX_DFLEXDPMLE1_FIA1,
913 DPCLKA_CFGCR0,
914 DPLL_0_CFGCR0,
915 DPLL_0_CFGCR1,
916 DPLL_1_CFGCR0,
917 DPLL_1_CFGCR1,
918 DPLL_4_CFGCR0,
919 DPLL_4_CFGCR1,
920 DPLL_0_SSC,
921 DPLL_1_SSC,
922 DPLL_4_SSC,
923 DKL_PCS_DW5_1,
924 DKL_DP_MODE_1,
925 DKL_CLKTOP2_HSCC_1,
926 DKL_CLKTOP2_CCC1_1,
927 DKL_REFCLKIN_CTL_1,
928 DKL_PLL_DIV0_1,
929 DKL_PLL_DIV1_1,
930 DKL_PLL_SSC_1,
931 DKL_PLL_BIAS_1,
932 DKL_PLL_COLDST_BIAS_1,
933 DKL_TX_DPCNTL0_1,
934 DKL_TX_DPCNTL1_1,
935 DKL_TX_DPCNTL2_1,
936 DKL_CMN_UC_DW_27_1,
937 DKL_TX_PMD_LANE_SUS_1,
938 DKL_PCS_DW5_2,
939 DKL_DP_MODE_2,
940 DKL_CLKTOP2_HSCC_2,
941 DKL_CLKTOP2_CCC1_2,
942 DKL_REFCLKIN_CTL_2,
943 DKL_PLL_DIV0_2,
944 DKL_PLL_DIV1_2,
945 DKL_PLL_SSC_2,
946 DKL_PLL_BIAS_2,
947 DKL_PLL_COLDST_BIAS_2,
948 DKL_TX_DPCNTL0_2,
949 DKL_TX_DPCNTL1_2,
950 DKL_TX_DPCNTL2_2,
951 DKL_CMN_UC_DW_27_2,
952 DKL_TX_PMD_LANE_SUS_2,
953 DKL_PCS_DW5_3,
954 DKL_DP_MODE_3,
955 DKL_CLKTOP2_HSCC_3,
956 DKL_CLKTOP2_CCC1_3,
957 DKL_REFCLKIN_CTL_3,
958 DKL_PLL_DIV0_3,
959 DKL_PLL_DIV1_3,
960 DKL_PLL_SSC_3,
961 DKL_PLL_BIAS_3,
962 DKL_PLL_COLDST_BIAS_3,
963 DKL_TX_DPCNTL0_3,
964 DKL_TX_DPCNTL1_3,
965 DKL_TX_DPCNTL2_3,
966 DKL_CMN_UC_DW_27_3,
967 DKL_TX_PMD_LANE_SUS_3,
968 DKL_PCS_DW5_4,
969 DKL_DP_MODE_4,
970 DKL_CLKTOP2_HSCC_4,
971 DKL_CLKTOP2_CCC1_4,
972 DKL_REFCLKIN_CTL_4,
973 DKL_PLL_DIV0_4,
974 DKL_PLL_DIV1_4,
975 DKL_PLL_SSC_4,
976 DKL_PLL_BIAS_4,
977 DKL_PLL_COLDST_BIAS_4,
978 DKL_TX_DPCNTL0_4,
979 DKL_TX_DPCNTL1_4,
980 DKL_TX_DPCNTL2_4,
981 DKL_CMN_UC_DW_27_4,
982 DKL_TX_PMD_LANE_SUS_4,
983 DKL_DP_MODE_5,
984 DKL_CLKTOP2_HSCC_5,
985 DKL_CLKTOP2_CCC1_5,
986 DKL_REFCLKIN_CTL_5,
987 DKL_PLL_DIV0_5,
988 DKL_PLL_DIV1_5,
989 DKL_PLL_SSC_5,
990 DKL_PLL_BIAS_5,
991 DKL_PLL_COLDST_BIAS_5,
992 DKL_TX_DPCNTL0_5,
993 DKL_TX_DPCNTL1_5,
994 DKL_TX_DPCNTL2_5,
995 DKL_CMN_UC_DW_27_5,
996 DKL_TX_PMD_LANE_SUS_5,
997 DKL_DP_MODE_6,
998 DKL_CLKTOP2_HSCC_6,
999 DKL_CLKTOP2_CCC1_6,
1000 DKL_REFCLKIN_CTL_6,
1001 DKL_PLL_DIV0_6,
1002 DKL_PLL_DIV1_6,
1003 DKL_PLL_SSC_6,
1004 DKL_PLL_BIAS_6,
1005 DKL_PLL_COLDST_BIAS_6,
1006 DKL_TX_DPCNTL0_6,
1007 DKL_TX_DPCNTL1_6,
1008 DKL_TX_DPCNTL2_6,
1009 DKL_CMN_UC_DW_27_6,
1010 DKL_TX_PMD_LANE_SUS_6,
1011 PORT_TX_DFLEXPA1_FIA2,
1012 PORT_TX_DFLEXDPPMS_FIA2,
1013 PORT_TX_DFLEXDPCSSS_FIA2,
1014 PORT_TX_DFLEXDPSP_FIA2,
1015 PORT_TX_DFLEXDPMLE1_FIA2,
1016 PORT_TX_DFLEXPA1_FIA3,
1017 PORT_TX_DFLEXDPPMS_FIA3,
1018 PORT_TX_DFLEXDPCSSS_FIA3,
1019 PORT_TX_DFLEXDPSP_FIA3,
1020 PORT_TX_DFLEXDPMLE1_FIA3);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1021 pragma Warnings
1022 (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)",
1023 Reason => "TODO: Should it matter?");
1024 pragma Keep_Names (Registers_Invalid_Index);
1025 pragma Warnings
1026 (GNATprove, On, "pragma ""KEEP_NAMES"" ignored *(not yet supported)");
1027
1028 Register_Width : constant := 4;
1029
1030 for Registers_Invalid_Index use
1031 (Invalid_Register => 0,
1032
1033 ---------------------------------------------------------------------------
1034 -- Pipe A registers
1035 ---------------------------------------------------------------------------
1036
1037 -- pipe timing registers
1038
1039 HTOTAL_A => 16#06_0000# / Register_Width,
1040 HBLANK_A => 16#06_0004# / Register_Width,
1041 HSYNC_A => 16#06_0008# / Register_Width,
1042 VTOTAL_A => 16#06_000c# / Register_Width,
1043 VBLANK_A => 16#06_0010# / Register_Width,
1044 VSYNC_A => 16#06_0014# / Register_Width,
1045 PIPEASRC => 16#06_001c# / Register_Width,
1046 PIPEACONF => 16#07_0008# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1047 PIPEA_ARB_CTL => 16#07_0028# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1048 PIPEAMISC => 16#07_0030# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1049 PIPEA_CHICKEN => 16#07_0038# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1050 TRANS_HTOTAL_A => 16#0e_0000# / Register_Width,
1051 TRANS_HBLANK_A => 16#0e_0004# / Register_Width,
1052 TRANS_HSYNC_A => 16#0e_0008# / Register_Width,
1053 TRANS_VTOTAL_A => 16#0e_000c# / Register_Width,
1054 TRANS_VBLANK_A => 16#0e_0010# / Register_Width,
1055 TRANS_VSYNC_A => 16#0e_0014# / Register_Width,
1056 TRANSA_DATA_M1 => 16#0e_0030# / Register_Width,
1057 TRANSA_DATA_N1 => 16#0e_0034# / Register_Width,
1058 TRANSA_DP_LINK_M1 => 16#0e_0040# / Register_Width,
1059 TRANSA_DP_LINK_N1 => 16#0e_0044# / Register_Width,
1060 PIPEA_DATA_M1 => 16#06_0030# / Register_Width,
1061 PIPEA_DATA_N1 => 16#06_0034# / Register_Width,
1062 PIPEA_LINK_M1 => 16#06_0040# / Register_Width,
1063 PIPEA_LINK_N1 => 16#06_0044# / Register_Width,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]1064 PIPEA_GMCH_DATA_M => 16#07_0050# / Register_Width,
1065 PIPEA_GMCH_DATA_N => 16#07_0054# / Register_Width,
1066 PIPEA_GMCH_LINK_M => 16#07_0060# / Register_Width,
1067 PIPEA_GMCH_LINK_N => 16#07_0064# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1068 PIPEA_DDI_FUNC_CTL => 16#06_0400# / Register_Width,
1069 PIPEA_MSA_MISC => 16#06_0410# / Register_Width,
1070
1071 -- PCH sideband interface registers
1072 SBI_ADDR => 16#0c_6000# / Register_Width,
1073 SBI_DATA => 16#0c_6004# / Register_Width,
1074 SBI_CTL_STAT => 16#0c_6008# / Register_Width,
1075
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1076 -- GMCH clock registers
1077 GMCH_DPLL_A => 16#00_6014# / Register_Width,
1078 GMCH_FPA0 => 16#00_6040# / Register_Width,
1079 GMCH_FPA1 => 16#00_6044# / Register_Width,
1080
1081 -- PCH clock registers
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1082 PCH_DPLL_A => 16#0c_6014# / Register_Width,
1083 PCH_PIXCLK_GATE => 16#0c_6020# / Register_Width,
1084 PCH_FPA0 => 16#0c_6040# / Register_Width,
1085 PCH_FPA1 => 16#0c_6044# / Register_Width,
1086
1087 -- panel fitter
1088 PFA_CTL_1 => 16#06_8080# / Register_Width,
1089 PFA_WIN_POS => 16#06_8070# / Register_Width,
1090 PFA_WIN_SZ => 16#06_8074# / Register_Width,
1091 PS_WIN_POS_1_A => 16#06_8170# / Register_Width,
1092 PS_WIN_SZ_1_A => 16#06_8174# / Register_Width,
1093 PS_CTRL_1_A => 16#06_8180# / Register_Width,
1094 PS_WIN_POS_2_A => 16#06_8270# / Register_Width,
1095 PS_WIN_SZ_2_A => 16#06_8274# / Register_Width,
1096 PS_CTRL_2_A => 16#06_8280# / Register_Width,
1097
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1098 -- cursor control
1099 CUR_CTL_A => 16#07_0080# / Register_Width,
1100 CUR_BASE_A => 16#07_0084# / Register_Width,
1101 CUR_POS_A => 16#07_0088# / Register_Width,
1102 CUR_FBC_CTL_A => 16#07_00a0# / Register_Width,
1103
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1104 -- display control
1105 DSPACNTR => 16#07_0180# / Register_Width,
1106 DSPALINOFF => 16#07_0184# / Register_Width,
1107 DSPASTRIDE => 16#07_0188# / Register_Width,
1108 PLANE_POS_1_A => 16#07_018c# / Register_Width,
1109 PLANE_SIZE_1_A => 16#07_0190# / Register_Width,
1110 DSPASURF => 16#07_019c# / Register_Width,
1111 DSPATILEOFF => 16#07_01a4# / Register_Width,
1112
1113 -- sprite control
1114 SPACNTR => 16#07_0280# / Register_Width,
1115
1116 -- FDI and PCH transcoder control
1117 FDI_TX_CTL_A => 16#06_0100# / Register_Width,
1118 FDI_RXA_CTL => 16#0f_000c# / Register_Width,
1119 FDI_RX_MISC_A => 16#0f_0010# / Register_Width,
1120 FDI_RXA_IIR => 16#0f_0014# / Register_Width,
1121 FDI_RXA_IMR => 16#0f_0018# / Register_Width,
1122 FDI_RXA_TUSIZE1 => 16#0f_0030# / Register_Width,
1123 TRANSACONF => 16#0f_0008# / Register_Width,
1124 TRANSA_CHICKEN2 => 16#0f_0064# / Register_Width,
1125
1126 -- watermark registers
1127 WM_LINETIME_A => 16#04_5270# / Register_Width,
1128 PLANE_WM_1_A_0 => 16#07_0240# / Register_Width,
1129 PLANE_WM_1_A_1 => 16#07_0244# / Register_Width,
1130 PLANE_WM_1_A_2 => 16#07_0248# / Register_Width,
1131 PLANE_WM_1_A_3 => 16#07_024c# / Register_Width,
1132 PLANE_WM_1_A_4 => 16#07_0250# / Register_Width,
1133 PLANE_WM_1_A_5 => 16#07_0254# / Register_Width,
1134 PLANE_WM_1_A_6 => 16#07_0258# / Register_Width,
1135 PLANE_WM_1_A_7 => 16#07_025c# / Register_Width,
1136 PLANE_BUF_CFG_1_A => 16#07_027c# / Register_Width,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1137 CUR_WM_A_0 => 16#07_0140# / Register_Width,
1138 CUR_WM_A_1 => 16#07_0144# / Register_Width,
1139 CUR_WM_A_2 => 16#07_0148# / Register_Width,
1140 CUR_WM_A_3 => 16#07_014c# / Register_Width,
1141 CUR_WM_A_4 => 16#07_0150# / Register_Width,
1142 CUR_WM_A_5 => 16#07_0154# / Register_Width,
1143 CUR_WM_A_6 => 16#07_0158# / Register_Width,
1144 CUR_WM_A_7 => 16#07_015c# / Register_Width,
1145 CUR_BUF_CFG_A => 16#07_017c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1146
1147 -- CPU transcoder clock select
1148 TRANSA_CLK_SEL => 16#04_6140# / Register_Width,
1149
1150 ---------------------------------------------------------------------------
1151 -- Pipe B registers
1152 ---------------------------------------------------------------------------
1153
1154 -- pipe timing registers
1155
1156 HTOTAL_B => 16#06_1000# / Register_Width,
1157 HBLANK_B => 16#06_1004# / Register_Width,
1158 HSYNC_B => 16#06_1008# / Register_Width,
1159 VTOTAL_B => 16#06_100c# / Register_Width,
1160 VBLANK_B => 16#06_1010# / Register_Width,
1161 VSYNC_B => 16#06_1014# / Register_Width,
1162 PIPEBSRC => 16#06_101c# / Register_Width,
1163 PIPEBCONF => 16#07_1008# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1164 PIPEB_ARB_CTL => 16#07_1028# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1165 PIPEBMISC => 16#07_1030# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1166 PIPEB_CHICKEN => 16#07_1038# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1167 TRANS_HTOTAL_B => 16#0e_1000# / Register_Width,
1168 TRANS_HBLANK_B => 16#0e_1004# / Register_Width,
1169 TRANS_HSYNC_B => 16#0e_1008# / Register_Width,
1170 TRANS_VTOTAL_B => 16#0e_100c# / Register_Width,
1171 TRANS_VBLANK_B => 16#0e_1010# / Register_Width,
1172 TRANS_VSYNC_B => 16#0e_1014# / Register_Width,
1173 TRANSB_DATA_M1 => 16#0e_1030# / Register_Width,
1174 TRANSB_DATA_N1 => 16#0e_1034# / Register_Width,
1175 TRANSB_DP_LINK_M1 => 16#0e_1040# / Register_Width,
1176 TRANSB_DP_LINK_N1 => 16#0e_1044# / Register_Width,
1177 PIPEB_DATA_M1 => 16#06_1030# / Register_Width,
1178 PIPEB_DATA_N1 => 16#06_1034# / Register_Width,
1179 PIPEB_LINK_M1 => 16#06_1040# / Register_Width,
1180 PIPEB_LINK_N1 => 16#06_1044# / Register_Width,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]1181 PIPEB_GMCH_DATA_M => 16#07_1050# / Register_Width,
1182 PIPEB_GMCH_DATA_N => 16#07_1054# / Register_Width,
1183 PIPEB_GMCH_LINK_M => 16#07_1060# / Register_Width,
1184 PIPEB_GMCH_LINK_N => 16#07_1064# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1185 PIPEB_DDI_FUNC_CTL => 16#06_1400# / Register_Width,
1186 PIPEB_MSA_MISC => 16#06_1410# / Register_Width,
1187
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1188 -- GMCH clock registers
1189 GMCH_DPLL_B => 16#00_6018# / Register_Width,
1190 GMCH_FPB0 => 16#00_6048# / Register_Width,
1191 GMCH_FPB1 => 16#00_604c# / Register_Width,
1192
1193 -- PCH clock registers
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1194 PCH_DPLL_B => 16#0c_6018# / Register_Width,
1195 PCH_FPB0 => 16#0c_6048# / Register_Width,
1196 PCH_FPB1 => 16#0c_604c# / Register_Width,
1197
1198 -- panel fitter
1199 PFB_CTL_1 => 16#06_8880# / Register_Width,
1200 PFB_WIN_POS => 16#06_8870# / Register_Width,
1201 PFB_WIN_SZ => 16#06_8874# / Register_Width,
1202 PS_WIN_POS_1_B => 16#06_8970# / Register_Width,
1203 PS_WIN_SZ_1_B => 16#06_8974# / Register_Width,
1204 PS_CTRL_1_B => 16#06_8980# / Register_Width,
1205 PS_WIN_POS_2_B => 16#06_8a70# / Register_Width,
1206 PS_WIN_SZ_2_B => 16#06_8a74# / Register_Width,
1207 PS_CTRL_2_B => 16#06_8a80# / Register_Width,
1208
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1209 -- cursor control
Nico Huber75a707f2018-06-18 16:28:33 +0200[diff] [blame]1210 CURBCNTR => 16#07_00c0# / Register_Width, -- <= SNB
1211 CURBBASE => 16#07_00c4# / Register_Width, -- <= SNB
1212 CURBPOS => 16#07_00c8# / Register_Width, -- <= SNB
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1213 CUR_CTL_B => 16#07_1080# / Register_Width,
1214 CUR_BASE_B => 16#07_1084# / Register_Width,
1215 CUR_POS_B => 16#07_1088# / Register_Width,
1216 CUR_FBC_CTL_B => 16#07_10a0# / Register_Width,
1217
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1218 -- display control
1219 DSPBCNTR => 16#07_1180# / Register_Width,
1220 DSPBLINOFF => 16#07_1184# / Register_Width,
1221 DSPBSTRIDE => 16#07_1188# / Register_Width,
1222 PLANE_POS_1_B => 16#07_118c# / Register_Width,
1223 PLANE_SIZE_1_B => 16#07_1190# / Register_Width,
1224 DSPBSURF => 16#07_119c# / Register_Width,
1225 DSPBTILEOFF => 16#07_11a4# / Register_Width,
1226
1227 -- sprite control
1228 SPBCNTR => 16#07_1280# / Register_Width,
1229
1230 -- FDI and PCH transcoder control
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1231 FDI_TX_CTL_B => 16#06_1100# / Register_Width, -- aliased by GMCH_ADPA
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1232 FDI_RXB_CTL => 16#0f_100c# / Register_Width,
1233 FDI_RX_MISC_B => 16#0f_1010# / Register_Width,
1234 FDI_RXB_IIR => 16#0f_1014# / Register_Width,
1235 FDI_RXB_IMR => 16#0f_1018# / Register_Width,
1236 FDI_RXB_TUSIZE1 => 16#0f_1030# / Register_Width,
1237 TRANSBCONF => 16#0f_1008# / Register_Width,
1238 TRANSB_CHICKEN2 => 16#0f_1064# / Register_Width,
1239
1240 -- watermark registers
1241 WM_LINETIME_B => 16#04_5274# / Register_Width,
1242 PLANE_WM_1_B_0 => 16#07_1240# / Register_Width,
1243 PLANE_WM_1_B_1 => 16#07_1244# / Register_Width,
1244 PLANE_WM_1_B_2 => 16#07_1248# / Register_Width,
1245 PLANE_WM_1_B_3 => 16#07_124c# / Register_Width,
1246 PLANE_WM_1_B_4 => 16#07_1250# / Register_Width,
1247 PLANE_WM_1_B_5 => 16#07_1254# / Register_Width,
1248 PLANE_WM_1_B_6 => 16#07_1258# / Register_Width,
1249 PLANE_WM_1_B_7 => 16#07_125c# / Register_Width,
1250 PLANE_BUF_CFG_1_B => 16#07_127c# / Register_Width,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1251 CUR_WM_B_0 => 16#07_1140# / Register_Width,
1252 CUR_WM_B_1 => 16#07_1144# / Register_Width,
1253 CUR_WM_B_2 => 16#07_1148# / Register_Width,
1254 CUR_WM_B_3 => 16#07_114c# / Register_Width,
1255 CUR_WM_B_4 => 16#07_1150# / Register_Width,
1256 CUR_WM_B_5 => 16#07_1154# / Register_Width,
1257 CUR_WM_B_6 => 16#07_1158# / Register_Width,
1258 CUR_WM_B_7 => 16#07_115c# / Register_Width,
1259 CUR_BUF_CFG_B => 16#07_117c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1260
1261 -- CPU transcoder clock select
1262 TRANSB_CLK_SEL => 16#04_6144# / Register_Width,
1263
1264 ---------------------------------------------------------------------------
1265 -- Pipe C registers
1266 ---------------------------------------------------------------------------
1267
1268 -- pipe timing registers
1269
1270 HTOTAL_C => 16#06_2000# / Register_Width,
1271 HBLANK_C => 16#06_2004# / Register_Width,
1272 HSYNC_C => 16#06_2008# / Register_Width,
1273 VTOTAL_C => 16#06_200c# / Register_Width,
1274 VBLANK_C => 16#06_2010# / Register_Width,
1275 VSYNC_C => 16#06_2014# / Register_Width,
1276 PIPECSRC => 16#06_201c# / Register_Width,
1277 PIPECCONF => 16#07_2008# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1278 PIPEC_ARB_CTL => 16#07_2028# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1279 PIPECMISC => 16#07_2030# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1280 PIPEC_CHICKEN => 16#07_2038# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1281 TRANS_HTOTAL_C => 16#0e_2000# / Register_Width,
1282 TRANS_HBLANK_C => 16#0e_2004# / Register_Width,
1283 TRANS_HSYNC_C => 16#0e_2008# / Register_Width,
1284 TRANS_VTOTAL_C => 16#0e_200c# / Register_Width,
1285 TRANS_VBLANK_C => 16#0e_2010# / Register_Width,
1286 TRANS_VSYNC_C => 16#0e_2014# / Register_Width,
1287 TRANSC_DATA_M1 => 16#0e_2030# / Register_Width,
1288 TRANSC_DATA_N1 => 16#0e_2034# / Register_Width,
1289 TRANSC_DP_LINK_M1 => 16#0e_2040# / Register_Width,
1290 TRANSC_DP_LINK_N1 => 16#0e_2044# / Register_Width,
1291 PIPEC_DATA_M1 => 16#06_2030# / Register_Width,
1292 PIPEC_DATA_N1 => 16#06_2034# / Register_Width,
1293 PIPEC_LINK_M1 => 16#06_2040# / Register_Width,
1294 PIPEC_LINK_N1 => 16#06_2044# / Register_Width,
1295 PIPEC_DDI_FUNC_CTL => 16#06_2400# / Register_Width,
1296 PIPEC_MSA_MISC => 16#06_2410# / Register_Width,
1297
1298 -- panel fitter
1299 PFC_CTL_1 => 16#06_9080# / Register_Width,
1300 PFC_WIN_POS => 16#06_9070# / Register_Width,
1301 PFC_WIN_SZ => 16#06_9074# / Register_Width,
1302 PS_WIN_POS_1_C => 16#06_9170# / Register_Width,
1303 PS_WIN_SZ_1_C => 16#06_9174# / Register_Width,
1304 PS_CTRL_1_C => 16#06_9180# / Register_Width,
1305
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1306 -- cursor control
1307 CUR_CTL_C => 16#07_2080# / Register_Width,
1308 CUR_BASE_C => 16#07_2084# / Register_Width,
1309 CUR_POS_C => 16#07_2088# / Register_Width,
1310 CUR_FBC_CTL_C => 16#07_20a0# / Register_Width,
1311
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1312 -- display control
1313 DSPCCNTR => 16#07_2180# / Register_Width,
1314 DSPCLINOFF => 16#07_2184# / Register_Width,
1315 DSPCSTRIDE => 16#07_2188# / Register_Width,
1316 PLANE_POS_1_C => 16#07_218c# / Register_Width,
1317 PLANE_SIZE_1_C => 16#07_2190# / Register_Width,
1318 DSPCSURF => 16#07_219c# / Register_Width,
1319 DSPCTILEOFF => 16#07_21a4# / Register_Width,
1320
1321 -- sprite control
1322 SPCCNTR => 16#07_2280# / Register_Width,
1323
1324 -- PCH transcoder control
1325 FDI_TX_CTL_C => 16#06_2100# / Register_Width,
1326 FDI_RXC_CTL => 16#0f_200c# / Register_Width,
1327 FDI_RX_MISC_C => 16#0f_2010# / Register_Width,
1328 FDI_RXC_IIR => 16#0f_2014# / Register_Width,
1329 FDI_RXC_IMR => 16#0f_2018# / Register_Width,
1330 FDI_RXC_TUSIZE1 => 16#0f_2030# / Register_Width,
1331 TRANSCCONF => 16#0f_2008# / Register_Width,
1332 TRANSC_CHICKEN2 => 16#0f_2064# / Register_Width,
1333
1334 -- watermark registers
1335 WM_LINETIME_C => 16#04_5278# / Register_Width,
1336 PLANE_WM_1_C_0 => 16#07_2240# / Register_Width,
1337 PLANE_WM_1_C_1 => 16#07_2244# / Register_Width,
1338 PLANE_WM_1_C_2 => 16#07_2248# / Register_Width,
1339 PLANE_WM_1_C_3 => 16#07_224c# / Register_Width,
1340 PLANE_WM_1_C_4 => 16#07_2250# / Register_Width,
1341 PLANE_WM_1_C_5 => 16#07_2254# / Register_Width,
1342 PLANE_WM_1_C_6 => 16#07_2258# / Register_Width,
1343 PLANE_WM_1_C_7 => 16#07_225c# / Register_Width,
1344 PLANE_BUF_CFG_1_C => 16#07_227c# / Register_Width,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1345 CUR_WM_C_0 => 16#07_2140# / Register_Width,
1346 CUR_WM_C_1 => 16#07_2144# / Register_Width,
1347 CUR_WM_C_2 => 16#07_2148# / Register_Width,
1348 CUR_WM_C_3 => 16#07_214c# / Register_Width,
1349 CUR_WM_C_4 => 16#07_2150# / Register_Width,
1350 CUR_WM_C_5 => 16#07_2154# / Register_Width,
1351 CUR_WM_C_6 => 16#07_2158# / Register_Width,
1352 CUR_WM_C_7 => 16#07_215c# / Register_Width,
1353 CUR_BUF_CFG_C => 16#07_217c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1354
1355 -- CPU transcoder clock select
1356 TRANSC_CLK_SEL => 16#04_6148# / Register_Width,
1357
1358 ---------------------------------------------------------------------------
1359 -- Pipe EDP registers
1360 ---------------------------------------------------------------------------
1361
1362 -- pipe timing registers
1363
1364 HTOTAL_EDP => 16#06_f000# / Register_Width,
1365 HBLANK_EDP => 16#06_f004# / Register_Width,
1366 HSYNC_EDP => 16#06_f008# / Register_Width,
1367 VTOTAL_EDP => 16#06_f00c# / Register_Width,
1368 VBLANK_EDP => 16#06_f010# / Register_Width,
1369 VSYNC_EDP => 16#06_f014# / Register_Width,
1370 PIPE_EDP_CONF => 16#07_f008# / Register_Width,
1371 PIPE_EDP_DATA_M1 => 16#06_f030# / Register_Width,
1372 PIPE_EDP_DATA_N1 => 16#06_f034# / Register_Width,
1373 PIPE_EDP_LINK_M1 => 16#06_f040# / Register_Width,
1374 PIPE_EDP_LINK_N1 => 16#06_f044# / Register_Width,
1375 PIPE_EDP_DDI_FUNC_CTL => 16#06_f400# / Register_Width,
1376 PIPE_EDP_MSA_MISC => 16#06_f410# / Register_Width,
1377
1378 -- PSR registers
1379 SRD_CTL => 16#06_4800# / Register_Width,
1380 SRD_CTL_A => 16#06_0800# / Register_Width,
1381 SRD_CTL_B => 16#06_1800# / Register_Width,
1382 SRD_CTL_C => 16#06_2800# / Register_Width,
1383 SRD_CTL_EDP => 16#06_f800# / Register_Width,
1384 SRD_STATUS => 16#06_4840# / Register_Width,
1385 SRD_STATUS_A => 16#06_0840# / Register_Width,
1386 SRD_STATUS_B => 16#06_1840# / Register_Width,
1387 SRD_STATUS_C => 16#06_2840# / Register_Width,
1388 SRD_STATUS_EDP => 16#06_f840# / Register_Width,
1389
1390 -- DDI registers
1391 DDI_BUF_CTL_A => 16#06_4000# / Register_Width, -- aliased by DP_CTL_A
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1392 DDI_BUF_TRANS_A_S0T1 => 16#06_4e00# / Register_Width,
1393 DDI_BUF_TRANS_A_S0T2 => 16#06_4e04# / Register_Width,
1394 DDI_BUF_TRANS_A_S1T1 => 16#06_4e08# / Register_Width,
1395 DDI_BUF_TRANS_A_S1T2 => 16#06_4e0c# / Register_Width,
1396 DDI_BUF_TRANS_A_S2T1 => 16#06_4e10# / Register_Width,
1397 DDI_BUF_TRANS_A_S2T2 => 16#06_4e14# / Register_Width,
1398 DDI_BUF_TRANS_A_S3T1 => 16#06_4e18# / Register_Width,
1399 DDI_BUF_TRANS_A_S3T2 => 16#06_4e1c# / Register_Width,
1400 DDI_BUF_TRANS_A_S4T1 => 16#06_4e20# / Register_Width,
1401 DDI_BUF_TRANS_A_S4T2 => 16#06_4e24# / Register_Width,
1402 DDI_BUF_TRANS_A_S5T1 => 16#06_4e28# / Register_Width,
1403 DDI_BUF_TRANS_A_S5T2 => 16#06_4e2c# / Register_Width,
1404 DDI_BUF_TRANS_A_S6T1 => 16#06_4e30# / Register_Width,
1405 DDI_BUF_TRANS_A_S6T2 => 16#06_4e34# / Register_Width,
1406 DDI_BUF_TRANS_A_S7T1 => 16#06_4e38# / Register_Width,
1407 DDI_BUF_TRANS_A_S7T2 => 16#06_4e3c# / Register_Width,
1408 DDI_BUF_TRANS_A_S8T1 => 16#06_4e40# / Register_Width,
1409 DDI_BUF_TRANS_A_S8T2 => 16#06_4e44# / Register_Width,
1410 DDI_BUF_TRANS_A_S9T1 => 16#06_4e48# / Register_Width,
1411 DDI_BUF_TRANS_A_S9T2 => 16#06_4e4c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1412 DDI_AUX_CTL_A => 16#06_4010# / Register_Width, -- aliased by DP_AUX_CTL_A
1413 DDI_AUX_DATA_A_1 => 16#06_4014# / Register_Width, -- aliased by DP_AUX_DATA_A_1
1414 DDI_AUX_DATA_A_2 => 16#06_4018# / Register_Width, -- aliased by DP_AUX_DATA_A_2
1415 DDI_AUX_DATA_A_3 => 16#06_401c# / Register_Width, -- aliased by DP_AUX_DATA_A_3
1416 DDI_AUX_DATA_A_4 => 16#06_4020# / Register_Width, -- aliased by DP_AUX_DATA_A_4
1417 DDI_AUX_DATA_A_5 => 16#06_4024# / Register_Width, -- aliased by DP_AUX_DATA_A_5
1418 DDI_AUX_MUTEX_A => 16#06_402c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1419
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1420 DDI_BUF_CTL_B => 16#06_4100# / Register_Width, -- aliased by GMCH_DP_B
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1421 DDI_BUF_TRANS_B_S0T1 => 16#06_4e60# / Register_Width,
1422 DDI_BUF_TRANS_B_S0T2 => 16#06_4e64# / Register_Width,
1423 DDI_BUF_TRANS_B_S1T1 => 16#06_4e68# / Register_Width,
1424 DDI_BUF_TRANS_B_S1T2 => 16#06_4e6c# / Register_Width,
1425 DDI_BUF_TRANS_B_S2T1 => 16#06_4e70# / Register_Width,
1426 DDI_BUF_TRANS_B_S2T2 => 16#06_4e74# / Register_Width,
1427 DDI_BUF_TRANS_B_S3T1 => 16#06_4e78# / Register_Width,
1428 DDI_BUF_TRANS_B_S3T2 => 16#06_4e7c# / Register_Width,
1429 DDI_BUF_TRANS_B_S4T1 => 16#06_4e80# / Register_Width,
1430 DDI_BUF_TRANS_B_S4T2 => 16#06_4e84# / Register_Width,
1431 DDI_BUF_TRANS_B_S5T1 => 16#06_4e88# / Register_Width,
1432 DDI_BUF_TRANS_B_S5T2 => 16#06_4e8c# / Register_Width,
1433 DDI_BUF_TRANS_B_S6T1 => 16#06_4e90# / Register_Width,
1434 DDI_BUF_TRANS_B_S6T2 => 16#06_4e94# / Register_Width,
1435 DDI_BUF_TRANS_B_S7T1 => 16#06_4e98# / Register_Width,
1436 DDI_BUF_TRANS_B_S7T2 => 16#06_4e9c# / Register_Width,
1437 DDI_BUF_TRANS_B_S8T1 => 16#06_4ea0# / Register_Width,
1438 DDI_BUF_TRANS_B_S8T2 => 16#06_4ea4# / Register_Width,
1439 DDI_BUF_TRANS_B_S9T1 => 16#06_4ea8# / Register_Width,
1440 DDI_BUF_TRANS_B_S9T2 => 16#06_4eac# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1441 DDI_AUX_CTL_B => 16#06_4110# / Register_Width,
1442 DDI_AUX_DATA_B_1 => 16#06_4114# / Register_Width,
1443 DDI_AUX_DATA_B_2 => 16#06_4118# / Register_Width,
1444 DDI_AUX_DATA_B_3 => 16#06_411c# / Register_Width,
1445 DDI_AUX_DATA_B_4 => 16#06_4120# / Register_Width,
1446 DDI_AUX_DATA_B_5 => 16#06_4124# / Register_Width,
1447 DDI_AUX_MUTEX_B => 16#06_412c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1448
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1449 DDI_BUF_CTL_C => 16#06_4200# / Register_Width, -- aliased by GMCH_DP_C
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1450 DDI_BUF_TRANS_C_S0T1 => 16#06_4ec0# / Register_Width,
1451 DDI_BUF_TRANS_C_S0T2 => 16#06_4ec4# / Register_Width,
1452 DDI_BUF_TRANS_C_S1T1 => 16#06_4ec8# / Register_Width,
1453 DDI_BUF_TRANS_C_S1T2 => 16#06_4ecc# / Register_Width,
1454 DDI_BUF_TRANS_C_S2T1 => 16#06_4ed0# / Register_Width,
1455 DDI_BUF_TRANS_C_S2T2 => 16#06_4ed4# / Register_Width,
1456 DDI_BUF_TRANS_C_S3T1 => 16#06_4ed8# / Register_Width,
1457 DDI_BUF_TRANS_C_S3T2 => 16#06_4edc# / Register_Width,
1458 DDI_BUF_TRANS_C_S4T1 => 16#06_4ee0# / Register_Width,
1459 DDI_BUF_TRANS_C_S4T2 => 16#06_4ee4# / Register_Width,
1460 DDI_BUF_TRANS_C_S5T1 => 16#06_4ee8# / Register_Width,
1461 DDI_BUF_TRANS_C_S5T2 => 16#06_4eec# / Register_Width,
1462 DDI_BUF_TRANS_C_S6T1 => 16#06_4ef0# / Register_Width,
1463 DDI_BUF_TRANS_C_S6T2 => 16#06_4ef4# / Register_Width,
1464 DDI_BUF_TRANS_C_S7T1 => 16#06_4ef8# / Register_Width,
1465 DDI_BUF_TRANS_C_S7T2 => 16#06_4efc# / Register_Width,
1466 DDI_BUF_TRANS_C_S8T1 => 16#06_4f00# / Register_Width,
1467 DDI_BUF_TRANS_C_S8T2 => 16#06_4f04# / Register_Width,
1468 DDI_BUF_TRANS_C_S9T1 => 16#06_4f08# / Register_Width,
1469 DDI_BUF_TRANS_C_S9T2 => 16#06_4f0c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1470 DDI_AUX_CTL_C => 16#06_4210# / Register_Width,
1471 DDI_AUX_DATA_C_1 => 16#06_4214# / Register_Width,
1472 DDI_AUX_DATA_C_2 => 16#06_4218# / Register_Width,
1473 DDI_AUX_DATA_C_3 => 16#06_421c# / Register_Width,
1474 DDI_AUX_DATA_C_4 => 16#06_4220# / Register_Width,
1475 DDI_AUX_DATA_C_5 => 16#06_4224# / Register_Width,
1476 DDI_AUX_MUTEX_C => 16#06_422c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1477
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1478 DDI_BUF_CTL_D => 16#06_4300# / Register_Width, -- aliased by GMCH_DP_D
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1479 DDI_BUF_TRANS_D_S0T1 => 16#06_4f20# / Register_Width,
1480 DDI_BUF_TRANS_D_S0T2 => 16#06_4f24# / Register_Width,
1481 DDI_BUF_TRANS_D_S1T1 => 16#06_4f28# / Register_Width,
1482 DDI_BUF_TRANS_D_S1T2 => 16#06_4f2c# / Register_Width,
1483 DDI_BUF_TRANS_D_S2T1 => 16#06_4f30# / Register_Width,
1484 DDI_BUF_TRANS_D_S2T2 => 16#06_4f34# / Register_Width,
1485 DDI_BUF_TRANS_D_S3T1 => 16#06_4f38# / Register_Width,
1486 DDI_BUF_TRANS_D_S3T2 => 16#06_4f3c# / Register_Width,
1487 DDI_BUF_TRANS_D_S4T1 => 16#06_4f40# / Register_Width,
1488 DDI_BUF_TRANS_D_S4T2 => 16#06_4f44# / Register_Width,
1489 DDI_BUF_TRANS_D_S5T1 => 16#06_4f48# / Register_Width,
1490 DDI_BUF_TRANS_D_S5T2 => 16#06_4f4c# / Register_Width,
1491 DDI_BUF_TRANS_D_S6T1 => 16#06_4f50# / Register_Width,
1492 DDI_BUF_TRANS_D_S6T2 => 16#06_4f54# / Register_Width,
1493 DDI_BUF_TRANS_D_S7T1 => 16#06_4f58# / Register_Width,
1494 DDI_BUF_TRANS_D_S7T2 => 16#06_4f5c# / Register_Width,
1495 DDI_BUF_TRANS_D_S8T1 => 16#06_4f60# / Register_Width,
1496 DDI_BUF_TRANS_D_S8T2 => 16#06_4f64# / Register_Width,
1497 DDI_BUF_TRANS_D_S9T1 => 16#06_4f68# / Register_Width,
1498 DDI_BUF_TRANS_D_S9T2 => 16#06_4f6c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1499 DDI_AUX_CTL_D => 16#06_4310# / Register_Width,
1500 DDI_AUX_DATA_D_1 => 16#06_4314# / Register_Width,
1501 DDI_AUX_DATA_D_2 => 16#06_4318# / Register_Width,
1502 DDI_AUX_DATA_D_3 => 16#06_431c# / Register_Width,
1503 DDI_AUX_DATA_D_4 => 16#06_4320# / Register_Width,
1504 DDI_AUX_DATA_D_5 => 16#06_4324# / Register_Width,
1505 DDI_AUX_MUTEX_D => 16#06_432c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1506
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1507 -- USB-C AUX control and data
1508 DDI_AUX_CTL_USBC2 => 16#06_4410# / Register_Width,
1509 DDI_AUX_DATA_USBC2_1 => 16#06_4414# / Register_Width,
1510 DDI_AUX_DATA_USBC2_2 => 16#06_4418# / Register_Width,
1511 DDI_AUX_DATA_USBC2_3 => 16#06_441c# / Register_Width,
1512 DDI_AUX_DATA_USBC2_4 => 16#06_4420# / Register_Width,
1513 DDI_AUX_DATA_USBC2_5 => 16#06_4424# / Register_Width,
1514 DDI_AUX_CTL_USBC3 => 16#06_4510# / Register_Width,
1515 DDI_AUX_DATA_USBC3_1 => 16#06_4514# / Register_Width,
1516 DDI_AUX_DATA_USBC3_2 => 16#06_4518# / Register_Width,
1517 DDI_AUX_DATA_USBC3_3 => 16#06_451c# / Register_Width,
1518 DDI_AUX_DATA_USBC3_4 => 16#06_4520# / Register_Width,
1519 DDI_AUX_DATA_USBC3_5 => 16#06_4524# / Register_Width,
1520 DDI_AUX_CTL_USBC4 => 16#06_4610# / Register_Width,
1521 DDI_AUX_DATA_USBC4_1 => 16#06_4614# / Register_Width,
1522 DDI_AUX_DATA_USBC4_2 => 16#06_4618# / Register_Width,
1523 DDI_AUX_DATA_USBC4_3 => 16#06_461c# / Register_Width,
1524 DDI_AUX_DATA_USBC4_4 => 16#06_4620# / Register_Width,
1525 DDI_AUX_DATA_USBC4_5 => 16#06_4624# / Register_Width,
1526 DDI_AUX_CTL_USBC5 => 16#06_4710# / Register_Width,
1527 DDI_AUX_DATA_USBC5_1 => 16#06_4714# / Register_Width,
1528 DDI_AUX_DATA_USBC5_2 => 16#06_4718# / Register_Width,
1529 DDI_AUX_DATA_USBC5_3 => 16#06_471c# / Register_Width,
1530 DDI_AUX_DATA_USBC5_4 => 16#06_4720# / Register_Width,
1531 DDI_AUX_DATA_USBC5_5 => 16#06_4724# / Register_Width,
1532 DDI_AUX_CTL_USBC6 => 16#06_4810# / Register_Width,
1533 DDI_AUX_DATA_USBC6_1 => 16#06_4814# / Register_Width,
1534 DDI_AUX_DATA_USBC6_2 => 16#06_4818# / Register_Width,
1535 DDI_AUX_DATA_USBC6_3 => 16#06_481c# / Register_Width,
1536 DDI_AUX_DATA_USBC6_4 => 16#06_4820# / Register_Width,
1537 DDI_AUX_DATA_USBC6_5 => 16#06_4824# / Register_Width,
1538
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1539 DDI_BUF_CTL_E => 16#06_4400# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1540 DDI_BUF_TRANS_E_S0T1 => 16#06_4f80# / Register_Width,
1541 DDI_BUF_TRANS_E_S0T2 => 16#06_4f84# / Register_Width,
1542 DDI_BUF_TRANS_E_S1T1 => 16#06_4f88# / Register_Width,
1543 DDI_BUF_TRANS_E_S1T2 => 16#06_4f8c# / Register_Width,
1544 DDI_BUF_TRANS_E_S2T1 => 16#06_4f90# / Register_Width,
1545 DDI_BUF_TRANS_E_S2T2 => 16#06_4f94# / Register_Width,
1546 DDI_BUF_TRANS_E_S3T1 => 16#06_4f98# / Register_Width,
1547 DDI_BUF_TRANS_E_S3T2 => 16#06_4f9c# / Register_Width,
1548 DDI_BUF_TRANS_E_S4T1 => 16#06_4fa0# / Register_Width,
1549 DDI_BUF_TRANS_E_S4T2 => 16#06_4fa4# / Register_Width,
1550 DDI_BUF_TRANS_E_S5T1 => 16#06_4fa8# / Register_Width,
1551 DDI_BUF_TRANS_E_S5T2 => 16#06_4fac# / Register_Width,
1552 DDI_BUF_TRANS_E_S6T1 => 16#06_4fb0# / Register_Width,
1553 DDI_BUF_TRANS_E_S6T2 => 16#06_4fb4# / Register_Width,
1554 DDI_BUF_TRANS_E_S7T1 => 16#06_4fb8# / Register_Width,
1555 DDI_BUF_TRANS_E_S7T2 => 16#06_4fbc# / Register_Width,
1556 DDI_BUF_TRANS_E_S8T1 => 16#06_4fc0# / Register_Width,
1557 DDI_BUF_TRANS_E_S8T2 => 16#06_4fc4# / Register_Width,
1558 DDI_BUF_TRANS_E_S9T1 => 16#06_4fc8# / Register_Width,
1559 DDI_BUF_TRANS_E_S9T2 => 16#06_4fcc# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1560 DP_TP_CTL_A => 16#06_4040# / Register_Width,
1561 DP_TP_CTL_B => 16#06_4140# / Register_Width,
1562 DP_TP_CTL_C => 16#06_4240# / Register_Width,
1563 DP_TP_CTL_D => 16#06_4340# / Register_Width,
1564 DP_TP_CTL_E => 16#06_4440# / Register_Width,
1565 DP_TP_STATUS_B => 16#06_4144# / Register_Width,
1566 DP_TP_STATUS_C => 16#06_4244# / Register_Width,
1567 DP_TP_STATUS_D => 16#06_4344# / Register_Width,
1568 DP_TP_STATUS_E => 16#06_4444# / Register_Width,
1569 PORT_CLK_SEL_DDIA => 16#04_6100# / Register_Width,
1570 PORT_CLK_SEL_DDIB => 16#04_6104# / Register_Width,
1571 PORT_CLK_SEL_DDIC => 16#04_6108# / Register_Width,
1572 PORT_CLK_SEL_DDID => 16#04_610c# / Register_Width,
1573 PORT_CLK_SEL_DDIE => 16#04_6110# / Register_Width,
1574
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]1575 -- Haswell LCPLL registers
1576 LCPLL_CTL => 16#13_0040# / Register_Width,
1577
Nico Huber58afc202017-06-12 21:34:55 +0200[diff] [blame]1578 -- Skylake I_boost configuration
1579 DISPIO_CR_TX_BMU_CR0 => 16#06_c00c# / Register_Width,
1580
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1581 -- Skylake DPLL registers
1582 DPLL1_CFGR1 => 16#06_c040# / Register_Width,
1583 DPLL1_CFGR2 => 16#06_c044# / Register_Width,
1584 DPLL2_CFGR1 => 16#06_c048# / Register_Width,
1585 DPLL2_CFGR2 => 16#06_c04c# / Register_Width,
1586 DPLL3_CFGR1 => 16#06_c050# / Register_Width,
1587 DPLL3_CFGR2 => 16#06_c054# / Register_Width,
1588 DPLL_CTRL1 => 16#06_c058# / Register_Width,
1589 DPLL_CTRL2 => 16#06_c05c# / Register_Width,
1590 DPLL_STATUS => 16#06_c060# / Register_Width,
1591
1592 -- CD CLK register
1593 CDCLK_CTL => 16#04_6000# / Register_Width,
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]1594 CDCLK_FREQ => 16#04_6200# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1595
1596 -- Skylake LCPLL registers
1597 LCPLL1_CTL => 16#04_6010# / Register_Width,
1598 LCPLL2_CTL => 16#04_6014# / Register_Width,
1599
1600 -- SPLL register
1601 SPLL_CTL => 16#04_6020# / Register_Width,
1602
1603 -- WRPLL registers
1604 WRPLL_CTL_1 => 16#04_6040# / Register_Width,
1605 WRPLL_CTL_2 => 16#04_6060# / Register_Width,
1606
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]1607 -- Broxton Display Engine PLL registers
1608 BXT_DE_PLL_CTL => 16#06_d000# / Register_Width,
1609 BXT_DE_PLL_ENABLE => 16#04_6070# / Register_Width,
1610
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1611 -- Broxton DDI PHY PLL registers
1612 BXT_PORT_PLL_ENABLE_A => 16#04_6074# / Register_Width,
1613 BXT_PORT_PLL_ENABLE_B => 16#04_6078# / Register_Width,
1614 BXT_PORT_PLL_ENABLE_C => 16#04_607c# / Register_Width,
1615 BXT_PORT_PLL_EBB_0_A => 16#16_2034# / Register_Width,
1616 BXT_PORT_PLL_EBB_4_A => 16#16_2038# / Register_Width,
1617 BXT_PORT_PLL_0_A => 16#16_2100# / Register_Width,
1618 BXT_PORT_PLL_1_A => 16#16_2104# / Register_Width,
1619 BXT_PORT_PLL_2_A => 16#16_2108# / Register_Width,
1620 BXT_PORT_PLL_3_A => 16#16_210c# / Register_Width,
1621 BXT_PORT_PLL_6_A => 16#16_2118# / Register_Width,
1622 BXT_PORT_PLL_8_A => 16#16_2120# / Register_Width,
1623 BXT_PORT_PLL_9_A => 16#16_2124# / Register_Width,
1624 BXT_PORT_PLL_10_A => 16#16_2128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1625 BXT_PORT_PLL_EBB_0_B => 16#06_c034# / Register_Width,
1626 BXT_PORT_PLL_EBB_4_B => 16#06_c038# / Register_Width,
1627 BXT_PORT_PLL_0_B => 16#06_c100# / Register_Width,
1628 BXT_PORT_PLL_1_B => 16#06_c104# / Register_Width,
1629 BXT_PORT_PLL_2_B => 16#06_c108# / Register_Width,
1630 BXT_PORT_PLL_3_B => 16#06_c10c# / Register_Width,
1631 BXT_PORT_PLL_6_B => 16#06_c118# / Register_Width,
1632 BXT_PORT_PLL_8_B => 16#06_c120# / Register_Width,
1633 BXT_PORT_PLL_9_B => 16#06_c124# / Register_Width,
1634 BXT_PORT_PLL_10_B => 16#06_c128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1635 BXT_PORT_PLL_EBB_0_C => 16#06_c340# / Register_Width,
1636 BXT_PORT_PLL_EBB_4_C => 16#06_c344# / Register_Width,
1637 BXT_PORT_PLL_0_C => 16#06_c380# / Register_Width,
1638 BXT_PORT_PLL_1_C => 16#06_c384# / Register_Width,
1639 BXT_PORT_PLL_2_C => 16#06_c388# / Register_Width,
1640 BXT_PORT_PLL_3_C => 16#06_c38c# / Register_Width,
1641 BXT_PORT_PLL_6_C => 16#06_c398# / Register_Width,
1642 BXT_PORT_PLL_8_C => 16#06_c3a0# / Register_Width,
1643 BXT_PORT_PLL_9_C => 16#06_c3a4# / Register_Width,
1644 BXT_PORT_PLL_10_C => 16#06_c3a8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1645
1646 -- Broxton DDI PHY PCS? registers
1647 BXT_PORT_PCS_DW10_01_A => 16#16_2428# / Register_Width,
1648 BXT_PORT_PCS_DW12_01_A => 16#16_2430# / Register_Width,
1649 BXT_PORT_PCS_DW10_GRP_A => 16#16_2c28# / Register_Width,
1650 BXT_PORT_PCS_DW12_GRP_A => 16#16_2c30# / Register_Width,
1651 BXT_PORT_PCS_DW10_01_B => 16#06_c428# / Register_Width,
1652 BXT_PORT_PCS_DW12_01_B => 16#06_c430# / Register_Width,
1653 BXT_PORT_PCS_DW10_01_C => 16#06_c828# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1654 BXT_PORT_PCS_DW12_01_C => 16#06_c830# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1655 BXT_PORT_PCS_DW10_GRP_B => 16#06_cc28# / Register_Width,
1656 BXT_PORT_PCS_DW12_GRP_B => 16#06_cc30# / Register_Width,
1657 BXT_PORT_PCS_DW10_GRP_C => 16#06_ce28# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1658 BXT_PORT_PCS_DW12_GRP_C => 16#06_ce30# / Register_Width,
1659
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]1660 -- Broxton DDI PHY registers
1661 BXT_P_CR_GT_DISP_PWRON => 16#13_8090# / Register_Width,
1662 BXT_PHY_CTL_A => 16#06_4c00# / Register_Width,
1663 BXT_PHY_CTL_B => 16#06_4c10# / Register_Width,
1664 BXT_PHY_CTL_C => 16#06_4c20# / Register_Width,
1665 BXT_PHY_CTL_FAM_EDP => 16#06_4c80# / Register_Width,
1666 BXT_PHY_CTL_FAM_DDI => 16#06_4c90# / Register_Width,
1667
1668 -- Broxton DDI PHY common lane registers
1669 BXT_PORT_CL1CM_DW0_A => 16#16_2000# / Register_Width,
1670 BXT_PORT_CL1CM_DW0_BC => 16#06_c000# / Register_Width,
1671 BXT_PORT_CL1CM_DW9_A => 16#16_2024# / Register_Width,
1672 BXT_PORT_CL1CM_DW9_BC => 16#06_c024# / Register_Width,
1673 BXT_PORT_CL1CM_DW10_A => 16#16_2028# / Register_Width,
1674 BXT_PORT_CL1CM_DW10_BC => 16#06_c028# / Register_Width,
1675 BXT_PORT_CL1CM_DW28_A => 16#16_2070# / Register_Width,
1676 BXT_PORT_CL1CM_DW28_BC => 16#06_c070# / Register_Width,
1677 BXT_PORT_CL1CM_DW30_A => 16#16_2078# / Register_Width,
1678 BXT_PORT_CL1CM_DW30_BC => 16#06_c078# / Register_Width,
1679 BXT_PORT_CL2CM_DW6_BC => 16#06_c358# / Register_Width,
1680
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1681 -- Broxton DDI PHY TX lane registers
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1682 BXT_PORT_TX_DW2_LN0_A => 16#16_2508# / Register_Width,
1683 BXT_PORT_TX_DW3_LN0_A => 16#16_250c# / Register_Width,
1684 BXT_PORT_TX_DW4_LN0_A => 16#16_2510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1685 BXT_PORT_TX_DW14_LN0_A => 16#16_2538# / Register_Width,
1686 BXT_PORT_TX_DW14_LN1_A => 16#16_25b8# / Register_Width,
1687 BXT_PORT_TX_DW14_LN2_A => 16#16_2738# / Register_Width,
1688 BXT_PORT_TX_DW14_LN3_A => 16#16_27b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1689 BXT_PORT_TX_DW2_GRP_A => 16#16_2d08# / Register_Width,
1690 BXT_PORT_TX_DW3_GRP_A => 16#16_2d0c# / Register_Width,
1691 BXT_PORT_TX_DW4_GRP_A => 16#16_2d10# / Register_Width,
1692 BXT_PORT_TX_DW2_LN0_B => 16#06_c508# / Register_Width,
1693 BXT_PORT_TX_DW3_LN0_B => 16#06_c50c# / Register_Width,
1694 BXT_PORT_TX_DW4_LN0_B => 16#06_c510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1695 BXT_PORT_TX_DW14_LN0_B => 16#06_c538# / Register_Width,
1696 BXT_PORT_TX_DW14_LN1_B => 16#06_c5b8# / Register_Width,
1697 BXT_PORT_TX_DW14_LN2_B => 16#06_c738# / Register_Width,
1698 BXT_PORT_TX_DW14_LN3_B => 16#06_c7b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1699 BXT_PORT_TX_DW2_GRP_B => 16#06_cd08# / Register_Width,
1700 BXT_PORT_TX_DW3_GRP_B => 16#06_cd0c# / Register_Width,
1701 BXT_PORT_TX_DW4_GRP_B => 16#06_cd10# / Register_Width,
1702 BXT_PORT_TX_DW2_LN0_C => 16#06_c908# / Register_Width,
1703 BXT_PORT_TX_DW3_LN0_C => 16#06_c90c# / Register_Width,
1704 BXT_PORT_TX_DW4_LN0_C => 16#06_c910# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1705 BXT_PORT_TX_DW14_LN0_C => 16#06_c938# / Register_Width,
1706 BXT_PORT_TX_DW14_LN1_C => 16#06_c9b8# / Register_Width,
1707 BXT_PORT_TX_DW14_LN2_C => 16#06_cb38# / Register_Width,
1708 BXT_PORT_TX_DW14_LN3_C => 16#06_cbb8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1709 BXT_PORT_TX_DW2_GRP_C => 16#06_cf08# / Register_Width,
1710 BXT_PORT_TX_DW3_GRP_C => 16#06_cf0c# / Register_Width,
1711 BXT_PORT_TX_DW4_GRP_C => 16#06_cf10# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1712
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]1713 -- Broxton DDI PHY ref registers
1714 BXT_PORT_REF_DW3_A => 16#16_218c# / Register_Width,
1715 BXT_PORT_REF_DW3_BC => 16#06_c18c# / Register_Width,
1716 BXT_PORT_REF_DW6_A => 16#16_2198# / Register_Width,
1717 BXT_PORT_REF_DW6_BC => 16#06_c198# / Register_Width,
1718 BXT_PORT_REF_DW8_A => 16#16_21a0# / Register_Width,
1719 BXT_PORT_REF_DW8_BC => 16#06_c1a0# / Register_Width,
1720
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1721 -- Power Down Well registers
1722 PWR_WELL_CTL_BIOS => 16#04_5400# / Register_Width,
1723 PWR_WELL_CTL_DRIVER => 16#04_5404# / Register_Width,
1724 PWR_WELL_CTL_KVMR => 16#04_5408# / Register_Width,
1725 PWR_WELL_CTL_DEBUG => 16#04_540c# / Register_Width,
1726 PWR_WELL_CTL5 => 16#04_5410# / Register_Width,
1727 PWR_WELL_CTL6 => 16#04_5414# / Register_Width,
1728
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1729 PWR_AUX_CTL_BIOS => 16#04_5440# / Register_Width,
1730 PWR_AUX_CTL_DRIVER => 16#04_5444# / Register_Width,
1731 PWR_DDI_CTL_BIOS => 16#04_5450# / Register_Width,
1732 PWR_DDI_CTL_DRIVER => 16#04_5454# / Register_Width,
1733
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1734 -- class Panel registers
Arthur Heymanse87d0d12018-03-28 17:02:49 +0200[diff] [blame]1735 GMCH_PP_STATUS => 16#06_1200# / Register_Width,
1736 GMCH_PP_CONTROL => 16#06_1204# / Register_Width,
1737 GMCH_PP_ON_DELAYS => 16#06_1208# / Register_Width,
1738 GMCH_PP_OFF_DELAYS => 16#06_120c# / Register_Width,
1739 GMCH_PP_DIVISOR => 16#06_1210# / Register_Width,
Arthur Heymansd5198442018-03-28 17:05:12 +0200[diff] [blame]1740 GMCH_PFIT_CONTROL => 16#06_1230# / Register_Width,
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]1741 PCH_PP_STATUS => 16#0c_7200# / Register_Width, -- aliased with BXT_PP_STATUS_1
1742 PCH_PP_CONTROL => 16#0c_7204# / Register_Width, -- aliased with BXT_PP_CONTROL_1
1743 PCH_PP_ON_DELAYS => 16#0c_7208# / Register_Width, -- aliased with BXT_PP_ON_DELAYS_1
1744 PCH_PP_OFF_DELAYS => 16#0c_720c# / Register_Width, -- aliased with BXT_PP_OFF_DELAYS_1
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1745 PCH_PP_DIVISOR => 16#0c_7210# / Register_Width,
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]1746 BXT_PP_STATUS_2 => 16#0c_7300# / Register_Width,
1747 BXT_PP_CONTROL_2 => 16#0c_7304# / Register_Width,
1748 BXT_PP_ON_DELAYS_2 => 16#0c_7308# / Register_Width,
1749 BXT_PP_OFF_DELAYS_2 => 16#0c_730c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1750 BLC_PWM_CPU_CTL => 16#04_8254# / Register_Width,
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]1751 BLC_PWM_CPU_CTL2 => 16#04_8250# / Register_Width,
1752 BLC_PWM_PCH_CTL1 => 16#0c_8250# / Register_Width, -- aliased with BXT_BLC_PWM_CTL_1
1753 BLC_PWM_PCH_CTL2 => 16#0c_8254# / Register_Width, -- aliased with BXT_BLC_PWM_FREQ_1
1754 BXT_BLC_PWM_DUTY_1 => 16#0c_8258# / Register_Width,
1755 BXT_BLC_PWM_CTL_2 => 16#0c_8350# / Register_Width,
1756 BXT_BLC_PWM_FREQ_2 => 16#0c_8354# / Register_Width,
1757 BXT_BLC_PWM_DUTY_2 => 16#0c_8358# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1758
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1759 -- GMCH LVDS Connector Registers
1760 GMCH_LVDS => 16#06_1180# / Register_Width,
1761
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1762 -- PCH LVDS Connector Registers
1763 PCH_LVDS => 16#0e_1180# / Register_Width,
1764
1765 -- PCH ADPA Connector Registers
1766 PCH_ADPA => 16#0e_1100# / Register_Width,
1767
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1768 -- GMCH DVOB Connector Registers
1769 GMCH_SDVOB => 16#06_1140# / Register_Width,
1770
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1771 -- PCH HDMIB Connector Registers
1772 PCH_HDMIB => 16#0e_1140# / Register_Width,
1773
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1774 -- GMCH DVOC Connector Registers
1775 GMCH_SDVOC => 16#06_1160# / Register_Width,
1776
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1777 -- PCH HDMIC Connector Registers
1778 PCH_HDMIC => 16#0e_1150# / Register_Width,
1779
1780 -- PCH HDMID Connector Registers
1781 PCH_HDMID => 16#0e_1160# / Register_Width,
1782
1783 -- Intel Registers
Nico Huber6b4678d2019-09-22 21:31:52 +0200[diff] [blame]1784 DFSM => 16#05_1000# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1785 DSSM => 16#05_1004# / Register_Width,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]1786 CPU_VGACNTRL => 16#04_1000# / Register_Width,
1787 GMCH_VGACNTRL => 16#07_1400# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1788 FUSE_STATUS => 16#04_2000# / Register_Width,
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]1789 FUSE_STRAP => 16#04_2014# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1790 FBA_CFB_BASE => 16#04_3200# / Register_Width,
1791 IPS_CTL => 16#04_3408# / Register_Width,
1792 ARB_CTL => 16#04_5000# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1793 DBUF_CTL_S0 => 16#04_5008# / Register_Width,
1794 DBUF_CTL_S1 => 16#04_4fe8# / Register_Width,
1795 DBUF_CTL_S2 => 16#04_4300# / Register_Width,
1796 DBUF_CTL_S3 => 16#04_4304# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1797 NDE_RSTWRN_OPT => 16#04_6408# / Register_Width,
Angel Ponsae186bd2020-10-21 21:37:34 +0200[diff] [blame]1798 GEN8_CHICKEN_DCPR_1 => 16#04_6430# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1799 GEN11_CHICKEN_DCPR_2 => 16#04_6434# / Register_Width,
1800 GEN9_CLKGATE_DIS_0 => 16#04_6530# / Register_Width,
1801 GEN9_CLKGATE_DIS_5 => 16#04_6540# / Register_Width,
1802 GEN9_CHICKEN_DPCR_3 => 16#04_6538# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1803 PCH_DREF_CONTROL => 16#0c_6200# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1804 PCH_DPLL_SEL => 16#0c_7000# / Register_Width,
1805 GT_MAILBOX => 16#13_8124# / Register_Width,
1806 GT_MAILBOX_DATA => 16#13_8128# / Register_Width,
1807 GT_MAILBOX_DATA_1 => 16#13_812c# / Register_Width,
1808
1809 PCH_DP_B => 16#0e_4100# / Register_Width,
1810 PCH_DP_AUX_CTL_B => 16#0e_4110# / Register_Width,
1811 PCH_DP_AUX_DATA_B_1 => 16#0e_4114# / Register_Width,
1812 PCH_DP_AUX_DATA_B_2 => 16#0e_4118# / Register_Width,
1813 PCH_DP_AUX_DATA_B_3 => 16#0e_411c# / Register_Width,
1814 PCH_DP_AUX_DATA_B_4 => 16#0e_4120# / Register_Width,
1815 PCH_DP_AUX_DATA_B_5 => 16#0e_4124# / Register_Width,
1816 PCH_DP_C => 16#0e_4200# / Register_Width,
1817 PCH_DP_AUX_CTL_C => 16#0e_4210# / Register_Width,
1818 PCH_DP_AUX_DATA_C_1 => 16#0e_4214# / Register_Width,
1819 PCH_DP_AUX_DATA_C_2 => 16#0e_4218# / Register_Width,
1820 PCH_DP_AUX_DATA_C_3 => 16#0e_421c# / Register_Width,
1821 PCH_DP_AUX_DATA_C_4 => 16#0e_4220# / Register_Width,
1822 PCH_DP_AUX_DATA_C_5 => 16#0e_4224# / Register_Width,
1823 PCH_DP_D => 16#0e_4300# / Register_Width,
1824 PCH_DP_AUX_CTL_D => 16#0e_4310# / Register_Width,
1825 PCH_DP_AUX_DATA_D_1 => 16#0e_4314# / Register_Width,
1826 PCH_DP_AUX_DATA_D_2 => 16#0e_4318# / Register_Width,
1827 PCH_DP_AUX_DATA_D_3 => 16#0e_431c# / Register_Width,
1828 PCH_DP_AUX_DATA_D_4 => 16#0e_4320# / Register_Width,
1829 PCH_DP_AUX_DATA_D_5 => 16#0e_4324# / Register_Width,
1830
1831 -- watermark registers
1832 WM1_LP_ILK => 16#04_5108# / Register_Width,
1833 WM2_LP_ILK => 16#04_510c# / Register_Width,
1834 WM3_LP_ILK => 16#04_5110# / Register_Width,
1835
1836 -- audio VID/DID
1837 AUD_VID_DID => 16#06_5020# / Register_Width,
1838 PCH_AUD_VID_DID => 16#0e_5020# / Register_Width,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1839 G4X_AUD_VID_DID => 16#06_2020# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1840
1841 -- interrupt registers
1842 DEISR => 16#04_4000# / Register_Width,
1843 DEIMR => 16#04_4004# / Register_Width,
1844 DEIIR => 16#04_4008# / Register_Width,
1845 DEIER => 16#04_400c# / Register_Width,
1846 GTISR => 16#04_4010# / Register_Width,
1847 GTIMR => 16#04_4014# / Register_Width,
1848 GTIIR => 16#04_4018# / Register_Width,
1849 GTIER => 16#04_401c# / Register_Width,
1850 SDEISR => 16#0c_4000# / Register_Width,
1851 SDEIMR => 16#0c_4004# / Register_Width,
1852 SDEIIR => 16#0c_4008# / Register_Width,
1853 SDEIER => 16#0c_400c# / Register_Width,
1854
1855 -- I2C stuff
Arthur Heymans229ed1c2018-03-28 16:45:43 +0200[diff] [blame]1856 GMCH_GMBUS0 => 16#00_5100# / Register_Width,
1857 GMCH_GMBUS1 => 16#00_5104# / Register_Width,
1858 GMCH_GMBUS2 => 16#00_5108# / Register_Width,
1859 GMCH_GMBUS3 => 16#00_510c# / Register_Width,
1860 GMCH_GMBUS4 => 16#00_5110# / Register_Width,
1861 GMCH_GMBUS5 => 16#00_5120# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1862 PCH_GMBUS0 => 16#0c_5100# / Register_Width,
1863 PCH_GMBUS1 => 16#0c_5104# / Register_Width,
1864 PCH_GMBUS2 => 16#0c_5108# / Register_Width,
1865 PCH_GMBUS3 => 16#0c_510c# / Register_Width,
1866 PCH_GMBUS4 => 16#0c_5110# / Register_Width,
1867 PCH_GMBUS5 => 16#0c_5120# / Register_Width,
1868
1869 -- clock gating -- maybe have to touch this
1870 DSPCLK_GATE_D => 16#04_2020# / Register_Width,
1871 PCH_FDI_CHICKEN_B_C => 16#0c_2000# / Register_Width,
1872 PCH_DSPCLK_GATE_D => 16#0c_2020# / Register_Width,
1873
1874 -- hotplug and initial detection
1875 HOTPLUG_CTL => 16#04_4030# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1876 TC_HOTPLUG_CTL => 16#04_4038# / Register_Width,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1877 PORT_HOTPLUG_EN => 16#06_1110# / Register_Width,
1878 PORT_HOTPLUG_STAT => 16#06_1114# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1879 SHOTPLUG_CTL => 16#0c_4030# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1880 SHOTPLUG_CTL_TC => 16#0c_4034# / Register_Width,
1881 SHPD_FILTER_CNT => 16#0c_4038# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1882 SFUSE_STRAP => 16#0c_2014# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1883 GEN11_DE_HPD_ISR => 16#04_4470# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1884
1885 -- Render Engine Command Streamer
1886 ARB_MODE => 16#00_4030# / Register_Width,
1887 HWS_PGA => 16#00_4080# / Register_Width,
1888 RCS_RING_BUFFER_TAIL => 16#00_2030# / Register_Width,
1889 VCS_RING_BUFFER_TAIL => 16#01_2030# / Register_Width,
1890 BCS_RING_BUFFER_TAIL => 16#02_2030# / Register_Width,
1891 RCS_RING_BUFFER_HEAD => 16#00_2034# / Register_Width,
1892 VCS_RING_BUFFER_HEAD => 16#01_2034# / Register_Width,
1893 BCS_RING_BUFFER_HEAD => 16#02_2034# / Register_Width,
1894 RCS_RING_BUFFER_STRT => 16#00_2038# / Register_Width,
1895 VCS_RING_BUFFER_STRT => 16#01_2038# / Register_Width,
1896 BCS_RING_BUFFER_STRT => 16#02_2038# / Register_Width,
1897 RCS_RING_BUFFER_CTL => 16#00_203c# / Register_Width,
1898 VCS_RING_BUFFER_CTL => 16#01_203c# / Register_Width,
1899 BCS_RING_BUFFER_CTL => 16#02_203c# / Register_Width,
1900 MI_MODE => 16#00_209c# / Register_Width,
1901 INSTPM => 16#00_20c0# / Register_Width,
1902 GAB_CTL_REG => 16#02_4000# / Register_Width,
1903 PP_DCLV_HIGH => 16#00_2220# / Register_Width,
1904 PP_DCLV_LOW => 16#00_2228# / Register_Width,
1905 VCS_PP_DCLV_HIGH => 16#01_2220# / Register_Width,
1906 VCS_PP_DCLV_LOW => 16#01_2228# / Register_Width,
1907 BCS_PP_DCLV_HIGH => 16#02_2220# / Register_Width,
1908 BCS_PP_DCLV_LOW => 16#02_2228# / Register_Width,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1909 ILK_DISPLAY_CHICKEN2 => 16#04_2004# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1910 UCGCTL1 => 16#00_9400# / Register_Width,
1911 UCGCTL2 => 16#00_9404# / Register_Width,
1912 MBCTL => 16#00_907c# / Register_Width,
1913 HWSTAM => 16#00_2098# / Register_Width,
1914 VCS_HWSTAM => 16#01_2098# / Register_Width,
1915 BCS_HWSTAM => 16#02_2098# / Register_Width,
1916 IIR => 16#04_4028# / Register_Width,
1917 PIPE_FRMCNT_A => 16#07_0040# / Register_Width,
1918 PIPE_FRMCNT_B => 16#07_1040# / Register_Width,
1919 PIPE_FRMCNT_C => 16#07_2040# / Register_Width,
1920 FBC_CTL => 16#04_3208# / Register_Width,
1921 PIPE_VSYNCSHIFT_A => 16#06_0028# / Register_Width,
1922 PIPE_VSYNCSHIFT_B => 16#06_1028# / Register_Width,
1923 PIPE_VSYNCSHIFT_C => 16#06_2028# / Register_Width,
1924 WM_PIPE_A => 16#04_5100# / Register_Width,
1925 WM_PIPE_B => 16#04_5104# / Register_Width,
1926 WM_PIPE_C => 16#04_5200# / Register_Width,
1927 PIPE_SCANLINE_A => 16#07_0000# / Register_Width,
1928 PIPE_SCANLINE_B => 16#07_1000# / Register_Width,
1929 PIPE_SCANLINE_C => 16#07_2000# / Register_Width,
1930 GFX_MODE => 16#00_2520# / Register_Width,
1931 CACHE_MODE_0 => 16#00_2120# / Register_Width,
1932 SLEEP_PSMI_CONTROL => 16#01_2050# / Register_Width,
1933 CTX_SIZE => 16#00_21a0# / Register_Width,
1934 GAC_ECO_BITS => 16#01_4090# / Register_Width,
1935 GAM_ECOCHK => 16#00_4090# / Register_Width,
1936 QUIRK_02084 => 16#00_2084# / Register_Width,
1937 QUIRK_02090 => 16#00_2090# / Register_Width,
1938 GT_MODE => 16#00_20d0# / Register_Width,
1939 QUIRK_F0060 => 16#0f_0060# / Register_Width,
1940 QUIRK_F1060 => 16#0f_1060# / Register_Width,
1941 QUIRK_F2060 => 16#0f_2060# / Register_Width,
1942 AUD_CNTRL_ST2 => 16#0e_50c0# / Register_Width,
1943 AUD_CNTL_ST_A => 16#0e_50b4# / Register_Width,
1944 AUD_CNTL_ST_B => 16#0e_51b4# / Register_Width,
1945 AUD_CNTL_ST_C => 16#0e_52b4# / Register_Width,
1946 AUD_HDMIW_HDMIEDID_A => 16#0e_5050# / Register_Width,
1947 AUD_HDMIW_HDMIEDID_B => 16#0e_5150# / Register_Width,
1948 AUD_HDMIW_HDMIEDID_C => 16#0e_5250# / Register_Width,
1949 AUD_CONFIG_A => 16#0e_5000# / Register_Width,
1950 AUD_CONFIG_B => 16#0e_5100# / Register_Width,
1951 AUD_CONFIG_C => 16#0e_5200# / Register_Width,
1952 TRANS_DP_CTL_A => 16#0e_0300# / Register_Width,
1953 TRANS_DP_CTL_B => 16#0e_1300# / Register_Width,
1954 TRANS_DP_CTL_C => 16#0e_2300# / Register_Width,
1955 TRANS_VSYNCSHIFT_A => 16#0e_0028# / Register_Width,
1956 TRANS_VSYNCSHIFT_B => 16#0e_1028# / Register_Width,
1957 TRANS_VSYNCSHIFT_C => 16#0e_2028# / Register_Width,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]1958 PCH_RAWCLK_FREQ => 16#0c_6204# / Register_Width,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1959 QUIRK_C2004 => 16#0c_2004# / Register_Width,
1960
1961 -- MCHBAR Mirror
1962
Nico Huberb47a5c42019-09-29 00:07:21 +0200[diff] [blame]1963 GMCH_CLKCFG => 16#01_0c00# / Register_Width,
1964 GMCH_HPLLVCO_MOBILE => 16#01_0c0f# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1965 GMCH_HPLLVCO => 16#01_0c38# / Register_Width,
1966
1967 -- Combo Phy Registers (Tigerlake on)
1968
1969 PHY_MISC_B => 16#06_4c04# / Register_Width,
1970 PHY_MISC_C => 16#06_4c08# / Register_Width,
1971 PORT_CL_DW5_A => 16#16_2014# / Register_Width,
1972 PORT_CL_DW5_B => 16#06_c014# / Register_Width,
1973 PORT_CL_DW5_C => 16#16_0014# / Register_Width,
1974 PORT_COMP_DW0_C => 16#16_0100# / Register_Width,
1975 PORT_COMP_DW1_C => 16#16_0104# / Register_Width,
1976 PORT_COMP_DW3_C => 16#16_010c# / Register_Width,
1977 PORT_COMP_DW8_C => 16#16_0120# / Register_Width,
1978 PORT_COMP_DW9_C => 16#16_0124# / Register_Width,
1979 PORT_COMP_DW10_C => 16#16_0128# / Register_Width,
1980 PORT_TX_DW8_LN0_A => 16#16_28a0# / Register_Width,
1981 PORT_TX_DW8_LN0_B => 16#06_c8a0# / Register_Width,
1982 PORT_TX_DW8_LN0_C => 16#16_08a0# / Register_Width,
1983 PORT_TX_DW8_GRP_A => 16#16_26a0# / Register_Width,
1984 PORT_TX_DW8_GRP_B => 16#06_c6a0# / Register_Width,
1985 PORT_TX_DW8_GRP_C => 16#16_06a0# / Register_Width,
1986 PORT_PCS_DW1_LN0_A => 16#16_2804# / Register_Width,
1987 PORT_PCS_DW1_LN0_B => 16#06_c804# / Register_Width,
1988 PORT_PCS_DW1_LN0_C => 16#16_0804# / Register_Width,
1989 PORT_PCS_DW1_GRP_A => 16#16_2604# / Register_Width,
1990 PORT_PCS_DW1_GRP_B => 16#06_c604# / Register_Width,
1991 PORT_PCS_DW1_GRP_C => 16#16_0604# / Register_Width,
1992 MBUS_ABOX_CTL => 16#04_5038# / Register_Width,
1993 MBUS_ABOX1_CTL => 16#04_5048# / Register_Width,
1994 MBUS_ABOX2_CTL => 16#04_504c# / Register_Width,
1995 BW_BUDDY1_PAGE_MASK => 16#04_5144# / Register_Width,
1996 BW_BUDDY2_PAGE_MASK => 16#04_5154# / Register_Width,
1997 BW_BUDDY1_CTL => 16#04_5140# / Register_Width,
1998 BW_BUDDY2_CTL => 16#04_5150# / Register_Width,
1999
2000 -- TGL DKL PHY registers
2001 HIP_INDEX_REG0 => 16#10_10a0# / Register_Width,
2002 HIP_INDEX_REG1 => 16#10_10a4# / Register_Width,
2003 -- Each type-C port PHY is addressed through a 4KB
2004 -- aperture. Each PHY has more than 4KB of register space, so a
2005 -- separate index is programmed in HIP_INDEX_REG0 or
2006 -- HIP_INDEX_REG1, based on the port number, to set the upper 2
2007 -- address bits that point the 4KB window into the full PHY
2008 -- register space.
2009 -- The registers below assumes index 2 has been programmed.
2010
2011 -- 16_8*** registers for DKL PHY 1
2012 DKL_CLKTOP2_HSCC_1 => 16#16_80d4# / Register_Width,
2013 DKL_CLKTOP2_CCC1_1 => 16#16_80d8# / Register_Width,
2014 DKL_REFCLKIN_CTL_1 => 16#16_812c# / Register_Width,
2015 DKL_PLL_DIV0_1 => 16#16_8200# / Register_Width,
2016 DKL_PLL_DIV1_1 => 16#16_8204# / Register_Width,
2017 DKL_PLL_SSC_1 => 16#16_8210# / Register_Width,
2018 DKL_PLL_BIAS_1 => 16#16_8214# / Register_Width,
2019 DKL_PLL_COLDST_BIAS_1 => 16#16_8218# / Register_Width,
2020 DKL_CMN_UC_DW_27_1 => 16#16_836c# / Register_Width,
2021 DKL_DP_MODE_1 => 16#16_80a0# / Register_Width,
2022 -- 16_9*** registers for DKL PHY 2
2023 DKL_CLKTOP2_HSCC_2 => 16#16_90d4# / Register_Width,
2024 DKL_CLKTOP2_CCC1_2 => 16#16_90d8# / Register_Width,
2025 DKL_REFCLKIN_CTL_2 => 16#16_912c# / Register_Width,
2026 DKL_PLL_DIV0_2 => 16#16_9200# / Register_Width,
2027 DKL_PLL_DIV1_2 => 16#16_9204# / Register_Width,
2028 DKL_PLL_SSC_2 => 16#16_9210# / Register_Width,
2029 DKL_PLL_BIAS_2 => 16#16_9214# / Register_Width,
2030 DKL_PLL_COLDST_BIAS_2 => 16#16_9218# / Register_Width,
2031 DKL_CMN_UC_DW_27_2 => 16#16_936c# / Register_Width,
2032 DKL_DP_MODE_2 => 16#16_90a0# / Register_Width,
2033 -- 16_a*** registers for DKL PHY 3
2034 DKL_CLKTOP2_HSCC_3 => 16#16_a0d4# / Register_Width,
2035 DKL_CLKTOP2_CCC1_3 => 16#16_a0d8# / Register_Width,
2036 DKL_REFCLKIN_CTL_3 => 16#16_a12c# / Register_Width,
2037 DKL_PLL_DIV0_3 => 16#16_a200# / Register_Width,
2038 DKL_PLL_DIV1_3 => 16#16_a204# / Register_Width,
2039 DKL_PLL_SSC_3 => 16#16_a210# / Register_Width,
2040 DKL_PLL_BIAS_3 => 16#16_a214# / Register_Width,
2041 DKL_PLL_COLDST_BIAS_3 => 16#16_a218# / Register_Width,
2042 DKL_CMN_UC_DW_27_3 => 16#16_a36c# / Register_Width,
2043 DKL_DP_MODE_3 => 16#16_a0a0# / Register_Width,
2044 -- 16_b*** registers for DKL PHY 4
2045 DKL_CLKTOP2_HSCC_4 => 16#16_b0d4# / Register_Width,
2046 DKL_CLKTOP2_CCC1_4 => 16#16_b0d8# / Register_Width,
2047 DKL_REFCLKIN_CTL_4 => 16#16_b12c# / Register_Width,
2048 DKL_PLL_DIV0_4 => 16#16_b200# / Register_Width,
2049 DKL_PLL_DIV1_4 => 16#16_b204# / Register_Width,
2050 DKL_PLL_SSC_4 => 16#16_b210# / Register_Width,
2051 DKL_PLL_BIAS_4 => 16#16_b214# / Register_Width,
2052 DKL_PLL_COLDST_BIAS_4 => 16#16_b218# / Register_Width,
2053 DKL_CMN_UC_DW_27_4 => 16#16_b36c# / Register_Width,
2054 DKL_DP_MODE_4 => 16#16_b0a0# / Register_Width,
2055 -- 16_c*** registers for DKL PHY 5
2056 DKL_CLKTOP2_HSCC_5 => 16#16_c0d4# / Register_Width,
2057 DKL_CLKTOP2_CCC1_5 => 16#16_c0d8# / Register_Width,
2058 DKL_REFCLKIN_CTL_5 => 16#16_c12c# / Register_Width,
2059 DKL_PLL_DIV0_5 => 16#16_c200# / Register_Width,
2060 DKL_PLL_DIV1_5 => 16#16_c204# / Register_Width,
2061 DKL_PLL_SSC_5 => 16#16_c210# / Register_Width,
2062 DKL_PLL_BIAS_5 => 16#16_c214# / Register_Width,
2063 DKL_PLL_COLDST_BIAS_5 => 16#16_c218# / Register_Width,
2064 DKL_CMN_UC_DW_27_5 => 16#16_c36c# / Register_Width,
2065 DKL_DP_MODE_5 => 16#16_c0a0# / Register_Width,
2066 -- 16_d*** registers for DKL PHY 6
2067 DKL_CLKTOP2_HSCC_6 => 16#16_d0d4# / Register_Width,
2068 DKL_CLKTOP2_CCC1_6 => 16#16_d0d8# / Register_Width,
2069 DKL_REFCLKIN_CTL_6 => 16#16_d12c# / Register_Width,
2070 DKL_PLL_DIV0_6 => 16#16_d200# / Register_Width,
2071 DKL_PLL_DIV1_6 => 16#16_d204# / Register_Width,
2072 DKL_PLL_SSC_6 => 16#16_d210# / Register_Width,
2073 DKL_PLL_BIAS_6 => 16#16_d214# / Register_Width,
2074 DKL_PLL_COLDST_BIAS_6 => 16#16_d218# / Register_Width,
2075 DKL_CMN_UC_DW_27_6 => 16#16_d36c# / Register_Width,
2076 DKL_DP_MODE_6 => 16#16_d0a0# / Register_Width,
2077
2078 -- TGL DPLL registers
2079 DPLL_4_ENABLE => 16#04_6018# / Register_Width,
2080 DPLL_0_CFGCR0 => 16#16_4284# / Register_Width,
2081 DPLL_0_CFGCR1 => 16#16_4288# / Register_Width,
2082 DPLL_1_CFGCR0 => 16#16_428c# / Register_Width,
2083 DPLL_1_CFGCR1 => 16#16_4290# / Register_Width,
2084 DPLL_4_CFGCR0 => 16#16_4294# / Register_Width,
2085 DPLL_4_CFGCR1 => 16#16_4298# / Register_Width,
2086 DPLL_0_SSC => 16#16_4b10# / Register_Width,
2087 DPLL_1_SSC => 16#16_4c10# / Register_Width,
2088 DPLL_4_SSC => 16#16_4e10# / Register_Width,
2089
2090 -- TGL DDI registers (some aliases too)
2091 DDI_BUF_CTL_USBC3 => 16#06_4500# / Register_Width,
2092 DDI_BUF_CTL_USBC4 => 16#06_4600# / Register_Width,
2093 DDI_BUF_CTL_USBC5 => 16#06_4700# / Register_Width,
2094 PORT_TX_DW2_LN0_A => 16#16_2888# / Register_Width,
2095 PORT_TX_DW2_LN0_B => 16#06_c888# / Register_Width,
2096 PORT_TX_DW2_LN0_C => 16#16_0888# / Register_Width,
2097 PORT_TX_DW2_GRP_A => 16#16_2688# / Register_Width,
2098 PORT_TX_DW2_GRP_B => 16#06_c688# / Register_Width,
2099 PORT_TX_DW2_GRP_C => 16#16_0688# / Register_Width,
2100 PORT_TX_DW4_LN0_A => 16#16_2890# / Register_Width,
2101 PORT_TX_DW4_LN1_A => 16#16_2990# / Register_Width,
2102 PORT_TX_DW4_LN2_A => 16#16_2a90# / Register_Width,
2103 PORT_TX_DW4_LN3_A => 16#16_2b90# / Register_Width,
2104 PORT_TX_DW4_LN0_B => 16#06_c890# / Register_Width,
2105 PORT_TX_DW4_LN1_B => 16#06_c990# / Register_Width,
2106 PORT_TX_DW4_LN2_B => 16#06_ca90# / Register_Width,
2107 PORT_TX_DW4_LN3_B => 16#06_cb90# / Register_Width,
2108 PORT_TX_DW4_LN0_C => 16#16_0890# / Register_Width,
2109 PORT_TX_DW4_LN1_C => 16#16_0990# / Register_Width,
2110 PORT_TX_DW4_LN2_C => 16#16_0a90# / Register_Width,
2111 PORT_TX_DW4_LN3_C => 16#16_0b90# / Register_Width,
2112 PORT_TX_DW4_GRP_A => 16#16_2690# / Register_Width,
2113 PORT_TX_DW4_GRP_B => 16#06_c690# / Register_Width,
2114 PORT_TX_DW4_GRP_C => 16#16_0690# / Register_Width,
2115 PORT_TX_DW5_LN0_A => 16#16_2894# / Register_Width,
2116 PORT_TX_DW5_LN0_B => 16#06_c894# / Register_Width,
2117 PORT_TX_DW5_LN0_C => 16#16_0894# / Register_Width,
2118 PORT_TX_DW5_GRP_A => 16#16_2694# / Register_Width,
2119 PORT_TX_DW5_GRP_B => 16#06_c694# / Register_Width,
2120 PORT_TX_DW5_GRP_C => 16#16_0694# / Register_Width,
2121 PORT_TX_DW7_LN0_A => 16#16_289c# / Register_Width,
2122 PORT_TX_DW7_LN0_B => 16#06_c89c# / Register_Width,
2123 PORT_TX_DW7_LN0_C => 16#16_089c# / Register_Width,
2124 PORT_TX_DW7_GRP_A => 16#16_269c# / Register_Width,
2125 PORT_TX_DW7_GRP_B => 16#06_c69c# / Register_Width,
2126 PORT_TX_DW7_GRP_C => 16#16_069c# / Register_Width,
2127
2128 -- TGL DisplayPort transport
2129 TGL_DP_TP_CTL_A => 16#06_0540# / Register_Width,
2130 TGL_DP_TP_CTL_B => 16#06_1540# / Register_Width,
2131 TGL_DP_TP_CTL_C => 16#06_2540# / Register_Width,
2132 TGL_DP_TP_STATUS_A => 16#06_0544# / Register_Width,
2133 TGL_DP_TP_STATUS_B => 16#06_1544# / Register_Width,
2134 TGL_DP_TP_STATUS_C => 16#06_2544# / Register_Width,
2135 DPCLKA_CFGCR0 => 16#16_4280# / Register_Width,
2136 PORT_CL_DW10_C => 16#16_0028# / Register_Width,
2137
2138 -- MBUS DBOX
2139 PIPE_MBUS_DBOX_CTL_A => 16#07_003c# / Register_Width,
2140 PIPE_MBUS_DBOX_CTL_B => 16#07_103c# / Register_Width,
2141 PIPE_MBUS_DBOX_CTL_C => 16#07_203c# / Register_Width,
2142
2143 -- TGL+ new plane control registers
2144 PLANE_AUX_DIST_1_A => 16#07_01c0# / Register_Width,
2145 PLANE_AUX_DIST_1_B => 16#07_11c0# / Register_Width,
2146 PLANE_AUX_DIST_1_C => 16#07_21c0# / Register_Width,
2147 PLANE_COLOR_CTL_1_A => 16#07_01cc# / Register_Width,
2148 PLANE_COLOR_CTL_1_B => 16#07_11cc# / Register_Width,
2149 PLANE_COLOR_CTL_1_C => 16#07_21cc# / Register_Width,
2150
2151 -- TGL FIA registers
2152 PORT_TX_DFLEXDPCSSS_FIA1 => 16#16_3894# / Register_Width,
2153 PORT_TX_DFLEXDPMLE1_FIA1 => 16#16_38c0# / Register_Width,
2154 PORT_TX_DFLEXDPPMS_FIA1 => 16#16_3890# / Register_Width,
2155 PORT_TX_DFLEXDPSP_FIA1 => 16#16_38a0# / Register_Width,
2156 PORT_TX_DFLEXPA1_FIA1 => 16#16_3880# / Register_Width,
2157 PORT_TX_DFLEXDPCSSS_FIA2 => 16#16_e894# / Register_Width,
2158 PORT_TX_DFLEXDPMLE1_FIA2 => 16#16_e8c0# / Register_Width,
2159 PORT_TX_DFLEXDPPMS_FIA2 => 16#16_e890# / Register_Width,
2160 PORT_TX_DFLEXDPSP_FIA2 => 16#16_e8a0# / Register_Width,
2161 PORT_TX_DFLEXPA1_FIA2 => 16#16_e880# / Register_Width,
2162 PORT_TX_DFLEXDPCSSS_FIA3 => 16#16_f894# / Register_Width,
2163 PORT_TX_DFLEXDPMLE1_FIA3 => 16#16_f8c0# / Register_Width,
2164 PORT_TX_DFLEXDPPMS_FIA3 => 16#16_f890# / Register_Width,
2165 PORT_TX_DFLEXDPSP_FIA3 => 16#16_f8a0# / Register_Width,
2166 PORT_TX_DFLEXPA1_FIA3 => 16#16_f880# / Register_Width,
2167
2168 -- TGL DDI clock select
2169 DDI_CLK_SEL_USBC3 => 16#04_6114# / Register_Width,
2170 DDI_CLK_SEL_USBC4 => 16#04_6118# / Register_Width,
2171 DDI_CLK_SEL_USBC5 => 16#04_611c# / Register_Width,
2172 DDI_CLK_SEL_USBC6 => 16#04_6120# / Register_Width,
2173
2174 -- TGL DKL PLLs
2175 MGPLL1_ENABLE => 16#04_6030# / Register_Width,
2176 MGPLL2_ENABLE => 16#04_6034# / Register_Width,
2177 MGPLL3_ENABLE => 16#04_6038# / Register_Width,
2178 MGPLL4_ENABLE => 16#04_603c# / Register_Width,
2179 MGPLL6_ENABLE => 16#04_6044# / Register_Width,
2180
2181 -- ADL-P DKL PLLs
2182 PORTTC3_PLL1_ENABLE => 16#04_6048# / Register_Width,
2183 PORTTC4_PLL0_ENABLE => 16#04_604c# / Register_Width,
2184 PORTTC4_PLL1_ENABLE => 16#04_6050# / Register_Width,
2185
2186 -- TGL DKL Vswing
2187 DKL_TX_PMD_LANE_SUS_1 => 16#16_8d00# / Register_Width,
2188 DKL_TX_PMD_LANE_SUS_2 => 16#16_9d00# / Register_Width,
2189 DKL_TX_PMD_LANE_SUS_3 => 16#16_ad00# / Register_Width,
2190 DKL_TX_PMD_LANE_SUS_4 => 16#16_bd00# / Register_Width,
2191 DKL_TX_PMD_LANE_SUS_5 => 16#16_cd00# / Register_Width,
2192 DKL_TX_PMD_LANE_SUS_6 => 16#16_dd00# / Register_Width,
2193 DKL_TX_DPCNTL0_1 => 16#16_82c0# / Register_Width,
2194 DKL_TX_DPCNTL0_2 => 16#16_92c0# / Register_Width,
2195 DKL_TX_DPCNTL0_3 => 16#16_a2c0# / Register_Width,
2196 DKL_TX_DPCNTL0_4 => 16#16_b2c0# / Register_Width,
2197 DKL_TX_DPCNTL0_5 => 16#16_c2c0# / Register_Width,
2198 DKL_TX_DPCNTL0_6 => 16#16_d2c0# / Register_Width,
2199 DKL_TX_DPCNTL1_1 => 16#16_82c4# / Register_Width,
2200 DKL_TX_DPCNTL1_2 => 16#16_92c4# / Register_Width,
2201 DKL_TX_DPCNTL1_3 => 16#16_a2c4# / Register_Width,
2202 DKL_TX_DPCNTL1_4 => 16#16_b2c4# / Register_Width,
2203 DKL_TX_DPCNTL1_5 => 16#16_c2c4# / Register_Width,
2204 DKL_TX_DPCNTL1_6 => 16#16_d2c4# / Register_Width,
2205 DKL_TX_DPCNTL2_1 => 16#16_82c8# / Register_Width,
2206 DKL_TX_DPCNTL2_2 => 16#16_92c8# / Register_Width,
2207 DKL_TX_DPCNTL2_3 => 16#16_a2c8# / Register_Width,
2208 DKL_TX_DPCNTL2_4 => 16#16_b2c8# / Register_Width,
2209 DKL_TX_DPCNTL2_5 => 16#16_c2c8# / Register_Width,
2210 DKL_TX_DPCNTL2_6 => 16#16_d2c8# / Register_Width,
2211
2212 -- ADL-P DKL registers
2213 DKL_PCS_DW5_1 => 16#16_8014# / Register_Width,
2214 DKL_PCS_DW5_2 => 16#16_9014# / Register_Width,
2215 DKL_PCS_DW5_3 => 16#16_a014# / Register_Width,
2216 DKL_PCS_DW5_4 => 16#16_b014# / Register_Width,
2217
2218 -- ADL-P DDI status
2219 TCSS_DDI_STATUS_1 => 16#16_1500# / Register_Width,
2220 TCSS_DDI_STATUS_2 => 16#16_1504# / Register_Width,
2221 TCSS_DDI_STATUS_3 => 16#16_1508# / Register_Width,
2222 TCSS_DDI_STATUS_4 => 16#16_150c# / Register_Width,
2223
2224 DISPLAY_ERR_FATAL_MASK => 16#04_421c# / Register_Width,
2225 MBUS_CTL => 16#04_438c# / Register_Width);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2226
2227 subtype Registers_Index is Registers_Invalid_Index range
2228 Registers_Invalid_Index'Succ (Invalid_Register) ..
2229 Registers_Invalid_Index'Last;
2230
2231 -- aliased registers
2232 DP_CTL_A : constant Registers_Index := DDI_BUF_CTL_A;
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]2233 GMCH_DP_B : constant Registers_Index := DDI_BUF_CTL_B;
2234 GMCH_DP_C : constant Registers_Index := DDI_BUF_CTL_C;
2235 GMCH_DP_D : constant Registers_Index := DDI_BUF_CTL_D;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2236 DP_AUX_CTL_A : constant Registers_Index := DDI_AUX_CTL_A;
2237 DP_AUX_DATA_A_1 : constant Registers_Index := DDI_AUX_DATA_A_1;
2238 DP_AUX_DATA_A_2 : constant Registers_Index := DDI_AUX_DATA_A_2;
2239 DP_AUX_DATA_A_3 : constant Registers_Index := DDI_AUX_DATA_A_3;
2240 DP_AUX_DATA_A_4 : constant Registers_Index := DDI_AUX_DATA_A_4;
2241 DP_AUX_DATA_A_5 : constant Registers_Index := DDI_AUX_DATA_A_5;
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]2242 ILK_DISPLAY_CHICKEN1 : constant Registers_Index := FUSE_STATUS;
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]2243 GMCH_ADPA : constant Registers_Index := FDI_TX_CTL_B;
2244 GMCH_HDMIB : constant Registers_Index := GMCH_SDVOB;
2245 GMCH_HDMIC : constant Registers_Index := GMCH_SDVOC;
Nico Huber75a707f2018-06-18 16:28:33 +0200[diff] [blame]2246 CURACNTR : constant Registers_Index := CUR_CTL_A;
2247 CURABASE : constant Registers_Index := CUR_BASE_A;
2248 CURAPOS : constant Registers_Index := CUR_POS_A;
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]2249 BXT_BLC_PWM_CTL_1 : constant Registers_Index := BLC_PWM_PCH_CTL1;
2250 BXT_BLC_PWM_FREQ_1 : constant Registers_Index := BLC_PWM_PCH_CTL2;
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]2251 PHY_MISC_A : constant Registers_Index := BXT_PHY_CTL_A;
2252 PORT_COMP_DW0_B : constant Registers_Index := BXT_PORT_PLL_0_B;
2253 PORT_COMP_DW1_B : constant Registers_Index := BXT_PORT_PLL_1_B;
2254 PORT_COMP_DW3_B : constant Registers_Index := BXT_PORT_PLL_3_B;
2255 PORT_COMP_DW0_A : constant Registers_Index := BXT_PORT_PLL_0_A;
2256 PORT_COMP_DW1_A : constant Registers_Index := BXT_PORT_PLL_1_A;
2257 PORT_COMP_DW3_A : constant Registers_Index := BXT_PORT_PLL_3_A;
2258 PORT_COMP_DW9_A : constant Registers_Index := BXT_PORT_PLL_9_A;
2259 PORT_COMP_DW9_B : constant Registers_Index := BXT_PORT_PLL_9_B;
2260 PORT_COMP_DW8_A : constant Registers_Index := BXT_PORT_PLL_8_A;
2261 PORT_COMP_DW8_B : constant Registers_Index := BXT_PORT_PLL_8_B;
2262 PORT_COMP_DW10_A : constant Registers_Index := BXT_PORT_PLL_10_A;
2263 PORT_COMP_DW10_B : constant Registers_Index := BXT_PORT_PLL_10_B;
2264 CDCLK_PLL_ENABLE : constant Registers_Index := BXT_DE_PLL_ENABLE;
2265 DDI_AUX_CTL_USBC1 : constant Registers_Index := DDI_AUX_CTL_D;
2266 DDI_AUX_DATA_USBC1_1 : constant Registers_Index := DDI_AUX_DATA_D_1;
2267 DDI_AUX_DATA_USBC1_2 : constant Registers_Index := DDI_AUX_DATA_D_2;
2268 DDI_AUX_DATA_USBC1_3 : constant Registers_Index := DDI_AUX_DATA_D_3;
2269 DDI_AUX_DATA_USBC1_4 : constant Registers_Index := DDI_AUX_DATA_D_4;
2270 DDI_AUX_DATA_USBC1_5 : constant Registers_Index := DDI_AUX_DATA_D_5;
2271 DPLL_0_ENABLE : constant Registers_Index := LCPLL1_CTL;
2272 DPLL_1_ENABLE : constant Registers_Index := LCPLL2_CTL;
2273 PORT_CL_DW10_A : constant Registers_Index := BXT_PORT_CL1CM_DW10_A;
2274 PORT_CL_DW10_B : constant Registers_Index := BXT_PORT_CL1CM_DW10_BC;
2275 DDI_CLK_SEL_USBC1 : constant Registers_Index := PORT_CLK_SEL_DDID;
2276 DDI_CLK_SEL_USBC2 : constant Registers_Index := PORT_CLK_SEL_DDIE;
2277 MGPLL5_ENABLE : constant Registers_Index := WRPLL_CTL_1;
2278 DDI_BUF_CTL_USBC1 : constant Registers_Index := DDI_BUF_CTL_D;
2279 DDI_BUF_CTL_USBC2 : constant Registers_Index := DDI_BUF_CTL_E;
2280 DDI_BUF_CTL_USBC6 : constant Registers_Index := SRD_CTL;
2281 PORTTC1_PLL0_ENABLE : constant Registers_Index := MGPLL2_ENABLE;
2282 PORTTC1_PLL1_ENABLE : constant Registers_Index := MGPLL3_ENABLE;
2283 PORTTC2_PLL0_ENABLE : constant Registers_Index := MGPLL4_ENABLE;
2284 PORTTC2_PLL1_ENABLE : constant Registers_Index := WRPLL_CTL_1;
2285 PORTTC3_PLL0_ENABLE : constant Registers_Index := MGPLL6_ENABLE;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2286
2287 ---------------------------------------------------------------------------
2288
2289 Default_Timeout_MS : constant := 10;
2290
2291 ---------------------------------------------------------------------------
2292
2293 procedure Posting_Read
2294 (Register : in Registers_Index)
2295 with
2296 Global => (In_Out => Register_State),
2297 Depends => (Register_State =>+ (Register)),
2298 Pre => True,
2299 Post => True;
2300
2301 pragma Warnings (GNATprove, Off, "unused variable ""Verbose""",
2302 Reason => "Only used on debugging path");
2303 procedure Read
2304 (Register : in Registers_Index;
2305 Value : out Word32;
2306 Verbose : in Boolean := True)
2307 with
2308 Global => (In_Out => Register_State),
2309 Depends => ((Value, Register_State) => (Register, Register_State),
2310 null => Verbose),
2311 Pre => True,
2312 Post => True;
2313 pragma Warnings (GNATprove, On, "unused variable ""Verbose""");
2314
Arthur Heymans3f37cce2026-03-03 18:52:12 +0100[diff] [blame^]2315 procedure Read_AUD_VID_DID (Value : out Word32)
2316 with
2317 Global => (In_Out => Register_State),
2318 Depends => ((Value, Register_State) => Register_State),
2319 Pre => True,
2320 Post => True;
2321
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2322 procedure Write
2323 (Register : Registers_Index;
2324 Value : Word32)
2325 with
2326 Global => (In_Out => Register_State),
2327 Depends => (Register_State => (Register, Register_State, Value)),
2328 Pre => True,
2329 Post => True;
2330
2331 procedure Is_Set_Mask
2332 (Register : in Registers_Index;
2333 Mask : in Word32;
2334 Result : out Boolean);
2335
2336 pragma Warnings (GNATprove, Off, "unused initial value of ""Verbose""",
2337 Reason => "Only used on debugging path");
Nico Huberbcb2c472017-02-02 16:39:26 +0100[diff] [blame]2338 procedure Wait
Nico Huber82ca09f2019-09-28 02:37:50 +0200[diff] [blame]2339 (Register : in Registers_Index;
2340 Mask : in Word32;
2341 Value : in Word32;
2342 TOut_MS : in Natural := Default_Timeout_MS;
2343 Verbose : in Boolean := False;
2344 Success : out Boolean);
2345 procedure Wait
Nico Huberbcb2c472017-02-02 16:39:26 +0100[diff] [blame]2346 (Register : Registers_Index;
2347 Mask : Word32;
2348 Value : Word32;
2349 TOut_MS : Natural := Default_Timeout_MS;
2350 Verbose : Boolean := False);
2351
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2352 procedure Wait_Set_Mask
Nico Huber82ca09f2019-09-28 02:37:50 +0200[diff] [blame]2353 (Register : in Registers_Index;
2354 Mask : in Word32;
2355 TOut_MS : in Natural := Default_Timeout_MS;
2356 Verbose : in Boolean := False;
2357 Success : out Boolean);
2358 procedure Wait_Set_Mask
2359 (Register : Registers_Index;
2360 Mask : Word32;
2361 TOut_MS : Natural := Default_Timeout_MS;
2362 Verbose : Boolean := False);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2363
2364 procedure Wait_Unset_Mask
Nico Huber82ca09f2019-09-28 02:37:50 +0200[diff] [blame]2365 (Register : in Registers_Index;
2366 Mask : in Word32;
2367 TOut_MS : in Natural := Default_Timeout_MS;
2368 Verbose : in Boolean := False;
2369 Success : out Boolean);
2370 procedure Wait_Unset_Mask
2371 (Register : Registers_Index;
2372 Mask : Word32;
2373 TOut_MS : Natural := Default_Timeout_MS;
2374 Verbose : Boolean := False);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2375 pragma Warnings (GNATprove, On, "unused initial value of ""Verbose""");
2376
2377 procedure Set_Mask
2378 (Register : Registers_Index;
2379 Mask : Word32);
2380
2381 procedure Unset_Mask
2382 (Register : Registers_Index;
2383 Mask : Word32);
2384
2385 procedure Unset_And_Set_Mask
2386 (Register : Registers_Index;
2387 Mask_Unset : Word32;
2388 Mask_Set : Word32);
2389
Nico Huber17d64b62017-07-15 20:51:25 +0200[diff] [blame]2390 procedure Clear_Fences;
2391
Nico Huberb03c8f12017-08-25 13:29:08 +0200[diff] [blame]2392 procedure Add_Fence
2393 (First_Page : in GTT_Range;
2394 Last_Page : in GTT_Range;
2395 Tiling : in XY_Tiling;
2396 Pitch : in Natural;
Arthur Heymans960e2392026-03-03 19:45:24 +0100[diff] [blame]2397 Success : out Boolean)
2398 with
2399 Pre => Last_Page >= First_Page;
Nico Huberb03c8f12017-08-25 13:29:08 +0200[diff] [blame]2400
2401 procedure Remove_Fence (First_Page, Last_Page : GTT_Range);
2402
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]2403 pragma Warnings (GNATprove, Off, "no check message justified by this",
2404 Reason => "see Annotate aspects.");
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2405 procedure Write_GTT
2406 (GTT_Page : GTT_Range;
2407 Device_Address : GTT_Address_Type;
2408 Valid : Boolean)
2409 with
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]2410 Global =>
2411 (Input => Config.Variable,
2412 In_Out => GTT_State),
2413 Depends =>
2414 (GTT_State =>+ (Config.Variable, GTT_Page, Device_Address, Valid)),
2415 Annotate =>
2416 (GNATprove, Intentional,
Nico Hubere317e9c2019-09-29 03:03:18 +0200[diff] [blame]2417 """GMA.State"" of ""Write_GTT"" not read",
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]2418 "Reading of Config_State depends on the platform configuration.");
Nico Huberceda17d2018-06-09 22:00:29 +0200[diff] [blame]2419
2420 procedure Read_GTT
2421 (Device_Address : out GTT_Address_Type;
2422 Valid : out Boolean;
2423 GTT_Page : in GTT_Range)
2424 with
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]2425 Global =>
2426 (Input => Config.Variable,
2427 In_Out => GTT_State),
2428 Depends =>
2429 ((Device_Address, Valid, GTT_State) =>
2430 (Config.Variable, GTT_State, GTT_Page)),
2431 Annotate =>
2432 (GNATprove, Intentional,
Nico Hubere317e9c2019-09-29 03:03:18 +0200[diff] [blame]2433 """GMA.State"" of ""Read_GTT"" not read",
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]2434 "Reading of Config_State depends on the platform configuration.");
2435 pragma Warnings (GNATprove, On, "no check message justified by this");
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2436
Nico Huber2b6f6992017-07-09 18:11:34 +0200[diff] [blame]2437 procedure Set_Register_Base (Base : Word64; GTT_Base : Word64 := 0)
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2438 with
2439 Global => (Output => Address_State),
Nico Huber2b6f6992017-07-09 18:11:34 +0200[diff] [blame]2440 Depends => (Address_State => (Base, GTT_Base)),
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2441 Pre => True,
2442 Post => True;
2443
2444end HW.GFX.GMA.Registers;