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review.sourcearcade.org / libgfxinit / dfcdd77f8e9b7c499a7a89de7d0d4dc29a3fc91f / . / common / hw-gfx-gma-registers.ads
blob: 1515fab9e6e9ac9ed3171a54d3ae8cf335062e15 [file] [log] [blame]
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1--
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]2-- Copyright (C) 2015-2017 secunet Security Networks AG
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
Nico Huber125a29e2016-10-18 00:23:54 +0200[diff] [blame]6-- the Free Software Foundation; either version 2 of the License, or
7-- (at your option) any later version.
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]8--
9-- This program is distributed in the hope that it will be useful,
10-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12-- GNU General Public License for more details.
13--
14
15with System;
16with HW.GFX.GMA;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]17
18private package HW.GFX.GMA.Registers
19with
20 Abstract_State =>
21 ((Address_State with Part_Of => GMA.State),
22 (Register_State with External, Part_Of => GMA.Device_State),
23 (GTT_State with External, Part_Of => GMA.Device_State)),
24 Initializes => Address_State
25is
26 type Registers_Invalid_Index is
27 (Invalid_Register, -- Allow a placeholder when access is not acceptable
28
29 RCS_RING_BUFFER_TAIL,
30 RCS_RING_BUFFER_HEAD,
31 RCS_RING_BUFFER_STRT,
32 RCS_RING_BUFFER_CTL,
33 QUIRK_02084,
34 QUIRK_02090,
35 HWSTAM,
36 MI_MODE,
37 INSTPM,
38 GT_MODE,
39 CACHE_MODE_0,
40 CTX_SIZE,
41 PP_DCLV_HIGH,
42 PP_DCLV_LOW,
43 GFX_MODE,
44 ARB_MODE,
45 HWS_PGA,
46 GAM_ECOCHK,
47 MBCTL,
48 UCGCTL1,
49 UCGCTL2,
50 VCS_RING_BUFFER_TAIL,
51 VCS_RING_BUFFER_HEAD,
52 VCS_RING_BUFFER_STRT,
53 VCS_RING_BUFFER_CTL,
54 SLEEP_PSMI_CONTROL,
55 VCS_HWSTAM,
56 VCS_PP_DCLV_HIGH,
57 VCS_PP_DCLV_LOW,
58 GAC_ECO_BITS,
59 BCS_RING_BUFFER_TAIL,
60 BCS_RING_BUFFER_HEAD,
61 BCS_RING_BUFFER_STRT,
62 BCS_RING_BUFFER_CTL,
63 BCS_HWSTAM,
64 BCS_PP_DCLV_HIGH,
65 BCS_PP_DCLV_LOW,
66 GAB_CTL_REG,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame^]67 CPU_VGACNTRL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]68 FUSE_STATUS,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]69 ILK_DISPLAY_CHICKEN2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]70 DSPCLK_GATE_D,
71 FBA_CFB_BASE,
72 FBC_CTL,
73 IPS_CTL,
74 DEISR,
75 DEIMR,
76 DEIIR,
77 DEIER,
78 GTISR,
79 GTIMR,
80 GTIIR,
81 GTIER,
82 IIR,
83 HOTPLUG_CTL,
84 ARB_CTL,
85 DBUF_CTL,
86 WM_PIPE_A,
87 WM_PIPE_B,
88 WM1_LP_ILK,
89 WM2_LP_ILK,
90 WM3_LP_ILK,
91 WM_PIPE_C,
92 WM_LINETIME_A,
93 WM_LINETIME_B,
94 WM_LINETIME_C,
95 PWR_WELL_CTL_BIOS,
96 PWR_WELL_CTL_DRIVER,
97 PWR_WELL_CTL_KVMR,
98 PWR_WELL_CTL_DEBUG,
99 PWR_WELL_CTL5,
100 PWR_WELL_CTL6,
101 CDCLK_CTL,
102 LCPLL1_CTL,
103 LCPLL2_CTL,
104 SPLL_CTL,
105 WRPLL_CTL_1,
106 WRPLL_CTL_2,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]107 BXT_DE_PLL_ENABLE,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]108 BXT_PORT_PLL_ENABLE_A,
109 BXT_PORT_PLL_ENABLE_B,
110 BXT_PORT_PLL_ENABLE_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]111 PORT_CLK_SEL_DDIA,
112 PORT_CLK_SEL_DDIB,
113 PORT_CLK_SEL_DDIC,
114 PORT_CLK_SEL_DDID,
115 PORT_CLK_SEL_DDIE,
116 TRANSA_CLK_SEL,
117 TRANSB_CLK_SEL,
118 TRANSC_CLK_SEL,
119 NDE_RSTWRN_OPT,
120 BLC_PWM_CPU_CTL2,
121 BLC_PWM_CPU_CTL,
122 HTOTAL_A,
123 HBLANK_A,
124 HSYNC_A,
125 VTOTAL_A,
126 VBLANK_A,
127 VSYNC_A,
128 PIPEASRC,
129 PIPE_VSYNCSHIFT_A,
130 PIPEA_DATA_M1,
131 PIPEA_DATA_N1,
132 PIPEA_LINK_M1,
133 PIPEA_LINK_N1,
134 FDI_TX_CTL_A,
135 PIPEA_DDI_FUNC_CTL,
136 PIPEA_MSA_MISC,
137 SRD_CTL_A,
138 SRD_STATUS_A,
139 HTOTAL_B,
140 HBLANK_B,
141 HSYNC_B,
142 VTOTAL_B,
143 VBLANK_B,
144 VSYNC_B,
145 PIPEBSRC,
146 PIPE_VSYNCSHIFT_B,
147 PIPEB_DATA_M1,
148 PIPEB_DATA_N1,
149 PIPEB_LINK_M1,
150 PIPEB_LINK_N1,
151 FDI_TX_CTL_B,
152 PIPEB_DDI_FUNC_CTL,
153 PIPEB_MSA_MISC,
154 SRD_CTL_B,
155 SRD_STATUS_B,
156 HTOTAL_C,
157 HBLANK_C,
158 HSYNC_C,
159 VTOTAL_C,
160 VBLANK_C,
161 VSYNC_C,
162 PIPECSRC,
163 PIPE_VSYNCSHIFT_C,
164 PIPEC_DATA_M1,
165 PIPEC_DATA_N1,
166 PIPEC_LINK_M1,
167 PIPEC_LINK_N1,
168 FDI_TX_CTL_C,
169 PIPEC_DDI_FUNC_CTL,
170 PIPEC_MSA_MISC,
171 SRD_CTL_C,
172 SRD_STATUS_C,
173 DDI_BUF_CTL_A,
174 DDI_AUX_CTL_A,
175 DDI_AUX_DATA_A_1,
176 DDI_AUX_DATA_A_2,
177 DDI_AUX_DATA_A_3,
178 DDI_AUX_DATA_A_4,
179 DDI_AUX_DATA_A_5,
180 DDI_AUX_MUTEX_A,
181 DP_TP_CTL_A,
182 DDI_BUF_CTL_B,
183 DDI_AUX_CTL_B,
184 DDI_AUX_DATA_B_1,
185 DDI_AUX_DATA_B_2,
186 DDI_AUX_DATA_B_3,
187 DDI_AUX_DATA_B_4,
188 DDI_AUX_DATA_B_5,
189 DDI_AUX_MUTEX_B,
190 DP_TP_CTL_B,
191 DP_TP_STATUS_B,
192 DDI_BUF_CTL_C,
193 DDI_AUX_CTL_C,
194 DDI_AUX_DATA_C_1,
195 DDI_AUX_DATA_C_2,
196 DDI_AUX_DATA_C_3,
197 DDI_AUX_DATA_C_4,
198 DDI_AUX_DATA_C_5,
199 DDI_AUX_MUTEX_C,
200 DP_TP_CTL_C,
201 DP_TP_STATUS_C,
202 DDI_BUF_CTL_D,
203 DDI_AUX_CTL_D,
204 DDI_AUX_DATA_D_1,
205 DDI_AUX_DATA_D_2,
206 DDI_AUX_DATA_D_3,
207 DDI_AUX_DATA_D_4,
208 DDI_AUX_DATA_D_5,
209 DDI_AUX_MUTEX_D,
210 DP_TP_CTL_D,
211 DP_TP_STATUS_D,
212 DDI_BUF_CTL_E,
213 DP_TP_CTL_E,
214 DP_TP_STATUS_E,
215 SRD_CTL,
216 SRD_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]217 BXT_PHY_CTL_A,
218 BXT_PHY_CTL_B,
219 BXT_PHY_CTL_C,
220 BXT_PHY_CTL_FAM_EDP,
221 BXT_PHY_CTL_FAM_DDI,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]222 DDI_BUF_TRANS_A_S0T1,
223 DDI_BUF_TRANS_A_S0T2,
224 DDI_BUF_TRANS_A_S1T1,
225 DDI_BUF_TRANS_A_S1T2,
226 DDI_BUF_TRANS_A_S2T1,
227 DDI_BUF_TRANS_A_S2T2,
228 DDI_BUF_TRANS_A_S3T1,
229 DDI_BUF_TRANS_A_S3T2,
230 DDI_BUF_TRANS_A_S4T1,
231 DDI_BUF_TRANS_A_S4T2,
232 DDI_BUF_TRANS_A_S5T1,
233 DDI_BUF_TRANS_A_S5T2,
234 DDI_BUF_TRANS_A_S6T1,
235 DDI_BUF_TRANS_A_S6T2,
236 DDI_BUF_TRANS_A_S7T1,
237 DDI_BUF_TRANS_A_S7T2,
238 DDI_BUF_TRANS_A_S8T1,
239 DDI_BUF_TRANS_A_S8T2,
240 DDI_BUF_TRANS_A_S9T1,
241 DDI_BUF_TRANS_A_S9T2,
242 DDI_BUF_TRANS_B_S0T1,
243 DDI_BUF_TRANS_B_S0T2,
244 DDI_BUF_TRANS_B_S1T1,
245 DDI_BUF_TRANS_B_S1T2,
246 DDI_BUF_TRANS_B_S2T1,
247 DDI_BUF_TRANS_B_S2T2,
248 DDI_BUF_TRANS_B_S3T1,
249 DDI_BUF_TRANS_B_S3T2,
250 DDI_BUF_TRANS_B_S4T1,
251 DDI_BUF_TRANS_B_S4T2,
252 DDI_BUF_TRANS_B_S5T1,
253 DDI_BUF_TRANS_B_S5T2,
254 DDI_BUF_TRANS_B_S6T1,
255 DDI_BUF_TRANS_B_S6T2,
256 DDI_BUF_TRANS_B_S7T1,
257 DDI_BUF_TRANS_B_S7T2,
258 DDI_BUF_TRANS_B_S8T1,
259 DDI_BUF_TRANS_B_S8T2,
260 DDI_BUF_TRANS_B_S9T1,
261 DDI_BUF_TRANS_B_S9T2,
262 DDI_BUF_TRANS_C_S0T1,
263 DDI_BUF_TRANS_C_S0T2,
264 DDI_BUF_TRANS_C_S1T1,
265 DDI_BUF_TRANS_C_S1T2,
266 DDI_BUF_TRANS_C_S2T1,
267 DDI_BUF_TRANS_C_S2T2,
268 DDI_BUF_TRANS_C_S3T1,
269 DDI_BUF_TRANS_C_S3T2,
270 DDI_BUF_TRANS_C_S4T1,
271 DDI_BUF_TRANS_C_S4T2,
272 DDI_BUF_TRANS_C_S5T1,
273 DDI_BUF_TRANS_C_S5T2,
274 DDI_BUF_TRANS_C_S6T1,
275 DDI_BUF_TRANS_C_S6T2,
276 DDI_BUF_TRANS_C_S7T1,
277 DDI_BUF_TRANS_C_S7T2,
278 DDI_BUF_TRANS_C_S8T1,
279 DDI_BUF_TRANS_C_S8T2,
280 DDI_BUF_TRANS_C_S9T1,
281 DDI_BUF_TRANS_C_S9T2,
282 DDI_BUF_TRANS_D_S0T1,
283 DDI_BUF_TRANS_D_S0T2,
284 DDI_BUF_TRANS_D_S1T1,
285 DDI_BUF_TRANS_D_S1T2,
286 DDI_BUF_TRANS_D_S2T1,
287 DDI_BUF_TRANS_D_S2T2,
288 DDI_BUF_TRANS_D_S3T1,
289 DDI_BUF_TRANS_D_S3T2,
290 DDI_BUF_TRANS_D_S4T1,
291 DDI_BUF_TRANS_D_S4T2,
292 DDI_BUF_TRANS_D_S5T1,
293 DDI_BUF_TRANS_D_S5T2,
294 DDI_BUF_TRANS_D_S6T1,
295 DDI_BUF_TRANS_D_S6T2,
296 DDI_BUF_TRANS_D_S7T1,
297 DDI_BUF_TRANS_D_S7T2,
298 DDI_BUF_TRANS_D_S8T1,
299 DDI_BUF_TRANS_D_S8T2,
300 DDI_BUF_TRANS_D_S9T1,
301 DDI_BUF_TRANS_D_S9T2,
302 DDI_BUF_TRANS_E_S0T1,
303 DDI_BUF_TRANS_E_S0T2,
304 DDI_BUF_TRANS_E_S1T1,
305 DDI_BUF_TRANS_E_S1T2,
306 DDI_BUF_TRANS_E_S2T1,
307 DDI_BUF_TRANS_E_S2T2,
308 DDI_BUF_TRANS_E_S3T1,
309 DDI_BUF_TRANS_E_S3T2,
310 DDI_BUF_TRANS_E_S4T1,
311 DDI_BUF_TRANS_E_S4T2,
312 DDI_BUF_TRANS_E_S5T1,
313 DDI_BUF_TRANS_E_S5T2,
314 DDI_BUF_TRANS_E_S6T1,
315 DDI_BUF_TRANS_E_S6T2,
316 DDI_BUF_TRANS_E_S7T1,
317 DDI_BUF_TRANS_E_S7T2,
318 DDI_BUF_TRANS_E_S8T1,
319 DDI_BUF_TRANS_E_S8T2,
320 DDI_BUF_TRANS_E_S9T1,
321 DDI_BUF_TRANS_E_S9T2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]322 AUD_VID_DID,
323 PFA_WIN_POS,
324 PFA_WIN_SZ,
325 PFA_CTL_1,
326 PS_WIN_POS_1_A,
327 PS_WIN_SZ_1_A,
328 PS_CTRL_1_A,
329 PS_WIN_POS_2_A,
330 PS_WIN_SZ_2_A,
331 PS_CTRL_2_A,
332 PFB_WIN_POS,
333 PFB_WIN_SZ,
334 PFB_CTL_1,
335 PS_WIN_POS_1_B,
336 PS_WIN_SZ_1_B,
337 PS_CTRL_1_B,
338 PS_WIN_POS_2_B,
339 PS_WIN_SZ_2_B,
340 PS_CTRL_2_B,
341 PFC_WIN_POS,
342 PFC_WIN_SZ,
343 PFC_CTL_1,
344 PS_WIN_POS_1_C,
345 PS_WIN_SZ_1_C,
346 PS_CTRL_1_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]347 BXT_PORT_CL1CM_DW0_BC,
Nico Huber58afc202017-06-12 21:34:55 +0200[diff] [blame]348 DISPIO_CR_TX_BMU_CR0,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]349 BXT_PORT_CL1CM_DW9_BC,
350 BXT_PORT_CL1CM_DW10_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]351 BXT_PORT_PLL_EBB_0_B,
352 BXT_PORT_PLL_EBB_4_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]353 DPLL1_CFGR1,
354 DPLL1_CFGR2,
355 DPLL2_CFGR1,
356 DPLL2_CFGR2,
357 DPLL3_CFGR1,
358 DPLL3_CFGR2,
359 DPLL_CTRL1,
360 DPLL_CTRL2,
361 DPLL_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]362 BXT_PORT_CL1CM_DW28_BC,
363 BXT_PORT_CL1CM_DW30_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]364 BXT_PORT_PLL_0_B,
365 BXT_PORT_PLL_1_B,
366 BXT_PORT_PLL_2_B,
367 BXT_PORT_PLL_3_B,
368 BXT_PORT_PLL_6_B,
369 BXT_PORT_PLL_8_B,
370 BXT_PORT_PLL_9_B,
371 BXT_PORT_PLL_10_B,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]372 BXT_PORT_REF_DW3_BC,
373 BXT_PORT_REF_DW6_BC,
374 BXT_PORT_REF_DW8_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]375 BXT_PORT_PLL_EBB_0_C,
376 BXT_PORT_PLL_EBB_4_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]377 BXT_PORT_CL2CM_DW6_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]378 BXT_PORT_PLL_0_C,
379 BXT_PORT_PLL_1_C,
380 BXT_PORT_PLL_2_C,
381 BXT_PORT_PLL_3_C,
382 BXT_PORT_PLL_6_C,
383 BXT_PORT_PLL_8_C,
384 BXT_PORT_PLL_9_C,
385 BXT_PORT_PLL_10_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]386 BXT_PORT_PCS_DW10_01_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]387 BXT_PORT_PCS_DW12_01_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]388 BXT_PORT_TX_DW2_LN0_B,
389 BXT_PORT_TX_DW3_LN0_B,
390 BXT_PORT_TX_DW4_LN0_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]391 BXT_PORT_TX_DW14_LN0_B,
392 BXT_PORT_TX_DW14_LN1_B,
393 BXT_PORT_TX_DW14_LN2_B,
394 BXT_PORT_TX_DW14_LN3_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]395 BXT_PORT_PCS_DW10_01_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]396 BXT_PORT_PCS_DW12_01_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]397 BXT_PORT_TX_DW2_LN0_C,
398 BXT_PORT_TX_DW3_LN0_C,
399 BXT_PORT_TX_DW4_LN0_C,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]400 BXT_PORT_TX_DW14_LN0_C,
401 BXT_PORT_TX_DW14_LN1_C,
402 BXT_PORT_TX_DW14_LN2_C,
403 BXT_PORT_TX_DW14_LN3_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]404 BXT_PORT_PCS_DW10_GRP_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]405 BXT_PORT_PCS_DW12_GRP_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]406 BXT_PORT_TX_DW2_GRP_B,
407 BXT_PORT_TX_DW3_GRP_B,
408 BXT_PORT_TX_DW4_GRP_B,
409 BXT_PORT_PCS_DW10_GRP_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]410 BXT_PORT_PCS_DW12_GRP_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]411 BXT_PORT_TX_DW2_GRP_C,
412 BXT_PORT_TX_DW3_GRP_C,
413 BXT_PORT_TX_DW4_GRP_C,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]414 BXT_DE_PLL_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]415 HTOTAL_EDP,
416 HBLANK_EDP,
417 HSYNC_EDP,
418 VTOTAL_EDP,
419 VBLANK_EDP,
420 VSYNC_EDP,
421 PIPE_EDP_DATA_M1,
422 PIPE_EDP_DATA_N1,
423 PIPE_EDP_LINK_M1,
424 PIPE_EDP_LINK_N1,
425 PIPE_EDP_DDI_FUNC_CTL,
426 PIPE_EDP_MSA_MISC,
427 SRD_CTL_EDP,
428 SRD_STATUS_EDP,
429 PIPE_SCANLINE_A,
430 PIPEACONF,
431 PIPEAMISC,
432 PIPE_FRMCNT_A,
433 DSPACNTR,
434 DSPALINOFF,
435 DSPASTRIDE,
436 PLANE_POS_1_A,
437 PLANE_SIZE_1_A,
438 DSPASURF,
439 DSPATILEOFF,
440 PLANE_WM_1_A_0,
441 PLANE_WM_1_A_1,
442 PLANE_WM_1_A_2,
443 PLANE_WM_1_A_3,
444 PLANE_WM_1_A_4,
445 PLANE_WM_1_A_5,
446 PLANE_WM_1_A_6,
447 PLANE_WM_1_A_7,
448 PLANE_BUF_CFG_1_A,
449 SPACNTR,
450 PIPE_SCANLINE_B,
451 PIPEBCONF,
452 PIPEBMISC,
453 PIPE_FRMCNT_B,
454 DSPBCNTR,
455 DSPBLINOFF,
456 DSPBSTRIDE,
457 PLANE_POS_1_B,
458 PLANE_SIZE_1_B,
459 DSPBSURF,
460 DSPBTILEOFF,
461 PLANE_WM_1_B_0,
462 PLANE_WM_1_B_1,
463 PLANE_WM_1_B_2,
464 PLANE_WM_1_B_3,
465 PLANE_WM_1_B_4,
466 PLANE_WM_1_B_5,
467 PLANE_WM_1_B_6,
468 PLANE_WM_1_B_7,
469 PLANE_BUF_CFG_1_B,
470 SPBCNTR,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame^]471 GMCH_VGACNTRL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]472 PIPE_SCANLINE_C,
473 PIPECCONF,
474 PIPECMISC,
475 PIPE_FRMCNT_C,
476 DSPCCNTR,
477 DSPCLINOFF,
478 DSPCSTRIDE,
479 PLANE_POS_1_C,
480 PLANE_SIZE_1_C,
481 DSPCSURF,
482 DSPCTILEOFF,
483 PLANE_WM_1_C_0,
484 PLANE_WM_1_C_1,
485 PLANE_WM_1_C_2,
486 PLANE_WM_1_C_3,
487 PLANE_WM_1_C_4,
488 PLANE_WM_1_C_5,
489 PLANE_WM_1_C_6,
490 PLANE_WM_1_C_7,
491 PLANE_BUF_CFG_1_C,
492 SPCCNTR,
493 PIPE_EDP_CONF,
494 PCH_FDI_CHICKEN_B_C,
495 QUIRK_C2004,
496 SFUSE_STRAP,
497 PCH_DSPCLK_GATE_D,
498 SDEISR,
499 SDEIMR,
500 SDEIIR,
501 SDEIER,
502 SHOTPLUG_CTL,
503 PCH_GMBUS0,
504 PCH_GMBUS1,
505 PCH_GMBUS2,
506 PCH_GMBUS3,
507 PCH_GMBUS4,
508 PCH_GMBUS5,
509 SBI_ADDR,
510 SBI_DATA,
511 SBI_CTL_STAT,
512 PCH_DPLL_A,
513 PCH_DPLL_B,
514 PCH_PIXCLK_GATE,
515 PCH_FPA0,
516 PCH_FPA1,
517 PCH_FPB0,
518 PCH_FPB1,
519 PCH_DREF_CONTROL,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]520 PCH_RAWCLK_FREQ,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]521 PCH_DPLL_SEL,
522 PCH_PP_STATUS,
523 PCH_PP_CONTROL,
524 PCH_PP_ON_DELAYS,
525 PCH_PP_OFF_DELAYS,
526 PCH_PP_DIVISOR,
527 BLC_PWM_PCH_CTL1,
528 BLC_PWM_PCH_CTL2,
529 TRANS_HTOTAL_A,
530 TRANS_HBLANK_A,
531 TRANS_HSYNC_A,
532 TRANS_VTOTAL_A,
533 TRANS_VBLANK_A,
534 TRANS_VSYNC_A,
535 TRANS_VSYNCSHIFT_A,
536 TRANSA_DATA_M1,
537 TRANSA_DATA_N1,
538 TRANSA_DP_LINK_M1,
539 TRANSA_DP_LINK_N1,
540 TRANS_DP_CTL_A,
541 TRANS_HTOTAL_B,
542 TRANS_HBLANK_B,
543 TRANS_HSYNC_B,
544 TRANS_VTOTAL_B,
545 TRANS_VBLANK_B,
546 TRANS_VSYNC_B,
547 TRANS_VSYNCSHIFT_B,
548 TRANSB_DATA_M1,
549 TRANSB_DATA_N1,
550 TRANSB_DP_LINK_M1,
551 TRANSB_DP_LINK_N1,
552 PCH_ADPA,
553 PCH_HDMIB,
554 PCH_HDMIC,
555 PCH_HDMID,
556 PCH_LVDS,
557 TRANS_DP_CTL_B,
558 TRANS_HTOTAL_C,
559 TRANS_HBLANK_C,
560 TRANS_HSYNC_C,
561 TRANS_VTOTAL_C,
562 TRANS_VBLANK_C,
563 TRANS_VSYNC_C,
564 TRANS_VSYNCSHIFT_C,
565 TRANSC_DATA_M1,
566 TRANSC_DATA_N1,
567 TRANSC_DP_LINK_M1,
568 TRANSC_DP_LINK_N1,
569 TRANS_DP_CTL_C,
570 PCH_DP_B,
571 PCH_DP_AUX_CTL_B,
572 PCH_DP_AUX_DATA_B_1,
573 PCH_DP_AUX_DATA_B_2,
574 PCH_DP_AUX_DATA_B_3,
575 PCH_DP_AUX_DATA_B_4,
576 PCH_DP_AUX_DATA_B_5,
577 PCH_DP_C,
578 PCH_DP_AUX_CTL_C,
579 PCH_DP_AUX_DATA_C_1,
580 PCH_DP_AUX_DATA_C_2,
581 PCH_DP_AUX_DATA_C_3,
582 PCH_DP_AUX_DATA_C_4,
583 PCH_DP_AUX_DATA_C_5,
584 PCH_DP_D,
585 PCH_DP_AUX_CTL_D,
586 PCH_DP_AUX_DATA_D_1,
587 PCH_DP_AUX_DATA_D_2,
588 PCH_DP_AUX_DATA_D_3,
589 PCH_DP_AUX_DATA_D_4,
590 PCH_DP_AUX_DATA_D_5,
591 AUD_CONFIG_A,
592 PCH_AUD_VID_DID,
593 AUD_HDMIW_HDMIEDID_A,
594 AUD_CNTL_ST_A,
595 AUD_CNTRL_ST2,
596 AUD_CONFIG_B,
597 AUD_HDMIW_HDMIEDID_B,
598 AUD_CNTL_ST_B,
599 AUD_CONFIG_C,
600 AUD_HDMIW_HDMIEDID_C,
601 AUD_CNTL_ST_C,
602 TRANSACONF,
603 FDI_RXA_CTL,
604 FDI_RX_MISC_A,
605 FDI_RXA_IIR,
606 FDI_RXA_IMR,
607 FDI_RXA_TUSIZE1,
608 QUIRK_F0060,
609 TRANSA_CHICKEN2,
610 TRANSBCONF,
611 FDI_RXB_CTL,
612 FDI_RX_MISC_B,
613 FDI_RXB_IIR,
614 FDI_RXB_IMR,
615 FDI_RXB_TUSIZE1,
616 QUIRK_F1060,
617 TRANSB_CHICKEN2,
618 TRANSCCONF,
619 FDI_RXC_CTL,
620 FDI_RX_MISC_C,
621 FDI_RXC_IIR,
622 FDI_RXC_IMR,
623 FDI_RXC_TUSIZE1,
624 QUIRK_F2060,
625 TRANSC_CHICKEN2,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]626 BXT_P_CR_GT_DISP_PWRON,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]627 GT_MAILBOX,
628 GT_MAILBOX_DATA,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]629 GT_MAILBOX_DATA_1,
630 BXT_PORT_CL1CM_DW0_A,
631 BXT_PORT_CL1CM_DW9_A,
632 BXT_PORT_CL1CM_DW10_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]633 BXT_PORT_PLL_EBB_0_A,
634 BXT_PORT_PLL_EBB_4_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]635 BXT_PORT_CL1CM_DW28_A,
636 BXT_PORT_CL1CM_DW30_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]637 BXT_PORT_PLL_0_A,
638 BXT_PORT_PLL_1_A,
639 BXT_PORT_PLL_2_A,
640 BXT_PORT_PLL_3_A,
641 BXT_PORT_PLL_6_A,
642 BXT_PORT_PLL_8_A,
643 BXT_PORT_PLL_9_A,
644 BXT_PORT_PLL_10_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]645 BXT_PORT_REF_DW3_A,
646 BXT_PORT_REF_DW6_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]647 BXT_PORT_REF_DW8_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]648 BXT_PORT_PCS_DW10_01_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]649 BXT_PORT_PCS_DW12_01_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]650 BXT_PORT_TX_DW2_LN0_A,
651 BXT_PORT_TX_DW3_LN0_A,
652 BXT_PORT_TX_DW4_LN0_A,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]653 BXT_PORT_TX_DW14_LN0_A,
654 BXT_PORT_TX_DW14_LN1_A,
655 BXT_PORT_TX_DW14_LN2_A,
656 BXT_PORT_TX_DW14_LN3_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]657 BXT_PORT_PCS_DW10_GRP_A,
658 BXT_PORT_PCS_DW12_GRP_A,
659 BXT_PORT_TX_DW2_GRP_A,
660 BXT_PORT_TX_DW3_GRP_A,
661 BXT_PORT_TX_DW4_GRP_A);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]662
663 pragma Warnings
664 (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)",
665 Reason => "TODO: Should it matter?");
666 pragma Keep_Names (Registers_Invalid_Index);
667 pragma Warnings
668 (GNATprove, On, "pragma ""KEEP_NAMES"" ignored *(not yet supported)");
669
670 Register_Width : constant := 4;
671
672 for Registers_Invalid_Index use
673 (Invalid_Register => 0,
674
675 ---------------------------------------------------------------------------
676 -- Pipe A registers
677 ---------------------------------------------------------------------------
678
679 -- pipe timing registers
680
681 HTOTAL_A => 16#06_0000# / Register_Width,
682 HBLANK_A => 16#06_0004# / Register_Width,
683 HSYNC_A => 16#06_0008# / Register_Width,
684 VTOTAL_A => 16#06_000c# / Register_Width,
685 VBLANK_A => 16#06_0010# / Register_Width,
686 VSYNC_A => 16#06_0014# / Register_Width,
687 PIPEASRC => 16#06_001c# / Register_Width,
688 PIPEACONF => 16#07_0008# / Register_Width,
689 PIPEAMISC => 16#07_0030# / Register_Width,
690 TRANS_HTOTAL_A => 16#0e_0000# / Register_Width,
691 TRANS_HBLANK_A => 16#0e_0004# / Register_Width,
692 TRANS_HSYNC_A => 16#0e_0008# / Register_Width,
693 TRANS_VTOTAL_A => 16#0e_000c# / Register_Width,
694 TRANS_VBLANK_A => 16#0e_0010# / Register_Width,
695 TRANS_VSYNC_A => 16#0e_0014# / Register_Width,
696 TRANSA_DATA_M1 => 16#0e_0030# / Register_Width,
697 TRANSA_DATA_N1 => 16#0e_0034# / Register_Width,
698 TRANSA_DP_LINK_M1 => 16#0e_0040# / Register_Width,
699 TRANSA_DP_LINK_N1 => 16#0e_0044# / Register_Width,
700 PIPEA_DATA_M1 => 16#06_0030# / Register_Width,
701 PIPEA_DATA_N1 => 16#06_0034# / Register_Width,
702 PIPEA_LINK_M1 => 16#06_0040# / Register_Width,
703 PIPEA_LINK_N1 => 16#06_0044# / Register_Width,
704 PIPEA_DDI_FUNC_CTL => 16#06_0400# / Register_Width,
705 PIPEA_MSA_MISC => 16#06_0410# / Register_Width,
706
707 -- PCH sideband interface registers
708 SBI_ADDR => 16#0c_6000# / Register_Width,
709 SBI_DATA => 16#0c_6004# / Register_Width,
710 SBI_CTL_STAT => 16#0c_6008# / Register_Width,
711
712 -- clock registers
713 PCH_DPLL_A => 16#0c_6014# / Register_Width,
714 PCH_PIXCLK_GATE => 16#0c_6020# / Register_Width,
715 PCH_FPA0 => 16#0c_6040# / Register_Width,
716 PCH_FPA1 => 16#0c_6044# / Register_Width,
717
718 -- panel fitter
719 PFA_CTL_1 => 16#06_8080# / Register_Width,
720 PFA_WIN_POS => 16#06_8070# / Register_Width,
721 PFA_WIN_SZ => 16#06_8074# / Register_Width,
722 PS_WIN_POS_1_A => 16#06_8170# / Register_Width,
723 PS_WIN_SZ_1_A => 16#06_8174# / Register_Width,
724 PS_CTRL_1_A => 16#06_8180# / Register_Width,
725 PS_WIN_POS_2_A => 16#06_8270# / Register_Width,
726 PS_WIN_SZ_2_A => 16#06_8274# / Register_Width,
727 PS_CTRL_2_A => 16#06_8280# / Register_Width,
728
729 -- display control
730 DSPACNTR => 16#07_0180# / Register_Width,
731 DSPALINOFF => 16#07_0184# / Register_Width,
732 DSPASTRIDE => 16#07_0188# / Register_Width,
733 PLANE_POS_1_A => 16#07_018c# / Register_Width,
734 PLANE_SIZE_1_A => 16#07_0190# / Register_Width,
735 DSPASURF => 16#07_019c# / Register_Width,
736 DSPATILEOFF => 16#07_01a4# / Register_Width,
737
738 -- sprite control
739 SPACNTR => 16#07_0280# / Register_Width,
740
741 -- FDI and PCH transcoder control
742 FDI_TX_CTL_A => 16#06_0100# / Register_Width,
743 FDI_RXA_CTL => 16#0f_000c# / Register_Width,
744 FDI_RX_MISC_A => 16#0f_0010# / Register_Width,
745 FDI_RXA_IIR => 16#0f_0014# / Register_Width,
746 FDI_RXA_IMR => 16#0f_0018# / Register_Width,
747 FDI_RXA_TUSIZE1 => 16#0f_0030# / Register_Width,
748 TRANSACONF => 16#0f_0008# / Register_Width,
749 TRANSA_CHICKEN2 => 16#0f_0064# / Register_Width,
750
751 -- watermark registers
752 WM_LINETIME_A => 16#04_5270# / Register_Width,
753 PLANE_WM_1_A_0 => 16#07_0240# / Register_Width,
754 PLANE_WM_1_A_1 => 16#07_0244# / Register_Width,
755 PLANE_WM_1_A_2 => 16#07_0248# / Register_Width,
756 PLANE_WM_1_A_3 => 16#07_024c# / Register_Width,
757 PLANE_WM_1_A_4 => 16#07_0250# / Register_Width,
758 PLANE_WM_1_A_5 => 16#07_0254# / Register_Width,
759 PLANE_WM_1_A_6 => 16#07_0258# / Register_Width,
760 PLANE_WM_1_A_7 => 16#07_025c# / Register_Width,
761 PLANE_BUF_CFG_1_A => 16#07_027c# / Register_Width,
762
763 -- CPU transcoder clock select
764 TRANSA_CLK_SEL => 16#04_6140# / Register_Width,
765
766 ---------------------------------------------------------------------------
767 -- Pipe B registers
768 ---------------------------------------------------------------------------
769
770 -- pipe timing registers
771
772 HTOTAL_B => 16#06_1000# / Register_Width,
773 HBLANK_B => 16#06_1004# / Register_Width,
774 HSYNC_B => 16#06_1008# / Register_Width,
775 VTOTAL_B => 16#06_100c# / Register_Width,
776 VBLANK_B => 16#06_1010# / Register_Width,
777 VSYNC_B => 16#06_1014# / Register_Width,
778 PIPEBSRC => 16#06_101c# / Register_Width,
779 PIPEBCONF => 16#07_1008# / Register_Width,
780 PIPEBMISC => 16#07_1030# / Register_Width,
781 TRANS_HTOTAL_B => 16#0e_1000# / Register_Width,
782 TRANS_HBLANK_B => 16#0e_1004# / Register_Width,
783 TRANS_HSYNC_B => 16#0e_1008# / Register_Width,
784 TRANS_VTOTAL_B => 16#0e_100c# / Register_Width,
785 TRANS_VBLANK_B => 16#0e_1010# / Register_Width,
786 TRANS_VSYNC_B => 16#0e_1014# / Register_Width,
787 TRANSB_DATA_M1 => 16#0e_1030# / Register_Width,
788 TRANSB_DATA_N1 => 16#0e_1034# / Register_Width,
789 TRANSB_DP_LINK_M1 => 16#0e_1040# / Register_Width,
790 TRANSB_DP_LINK_N1 => 16#0e_1044# / Register_Width,
791 PIPEB_DATA_M1 => 16#06_1030# / Register_Width,
792 PIPEB_DATA_N1 => 16#06_1034# / Register_Width,
793 PIPEB_LINK_M1 => 16#06_1040# / Register_Width,
794 PIPEB_LINK_N1 => 16#06_1044# / Register_Width,
795 PIPEB_DDI_FUNC_CTL => 16#06_1400# / Register_Width,
796 PIPEB_MSA_MISC => 16#06_1410# / Register_Width,
797
798 -- clock registers
799 PCH_DPLL_B => 16#0c_6018# / Register_Width,
800 PCH_FPB0 => 16#0c_6048# / Register_Width,
801 PCH_FPB1 => 16#0c_604c# / Register_Width,
802
803 -- panel fitter
804 PFB_CTL_1 => 16#06_8880# / Register_Width,
805 PFB_WIN_POS => 16#06_8870# / Register_Width,
806 PFB_WIN_SZ => 16#06_8874# / Register_Width,
807 PS_WIN_POS_1_B => 16#06_8970# / Register_Width,
808 PS_WIN_SZ_1_B => 16#06_8974# / Register_Width,
809 PS_CTRL_1_B => 16#06_8980# / Register_Width,
810 PS_WIN_POS_2_B => 16#06_8a70# / Register_Width,
811 PS_WIN_SZ_2_B => 16#06_8a74# / Register_Width,
812 PS_CTRL_2_B => 16#06_8a80# / Register_Width,
813
814 -- display control
815 DSPBCNTR => 16#07_1180# / Register_Width,
816 DSPBLINOFF => 16#07_1184# / Register_Width,
817 DSPBSTRIDE => 16#07_1188# / Register_Width,
818 PLANE_POS_1_B => 16#07_118c# / Register_Width,
819 PLANE_SIZE_1_B => 16#07_1190# / Register_Width,
820 DSPBSURF => 16#07_119c# / Register_Width,
821 DSPBTILEOFF => 16#07_11a4# / Register_Width,
822
823 -- sprite control
824 SPBCNTR => 16#07_1280# / Register_Width,
825
826 -- FDI and PCH transcoder control
827 FDI_TX_CTL_B => 16#06_1100# / Register_Width,
828 FDI_RXB_CTL => 16#0f_100c# / Register_Width,
829 FDI_RX_MISC_B => 16#0f_1010# / Register_Width,
830 FDI_RXB_IIR => 16#0f_1014# / Register_Width,
831 FDI_RXB_IMR => 16#0f_1018# / Register_Width,
832 FDI_RXB_TUSIZE1 => 16#0f_1030# / Register_Width,
833 TRANSBCONF => 16#0f_1008# / Register_Width,
834 TRANSB_CHICKEN2 => 16#0f_1064# / Register_Width,
835
836 -- watermark registers
837 WM_LINETIME_B => 16#04_5274# / Register_Width,
838 PLANE_WM_1_B_0 => 16#07_1240# / Register_Width,
839 PLANE_WM_1_B_1 => 16#07_1244# / Register_Width,
840 PLANE_WM_1_B_2 => 16#07_1248# / Register_Width,
841 PLANE_WM_1_B_3 => 16#07_124c# / Register_Width,
842 PLANE_WM_1_B_4 => 16#07_1250# / Register_Width,
843 PLANE_WM_1_B_5 => 16#07_1254# / Register_Width,
844 PLANE_WM_1_B_6 => 16#07_1258# / Register_Width,
845 PLANE_WM_1_B_7 => 16#07_125c# / Register_Width,
846 PLANE_BUF_CFG_1_B => 16#07_127c# / Register_Width,
847
848 -- CPU transcoder clock select
849 TRANSB_CLK_SEL => 16#04_6144# / Register_Width,
850
851 ---------------------------------------------------------------------------
852 -- Pipe C registers
853 ---------------------------------------------------------------------------
854
855 -- pipe timing registers
856
857 HTOTAL_C => 16#06_2000# / Register_Width,
858 HBLANK_C => 16#06_2004# / Register_Width,
859 HSYNC_C => 16#06_2008# / Register_Width,
860 VTOTAL_C => 16#06_200c# / Register_Width,
861 VBLANK_C => 16#06_2010# / Register_Width,
862 VSYNC_C => 16#06_2014# / Register_Width,
863 PIPECSRC => 16#06_201c# / Register_Width,
864 PIPECCONF => 16#07_2008# / Register_Width,
865 PIPECMISC => 16#07_2030# / Register_Width,
866 TRANS_HTOTAL_C => 16#0e_2000# / Register_Width,
867 TRANS_HBLANK_C => 16#0e_2004# / Register_Width,
868 TRANS_HSYNC_C => 16#0e_2008# / Register_Width,
869 TRANS_VTOTAL_C => 16#0e_200c# / Register_Width,
870 TRANS_VBLANK_C => 16#0e_2010# / Register_Width,
871 TRANS_VSYNC_C => 16#0e_2014# / Register_Width,
872 TRANSC_DATA_M1 => 16#0e_2030# / Register_Width,
873 TRANSC_DATA_N1 => 16#0e_2034# / Register_Width,
874 TRANSC_DP_LINK_M1 => 16#0e_2040# / Register_Width,
875 TRANSC_DP_LINK_N1 => 16#0e_2044# / Register_Width,
876 PIPEC_DATA_M1 => 16#06_2030# / Register_Width,
877 PIPEC_DATA_N1 => 16#06_2034# / Register_Width,
878 PIPEC_LINK_M1 => 16#06_2040# / Register_Width,
879 PIPEC_LINK_N1 => 16#06_2044# / Register_Width,
880 PIPEC_DDI_FUNC_CTL => 16#06_2400# / Register_Width,
881 PIPEC_MSA_MISC => 16#06_2410# / Register_Width,
882
883 -- panel fitter
884 PFC_CTL_1 => 16#06_9080# / Register_Width,
885 PFC_WIN_POS => 16#06_9070# / Register_Width,
886 PFC_WIN_SZ => 16#06_9074# / Register_Width,
887 PS_WIN_POS_1_C => 16#06_9170# / Register_Width,
888 PS_WIN_SZ_1_C => 16#06_9174# / Register_Width,
889 PS_CTRL_1_C => 16#06_9180# / Register_Width,
890
891 -- display control
892 DSPCCNTR => 16#07_2180# / Register_Width,
893 DSPCLINOFF => 16#07_2184# / Register_Width,
894 DSPCSTRIDE => 16#07_2188# / Register_Width,
895 PLANE_POS_1_C => 16#07_218c# / Register_Width,
896 PLANE_SIZE_1_C => 16#07_2190# / Register_Width,
897 DSPCSURF => 16#07_219c# / Register_Width,
898 DSPCTILEOFF => 16#07_21a4# / Register_Width,
899
900 -- sprite control
901 SPCCNTR => 16#07_2280# / Register_Width,
902
903 -- PCH transcoder control
904 FDI_TX_CTL_C => 16#06_2100# / Register_Width,
905 FDI_RXC_CTL => 16#0f_200c# / Register_Width,
906 FDI_RX_MISC_C => 16#0f_2010# / Register_Width,
907 FDI_RXC_IIR => 16#0f_2014# / Register_Width,
908 FDI_RXC_IMR => 16#0f_2018# / Register_Width,
909 FDI_RXC_TUSIZE1 => 16#0f_2030# / Register_Width,
910 TRANSCCONF => 16#0f_2008# / Register_Width,
911 TRANSC_CHICKEN2 => 16#0f_2064# / Register_Width,
912
913 -- watermark registers
914 WM_LINETIME_C => 16#04_5278# / Register_Width,
915 PLANE_WM_1_C_0 => 16#07_2240# / Register_Width,
916 PLANE_WM_1_C_1 => 16#07_2244# / Register_Width,
917 PLANE_WM_1_C_2 => 16#07_2248# / Register_Width,
918 PLANE_WM_1_C_3 => 16#07_224c# / Register_Width,
919 PLANE_WM_1_C_4 => 16#07_2250# / Register_Width,
920 PLANE_WM_1_C_5 => 16#07_2254# / Register_Width,
921 PLANE_WM_1_C_6 => 16#07_2258# / Register_Width,
922 PLANE_WM_1_C_7 => 16#07_225c# / Register_Width,
923 PLANE_BUF_CFG_1_C => 16#07_227c# / Register_Width,
924
925 -- CPU transcoder clock select
926 TRANSC_CLK_SEL => 16#04_6148# / Register_Width,
927
928 ---------------------------------------------------------------------------
929 -- Pipe EDP registers
930 ---------------------------------------------------------------------------
931
932 -- pipe timing registers
933
934 HTOTAL_EDP => 16#06_f000# / Register_Width,
935 HBLANK_EDP => 16#06_f004# / Register_Width,
936 HSYNC_EDP => 16#06_f008# / Register_Width,
937 VTOTAL_EDP => 16#06_f00c# / Register_Width,
938 VBLANK_EDP => 16#06_f010# / Register_Width,
939 VSYNC_EDP => 16#06_f014# / Register_Width,
940 PIPE_EDP_CONF => 16#07_f008# / Register_Width,
941 PIPE_EDP_DATA_M1 => 16#06_f030# / Register_Width,
942 PIPE_EDP_DATA_N1 => 16#06_f034# / Register_Width,
943 PIPE_EDP_LINK_M1 => 16#06_f040# / Register_Width,
944 PIPE_EDP_LINK_N1 => 16#06_f044# / Register_Width,
945 PIPE_EDP_DDI_FUNC_CTL => 16#06_f400# / Register_Width,
946 PIPE_EDP_MSA_MISC => 16#06_f410# / Register_Width,
947
948 -- PSR registers
949 SRD_CTL => 16#06_4800# / Register_Width,
950 SRD_CTL_A => 16#06_0800# / Register_Width,
951 SRD_CTL_B => 16#06_1800# / Register_Width,
952 SRD_CTL_C => 16#06_2800# / Register_Width,
953 SRD_CTL_EDP => 16#06_f800# / Register_Width,
954 SRD_STATUS => 16#06_4840# / Register_Width,
955 SRD_STATUS_A => 16#06_0840# / Register_Width,
956 SRD_STATUS_B => 16#06_1840# / Register_Width,
957 SRD_STATUS_C => 16#06_2840# / Register_Width,
958 SRD_STATUS_EDP => 16#06_f840# / Register_Width,
959
960 -- DDI registers
961 DDI_BUF_CTL_A => 16#06_4000# / Register_Width, -- aliased by DP_CTL_A
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]962 DDI_BUF_TRANS_A_S0T1 => 16#06_4e00# / Register_Width,
963 DDI_BUF_TRANS_A_S0T2 => 16#06_4e04# / Register_Width,
964 DDI_BUF_TRANS_A_S1T1 => 16#06_4e08# / Register_Width,
965 DDI_BUF_TRANS_A_S1T2 => 16#06_4e0c# / Register_Width,
966 DDI_BUF_TRANS_A_S2T1 => 16#06_4e10# / Register_Width,
967 DDI_BUF_TRANS_A_S2T2 => 16#06_4e14# / Register_Width,
968 DDI_BUF_TRANS_A_S3T1 => 16#06_4e18# / Register_Width,
969 DDI_BUF_TRANS_A_S3T2 => 16#06_4e1c# / Register_Width,
970 DDI_BUF_TRANS_A_S4T1 => 16#06_4e20# / Register_Width,
971 DDI_BUF_TRANS_A_S4T2 => 16#06_4e24# / Register_Width,
972 DDI_BUF_TRANS_A_S5T1 => 16#06_4e28# / Register_Width,
973 DDI_BUF_TRANS_A_S5T2 => 16#06_4e2c# / Register_Width,
974 DDI_BUF_TRANS_A_S6T1 => 16#06_4e30# / Register_Width,
975 DDI_BUF_TRANS_A_S6T2 => 16#06_4e34# / Register_Width,
976 DDI_BUF_TRANS_A_S7T1 => 16#06_4e38# / Register_Width,
977 DDI_BUF_TRANS_A_S7T2 => 16#06_4e3c# / Register_Width,
978 DDI_BUF_TRANS_A_S8T1 => 16#06_4e40# / Register_Width,
979 DDI_BUF_TRANS_A_S8T2 => 16#06_4e44# / Register_Width,
980 DDI_BUF_TRANS_A_S9T1 => 16#06_4e48# / Register_Width,
981 DDI_BUF_TRANS_A_S9T2 => 16#06_4e4c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]982 DDI_AUX_CTL_A => 16#06_4010# / Register_Width, -- aliased by DP_AUX_CTL_A
983 DDI_AUX_DATA_A_1 => 16#06_4014# / Register_Width, -- aliased by DP_AUX_DATA_A_1
984 DDI_AUX_DATA_A_2 => 16#06_4018# / Register_Width, -- aliased by DP_AUX_DATA_A_2
985 DDI_AUX_DATA_A_3 => 16#06_401c# / Register_Width, -- aliased by DP_AUX_DATA_A_3
986 DDI_AUX_DATA_A_4 => 16#06_4020# / Register_Width, -- aliased by DP_AUX_DATA_A_4
987 DDI_AUX_DATA_A_5 => 16#06_4024# / Register_Width, -- aliased by DP_AUX_DATA_A_5
988 DDI_AUX_MUTEX_A => 16#06_402c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]989
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]990 DDI_BUF_CTL_B => 16#06_4100# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]991 DDI_BUF_TRANS_B_S0T1 => 16#06_4e60# / Register_Width,
992 DDI_BUF_TRANS_B_S0T2 => 16#06_4e64# / Register_Width,
993 DDI_BUF_TRANS_B_S1T1 => 16#06_4e68# / Register_Width,
994 DDI_BUF_TRANS_B_S1T2 => 16#06_4e6c# / Register_Width,
995 DDI_BUF_TRANS_B_S2T1 => 16#06_4e70# / Register_Width,
996 DDI_BUF_TRANS_B_S2T2 => 16#06_4e74# / Register_Width,
997 DDI_BUF_TRANS_B_S3T1 => 16#06_4e78# / Register_Width,
998 DDI_BUF_TRANS_B_S3T2 => 16#06_4e7c# / Register_Width,
999 DDI_BUF_TRANS_B_S4T1 => 16#06_4e80# / Register_Width,
1000 DDI_BUF_TRANS_B_S4T2 => 16#06_4e84# / Register_Width,
1001 DDI_BUF_TRANS_B_S5T1 => 16#06_4e88# / Register_Width,
1002 DDI_BUF_TRANS_B_S5T2 => 16#06_4e8c# / Register_Width,
1003 DDI_BUF_TRANS_B_S6T1 => 16#06_4e90# / Register_Width,
1004 DDI_BUF_TRANS_B_S6T2 => 16#06_4e94# / Register_Width,
1005 DDI_BUF_TRANS_B_S7T1 => 16#06_4e98# / Register_Width,
1006 DDI_BUF_TRANS_B_S7T2 => 16#06_4e9c# / Register_Width,
1007 DDI_BUF_TRANS_B_S8T1 => 16#06_4ea0# / Register_Width,
1008 DDI_BUF_TRANS_B_S8T2 => 16#06_4ea4# / Register_Width,
1009 DDI_BUF_TRANS_B_S9T1 => 16#06_4ea8# / Register_Width,
1010 DDI_BUF_TRANS_B_S9T2 => 16#06_4eac# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1011 DDI_AUX_CTL_B => 16#06_4110# / Register_Width,
1012 DDI_AUX_DATA_B_1 => 16#06_4114# / Register_Width,
1013 DDI_AUX_DATA_B_2 => 16#06_4118# / Register_Width,
1014 DDI_AUX_DATA_B_3 => 16#06_411c# / Register_Width,
1015 DDI_AUX_DATA_B_4 => 16#06_4120# / Register_Width,
1016 DDI_AUX_DATA_B_5 => 16#06_4124# / Register_Width,
1017 DDI_AUX_MUTEX_B => 16#06_412c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1018
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1019 DDI_BUF_CTL_C => 16#06_4200# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1020 DDI_BUF_TRANS_C_S0T1 => 16#06_4ec0# / Register_Width,
1021 DDI_BUF_TRANS_C_S0T2 => 16#06_4ec4# / Register_Width,
1022 DDI_BUF_TRANS_C_S1T1 => 16#06_4ec8# / Register_Width,
1023 DDI_BUF_TRANS_C_S1T2 => 16#06_4ecc# / Register_Width,
1024 DDI_BUF_TRANS_C_S2T1 => 16#06_4ed0# / Register_Width,
1025 DDI_BUF_TRANS_C_S2T2 => 16#06_4ed4# / Register_Width,
1026 DDI_BUF_TRANS_C_S3T1 => 16#06_4ed8# / Register_Width,
1027 DDI_BUF_TRANS_C_S3T2 => 16#06_4edc# / Register_Width,
1028 DDI_BUF_TRANS_C_S4T1 => 16#06_4ee0# / Register_Width,
1029 DDI_BUF_TRANS_C_S4T2 => 16#06_4ee4# / Register_Width,
1030 DDI_BUF_TRANS_C_S5T1 => 16#06_4ee8# / Register_Width,
1031 DDI_BUF_TRANS_C_S5T2 => 16#06_4eec# / Register_Width,
1032 DDI_BUF_TRANS_C_S6T1 => 16#06_4ef0# / Register_Width,
1033 DDI_BUF_TRANS_C_S6T2 => 16#06_4ef4# / Register_Width,
1034 DDI_BUF_TRANS_C_S7T1 => 16#06_4ef8# / Register_Width,
1035 DDI_BUF_TRANS_C_S7T2 => 16#06_4efc# / Register_Width,
1036 DDI_BUF_TRANS_C_S8T1 => 16#06_4f00# / Register_Width,
1037 DDI_BUF_TRANS_C_S8T2 => 16#06_4f04# / Register_Width,
1038 DDI_BUF_TRANS_C_S9T1 => 16#06_4f08# / Register_Width,
1039 DDI_BUF_TRANS_C_S9T2 => 16#06_4f0c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1040 DDI_AUX_CTL_C => 16#06_4210# / Register_Width,
1041 DDI_AUX_DATA_C_1 => 16#06_4214# / Register_Width,
1042 DDI_AUX_DATA_C_2 => 16#06_4218# / Register_Width,
1043 DDI_AUX_DATA_C_3 => 16#06_421c# / Register_Width,
1044 DDI_AUX_DATA_C_4 => 16#06_4220# / Register_Width,
1045 DDI_AUX_DATA_C_5 => 16#06_4224# / Register_Width,
1046 DDI_AUX_MUTEX_C => 16#06_422c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1047
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1048 DDI_BUF_CTL_D => 16#06_4300# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1049 DDI_BUF_TRANS_D_S0T1 => 16#06_4f20# / Register_Width,
1050 DDI_BUF_TRANS_D_S0T2 => 16#06_4f24# / Register_Width,
1051 DDI_BUF_TRANS_D_S1T1 => 16#06_4f28# / Register_Width,
1052 DDI_BUF_TRANS_D_S1T2 => 16#06_4f2c# / Register_Width,
1053 DDI_BUF_TRANS_D_S2T1 => 16#06_4f30# / Register_Width,
1054 DDI_BUF_TRANS_D_S2T2 => 16#06_4f34# / Register_Width,
1055 DDI_BUF_TRANS_D_S3T1 => 16#06_4f38# / Register_Width,
1056 DDI_BUF_TRANS_D_S3T2 => 16#06_4f3c# / Register_Width,
1057 DDI_BUF_TRANS_D_S4T1 => 16#06_4f40# / Register_Width,
1058 DDI_BUF_TRANS_D_S4T2 => 16#06_4f44# / Register_Width,
1059 DDI_BUF_TRANS_D_S5T1 => 16#06_4f48# / Register_Width,
1060 DDI_BUF_TRANS_D_S5T2 => 16#06_4f4c# / Register_Width,
1061 DDI_BUF_TRANS_D_S6T1 => 16#06_4f50# / Register_Width,
1062 DDI_BUF_TRANS_D_S6T2 => 16#06_4f54# / Register_Width,
1063 DDI_BUF_TRANS_D_S7T1 => 16#06_4f58# / Register_Width,
1064 DDI_BUF_TRANS_D_S7T2 => 16#06_4f5c# / Register_Width,
1065 DDI_BUF_TRANS_D_S8T1 => 16#06_4f60# / Register_Width,
1066 DDI_BUF_TRANS_D_S8T2 => 16#06_4f64# / Register_Width,
1067 DDI_BUF_TRANS_D_S9T1 => 16#06_4f68# / Register_Width,
1068 DDI_BUF_TRANS_D_S9T2 => 16#06_4f6c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1069 DDI_AUX_CTL_D => 16#06_4310# / Register_Width,
1070 DDI_AUX_DATA_D_1 => 16#06_4314# / Register_Width,
1071 DDI_AUX_DATA_D_2 => 16#06_4318# / Register_Width,
1072 DDI_AUX_DATA_D_3 => 16#06_431c# / Register_Width,
1073 DDI_AUX_DATA_D_4 => 16#06_4320# / Register_Width,
1074 DDI_AUX_DATA_D_5 => 16#06_4324# / Register_Width,
1075 DDI_AUX_MUTEX_D => 16#06_432c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1076
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1077 DDI_BUF_CTL_E => 16#06_4400# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1078 DDI_BUF_TRANS_E_S0T1 => 16#06_4f80# / Register_Width,
1079 DDI_BUF_TRANS_E_S0T2 => 16#06_4f84# / Register_Width,
1080 DDI_BUF_TRANS_E_S1T1 => 16#06_4f88# / Register_Width,
1081 DDI_BUF_TRANS_E_S1T2 => 16#06_4f8c# / Register_Width,
1082 DDI_BUF_TRANS_E_S2T1 => 16#06_4f90# / Register_Width,
1083 DDI_BUF_TRANS_E_S2T2 => 16#06_4f94# / Register_Width,
1084 DDI_BUF_TRANS_E_S3T1 => 16#06_4f98# / Register_Width,
1085 DDI_BUF_TRANS_E_S3T2 => 16#06_4f9c# / Register_Width,
1086 DDI_BUF_TRANS_E_S4T1 => 16#06_4fa0# / Register_Width,
1087 DDI_BUF_TRANS_E_S4T2 => 16#06_4fa4# / Register_Width,
1088 DDI_BUF_TRANS_E_S5T1 => 16#06_4fa8# / Register_Width,
1089 DDI_BUF_TRANS_E_S5T2 => 16#06_4fac# / Register_Width,
1090 DDI_BUF_TRANS_E_S6T1 => 16#06_4fb0# / Register_Width,
1091 DDI_BUF_TRANS_E_S6T2 => 16#06_4fb4# / Register_Width,
1092 DDI_BUF_TRANS_E_S7T1 => 16#06_4fb8# / Register_Width,
1093 DDI_BUF_TRANS_E_S7T2 => 16#06_4fbc# / Register_Width,
1094 DDI_BUF_TRANS_E_S8T1 => 16#06_4fc0# / Register_Width,
1095 DDI_BUF_TRANS_E_S8T2 => 16#06_4fc4# / Register_Width,
1096 DDI_BUF_TRANS_E_S9T1 => 16#06_4fc8# / Register_Width,
1097 DDI_BUF_TRANS_E_S9T2 => 16#06_4fcc# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1098 DP_TP_CTL_A => 16#06_4040# / Register_Width,
1099 DP_TP_CTL_B => 16#06_4140# / Register_Width,
1100 DP_TP_CTL_C => 16#06_4240# / Register_Width,
1101 DP_TP_CTL_D => 16#06_4340# / Register_Width,
1102 DP_TP_CTL_E => 16#06_4440# / Register_Width,
1103 DP_TP_STATUS_B => 16#06_4144# / Register_Width,
1104 DP_TP_STATUS_C => 16#06_4244# / Register_Width,
1105 DP_TP_STATUS_D => 16#06_4344# / Register_Width,
1106 DP_TP_STATUS_E => 16#06_4444# / Register_Width,
1107 PORT_CLK_SEL_DDIA => 16#04_6100# / Register_Width,
1108 PORT_CLK_SEL_DDIB => 16#04_6104# / Register_Width,
1109 PORT_CLK_SEL_DDIC => 16#04_6108# / Register_Width,
1110 PORT_CLK_SEL_DDID => 16#04_610c# / Register_Width,
1111 PORT_CLK_SEL_DDIE => 16#04_6110# / Register_Width,
1112
Nico Huber58afc202017-06-12 21:34:55 +0200[diff] [blame]1113 -- Skylake I_boost configuration
1114 DISPIO_CR_TX_BMU_CR0 => 16#06_c00c# / Register_Width,
1115
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1116 -- Skylake DPLL registers
1117 DPLL1_CFGR1 => 16#06_c040# / Register_Width,
1118 DPLL1_CFGR2 => 16#06_c044# / Register_Width,
1119 DPLL2_CFGR1 => 16#06_c048# / Register_Width,
1120 DPLL2_CFGR2 => 16#06_c04c# / Register_Width,
1121 DPLL3_CFGR1 => 16#06_c050# / Register_Width,
1122 DPLL3_CFGR2 => 16#06_c054# / Register_Width,
1123 DPLL_CTRL1 => 16#06_c058# / Register_Width,
1124 DPLL_CTRL2 => 16#06_c05c# / Register_Width,
1125 DPLL_STATUS => 16#06_c060# / Register_Width,
1126
1127 -- CD CLK register
1128 CDCLK_CTL => 16#04_6000# / Register_Width,
1129
1130 -- Skylake LCPLL registers
1131 LCPLL1_CTL => 16#04_6010# / Register_Width,
1132 LCPLL2_CTL => 16#04_6014# / Register_Width,
1133
1134 -- SPLL register
1135 SPLL_CTL => 16#04_6020# / Register_Width,
1136
1137 -- WRPLL registers
1138 WRPLL_CTL_1 => 16#04_6040# / Register_Width,
1139 WRPLL_CTL_2 => 16#04_6060# / Register_Width,
1140
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]1141 -- Broxton Display Engine PLL registers
1142 BXT_DE_PLL_CTL => 16#06_d000# / Register_Width,
1143 BXT_DE_PLL_ENABLE => 16#04_6070# / Register_Width,
1144
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1145 -- Broxton DDI PHY PLL registers
1146 BXT_PORT_PLL_ENABLE_A => 16#04_6074# / Register_Width,
1147 BXT_PORT_PLL_ENABLE_B => 16#04_6078# / Register_Width,
1148 BXT_PORT_PLL_ENABLE_C => 16#04_607c# / Register_Width,
1149 BXT_PORT_PLL_EBB_0_A => 16#16_2034# / Register_Width,
1150 BXT_PORT_PLL_EBB_4_A => 16#16_2038# / Register_Width,
1151 BXT_PORT_PLL_0_A => 16#16_2100# / Register_Width,
1152 BXT_PORT_PLL_1_A => 16#16_2104# / Register_Width,
1153 BXT_PORT_PLL_2_A => 16#16_2108# / Register_Width,
1154 BXT_PORT_PLL_3_A => 16#16_210c# / Register_Width,
1155 BXT_PORT_PLL_6_A => 16#16_2118# / Register_Width,
1156 BXT_PORT_PLL_8_A => 16#16_2120# / Register_Width,
1157 BXT_PORT_PLL_9_A => 16#16_2124# / Register_Width,
1158 BXT_PORT_PLL_10_A => 16#16_2128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1159 BXT_PORT_PLL_EBB_0_B => 16#06_c034# / Register_Width,
1160 BXT_PORT_PLL_EBB_4_B => 16#06_c038# / Register_Width,
1161 BXT_PORT_PLL_0_B => 16#06_c100# / Register_Width,
1162 BXT_PORT_PLL_1_B => 16#06_c104# / Register_Width,
1163 BXT_PORT_PLL_2_B => 16#06_c108# / Register_Width,
1164 BXT_PORT_PLL_3_B => 16#06_c10c# / Register_Width,
1165 BXT_PORT_PLL_6_B => 16#06_c118# / Register_Width,
1166 BXT_PORT_PLL_8_B => 16#06_c120# / Register_Width,
1167 BXT_PORT_PLL_9_B => 16#06_c124# / Register_Width,
1168 BXT_PORT_PLL_10_B => 16#06_c128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1169 BXT_PORT_PLL_EBB_0_C => 16#06_c340# / Register_Width,
1170 BXT_PORT_PLL_EBB_4_C => 16#06_c344# / Register_Width,
1171 BXT_PORT_PLL_0_C => 16#06_c380# / Register_Width,
1172 BXT_PORT_PLL_1_C => 16#06_c384# / Register_Width,
1173 BXT_PORT_PLL_2_C => 16#06_c388# / Register_Width,
1174 BXT_PORT_PLL_3_C => 16#06_c38c# / Register_Width,
1175 BXT_PORT_PLL_6_C => 16#06_c398# / Register_Width,
1176 BXT_PORT_PLL_8_C => 16#06_c3a0# / Register_Width,
1177 BXT_PORT_PLL_9_C => 16#06_c3a4# / Register_Width,
1178 BXT_PORT_PLL_10_C => 16#06_c3a8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1179
1180 -- Broxton DDI PHY PCS? registers
1181 BXT_PORT_PCS_DW10_01_A => 16#16_2428# / Register_Width,
1182 BXT_PORT_PCS_DW12_01_A => 16#16_2430# / Register_Width,
1183 BXT_PORT_PCS_DW10_GRP_A => 16#16_2c28# / Register_Width,
1184 BXT_PORT_PCS_DW12_GRP_A => 16#16_2c30# / Register_Width,
1185 BXT_PORT_PCS_DW10_01_B => 16#06_c428# / Register_Width,
1186 BXT_PORT_PCS_DW12_01_B => 16#06_c430# / Register_Width,
1187 BXT_PORT_PCS_DW10_01_C => 16#06_c828# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1188 BXT_PORT_PCS_DW12_01_C => 16#06_c830# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1189 BXT_PORT_PCS_DW10_GRP_B => 16#06_cc28# / Register_Width,
1190 BXT_PORT_PCS_DW12_GRP_B => 16#06_cc30# / Register_Width,
1191 BXT_PORT_PCS_DW10_GRP_C => 16#06_ce28# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1192 BXT_PORT_PCS_DW12_GRP_C => 16#06_ce30# / Register_Width,
1193
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]1194 -- Broxton DDI PHY registers
1195 BXT_P_CR_GT_DISP_PWRON => 16#13_8090# / Register_Width,
1196 BXT_PHY_CTL_A => 16#06_4c00# / Register_Width,
1197 BXT_PHY_CTL_B => 16#06_4c10# / Register_Width,
1198 BXT_PHY_CTL_C => 16#06_4c20# / Register_Width,
1199 BXT_PHY_CTL_FAM_EDP => 16#06_4c80# / Register_Width,
1200 BXT_PHY_CTL_FAM_DDI => 16#06_4c90# / Register_Width,
1201
1202 -- Broxton DDI PHY common lane registers
1203 BXT_PORT_CL1CM_DW0_A => 16#16_2000# / Register_Width,
1204 BXT_PORT_CL1CM_DW0_BC => 16#06_c000# / Register_Width,
1205 BXT_PORT_CL1CM_DW9_A => 16#16_2024# / Register_Width,
1206 BXT_PORT_CL1CM_DW9_BC => 16#06_c024# / Register_Width,
1207 BXT_PORT_CL1CM_DW10_A => 16#16_2028# / Register_Width,
1208 BXT_PORT_CL1CM_DW10_BC => 16#06_c028# / Register_Width,
1209 BXT_PORT_CL1CM_DW28_A => 16#16_2070# / Register_Width,
1210 BXT_PORT_CL1CM_DW28_BC => 16#06_c070# / Register_Width,
1211 BXT_PORT_CL1CM_DW30_A => 16#16_2078# / Register_Width,
1212 BXT_PORT_CL1CM_DW30_BC => 16#06_c078# / Register_Width,
1213 BXT_PORT_CL2CM_DW6_BC => 16#06_c358# / Register_Width,
1214
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1215 -- Broxton DDI PHY TX lane registers
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1216 BXT_PORT_TX_DW2_LN0_A => 16#16_2508# / Register_Width,
1217 BXT_PORT_TX_DW3_LN0_A => 16#16_250c# / Register_Width,
1218 BXT_PORT_TX_DW4_LN0_A => 16#16_2510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1219 BXT_PORT_TX_DW14_LN0_A => 16#16_2538# / Register_Width,
1220 BXT_PORT_TX_DW14_LN1_A => 16#16_25b8# / Register_Width,
1221 BXT_PORT_TX_DW14_LN2_A => 16#16_2738# / Register_Width,
1222 BXT_PORT_TX_DW14_LN3_A => 16#16_27b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1223 BXT_PORT_TX_DW2_GRP_A => 16#16_2d08# / Register_Width,
1224 BXT_PORT_TX_DW3_GRP_A => 16#16_2d0c# / Register_Width,
1225 BXT_PORT_TX_DW4_GRP_A => 16#16_2d10# / Register_Width,
1226 BXT_PORT_TX_DW2_LN0_B => 16#06_c508# / Register_Width,
1227 BXT_PORT_TX_DW3_LN0_B => 16#06_c50c# / Register_Width,
1228 BXT_PORT_TX_DW4_LN0_B => 16#06_c510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1229 BXT_PORT_TX_DW14_LN0_B => 16#06_c538# / Register_Width,
1230 BXT_PORT_TX_DW14_LN1_B => 16#06_c5b8# / Register_Width,
1231 BXT_PORT_TX_DW14_LN2_B => 16#06_c738# / Register_Width,
1232 BXT_PORT_TX_DW14_LN3_B => 16#06_c7b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1233 BXT_PORT_TX_DW2_GRP_B => 16#06_cd08# / Register_Width,
1234 BXT_PORT_TX_DW3_GRP_B => 16#06_cd0c# / Register_Width,
1235 BXT_PORT_TX_DW4_GRP_B => 16#06_cd10# / Register_Width,
1236 BXT_PORT_TX_DW2_LN0_C => 16#06_c908# / Register_Width,
1237 BXT_PORT_TX_DW3_LN0_C => 16#06_c90c# / Register_Width,
1238 BXT_PORT_TX_DW4_LN0_C => 16#06_c910# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1239 BXT_PORT_TX_DW14_LN0_C => 16#06_c938# / Register_Width,
1240 BXT_PORT_TX_DW14_LN1_C => 16#06_c9b8# / Register_Width,
1241 BXT_PORT_TX_DW14_LN2_C => 16#06_cb38# / Register_Width,
1242 BXT_PORT_TX_DW14_LN3_C => 16#06_cbb8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1243 BXT_PORT_TX_DW2_GRP_C => 16#06_cf08# / Register_Width,
1244 BXT_PORT_TX_DW3_GRP_C => 16#06_cf0c# / Register_Width,
1245 BXT_PORT_TX_DW4_GRP_C => 16#06_cf10# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1246
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]1247 -- Broxton DDI PHY ref registers
1248 BXT_PORT_REF_DW3_A => 16#16_218c# / Register_Width,
1249 BXT_PORT_REF_DW3_BC => 16#06_c18c# / Register_Width,
1250 BXT_PORT_REF_DW6_A => 16#16_2198# / Register_Width,
1251 BXT_PORT_REF_DW6_BC => 16#06_c198# / Register_Width,
1252 BXT_PORT_REF_DW8_A => 16#16_21a0# / Register_Width,
1253 BXT_PORT_REF_DW8_BC => 16#06_c1a0# / Register_Width,
1254
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1255 -- Power Down Well registers
1256 PWR_WELL_CTL_BIOS => 16#04_5400# / Register_Width,
1257 PWR_WELL_CTL_DRIVER => 16#04_5404# / Register_Width,
1258 PWR_WELL_CTL_KVMR => 16#04_5408# / Register_Width,
1259 PWR_WELL_CTL_DEBUG => 16#04_540c# / Register_Width,
1260 PWR_WELL_CTL5 => 16#04_5410# / Register_Width,
1261 PWR_WELL_CTL6 => 16#04_5414# / Register_Width,
1262
1263 -- class Panel registers
1264 PCH_PP_STATUS => 16#0c_7200# / Register_Width,
1265 PCH_PP_CONTROL => 16#0c_7204# / Register_Width,
1266 PCH_PP_ON_DELAYS => 16#0c_7208# / Register_Width,
1267 PCH_PP_OFF_DELAYS => 16#0c_720c# / Register_Width,
1268 PCH_PP_DIVISOR => 16#0c_7210# / Register_Width,
1269 BLC_PWM_CPU_CTL => 16#04_8254# / Register_Width,
1270 BLC_PWM_PCH_CTL2 => 16#0c_8254# / Register_Width,
1271
1272 -- PCH LVDS Connector Registers
1273 PCH_LVDS => 16#0e_1180# / Register_Width,
1274
1275 -- PCH ADPA Connector Registers
1276 PCH_ADPA => 16#0e_1100# / Register_Width,
1277
1278 -- PCH HDMIB Connector Registers
1279 PCH_HDMIB => 16#0e_1140# / Register_Width,
1280
1281 -- PCH HDMIC Connector Registers
1282 PCH_HDMIC => 16#0e_1150# / Register_Width,
1283
1284 -- PCH HDMID Connector Registers
1285 PCH_HDMID => 16#0e_1160# / Register_Width,
1286
1287 -- Intel Registers
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame^]1288 CPU_VGACNTRL => 16#04_1000# / Register_Width,
1289 GMCH_VGACNTRL => 16#07_1400# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1290 FUSE_STATUS => 16#04_2000# / Register_Width,
1291 FBA_CFB_BASE => 16#04_3200# / Register_Width,
1292 IPS_CTL => 16#04_3408# / Register_Width,
1293 ARB_CTL => 16#04_5000# / Register_Width,
1294 DBUF_CTL => 16#04_5008# / Register_Width,
1295 NDE_RSTWRN_OPT => 16#04_6408# / Register_Width,
1296 PCH_DREF_CONTROL => 16#0c_6200# / Register_Width,
1297 BLC_PWM_PCH_CTL1 => 16#0c_8250# / Register_Width,
1298 BLC_PWM_CPU_CTL2 => 16#04_8250# / Register_Width,
1299 PCH_DPLL_SEL => 16#0c_7000# / Register_Width,
1300 GT_MAILBOX => 16#13_8124# / Register_Width,
1301 GT_MAILBOX_DATA => 16#13_8128# / Register_Width,
1302 GT_MAILBOX_DATA_1 => 16#13_812c# / Register_Width,
1303
1304 PCH_DP_B => 16#0e_4100# / Register_Width,
1305 PCH_DP_AUX_CTL_B => 16#0e_4110# / Register_Width,
1306 PCH_DP_AUX_DATA_B_1 => 16#0e_4114# / Register_Width,
1307 PCH_DP_AUX_DATA_B_2 => 16#0e_4118# / Register_Width,
1308 PCH_DP_AUX_DATA_B_3 => 16#0e_411c# / Register_Width,
1309 PCH_DP_AUX_DATA_B_4 => 16#0e_4120# / Register_Width,
1310 PCH_DP_AUX_DATA_B_5 => 16#0e_4124# / Register_Width,
1311 PCH_DP_C => 16#0e_4200# / Register_Width,
1312 PCH_DP_AUX_CTL_C => 16#0e_4210# / Register_Width,
1313 PCH_DP_AUX_DATA_C_1 => 16#0e_4214# / Register_Width,
1314 PCH_DP_AUX_DATA_C_2 => 16#0e_4218# / Register_Width,
1315 PCH_DP_AUX_DATA_C_3 => 16#0e_421c# / Register_Width,
1316 PCH_DP_AUX_DATA_C_4 => 16#0e_4220# / Register_Width,
1317 PCH_DP_AUX_DATA_C_5 => 16#0e_4224# / Register_Width,
1318 PCH_DP_D => 16#0e_4300# / Register_Width,
1319 PCH_DP_AUX_CTL_D => 16#0e_4310# / Register_Width,
1320 PCH_DP_AUX_DATA_D_1 => 16#0e_4314# / Register_Width,
1321 PCH_DP_AUX_DATA_D_2 => 16#0e_4318# / Register_Width,
1322 PCH_DP_AUX_DATA_D_3 => 16#0e_431c# / Register_Width,
1323 PCH_DP_AUX_DATA_D_4 => 16#0e_4320# / Register_Width,
1324 PCH_DP_AUX_DATA_D_5 => 16#0e_4324# / Register_Width,
1325
1326 -- watermark registers
1327 WM1_LP_ILK => 16#04_5108# / Register_Width,
1328 WM2_LP_ILK => 16#04_510c# / Register_Width,
1329 WM3_LP_ILK => 16#04_5110# / Register_Width,
1330
1331 -- audio VID/DID
1332 AUD_VID_DID => 16#06_5020# / Register_Width,
1333 PCH_AUD_VID_DID => 16#0e_5020# / Register_Width,
1334
1335 -- interrupt registers
1336 DEISR => 16#04_4000# / Register_Width,
1337 DEIMR => 16#04_4004# / Register_Width,
1338 DEIIR => 16#04_4008# / Register_Width,
1339 DEIER => 16#04_400c# / Register_Width,
1340 GTISR => 16#04_4010# / Register_Width,
1341 GTIMR => 16#04_4014# / Register_Width,
1342 GTIIR => 16#04_4018# / Register_Width,
1343 GTIER => 16#04_401c# / Register_Width,
1344 SDEISR => 16#0c_4000# / Register_Width,
1345 SDEIMR => 16#0c_4004# / Register_Width,
1346 SDEIIR => 16#0c_4008# / Register_Width,
1347 SDEIER => 16#0c_400c# / Register_Width,
1348
1349 -- I2C stuff
1350 PCH_GMBUS0 => 16#0c_5100# / Register_Width,
1351 PCH_GMBUS1 => 16#0c_5104# / Register_Width,
1352 PCH_GMBUS2 => 16#0c_5108# / Register_Width,
1353 PCH_GMBUS3 => 16#0c_510c# / Register_Width,
1354 PCH_GMBUS4 => 16#0c_5110# / Register_Width,
1355 PCH_GMBUS5 => 16#0c_5120# / Register_Width,
1356
1357 -- clock gating -- maybe have to touch this
1358 DSPCLK_GATE_D => 16#04_2020# / Register_Width,
1359 PCH_FDI_CHICKEN_B_C => 16#0c_2000# / Register_Width,
1360 PCH_DSPCLK_GATE_D => 16#0c_2020# / Register_Width,
1361
1362 -- hotplug and initial detection
1363 HOTPLUG_CTL => 16#04_4030# / Register_Width,
1364 SHOTPLUG_CTL => 16#0c_4030# / Register_Width,
1365 SFUSE_STRAP => 16#0c_2014# / Register_Width,
1366
1367 -- Render Engine Command Streamer
1368 ARB_MODE => 16#00_4030# / Register_Width,
1369 HWS_PGA => 16#00_4080# / Register_Width,
1370 RCS_RING_BUFFER_TAIL => 16#00_2030# / Register_Width,
1371 VCS_RING_BUFFER_TAIL => 16#01_2030# / Register_Width,
1372 BCS_RING_BUFFER_TAIL => 16#02_2030# / Register_Width,
1373 RCS_RING_BUFFER_HEAD => 16#00_2034# / Register_Width,
1374 VCS_RING_BUFFER_HEAD => 16#01_2034# / Register_Width,
1375 BCS_RING_BUFFER_HEAD => 16#02_2034# / Register_Width,
1376 RCS_RING_BUFFER_STRT => 16#00_2038# / Register_Width,
1377 VCS_RING_BUFFER_STRT => 16#01_2038# / Register_Width,
1378 BCS_RING_BUFFER_STRT => 16#02_2038# / Register_Width,
1379 RCS_RING_BUFFER_CTL => 16#00_203c# / Register_Width,
1380 VCS_RING_BUFFER_CTL => 16#01_203c# / Register_Width,
1381 BCS_RING_BUFFER_CTL => 16#02_203c# / Register_Width,
1382 MI_MODE => 16#00_209c# / Register_Width,
1383 INSTPM => 16#00_20c0# / Register_Width,
1384 GAB_CTL_REG => 16#02_4000# / Register_Width,
1385 PP_DCLV_HIGH => 16#00_2220# / Register_Width,
1386 PP_DCLV_LOW => 16#00_2228# / Register_Width,
1387 VCS_PP_DCLV_HIGH => 16#01_2220# / Register_Width,
1388 VCS_PP_DCLV_LOW => 16#01_2228# / Register_Width,
1389 BCS_PP_DCLV_HIGH => 16#02_2220# / Register_Width,
1390 BCS_PP_DCLV_LOW => 16#02_2228# / Register_Width,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1391 ILK_DISPLAY_CHICKEN2 => 16#04_2004# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1392 UCGCTL1 => 16#00_9400# / Register_Width,
1393 UCGCTL2 => 16#00_9404# / Register_Width,
1394 MBCTL => 16#00_907c# / Register_Width,
1395 HWSTAM => 16#00_2098# / Register_Width,
1396 VCS_HWSTAM => 16#01_2098# / Register_Width,
1397 BCS_HWSTAM => 16#02_2098# / Register_Width,
1398 IIR => 16#04_4028# / Register_Width,
1399 PIPE_FRMCNT_A => 16#07_0040# / Register_Width,
1400 PIPE_FRMCNT_B => 16#07_1040# / Register_Width,
1401 PIPE_FRMCNT_C => 16#07_2040# / Register_Width,
1402 FBC_CTL => 16#04_3208# / Register_Width,
1403 PIPE_VSYNCSHIFT_A => 16#06_0028# / Register_Width,
1404 PIPE_VSYNCSHIFT_B => 16#06_1028# / Register_Width,
1405 PIPE_VSYNCSHIFT_C => 16#06_2028# / Register_Width,
1406 WM_PIPE_A => 16#04_5100# / Register_Width,
1407 WM_PIPE_B => 16#04_5104# / Register_Width,
1408 WM_PIPE_C => 16#04_5200# / Register_Width,
1409 PIPE_SCANLINE_A => 16#07_0000# / Register_Width,
1410 PIPE_SCANLINE_B => 16#07_1000# / Register_Width,
1411 PIPE_SCANLINE_C => 16#07_2000# / Register_Width,
1412 GFX_MODE => 16#00_2520# / Register_Width,
1413 CACHE_MODE_0 => 16#00_2120# / Register_Width,
1414 SLEEP_PSMI_CONTROL => 16#01_2050# / Register_Width,
1415 CTX_SIZE => 16#00_21a0# / Register_Width,
1416 GAC_ECO_BITS => 16#01_4090# / Register_Width,
1417 GAM_ECOCHK => 16#00_4090# / Register_Width,
1418 QUIRK_02084 => 16#00_2084# / Register_Width,
1419 QUIRK_02090 => 16#00_2090# / Register_Width,
1420 GT_MODE => 16#00_20d0# / Register_Width,
1421 QUIRK_F0060 => 16#0f_0060# / Register_Width,
1422 QUIRK_F1060 => 16#0f_1060# / Register_Width,
1423 QUIRK_F2060 => 16#0f_2060# / Register_Width,
1424 AUD_CNTRL_ST2 => 16#0e_50c0# / Register_Width,
1425 AUD_CNTL_ST_A => 16#0e_50b4# / Register_Width,
1426 AUD_CNTL_ST_B => 16#0e_51b4# / Register_Width,
1427 AUD_CNTL_ST_C => 16#0e_52b4# / Register_Width,
1428 AUD_HDMIW_HDMIEDID_A => 16#0e_5050# / Register_Width,
1429 AUD_HDMIW_HDMIEDID_B => 16#0e_5150# / Register_Width,
1430 AUD_HDMIW_HDMIEDID_C => 16#0e_5250# / Register_Width,
1431 AUD_CONFIG_A => 16#0e_5000# / Register_Width,
1432 AUD_CONFIG_B => 16#0e_5100# / Register_Width,
1433 AUD_CONFIG_C => 16#0e_5200# / Register_Width,
1434 TRANS_DP_CTL_A => 16#0e_0300# / Register_Width,
1435 TRANS_DP_CTL_B => 16#0e_1300# / Register_Width,
1436 TRANS_DP_CTL_C => 16#0e_2300# / Register_Width,
1437 TRANS_VSYNCSHIFT_A => 16#0e_0028# / Register_Width,
1438 TRANS_VSYNCSHIFT_B => 16#0e_1028# / Register_Width,
1439 TRANS_VSYNCSHIFT_C => 16#0e_2028# / Register_Width,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]1440 PCH_RAWCLK_FREQ => 16#0c_6204# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1441 QUIRK_C2004 => 16#0c_2004# / Register_Width);
1442
1443 subtype Registers_Index is Registers_Invalid_Index range
1444 Registers_Invalid_Index'Succ (Invalid_Register) ..
1445 Registers_Invalid_Index'Last;
1446
1447 -- aliased registers
1448 DP_CTL_A : constant Registers_Index := DDI_BUF_CTL_A;
1449 DP_AUX_CTL_A : constant Registers_Index := DDI_AUX_CTL_A;
1450 DP_AUX_DATA_A_1 : constant Registers_Index := DDI_AUX_DATA_A_1;
1451 DP_AUX_DATA_A_2 : constant Registers_Index := DDI_AUX_DATA_A_2;
1452 DP_AUX_DATA_A_3 : constant Registers_Index := DDI_AUX_DATA_A_3;
1453 DP_AUX_DATA_A_4 : constant Registers_Index := DDI_AUX_DATA_A_4;
1454 DP_AUX_DATA_A_5 : constant Registers_Index := DDI_AUX_DATA_A_5;
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1455 ILK_DISPLAY_CHICKEN1 : constant Registers_Index := FUSE_STATUS;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1456
1457 ---------------------------------------------------------------------------
1458
1459 Default_Timeout_MS : constant := 10;
1460
1461 ---------------------------------------------------------------------------
1462
1463 procedure Posting_Read
1464 (Register : in Registers_Index)
1465 with
1466 Global => (In_Out => Register_State),
1467 Depends => (Register_State =>+ (Register)),
1468 Pre => True,
1469 Post => True;
1470
1471 pragma Warnings (GNATprove, Off, "unused variable ""Verbose""",
1472 Reason => "Only used on debugging path");
1473 procedure Read
1474 (Register : in Registers_Index;
1475 Value : out Word32;
1476 Verbose : in Boolean := True)
1477 with
1478 Global => (In_Out => Register_State),
1479 Depends => ((Value, Register_State) => (Register, Register_State),
1480 null => Verbose),
1481 Pre => True,
1482 Post => True;
1483 pragma Warnings (GNATprove, On, "unused variable ""Verbose""");
1484
1485 procedure Write
1486 (Register : Registers_Index;
1487 Value : Word32)
1488 with
1489 Global => (In_Out => Register_State),
1490 Depends => (Register_State => (Register, Register_State, Value)),
1491 Pre => True,
1492 Post => True;
1493
1494 procedure Is_Set_Mask
1495 (Register : in Registers_Index;
1496 Mask : in Word32;
1497 Result : out Boolean);
1498
1499 pragma Warnings (GNATprove, Off, "unused initial value of ""Verbose""",
1500 Reason => "Only used on debugging path");
Nico Huberbcb2c472017-02-02 16:39:26 +0100[diff] [blame]1501 procedure Wait
1502 (Register : Registers_Index;
1503 Mask : Word32;
1504 Value : Word32;
1505 TOut_MS : Natural := Default_Timeout_MS;
1506 Verbose : Boolean := False);
1507
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1508 procedure Wait_Set_Mask
1509 (Register : Registers_Index;
1510 Mask : Word32;
1511 TOut_MS : Natural := Default_Timeout_MS;
1512 Verbose : Boolean := False);
1513
1514 procedure Wait_Unset_Mask
1515 (Register : Registers_Index;
1516 Mask : Word32;
1517 TOut_MS : Natural := Default_Timeout_MS;
1518 Verbose : Boolean := False);
1519 pragma Warnings (GNATprove, On, "unused initial value of ""Verbose""");
1520
1521 procedure Set_Mask
1522 (Register : Registers_Index;
1523 Mask : Word32);
1524
1525 procedure Unset_Mask
1526 (Register : Registers_Index;
1527 Mask : Word32);
1528
1529 procedure Unset_And_Set_Mask
1530 (Register : Registers_Index;
1531 Mask_Unset : Word32;
1532 Mask_Set : Word32);
1533
Nico Huber17d64b62017-07-15 20:51:25 +0200[diff] [blame]1534 procedure Clear_Fences;
1535
Nico Huberb03c8f12017-08-25 13:29:08 +0200[diff] [blame]1536 procedure Add_Fence
1537 (First_Page : in GTT_Range;
1538 Last_Page : in GTT_Range;
1539 Tiling : in XY_Tiling;
1540 Pitch : in Natural;
1541 Success : out Boolean);
1542
1543 procedure Remove_Fence (First_Page, Last_Page : GTT_Range);
1544
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1545 pragma Warnings (Off, "declaration of ""Write_GTT"" hides one at *");
1546 procedure Write_GTT
1547 (GTT_Page : GTT_Range;
1548 Device_Address : GTT_Address_Type;
1549 Valid : Boolean)
1550 with
1551 Global => (In_Out => GTT_State),
1552 Depends => (GTT_State =>+ (GTT_Page, Device_Address, Valid)),
1553 Pre => True,
1554 Post => True;
1555 pragma Warnings (On, "declaration of ""Write_GTT"" hides one at *");
1556
Nico Huber2b6f6992017-07-09 18:11:34 +0200[diff] [blame]1557 procedure Set_Register_Base (Base : Word64; GTT_Base : Word64 := 0)
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1558 with
1559 Global => (Output => Address_State),
Nico Huber2b6f6992017-07-09 18:11:34 +0200[diff] [blame]1560 Depends => (Address_State => (Base, GTT_Base)),
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1561 Pre => True,
1562 Post => True;
1563
1564end HW.GFX.GMA.Registers;