| commit | 408204409b3324ae6ae7043826ee5ab7bb45bb2f | [log] [tgz] |
|---|---|---|
| author | Nico Huber <nico.huber@secunet.com> | Fri Jan 20 14:00:53 2017 +0100 |
| committer | Nico Huber <nico.h@gmx.de> | Sat Jun 03 15:22:31 2017 +0200 |
| tree | 771cd2b63dc548d61a0d3a42f7bce72c7ed3acd6 | |
| parent | 21da5741378af7c9f8db23b55aa316a905ae9183 [diff] |
gma broxton: Start off with power domains and CDClk It's close to the respective code for Skylake but still different enough for a separate implementation. We start with a default CDClk of 288MHz which is enough for resolutions up to 2560x1600. Change-Id: I44364191236f421b2b89c9a019a50713f7c20525 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18243 Tested-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>