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review.sourcearcade.org / libgfxinit / 4b0239f549c99b1c393f099fe21c7055860fbe7a / . / common / hw-gfx-gma-registers.ads
blob: 84caefc8708cb44ee81ae5f6d3150b785e280bdb [file] [log] [blame]
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1--
2-- Copyright (C) 2015-2016 secunet Security Networks AG
3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
Nico Huber125a29e2016-10-18 00:23:54 +0200[diff] [blame]6-- the Free Software Foundation; either version 2 of the License, or
7-- (at your option) any later version.
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]8--
9-- This program is distributed in the hope that it will be useful,
10-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12-- GNU General Public License for more details.
13--
14
15with System;
16with HW.GFX.GMA;
17with HW.GFX.GMA.Config;
18
19private package HW.GFX.GMA.Registers
20with
21 Abstract_State =>
22 ((Address_State with Part_Of => GMA.State),
23 (Register_State with External, Part_Of => GMA.Device_State),
24 (GTT_State with External, Part_Of => GMA.Device_State)),
25 Initializes => Address_State
26is
27 type Registers_Invalid_Index is
28 (Invalid_Register, -- Allow a placeholder when access is not acceptable
29
30 RCS_RING_BUFFER_TAIL,
31 RCS_RING_BUFFER_HEAD,
32 RCS_RING_BUFFER_STRT,
33 RCS_RING_BUFFER_CTL,
34 QUIRK_02084,
35 QUIRK_02090,
36 HWSTAM,
37 MI_MODE,
38 INSTPM,
39 GT_MODE,
40 CACHE_MODE_0,
41 CTX_SIZE,
42 PP_DCLV_HIGH,
43 PP_DCLV_LOW,
44 GFX_MODE,
45 ARB_MODE,
46 HWS_PGA,
47 GAM_ECOCHK,
48 MBCTL,
49 UCGCTL1,
50 UCGCTL2,
51 VCS_RING_BUFFER_TAIL,
52 VCS_RING_BUFFER_HEAD,
53 VCS_RING_BUFFER_STRT,
54 VCS_RING_BUFFER_CTL,
55 SLEEP_PSMI_CONTROL,
56 VCS_HWSTAM,
57 VCS_PP_DCLV_HIGH,
58 VCS_PP_DCLV_LOW,
59 GAC_ECO_BITS,
60 BCS_RING_BUFFER_TAIL,
61 BCS_RING_BUFFER_HEAD,
62 BCS_RING_BUFFER_STRT,
63 BCS_RING_BUFFER_CTL,
64 BCS_HWSTAM,
65 BCS_PP_DCLV_HIGH,
66 BCS_PP_DCLV_LOW,
67 GAB_CTL_REG,
68 VGACNTRL,
69 FUSE_STATUS,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]70 ILK_DISPLAY_CHICKEN2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]71 DSPCLK_GATE_D,
72 FBA_CFB_BASE,
73 FBC_CTL,
74 IPS_CTL,
75 DEISR,
76 DEIMR,
77 DEIIR,
78 DEIER,
79 GTISR,
80 GTIMR,
81 GTIIR,
82 GTIER,
83 IIR,
84 HOTPLUG_CTL,
85 ARB_CTL,
86 DBUF_CTL,
87 WM_PIPE_A,
88 WM_PIPE_B,
89 WM1_LP_ILK,
90 WM2_LP_ILK,
91 WM3_LP_ILK,
92 WM_PIPE_C,
93 WM_LINETIME_A,
94 WM_LINETIME_B,
95 WM_LINETIME_C,
96 PWR_WELL_CTL_BIOS,
97 PWR_WELL_CTL_DRIVER,
98 PWR_WELL_CTL_KVMR,
99 PWR_WELL_CTL_DEBUG,
100 PWR_WELL_CTL5,
101 PWR_WELL_CTL6,
102 CDCLK_CTL,
103 LCPLL1_CTL,
104 LCPLL2_CTL,
105 SPLL_CTL,
106 WRPLL_CTL_1,
107 WRPLL_CTL_2,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]108 BXT_DE_PLL_ENABLE,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame^]109 BXT_PORT_PLL_ENABLE_A,
110 BXT_PORT_PLL_ENABLE_B,
111 BXT_PORT_PLL_ENABLE_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]112 PORT_CLK_SEL_DDIA,
113 PORT_CLK_SEL_DDIB,
114 PORT_CLK_SEL_DDIC,
115 PORT_CLK_SEL_DDID,
116 PORT_CLK_SEL_DDIE,
117 TRANSA_CLK_SEL,
118 TRANSB_CLK_SEL,
119 TRANSC_CLK_SEL,
120 NDE_RSTWRN_OPT,
121 BLC_PWM_CPU_CTL2,
122 BLC_PWM_CPU_CTL,
123 HTOTAL_A,
124 HBLANK_A,
125 HSYNC_A,
126 VTOTAL_A,
127 VBLANK_A,
128 VSYNC_A,
129 PIPEASRC,
130 PIPE_VSYNCSHIFT_A,
131 PIPEA_DATA_M1,
132 PIPEA_DATA_N1,
133 PIPEA_LINK_M1,
134 PIPEA_LINK_N1,
135 FDI_TX_CTL_A,
136 PIPEA_DDI_FUNC_CTL,
137 PIPEA_MSA_MISC,
138 SRD_CTL_A,
139 SRD_STATUS_A,
140 HTOTAL_B,
141 HBLANK_B,
142 HSYNC_B,
143 VTOTAL_B,
144 VBLANK_B,
145 VSYNC_B,
146 PIPEBSRC,
147 PIPE_VSYNCSHIFT_B,
148 PIPEB_DATA_M1,
149 PIPEB_DATA_N1,
150 PIPEB_LINK_M1,
151 PIPEB_LINK_N1,
152 FDI_TX_CTL_B,
153 PIPEB_DDI_FUNC_CTL,
154 PIPEB_MSA_MISC,
155 SRD_CTL_B,
156 SRD_STATUS_B,
157 HTOTAL_C,
158 HBLANK_C,
159 HSYNC_C,
160 VTOTAL_C,
161 VBLANK_C,
162 VSYNC_C,
163 PIPECSRC,
164 PIPE_VSYNCSHIFT_C,
165 PIPEC_DATA_M1,
166 PIPEC_DATA_N1,
167 PIPEC_LINK_M1,
168 PIPEC_LINK_N1,
169 FDI_TX_CTL_C,
170 PIPEC_DDI_FUNC_CTL,
171 PIPEC_MSA_MISC,
172 SRD_CTL_C,
173 SRD_STATUS_C,
174 DDI_BUF_CTL_A,
175 DDI_AUX_CTL_A,
176 DDI_AUX_DATA_A_1,
177 DDI_AUX_DATA_A_2,
178 DDI_AUX_DATA_A_3,
179 DDI_AUX_DATA_A_4,
180 DDI_AUX_DATA_A_5,
181 DDI_AUX_MUTEX_A,
182 DP_TP_CTL_A,
183 DDI_BUF_CTL_B,
184 DDI_AUX_CTL_B,
185 DDI_AUX_DATA_B_1,
186 DDI_AUX_DATA_B_2,
187 DDI_AUX_DATA_B_3,
188 DDI_AUX_DATA_B_4,
189 DDI_AUX_DATA_B_5,
190 DDI_AUX_MUTEX_B,
191 DP_TP_CTL_B,
192 DP_TP_STATUS_B,
193 DDI_BUF_CTL_C,
194 DDI_AUX_CTL_C,
195 DDI_AUX_DATA_C_1,
196 DDI_AUX_DATA_C_2,
197 DDI_AUX_DATA_C_3,
198 DDI_AUX_DATA_C_4,
199 DDI_AUX_DATA_C_5,
200 DDI_AUX_MUTEX_C,
201 DP_TP_CTL_C,
202 DP_TP_STATUS_C,
203 DDI_BUF_CTL_D,
204 DDI_AUX_CTL_D,
205 DDI_AUX_DATA_D_1,
206 DDI_AUX_DATA_D_2,
207 DDI_AUX_DATA_D_3,
208 DDI_AUX_DATA_D_4,
209 DDI_AUX_DATA_D_5,
210 DDI_AUX_MUTEX_D,
211 DP_TP_CTL_D,
212 DP_TP_STATUS_D,
213 DDI_BUF_CTL_E,
214 DP_TP_CTL_E,
215 DP_TP_STATUS_E,
216 SRD_CTL,
217 SRD_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]218 BXT_PHY_CTL_A,
219 BXT_PHY_CTL_B,
220 BXT_PHY_CTL_C,
221 BXT_PHY_CTL_FAM_EDP,
222 BXT_PHY_CTL_FAM_DDI,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]223 AUD_VID_DID,
224 PFA_WIN_POS,
225 PFA_WIN_SZ,
226 PFA_CTL_1,
227 PS_WIN_POS_1_A,
228 PS_WIN_SZ_1_A,
229 PS_CTRL_1_A,
230 PS_WIN_POS_2_A,
231 PS_WIN_SZ_2_A,
232 PS_CTRL_2_A,
233 PFB_WIN_POS,
234 PFB_WIN_SZ,
235 PFB_CTL_1,
236 PS_WIN_POS_1_B,
237 PS_WIN_SZ_1_B,
238 PS_CTRL_1_B,
239 PS_WIN_POS_2_B,
240 PS_WIN_SZ_2_B,
241 PS_CTRL_2_B,
242 PFC_WIN_POS,
243 PFC_WIN_SZ,
244 PFC_CTL_1,
245 PS_WIN_POS_1_C,
246 PS_WIN_SZ_1_C,
247 PS_CTRL_1_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]248 BXT_PORT_CL1CM_DW0_BC,
249 BXT_PORT_CL1CM_DW9_BC,
250 BXT_PORT_CL1CM_DW10_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame^]251 BXT_PORT_PLL_EBB_0_B,
252 BXT_PORT_PLL_EBB_4_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]253 DPLL1_CFGR1,
254 DPLL1_CFGR2,
255 DPLL2_CFGR1,
256 DPLL2_CFGR2,
257 DPLL3_CFGR1,
258 DPLL3_CFGR2,
259 DPLL_CTRL1,
260 DPLL_CTRL2,
261 DPLL_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]262 BXT_PORT_CL1CM_DW28_BC,
263 BXT_PORT_CL1CM_DW30_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame^]264 BXT_PORT_PLL_0_B,
265 BXT_PORT_PLL_1_B,
266 BXT_PORT_PLL_2_B,
267 BXT_PORT_PLL_3_B,
268 BXT_PORT_PLL_6_B,
269 BXT_PORT_PLL_8_B,
270 BXT_PORT_PLL_9_B,
271 BXT_PORT_PLL_10_B,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]272 BXT_PORT_REF_DW3_BC,
273 BXT_PORT_REF_DW6_BC,
274 BXT_PORT_REF_DW8_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame^]275 BXT_PORT_PLL_EBB_0_C,
276 BXT_PORT_PLL_EBB_4_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]277 BXT_PORT_CL2CM_DW6_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame^]278 BXT_PORT_PLL_0_C,
279 BXT_PORT_PLL_1_C,
280 BXT_PORT_PLL_2_C,
281 BXT_PORT_PLL_3_C,
282 BXT_PORT_PLL_6_C,
283 BXT_PORT_PLL_8_C,
284 BXT_PORT_PLL_9_C,
285 BXT_PORT_PLL_10_C,
286 BXT_PORT_PCS_DW12_01_B,
287 BXT_PORT_PCS_DW12_01_C,
288 BXT_PORT_PCS_DW12_GRP_B,
289 BXT_PORT_PCS_DW12_GRP_C,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]290 BXT_DE_PLL_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]291 HTOTAL_EDP,
292 HBLANK_EDP,
293 HSYNC_EDP,
294 VTOTAL_EDP,
295 VBLANK_EDP,
296 VSYNC_EDP,
297 PIPE_EDP_DATA_M1,
298 PIPE_EDP_DATA_N1,
299 PIPE_EDP_LINK_M1,
300 PIPE_EDP_LINK_N1,
301 PIPE_EDP_DDI_FUNC_CTL,
302 PIPE_EDP_MSA_MISC,
303 SRD_CTL_EDP,
304 SRD_STATUS_EDP,
305 PIPE_SCANLINE_A,
306 PIPEACONF,
307 PIPEAMISC,
308 PIPE_FRMCNT_A,
309 DSPACNTR,
310 DSPALINOFF,
311 DSPASTRIDE,
312 PLANE_POS_1_A,
313 PLANE_SIZE_1_A,
314 DSPASURF,
315 DSPATILEOFF,
316 PLANE_WM_1_A_0,
317 PLANE_WM_1_A_1,
318 PLANE_WM_1_A_2,
319 PLANE_WM_1_A_3,
320 PLANE_WM_1_A_4,
321 PLANE_WM_1_A_5,
322 PLANE_WM_1_A_6,
323 PLANE_WM_1_A_7,
324 PLANE_BUF_CFG_1_A,
325 SPACNTR,
326 PIPE_SCANLINE_B,
327 PIPEBCONF,
328 PIPEBMISC,
329 PIPE_FRMCNT_B,
330 DSPBCNTR,
331 DSPBLINOFF,
332 DSPBSTRIDE,
333 PLANE_POS_1_B,
334 PLANE_SIZE_1_B,
335 DSPBSURF,
336 DSPBTILEOFF,
337 PLANE_WM_1_B_0,
338 PLANE_WM_1_B_1,
339 PLANE_WM_1_B_2,
340 PLANE_WM_1_B_3,
341 PLANE_WM_1_B_4,
342 PLANE_WM_1_B_5,
343 PLANE_WM_1_B_6,
344 PLANE_WM_1_B_7,
345 PLANE_BUF_CFG_1_B,
346 SPBCNTR,
347 PIPE_SCANLINE_C,
348 PIPECCONF,
349 PIPECMISC,
350 PIPE_FRMCNT_C,
351 DSPCCNTR,
352 DSPCLINOFF,
353 DSPCSTRIDE,
354 PLANE_POS_1_C,
355 PLANE_SIZE_1_C,
356 DSPCSURF,
357 DSPCTILEOFF,
358 PLANE_WM_1_C_0,
359 PLANE_WM_1_C_1,
360 PLANE_WM_1_C_2,
361 PLANE_WM_1_C_3,
362 PLANE_WM_1_C_4,
363 PLANE_WM_1_C_5,
364 PLANE_WM_1_C_6,
365 PLANE_WM_1_C_7,
366 PLANE_BUF_CFG_1_C,
367 SPCCNTR,
368 PIPE_EDP_CONF,
369 PCH_FDI_CHICKEN_B_C,
370 QUIRK_C2004,
371 SFUSE_STRAP,
372 PCH_DSPCLK_GATE_D,
373 SDEISR,
374 SDEIMR,
375 SDEIIR,
376 SDEIER,
377 SHOTPLUG_CTL,
378 PCH_GMBUS0,
379 PCH_GMBUS1,
380 PCH_GMBUS2,
381 PCH_GMBUS3,
382 PCH_GMBUS4,
383 PCH_GMBUS5,
384 SBI_ADDR,
385 SBI_DATA,
386 SBI_CTL_STAT,
387 PCH_DPLL_A,
388 PCH_DPLL_B,
389 PCH_PIXCLK_GATE,
390 PCH_FPA0,
391 PCH_FPA1,
392 PCH_FPB0,
393 PCH_FPB1,
394 PCH_DREF_CONTROL,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]395 PCH_RAWCLK_FREQ,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]396 PCH_DPLL_SEL,
397 PCH_PP_STATUS,
398 PCH_PP_CONTROL,
399 PCH_PP_ON_DELAYS,
400 PCH_PP_OFF_DELAYS,
401 PCH_PP_DIVISOR,
402 BLC_PWM_PCH_CTL1,
403 BLC_PWM_PCH_CTL2,
404 TRANS_HTOTAL_A,
405 TRANS_HBLANK_A,
406 TRANS_HSYNC_A,
407 TRANS_VTOTAL_A,
408 TRANS_VBLANK_A,
409 TRANS_VSYNC_A,
410 TRANS_VSYNCSHIFT_A,
411 TRANSA_DATA_M1,
412 TRANSA_DATA_N1,
413 TRANSA_DP_LINK_M1,
414 TRANSA_DP_LINK_N1,
415 TRANS_DP_CTL_A,
416 TRANS_HTOTAL_B,
417 TRANS_HBLANK_B,
418 TRANS_HSYNC_B,
419 TRANS_VTOTAL_B,
420 TRANS_VBLANK_B,
421 TRANS_VSYNC_B,
422 TRANS_VSYNCSHIFT_B,
423 TRANSB_DATA_M1,
424 TRANSB_DATA_N1,
425 TRANSB_DP_LINK_M1,
426 TRANSB_DP_LINK_N1,
427 PCH_ADPA,
428 PCH_HDMIB,
429 PCH_HDMIC,
430 PCH_HDMID,
431 PCH_LVDS,
432 TRANS_DP_CTL_B,
433 TRANS_HTOTAL_C,
434 TRANS_HBLANK_C,
435 TRANS_HSYNC_C,
436 TRANS_VTOTAL_C,
437 TRANS_VBLANK_C,
438 TRANS_VSYNC_C,
439 TRANS_VSYNCSHIFT_C,
440 TRANSC_DATA_M1,
441 TRANSC_DATA_N1,
442 TRANSC_DP_LINK_M1,
443 TRANSC_DP_LINK_N1,
444 TRANS_DP_CTL_C,
445 PCH_DP_B,
446 PCH_DP_AUX_CTL_B,
447 PCH_DP_AUX_DATA_B_1,
448 PCH_DP_AUX_DATA_B_2,
449 PCH_DP_AUX_DATA_B_3,
450 PCH_DP_AUX_DATA_B_4,
451 PCH_DP_AUX_DATA_B_5,
452 PCH_DP_C,
453 PCH_DP_AUX_CTL_C,
454 PCH_DP_AUX_DATA_C_1,
455 PCH_DP_AUX_DATA_C_2,
456 PCH_DP_AUX_DATA_C_3,
457 PCH_DP_AUX_DATA_C_4,
458 PCH_DP_AUX_DATA_C_5,
459 PCH_DP_D,
460 PCH_DP_AUX_CTL_D,
461 PCH_DP_AUX_DATA_D_1,
462 PCH_DP_AUX_DATA_D_2,
463 PCH_DP_AUX_DATA_D_3,
464 PCH_DP_AUX_DATA_D_4,
465 PCH_DP_AUX_DATA_D_5,
466 AUD_CONFIG_A,
467 PCH_AUD_VID_DID,
468 AUD_HDMIW_HDMIEDID_A,
469 AUD_CNTL_ST_A,
470 AUD_CNTRL_ST2,
471 AUD_CONFIG_B,
472 AUD_HDMIW_HDMIEDID_B,
473 AUD_CNTL_ST_B,
474 AUD_CONFIG_C,
475 AUD_HDMIW_HDMIEDID_C,
476 AUD_CNTL_ST_C,
477 TRANSACONF,
478 FDI_RXA_CTL,
479 FDI_RX_MISC_A,
480 FDI_RXA_IIR,
481 FDI_RXA_IMR,
482 FDI_RXA_TUSIZE1,
483 QUIRK_F0060,
484 TRANSA_CHICKEN2,
485 TRANSBCONF,
486 FDI_RXB_CTL,
487 FDI_RX_MISC_B,
488 FDI_RXB_IIR,
489 FDI_RXB_IMR,
490 FDI_RXB_TUSIZE1,
491 QUIRK_F1060,
492 TRANSB_CHICKEN2,
493 TRANSCCONF,
494 FDI_RXC_CTL,
495 FDI_RX_MISC_C,
496 FDI_RXC_IIR,
497 FDI_RXC_IMR,
498 FDI_RXC_TUSIZE1,
499 QUIRK_F2060,
500 TRANSC_CHICKEN2,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]501 BXT_P_CR_GT_DISP_PWRON,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]502 GT_MAILBOX,
503 GT_MAILBOX_DATA,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]504 GT_MAILBOX_DATA_1,
505 BXT_PORT_CL1CM_DW0_A,
506 BXT_PORT_CL1CM_DW9_A,
507 BXT_PORT_CL1CM_DW10_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame^]508 BXT_PORT_PLL_EBB_0_A,
509 BXT_PORT_PLL_EBB_4_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]510 BXT_PORT_CL1CM_DW28_A,
511 BXT_PORT_CL1CM_DW30_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame^]512 BXT_PORT_PLL_0_A,
513 BXT_PORT_PLL_1_A,
514 BXT_PORT_PLL_2_A,
515 BXT_PORT_PLL_3_A,
516 BXT_PORT_PLL_6_A,
517 BXT_PORT_PLL_8_A,
518 BXT_PORT_PLL_9_A,
519 BXT_PORT_PLL_10_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]520 BXT_PORT_REF_DW3_A,
521 BXT_PORT_REF_DW6_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame^]522 BXT_PORT_REF_DW8_A,
523 BXT_PORT_PCS_DW12_01_A,
524 BXT_PORT_PCS_DW12_GRP_A);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]525
526 pragma Warnings
527 (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)",
528 Reason => "TODO: Should it matter?");
529 pragma Keep_Names (Registers_Invalid_Index);
530 pragma Warnings
531 (GNATprove, On, "pragma ""KEEP_NAMES"" ignored *(not yet supported)");
532
533 Register_Width : constant := 4;
534
535 for Registers_Invalid_Index use
536 (Invalid_Register => 0,
537
538 ---------------------------------------------------------------------------
539 -- Pipe A registers
540 ---------------------------------------------------------------------------
541
542 -- pipe timing registers
543
544 HTOTAL_A => 16#06_0000# / Register_Width,
545 HBLANK_A => 16#06_0004# / Register_Width,
546 HSYNC_A => 16#06_0008# / Register_Width,
547 VTOTAL_A => 16#06_000c# / Register_Width,
548 VBLANK_A => 16#06_0010# / Register_Width,
549 VSYNC_A => 16#06_0014# / Register_Width,
550 PIPEASRC => 16#06_001c# / Register_Width,
551 PIPEACONF => 16#07_0008# / Register_Width,
552 PIPEAMISC => 16#07_0030# / Register_Width,
553 TRANS_HTOTAL_A => 16#0e_0000# / Register_Width,
554 TRANS_HBLANK_A => 16#0e_0004# / Register_Width,
555 TRANS_HSYNC_A => 16#0e_0008# / Register_Width,
556 TRANS_VTOTAL_A => 16#0e_000c# / Register_Width,
557 TRANS_VBLANK_A => 16#0e_0010# / Register_Width,
558 TRANS_VSYNC_A => 16#0e_0014# / Register_Width,
559 TRANSA_DATA_M1 => 16#0e_0030# / Register_Width,
560 TRANSA_DATA_N1 => 16#0e_0034# / Register_Width,
561 TRANSA_DP_LINK_M1 => 16#0e_0040# / Register_Width,
562 TRANSA_DP_LINK_N1 => 16#0e_0044# / Register_Width,
563 PIPEA_DATA_M1 => 16#06_0030# / Register_Width,
564 PIPEA_DATA_N1 => 16#06_0034# / Register_Width,
565 PIPEA_LINK_M1 => 16#06_0040# / Register_Width,
566 PIPEA_LINK_N1 => 16#06_0044# / Register_Width,
567 PIPEA_DDI_FUNC_CTL => 16#06_0400# / Register_Width,
568 PIPEA_MSA_MISC => 16#06_0410# / Register_Width,
569
570 -- PCH sideband interface registers
571 SBI_ADDR => 16#0c_6000# / Register_Width,
572 SBI_DATA => 16#0c_6004# / Register_Width,
573 SBI_CTL_STAT => 16#0c_6008# / Register_Width,
574
575 -- clock registers
576 PCH_DPLL_A => 16#0c_6014# / Register_Width,
577 PCH_PIXCLK_GATE => 16#0c_6020# / Register_Width,
578 PCH_FPA0 => 16#0c_6040# / Register_Width,
579 PCH_FPA1 => 16#0c_6044# / Register_Width,
580
581 -- panel fitter
582 PFA_CTL_1 => 16#06_8080# / Register_Width,
583 PFA_WIN_POS => 16#06_8070# / Register_Width,
584 PFA_WIN_SZ => 16#06_8074# / Register_Width,
585 PS_WIN_POS_1_A => 16#06_8170# / Register_Width,
586 PS_WIN_SZ_1_A => 16#06_8174# / Register_Width,
587 PS_CTRL_1_A => 16#06_8180# / Register_Width,
588 PS_WIN_POS_2_A => 16#06_8270# / Register_Width,
589 PS_WIN_SZ_2_A => 16#06_8274# / Register_Width,
590 PS_CTRL_2_A => 16#06_8280# / Register_Width,
591
592 -- display control
593 DSPACNTR => 16#07_0180# / Register_Width,
594 DSPALINOFF => 16#07_0184# / Register_Width,
595 DSPASTRIDE => 16#07_0188# / Register_Width,
596 PLANE_POS_1_A => 16#07_018c# / Register_Width,
597 PLANE_SIZE_1_A => 16#07_0190# / Register_Width,
598 DSPASURF => 16#07_019c# / Register_Width,
599 DSPATILEOFF => 16#07_01a4# / Register_Width,
600
601 -- sprite control
602 SPACNTR => 16#07_0280# / Register_Width,
603
604 -- FDI and PCH transcoder control
605 FDI_TX_CTL_A => 16#06_0100# / Register_Width,
606 FDI_RXA_CTL => 16#0f_000c# / Register_Width,
607 FDI_RX_MISC_A => 16#0f_0010# / Register_Width,
608 FDI_RXA_IIR => 16#0f_0014# / Register_Width,
609 FDI_RXA_IMR => 16#0f_0018# / Register_Width,
610 FDI_RXA_TUSIZE1 => 16#0f_0030# / Register_Width,
611 TRANSACONF => 16#0f_0008# / Register_Width,
612 TRANSA_CHICKEN2 => 16#0f_0064# / Register_Width,
613
614 -- watermark registers
615 WM_LINETIME_A => 16#04_5270# / Register_Width,
616 PLANE_WM_1_A_0 => 16#07_0240# / Register_Width,
617 PLANE_WM_1_A_1 => 16#07_0244# / Register_Width,
618 PLANE_WM_1_A_2 => 16#07_0248# / Register_Width,
619 PLANE_WM_1_A_3 => 16#07_024c# / Register_Width,
620 PLANE_WM_1_A_4 => 16#07_0250# / Register_Width,
621 PLANE_WM_1_A_5 => 16#07_0254# / Register_Width,
622 PLANE_WM_1_A_6 => 16#07_0258# / Register_Width,
623 PLANE_WM_1_A_7 => 16#07_025c# / Register_Width,
624 PLANE_BUF_CFG_1_A => 16#07_027c# / Register_Width,
625
626 -- CPU transcoder clock select
627 TRANSA_CLK_SEL => 16#04_6140# / Register_Width,
628
629 ---------------------------------------------------------------------------
630 -- Pipe B registers
631 ---------------------------------------------------------------------------
632
633 -- pipe timing registers
634
635 HTOTAL_B => 16#06_1000# / Register_Width,
636 HBLANK_B => 16#06_1004# / Register_Width,
637 HSYNC_B => 16#06_1008# / Register_Width,
638 VTOTAL_B => 16#06_100c# / Register_Width,
639 VBLANK_B => 16#06_1010# / Register_Width,
640 VSYNC_B => 16#06_1014# / Register_Width,
641 PIPEBSRC => 16#06_101c# / Register_Width,
642 PIPEBCONF => 16#07_1008# / Register_Width,
643 PIPEBMISC => 16#07_1030# / Register_Width,
644 TRANS_HTOTAL_B => 16#0e_1000# / Register_Width,
645 TRANS_HBLANK_B => 16#0e_1004# / Register_Width,
646 TRANS_HSYNC_B => 16#0e_1008# / Register_Width,
647 TRANS_VTOTAL_B => 16#0e_100c# / Register_Width,
648 TRANS_VBLANK_B => 16#0e_1010# / Register_Width,
649 TRANS_VSYNC_B => 16#0e_1014# / Register_Width,
650 TRANSB_DATA_M1 => 16#0e_1030# / Register_Width,
651 TRANSB_DATA_N1 => 16#0e_1034# / Register_Width,
652 TRANSB_DP_LINK_M1 => 16#0e_1040# / Register_Width,
653 TRANSB_DP_LINK_N1 => 16#0e_1044# / Register_Width,
654 PIPEB_DATA_M1 => 16#06_1030# / Register_Width,
655 PIPEB_DATA_N1 => 16#06_1034# / Register_Width,
656 PIPEB_LINK_M1 => 16#06_1040# / Register_Width,
657 PIPEB_LINK_N1 => 16#06_1044# / Register_Width,
658 PIPEB_DDI_FUNC_CTL => 16#06_1400# / Register_Width,
659 PIPEB_MSA_MISC => 16#06_1410# / Register_Width,
660
661 -- clock registers
662 PCH_DPLL_B => 16#0c_6018# / Register_Width,
663 PCH_FPB0 => 16#0c_6048# / Register_Width,
664 PCH_FPB1 => 16#0c_604c# / Register_Width,
665
666 -- panel fitter
667 PFB_CTL_1 => 16#06_8880# / Register_Width,
668 PFB_WIN_POS => 16#06_8870# / Register_Width,
669 PFB_WIN_SZ => 16#06_8874# / Register_Width,
670 PS_WIN_POS_1_B => 16#06_8970# / Register_Width,
671 PS_WIN_SZ_1_B => 16#06_8974# / Register_Width,
672 PS_CTRL_1_B => 16#06_8980# / Register_Width,
673 PS_WIN_POS_2_B => 16#06_8a70# / Register_Width,
674 PS_WIN_SZ_2_B => 16#06_8a74# / Register_Width,
675 PS_CTRL_2_B => 16#06_8a80# / Register_Width,
676
677 -- display control
678 DSPBCNTR => 16#07_1180# / Register_Width,
679 DSPBLINOFF => 16#07_1184# / Register_Width,
680 DSPBSTRIDE => 16#07_1188# / Register_Width,
681 PLANE_POS_1_B => 16#07_118c# / Register_Width,
682 PLANE_SIZE_1_B => 16#07_1190# / Register_Width,
683 DSPBSURF => 16#07_119c# / Register_Width,
684 DSPBTILEOFF => 16#07_11a4# / Register_Width,
685
686 -- sprite control
687 SPBCNTR => 16#07_1280# / Register_Width,
688
689 -- FDI and PCH transcoder control
690 FDI_TX_CTL_B => 16#06_1100# / Register_Width,
691 FDI_RXB_CTL => 16#0f_100c# / Register_Width,
692 FDI_RX_MISC_B => 16#0f_1010# / Register_Width,
693 FDI_RXB_IIR => 16#0f_1014# / Register_Width,
694 FDI_RXB_IMR => 16#0f_1018# / Register_Width,
695 FDI_RXB_TUSIZE1 => 16#0f_1030# / Register_Width,
696 TRANSBCONF => 16#0f_1008# / Register_Width,
697 TRANSB_CHICKEN2 => 16#0f_1064# / Register_Width,
698
699 -- watermark registers
700 WM_LINETIME_B => 16#04_5274# / Register_Width,
701 PLANE_WM_1_B_0 => 16#07_1240# / Register_Width,
702 PLANE_WM_1_B_1 => 16#07_1244# / Register_Width,
703 PLANE_WM_1_B_2 => 16#07_1248# / Register_Width,
704 PLANE_WM_1_B_3 => 16#07_124c# / Register_Width,
705 PLANE_WM_1_B_4 => 16#07_1250# / Register_Width,
706 PLANE_WM_1_B_5 => 16#07_1254# / Register_Width,
707 PLANE_WM_1_B_6 => 16#07_1258# / Register_Width,
708 PLANE_WM_1_B_7 => 16#07_125c# / Register_Width,
709 PLANE_BUF_CFG_1_B => 16#07_127c# / Register_Width,
710
711 -- CPU transcoder clock select
712 TRANSB_CLK_SEL => 16#04_6144# / Register_Width,
713
714 ---------------------------------------------------------------------------
715 -- Pipe C registers
716 ---------------------------------------------------------------------------
717
718 -- pipe timing registers
719
720 HTOTAL_C => 16#06_2000# / Register_Width,
721 HBLANK_C => 16#06_2004# / Register_Width,
722 HSYNC_C => 16#06_2008# / Register_Width,
723 VTOTAL_C => 16#06_200c# / Register_Width,
724 VBLANK_C => 16#06_2010# / Register_Width,
725 VSYNC_C => 16#06_2014# / Register_Width,
726 PIPECSRC => 16#06_201c# / Register_Width,
727 PIPECCONF => 16#07_2008# / Register_Width,
728 PIPECMISC => 16#07_2030# / Register_Width,
729 TRANS_HTOTAL_C => 16#0e_2000# / Register_Width,
730 TRANS_HBLANK_C => 16#0e_2004# / Register_Width,
731 TRANS_HSYNC_C => 16#0e_2008# / Register_Width,
732 TRANS_VTOTAL_C => 16#0e_200c# / Register_Width,
733 TRANS_VBLANK_C => 16#0e_2010# / Register_Width,
734 TRANS_VSYNC_C => 16#0e_2014# / Register_Width,
735 TRANSC_DATA_M1 => 16#0e_2030# / Register_Width,
736 TRANSC_DATA_N1 => 16#0e_2034# / Register_Width,
737 TRANSC_DP_LINK_M1 => 16#0e_2040# / Register_Width,
738 TRANSC_DP_LINK_N1 => 16#0e_2044# / Register_Width,
739 PIPEC_DATA_M1 => 16#06_2030# / Register_Width,
740 PIPEC_DATA_N1 => 16#06_2034# / Register_Width,
741 PIPEC_LINK_M1 => 16#06_2040# / Register_Width,
742 PIPEC_LINK_N1 => 16#06_2044# / Register_Width,
743 PIPEC_DDI_FUNC_CTL => 16#06_2400# / Register_Width,
744 PIPEC_MSA_MISC => 16#06_2410# / Register_Width,
745
746 -- panel fitter
747 PFC_CTL_1 => 16#06_9080# / Register_Width,
748 PFC_WIN_POS => 16#06_9070# / Register_Width,
749 PFC_WIN_SZ => 16#06_9074# / Register_Width,
750 PS_WIN_POS_1_C => 16#06_9170# / Register_Width,
751 PS_WIN_SZ_1_C => 16#06_9174# / Register_Width,
752 PS_CTRL_1_C => 16#06_9180# / Register_Width,
753
754 -- display control
755 DSPCCNTR => 16#07_2180# / Register_Width,
756 DSPCLINOFF => 16#07_2184# / Register_Width,
757 DSPCSTRIDE => 16#07_2188# / Register_Width,
758 PLANE_POS_1_C => 16#07_218c# / Register_Width,
759 PLANE_SIZE_1_C => 16#07_2190# / Register_Width,
760 DSPCSURF => 16#07_219c# / Register_Width,
761 DSPCTILEOFF => 16#07_21a4# / Register_Width,
762
763 -- sprite control
764 SPCCNTR => 16#07_2280# / Register_Width,
765
766 -- PCH transcoder control
767 FDI_TX_CTL_C => 16#06_2100# / Register_Width,
768 FDI_RXC_CTL => 16#0f_200c# / Register_Width,
769 FDI_RX_MISC_C => 16#0f_2010# / Register_Width,
770 FDI_RXC_IIR => 16#0f_2014# / Register_Width,
771 FDI_RXC_IMR => 16#0f_2018# / Register_Width,
772 FDI_RXC_TUSIZE1 => 16#0f_2030# / Register_Width,
773 TRANSCCONF => 16#0f_2008# / Register_Width,
774 TRANSC_CHICKEN2 => 16#0f_2064# / Register_Width,
775
776 -- watermark registers
777 WM_LINETIME_C => 16#04_5278# / Register_Width,
778 PLANE_WM_1_C_0 => 16#07_2240# / Register_Width,
779 PLANE_WM_1_C_1 => 16#07_2244# / Register_Width,
780 PLANE_WM_1_C_2 => 16#07_2248# / Register_Width,
781 PLANE_WM_1_C_3 => 16#07_224c# / Register_Width,
782 PLANE_WM_1_C_4 => 16#07_2250# / Register_Width,
783 PLANE_WM_1_C_5 => 16#07_2254# / Register_Width,
784 PLANE_WM_1_C_6 => 16#07_2258# / Register_Width,
785 PLANE_WM_1_C_7 => 16#07_225c# / Register_Width,
786 PLANE_BUF_CFG_1_C => 16#07_227c# / Register_Width,
787
788 -- CPU transcoder clock select
789 TRANSC_CLK_SEL => 16#04_6148# / Register_Width,
790
791 ---------------------------------------------------------------------------
792 -- Pipe EDP registers
793 ---------------------------------------------------------------------------
794
795 -- pipe timing registers
796
797 HTOTAL_EDP => 16#06_f000# / Register_Width,
798 HBLANK_EDP => 16#06_f004# / Register_Width,
799 HSYNC_EDP => 16#06_f008# / Register_Width,
800 VTOTAL_EDP => 16#06_f00c# / Register_Width,
801 VBLANK_EDP => 16#06_f010# / Register_Width,
802 VSYNC_EDP => 16#06_f014# / Register_Width,
803 PIPE_EDP_CONF => 16#07_f008# / Register_Width,
804 PIPE_EDP_DATA_M1 => 16#06_f030# / Register_Width,
805 PIPE_EDP_DATA_N1 => 16#06_f034# / Register_Width,
806 PIPE_EDP_LINK_M1 => 16#06_f040# / Register_Width,
807 PIPE_EDP_LINK_N1 => 16#06_f044# / Register_Width,
808 PIPE_EDP_DDI_FUNC_CTL => 16#06_f400# / Register_Width,
809 PIPE_EDP_MSA_MISC => 16#06_f410# / Register_Width,
810
811 -- PSR registers
812 SRD_CTL => 16#06_4800# / Register_Width,
813 SRD_CTL_A => 16#06_0800# / Register_Width,
814 SRD_CTL_B => 16#06_1800# / Register_Width,
815 SRD_CTL_C => 16#06_2800# / Register_Width,
816 SRD_CTL_EDP => 16#06_f800# / Register_Width,
817 SRD_STATUS => 16#06_4840# / Register_Width,
818 SRD_STATUS_A => 16#06_0840# / Register_Width,
819 SRD_STATUS_B => 16#06_1840# / Register_Width,
820 SRD_STATUS_C => 16#06_2840# / Register_Width,
821 SRD_STATUS_EDP => 16#06_f840# / Register_Width,
822
823 -- DDI registers
824 DDI_BUF_CTL_A => 16#06_4000# / Register_Width, -- aliased by DP_CTL_A
825 DDI_AUX_CTL_A => 16#06_4010# / Register_Width, -- aliased by DP_AUX_CTL_A
826 DDI_AUX_DATA_A_1 => 16#06_4014# / Register_Width, -- aliased by DP_AUX_DATA_A_1
827 DDI_AUX_DATA_A_2 => 16#06_4018# / Register_Width, -- aliased by DP_AUX_DATA_A_2
828 DDI_AUX_DATA_A_3 => 16#06_401c# / Register_Width, -- aliased by DP_AUX_DATA_A_3
829 DDI_AUX_DATA_A_4 => 16#06_4020# / Register_Width, -- aliased by DP_AUX_DATA_A_4
830 DDI_AUX_DATA_A_5 => 16#06_4024# / Register_Width, -- aliased by DP_AUX_DATA_A_5
831 DDI_AUX_MUTEX_A => 16#06_402c# / Register_Width,
832 DDI_BUF_CTL_B => 16#06_4100# / Register_Width,
833 DDI_AUX_CTL_B => 16#06_4110# / Register_Width,
834 DDI_AUX_DATA_B_1 => 16#06_4114# / Register_Width,
835 DDI_AUX_DATA_B_2 => 16#06_4118# / Register_Width,
836 DDI_AUX_DATA_B_3 => 16#06_411c# / Register_Width,
837 DDI_AUX_DATA_B_4 => 16#06_4120# / Register_Width,
838 DDI_AUX_DATA_B_5 => 16#06_4124# / Register_Width,
839 DDI_AUX_MUTEX_B => 16#06_412c# / Register_Width,
840 DDI_BUF_CTL_C => 16#06_4200# / Register_Width,
841 DDI_AUX_CTL_C => 16#06_4210# / Register_Width,
842 DDI_AUX_DATA_C_1 => 16#06_4214# / Register_Width,
843 DDI_AUX_DATA_C_2 => 16#06_4218# / Register_Width,
844 DDI_AUX_DATA_C_3 => 16#06_421c# / Register_Width,
845 DDI_AUX_DATA_C_4 => 16#06_4220# / Register_Width,
846 DDI_AUX_DATA_C_5 => 16#06_4224# / Register_Width,
847 DDI_AUX_MUTEX_C => 16#06_422c# / Register_Width,
848 DDI_BUF_CTL_D => 16#06_4300# / Register_Width,
849 DDI_AUX_CTL_D => 16#06_4310# / Register_Width,
850 DDI_AUX_DATA_D_1 => 16#06_4314# / Register_Width,
851 DDI_AUX_DATA_D_2 => 16#06_4318# / Register_Width,
852 DDI_AUX_DATA_D_3 => 16#06_431c# / Register_Width,
853 DDI_AUX_DATA_D_4 => 16#06_4320# / Register_Width,
854 DDI_AUX_DATA_D_5 => 16#06_4324# / Register_Width,
855 DDI_AUX_MUTEX_D => 16#06_432c# / Register_Width,
856 DDI_BUF_CTL_E => 16#06_4400# / Register_Width,
857 DP_TP_CTL_A => 16#06_4040# / Register_Width,
858 DP_TP_CTL_B => 16#06_4140# / Register_Width,
859 DP_TP_CTL_C => 16#06_4240# / Register_Width,
860 DP_TP_CTL_D => 16#06_4340# / Register_Width,
861 DP_TP_CTL_E => 16#06_4440# / Register_Width,
862 DP_TP_STATUS_B => 16#06_4144# / Register_Width,
863 DP_TP_STATUS_C => 16#06_4244# / Register_Width,
864 DP_TP_STATUS_D => 16#06_4344# / Register_Width,
865 DP_TP_STATUS_E => 16#06_4444# / Register_Width,
866 PORT_CLK_SEL_DDIA => 16#04_6100# / Register_Width,
867 PORT_CLK_SEL_DDIB => 16#04_6104# / Register_Width,
868 PORT_CLK_SEL_DDIC => 16#04_6108# / Register_Width,
869 PORT_CLK_SEL_DDID => 16#04_610c# / Register_Width,
870 PORT_CLK_SEL_DDIE => 16#04_6110# / Register_Width,
871
872 -- Skylake DPLL registers
873 DPLL1_CFGR1 => 16#06_c040# / Register_Width,
874 DPLL1_CFGR2 => 16#06_c044# / Register_Width,
875 DPLL2_CFGR1 => 16#06_c048# / Register_Width,
876 DPLL2_CFGR2 => 16#06_c04c# / Register_Width,
877 DPLL3_CFGR1 => 16#06_c050# / Register_Width,
878 DPLL3_CFGR2 => 16#06_c054# / Register_Width,
879 DPLL_CTRL1 => 16#06_c058# / Register_Width,
880 DPLL_CTRL2 => 16#06_c05c# / Register_Width,
881 DPLL_STATUS => 16#06_c060# / Register_Width,
882
883 -- CD CLK register
884 CDCLK_CTL => 16#04_6000# / Register_Width,
885
886 -- Skylake LCPLL registers
887 LCPLL1_CTL => 16#04_6010# / Register_Width,
888 LCPLL2_CTL => 16#04_6014# / Register_Width,
889
890 -- SPLL register
891 SPLL_CTL => 16#04_6020# / Register_Width,
892
893 -- WRPLL registers
894 WRPLL_CTL_1 => 16#04_6040# / Register_Width,
895 WRPLL_CTL_2 => 16#04_6060# / Register_Width,
896
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]897 -- Broxton Display Engine PLL registers
898 BXT_DE_PLL_CTL => 16#06_d000# / Register_Width,
899 BXT_DE_PLL_ENABLE => 16#04_6070# / Register_Width,
900
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame^]901 -- Broxton DDI PHY PLL registers
902 BXT_PORT_PLL_ENABLE_A => 16#04_6074# / Register_Width,
903 BXT_PORT_PLL_ENABLE_B => 16#04_6078# / Register_Width,
904 BXT_PORT_PLL_ENABLE_C => 16#04_607c# / Register_Width,
905 BXT_PORT_PLL_EBB_0_A => 16#16_2034# / Register_Width,
906 BXT_PORT_PLL_EBB_4_A => 16#16_2038# / Register_Width,
907 BXT_PORT_PLL_0_A => 16#16_2100# / Register_Width,
908 BXT_PORT_PLL_1_A => 16#16_2104# / Register_Width,
909 BXT_PORT_PLL_2_A => 16#16_2108# / Register_Width,
910 BXT_PORT_PLL_3_A => 16#16_210c# / Register_Width,
911 BXT_PORT_PLL_6_A => 16#16_2118# / Register_Width,
912 BXT_PORT_PLL_8_A => 16#16_2120# / Register_Width,
913 BXT_PORT_PLL_9_A => 16#16_2124# / Register_Width,
914 BXT_PORT_PLL_10_A => 16#16_2128# / Register_Width,
915 BXT_PORT_PCS_DW12_01_A => 16#16_2430# / Register_Width,
916 BXT_PORT_PCS_DW12_GRP_A => 16#16_2c30# / Register_Width,
917 BXT_PORT_PLL_EBB_0_B => 16#06_c034# / Register_Width,
918 BXT_PORT_PLL_EBB_4_B => 16#06_c038# / Register_Width,
919 BXT_PORT_PLL_0_B => 16#06_c100# / Register_Width,
920 BXT_PORT_PLL_1_B => 16#06_c104# / Register_Width,
921 BXT_PORT_PLL_2_B => 16#06_c108# / Register_Width,
922 BXT_PORT_PLL_3_B => 16#06_c10c# / Register_Width,
923 BXT_PORT_PLL_6_B => 16#06_c118# / Register_Width,
924 BXT_PORT_PLL_8_B => 16#06_c120# / Register_Width,
925 BXT_PORT_PLL_9_B => 16#06_c124# / Register_Width,
926 BXT_PORT_PLL_10_B => 16#06_c128# / Register_Width,
927 BXT_PORT_PCS_DW12_01_B => 16#06_c430# / Register_Width,
928 BXT_PORT_PCS_DW12_GRP_B => 16#06_cc30# / Register_Width,
929 BXT_PORT_PLL_EBB_0_C => 16#06_c340# / Register_Width,
930 BXT_PORT_PLL_EBB_4_C => 16#06_c344# / Register_Width,
931 BXT_PORT_PLL_0_C => 16#06_c380# / Register_Width,
932 BXT_PORT_PLL_1_C => 16#06_c384# / Register_Width,
933 BXT_PORT_PLL_2_C => 16#06_c388# / Register_Width,
934 BXT_PORT_PLL_3_C => 16#06_c38c# / Register_Width,
935 BXT_PORT_PLL_6_C => 16#06_c398# / Register_Width,
936 BXT_PORT_PLL_8_C => 16#06_c3a0# / Register_Width,
937 BXT_PORT_PLL_9_C => 16#06_c3a4# / Register_Width,
938 BXT_PORT_PLL_10_C => 16#06_c3a8# / Register_Width,
939 BXT_PORT_PCS_DW12_01_C => 16#06_c830# / Register_Width,
940 BXT_PORT_PCS_DW12_GRP_C => 16#06_ce30# / Register_Width,
941
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]942 -- Broxton DDI PHY registers
943 BXT_P_CR_GT_DISP_PWRON => 16#13_8090# / Register_Width,
944 BXT_PHY_CTL_A => 16#06_4c00# / Register_Width,
945 BXT_PHY_CTL_B => 16#06_4c10# / Register_Width,
946 BXT_PHY_CTL_C => 16#06_4c20# / Register_Width,
947 BXT_PHY_CTL_FAM_EDP => 16#06_4c80# / Register_Width,
948 BXT_PHY_CTL_FAM_DDI => 16#06_4c90# / Register_Width,
949
950 -- Broxton DDI PHY common lane registers
951 BXT_PORT_CL1CM_DW0_A => 16#16_2000# / Register_Width,
952 BXT_PORT_CL1CM_DW0_BC => 16#06_c000# / Register_Width,
953 BXT_PORT_CL1CM_DW9_A => 16#16_2024# / Register_Width,
954 BXT_PORT_CL1CM_DW9_BC => 16#06_c024# / Register_Width,
955 BXT_PORT_CL1CM_DW10_A => 16#16_2028# / Register_Width,
956 BXT_PORT_CL1CM_DW10_BC => 16#06_c028# / Register_Width,
957 BXT_PORT_CL1CM_DW28_A => 16#16_2070# / Register_Width,
958 BXT_PORT_CL1CM_DW28_BC => 16#06_c070# / Register_Width,
959 BXT_PORT_CL1CM_DW30_A => 16#16_2078# / Register_Width,
960 BXT_PORT_CL1CM_DW30_BC => 16#06_c078# / Register_Width,
961 BXT_PORT_CL2CM_DW6_BC => 16#06_c358# / Register_Width,
962
963 -- Broxton DDI PHY ref registers
964 BXT_PORT_REF_DW3_A => 16#16_218c# / Register_Width,
965 BXT_PORT_REF_DW3_BC => 16#06_c18c# / Register_Width,
966 BXT_PORT_REF_DW6_A => 16#16_2198# / Register_Width,
967 BXT_PORT_REF_DW6_BC => 16#06_c198# / Register_Width,
968 BXT_PORT_REF_DW8_A => 16#16_21a0# / Register_Width,
969 BXT_PORT_REF_DW8_BC => 16#06_c1a0# / Register_Width,
970
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]971 -- Power Down Well registers
972 PWR_WELL_CTL_BIOS => 16#04_5400# / Register_Width,
973 PWR_WELL_CTL_DRIVER => 16#04_5404# / Register_Width,
974 PWR_WELL_CTL_KVMR => 16#04_5408# / Register_Width,
975 PWR_WELL_CTL_DEBUG => 16#04_540c# / Register_Width,
976 PWR_WELL_CTL5 => 16#04_5410# / Register_Width,
977 PWR_WELL_CTL6 => 16#04_5414# / Register_Width,
978
979 -- class Panel registers
980 PCH_PP_STATUS => 16#0c_7200# / Register_Width,
981 PCH_PP_CONTROL => 16#0c_7204# / Register_Width,
982 PCH_PP_ON_DELAYS => 16#0c_7208# / Register_Width,
983 PCH_PP_OFF_DELAYS => 16#0c_720c# / Register_Width,
984 PCH_PP_DIVISOR => 16#0c_7210# / Register_Width,
985 BLC_PWM_CPU_CTL => 16#04_8254# / Register_Width,
986 BLC_PWM_PCH_CTL2 => 16#0c_8254# / Register_Width,
987
988 -- PCH LVDS Connector Registers
989 PCH_LVDS => 16#0e_1180# / Register_Width,
990
991 -- PCH ADPA Connector Registers
992 PCH_ADPA => 16#0e_1100# / Register_Width,
993
994 -- PCH HDMIB Connector Registers
995 PCH_HDMIB => 16#0e_1140# / Register_Width,
996
997 -- PCH HDMIC Connector Registers
998 PCH_HDMIC => 16#0e_1150# / Register_Width,
999
1000 -- PCH HDMID Connector Registers
1001 PCH_HDMID => 16#0e_1160# / Register_Width,
1002
1003 -- Intel Registers
1004 VGACNTRL => 16#04_1000# / Register_Width,
1005 FUSE_STATUS => 16#04_2000# / Register_Width,
1006 FBA_CFB_BASE => 16#04_3200# / Register_Width,
1007 IPS_CTL => 16#04_3408# / Register_Width,
1008 ARB_CTL => 16#04_5000# / Register_Width,
1009 DBUF_CTL => 16#04_5008# / Register_Width,
1010 NDE_RSTWRN_OPT => 16#04_6408# / Register_Width,
1011 PCH_DREF_CONTROL => 16#0c_6200# / Register_Width,
1012 BLC_PWM_PCH_CTL1 => 16#0c_8250# / Register_Width,
1013 BLC_PWM_CPU_CTL2 => 16#04_8250# / Register_Width,
1014 PCH_DPLL_SEL => 16#0c_7000# / Register_Width,
1015 GT_MAILBOX => 16#13_8124# / Register_Width,
1016 GT_MAILBOX_DATA => 16#13_8128# / Register_Width,
1017 GT_MAILBOX_DATA_1 => 16#13_812c# / Register_Width,
1018
1019 PCH_DP_B => 16#0e_4100# / Register_Width,
1020 PCH_DP_AUX_CTL_B => 16#0e_4110# / Register_Width,
1021 PCH_DP_AUX_DATA_B_1 => 16#0e_4114# / Register_Width,
1022 PCH_DP_AUX_DATA_B_2 => 16#0e_4118# / Register_Width,
1023 PCH_DP_AUX_DATA_B_3 => 16#0e_411c# / Register_Width,
1024 PCH_DP_AUX_DATA_B_4 => 16#0e_4120# / Register_Width,
1025 PCH_DP_AUX_DATA_B_5 => 16#0e_4124# / Register_Width,
1026 PCH_DP_C => 16#0e_4200# / Register_Width,
1027 PCH_DP_AUX_CTL_C => 16#0e_4210# / Register_Width,
1028 PCH_DP_AUX_DATA_C_1 => 16#0e_4214# / Register_Width,
1029 PCH_DP_AUX_DATA_C_2 => 16#0e_4218# / Register_Width,
1030 PCH_DP_AUX_DATA_C_3 => 16#0e_421c# / Register_Width,
1031 PCH_DP_AUX_DATA_C_4 => 16#0e_4220# / Register_Width,
1032 PCH_DP_AUX_DATA_C_5 => 16#0e_4224# / Register_Width,
1033 PCH_DP_D => 16#0e_4300# / Register_Width,
1034 PCH_DP_AUX_CTL_D => 16#0e_4310# / Register_Width,
1035 PCH_DP_AUX_DATA_D_1 => 16#0e_4314# / Register_Width,
1036 PCH_DP_AUX_DATA_D_2 => 16#0e_4318# / Register_Width,
1037 PCH_DP_AUX_DATA_D_3 => 16#0e_431c# / Register_Width,
1038 PCH_DP_AUX_DATA_D_4 => 16#0e_4320# / Register_Width,
1039 PCH_DP_AUX_DATA_D_5 => 16#0e_4324# / Register_Width,
1040
1041 -- watermark registers
1042 WM1_LP_ILK => 16#04_5108# / Register_Width,
1043 WM2_LP_ILK => 16#04_510c# / Register_Width,
1044 WM3_LP_ILK => 16#04_5110# / Register_Width,
1045
1046 -- audio VID/DID
1047 AUD_VID_DID => 16#06_5020# / Register_Width,
1048 PCH_AUD_VID_DID => 16#0e_5020# / Register_Width,
1049
1050 -- interrupt registers
1051 DEISR => 16#04_4000# / Register_Width,
1052 DEIMR => 16#04_4004# / Register_Width,
1053 DEIIR => 16#04_4008# / Register_Width,
1054 DEIER => 16#04_400c# / Register_Width,
1055 GTISR => 16#04_4010# / Register_Width,
1056 GTIMR => 16#04_4014# / Register_Width,
1057 GTIIR => 16#04_4018# / Register_Width,
1058 GTIER => 16#04_401c# / Register_Width,
1059 SDEISR => 16#0c_4000# / Register_Width,
1060 SDEIMR => 16#0c_4004# / Register_Width,
1061 SDEIIR => 16#0c_4008# / Register_Width,
1062 SDEIER => 16#0c_400c# / Register_Width,
1063
1064 -- I2C stuff
1065 PCH_GMBUS0 => 16#0c_5100# / Register_Width,
1066 PCH_GMBUS1 => 16#0c_5104# / Register_Width,
1067 PCH_GMBUS2 => 16#0c_5108# / Register_Width,
1068 PCH_GMBUS3 => 16#0c_510c# / Register_Width,
1069 PCH_GMBUS4 => 16#0c_5110# / Register_Width,
1070 PCH_GMBUS5 => 16#0c_5120# / Register_Width,
1071
1072 -- clock gating -- maybe have to touch this
1073 DSPCLK_GATE_D => 16#04_2020# / Register_Width,
1074 PCH_FDI_CHICKEN_B_C => 16#0c_2000# / Register_Width,
1075 PCH_DSPCLK_GATE_D => 16#0c_2020# / Register_Width,
1076
1077 -- hotplug and initial detection
1078 HOTPLUG_CTL => 16#04_4030# / Register_Width,
1079 SHOTPLUG_CTL => 16#0c_4030# / Register_Width,
1080 SFUSE_STRAP => 16#0c_2014# / Register_Width,
1081
1082 -- Render Engine Command Streamer
1083 ARB_MODE => 16#00_4030# / Register_Width,
1084 HWS_PGA => 16#00_4080# / Register_Width,
1085 RCS_RING_BUFFER_TAIL => 16#00_2030# / Register_Width,
1086 VCS_RING_BUFFER_TAIL => 16#01_2030# / Register_Width,
1087 BCS_RING_BUFFER_TAIL => 16#02_2030# / Register_Width,
1088 RCS_RING_BUFFER_HEAD => 16#00_2034# / Register_Width,
1089 VCS_RING_BUFFER_HEAD => 16#01_2034# / Register_Width,
1090 BCS_RING_BUFFER_HEAD => 16#02_2034# / Register_Width,
1091 RCS_RING_BUFFER_STRT => 16#00_2038# / Register_Width,
1092 VCS_RING_BUFFER_STRT => 16#01_2038# / Register_Width,
1093 BCS_RING_BUFFER_STRT => 16#02_2038# / Register_Width,
1094 RCS_RING_BUFFER_CTL => 16#00_203c# / Register_Width,
1095 VCS_RING_BUFFER_CTL => 16#01_203c# / Register_Width,
1096 BCS_RING_BUFFER_CTL => 16#02_203c# / Register_Width,
1097 MI_MODE => 16#00_209c# / Register_Width,
1098 INSTPM => 16#00_20c0# / Register_Width,
1099 GAB_CTL_REG => 16#02_4000# / Register_Width,
1100 PP_DCLV_HIGH => 16#00_2220# / Register_Width,
1101 PP_DCLV_LOW => 16#00_2228# / Register_Width,
1102 VCS_PP_DCLV_HIGH => 16#01_2220# / Register_Width,
1103 VCS_PP_DCLV_LOW => 16#01_2228# / Register_Width,
1104 BCS_PP_DCLV_HIGH => 16#02_2220# / Register_Width,
1105 BCS_PP_DCLV_LOW => 16#02_2228# / Register_Width,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1106 ILK_DISPLAY_CHICKEN2 => 16#04_2004# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1107 UCGCTL1 => 16#00_9400# / Register_Width,
1108 UCGCTL2 => 16#00_9404# / Register_Width,
1109 MBCTL => 16#00_907c# / Register_Width,
1110 HWSTAM => 16#00_2098# / Register_Width,
1111 VCS_HWSTAM => 16#01_2098# / Register_Width,
1112 BCS_HWSTAM => 16#02_2098# / Register_Width,
1113 IIR => 16#04_4028# / Register_Width,
1114 PIPE_FRMCNT_A => 16#07_0040# / Register_Width,
1115 PIPE_FRMCNT_B => 16#07_1040# / Register_Width,
1116 PIPE_FRMCNT_C => 16#07_2040# / Register_Width,
1117 FBC_CTL => 16#04_3208# / Register_Width,
1118 PIPE_VSYNCSHIFT_A => 16#06_0028# / Register_Width,
1119 PIPE_VSYNCSHIFT_B => 16#06_1028# / Register_Width,
1120 PIPE_VSYNCSHIFT_C => 16#06_2028# / Register_Width,
1121 WM_PIPE_A => 16#04_5100# / Register_Width,
1122 WM_PIPE_B => 16#04_5104# / Register_Width,
1123 WM_PIPE_C => 16#04_5200# / Register_Width,
1124 PIPE_SCANLINE_A => 16#07_0000# / Register_Width,
1125 PIPE_SCANLINE_B => 16#07_1000# / Register_Width,
1126 PIPE_SCANLINE_C => 16#07_2000# / Register_Width,
1127 GFX_MODE => 16#00_2520# / Register_Width,
1128 CACHE_MODE_0 => 16#00_2120# / Register_Width,
1129 SLEEP_PSMI_CONTROL => 16#01_2050# / Register_Width,
1130 CTX_SIZE => 16#00_21a0# / Register_Width,
1131 GAC_ECO_BITS => 16#01_4090# / Register_Width,
1132 GAM_ECOCHK => 16#00_4090# / Register_Width,
1133 QUIRK_02084 => 16#00_2084# / Register_Width,
1134 QUIRK_02090 => 16#00_2090# / Register_Width,
1135 GT_MODE => 16#00_20d0# / Register_Width,
1136 QUIRK_F0060 => 16#0f_0060# / Register_Width,
1137 QUIRK_F1060 => 16#0f_1060# / Register_Width,
1138 QUIRK_F2060 => 16#0f_2060# / Register_Width,
1139 AUD_CNTRL_ST2 => 16#0e_50c0# / Register_Width,
1140 AUD_CNTL_ST_A => 16#0e_50b4# / Register_Width,
1141 AUD_CNTL_ST_B => 16#0e_51b4# / Register_Width,
1142 AUD_CNTL_ST_C => 16#0e_52b4# / Register_Width,
1143 AUD_HDMIW_HDMIEDID_A => 16#0e_5050# / Register_Width,
1144 AUD_HDMIW_HDMIEDID_B => 16#0e_5150# / Register_Width,
1145 AUD_HDMIW_HDMIEDID_C => 16#0e_5250# / Register_Width,
1146 AUD_CONFIG_A => 16#0e_5000# / Register_Width,
1147 AUD_CONFIG_B => 16#0e_5100# / Register_Width,
1148 AUD_CONFIG_C => 16#0e_5200# / Register_Width,
1149 TRANS_DP_CTL_A => 16#0e_0300# / Register_Width,
1150 TRANS_DP_CTL_B => 16#0e_1300# / Register_Width,
1151 TRANS_DP_CTL_C => 16#0e_2300# / Register_Width,
1152 TRANS_VSYNCSHIFT_A => 16#0e_0028# / Register_Width,
1153 TRANS_VSYNCSHIFT_B => 16#0e_1028# / Register_Width,
1154 TRANS_VSYNCSHIFT_C => 16#0e_2028# / Register_Width,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]1155 PCH_RAWCLK_FREQ => 16#0c_6204# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1156 QUIRK_C2004 => 16#0c_2004# / Register_Width);
1157
1158 subtype Registers_Index is Registers_Invalid_Index range
1159 Registers_Invalid_Index'Succ (Invalid_Register) ..
1160 Registers_Invalid_Index'Last;
1161
1162 -- aliased registers
1163 DP_CTL_A : constant Registers_Index := DDI_BUF_CTL_A;
1164 DP_AUX_CTL_A : constant Registers_Index := DDI_AUX_CTL_A;
1165 DP_AUX_DATA_A_1 : constant Registers_Index := DDI_AUX_DATA_A_1;
1166 DP_AUX_DATA_A_2 : constant Registers_Index := DDI_AUX_DATA_A_2;
1167 DP_AUX_DATA_A_3 : constant Registers_Index := DDI_AUX_DATA_A_3;
1168 DP_AUX_DATA_A_4 : constant Registers_Index := DDI_AUX_DATA_A_4;
1169 DP_AUX_DATA_A_5 : constant Registers_Index := DDI_AUX_DATA_A_5;
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1170 ILK_DISPLAY_CHICKEN1 : constant Registers_Index := FUSE_STATUS;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1171
1172 ---------------------------------------------------------------------------
1173
1174 Default_Timeout_MS : constant := 10;
1175
1176 ---------------------------------------------------------------------------
1177
1178 procedure Posting_Read
1179 (Register : in Registers_Index)
1180 with
1181 Global => (In_Out => Register_State),
1182 Depends => (Register_State =>+ (Register)),
1183 Pre => True,
1184 Post => True;
1185
1186 pragma Warnings (GNATprove, Off, "unused variable ""Verbose""",
1187 Reason => "Only used on debugging path");
1188 procedure Read
1189 (Register : in Registers_Index;
1190 Value : out Word32;
1191 Verbose : in Boolean := True)
1192 with
1193 Global => (In_Out => Register_State),
1194 Depends => ((Value, Register_State) => (Register, Register_State),
1195 null => Verbose),
1196 Pre => True,
1197 Post => True;
1198 pragma Warnings (GNATprove, On, "unused variable ""Verbose""");
1199
1200 procedure Write
1201 (Register : Registers_Index;
1202 Value : Word32)
1203 with
1204 Global => (In_Out => Register_State),
1205 Depends => (Register_State => (Register, Register_State, Value)),
1206 Pre => True,
1207 Post => True;
1208
1209 procedure Is_Set_Mask
1210 (Register : in Registers_Index;
1211 Mask : in Word32;
1212 Result : out Boolean);
1213
1214 pragma Warnings (GNATprove, Off, "unused initial value of ""Verbose""",
1215 Reason => "Only used on debugging path");
Nico Huberbcb2c472017-02-02 16:39:26 +0100[diff] [blame]1216 procedure Wait
1217 (Register : Registers_Index;
1218 Mask : Word32;
1219 Value : Word32;
1220 TOut_MS : Natural := Default_Timeout_MS;
1221 Verbose : Boolean := False);
1222
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1223 procedure Wait_Set_Mask
1224 (Register : Registers_Index;
1225 Mask : Word32;
1226 TOut_MS : Natural := Default_Timeout_MS;
1227 Verbose : Boolean := False);
1228
1229 procedure Wait_Unset_Mask
1230 (Register : Registers_Index;
1231 Mask : Word32;
1232 TOut_MS : Natural := Default_Timeout_MS;
1233 Verbose : Boolean := False);
1234 pragma Warnings (GNATprove, On, "unused initial value of ""Verbose""");
1235
1236 procedure Set_Mask
1237 (Register : Registers_Index;
1238 Mask : Word32);
1239
1240 procedure Unset_Mask
1241 (Register : Registers_Index;
1242 Mask : Word32);
1243
1244 procedure Unset_And_Set_Mask
1245 (Register : Registers_Index;
1246 Mask_Unset : Word32;
1247 Mask_Set : Word32);
1248
1249 pragma Warnings (Off, "declaration of ""Write_GTT"" hides one at *");
1250 procedure Write_GTT
1251 (GTT_Page : GTT_Range;
1252 Device_Address : GTT_Address_Type;
1253 Valid : Boolean)
1254 with
1255 Global => (In_Out => GTT_State),
1256 Depends => (GTT_State =>+ (GTT_Page, Device_Address, Valid)),
1257 Pre => True,
1258 Post => True;
1259 pragma Warnings (On, "declaration of ""Write_GTT"" hides one at *");
1260
1261 procedure Set_Register_Base (Base : Word64)
1262 with
1263 Global => (Output => Address_State),
1264 Depends => (Address_State => Base),
1265 Pre => True,
1266 Post => True;
1267
1268end HW.GFX.GMA.Registers;