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review.sourcearcade.org / libgfxinit / 75a707f3ef80fb150fc0c3fdb69d7cb7c21480f6 / . / common / hw-gfx-gma-registers.ads
blob: 5cffe76b309d46fd24c0fa47c8d1f63c1dd39b64 [file] [log] [blame]
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1--
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]2-- Copyright (C) 2015-2017 secunet Security Networks AG
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
Nico Huber125a29e2016-10-18 00:23:54 +0200[diff] [blame]6-- the Free Software Foundation; either version 2 of the License, or
7-- (at your option) any later version.
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]8--
9-- This program is distributed in the hope that it will be useful,
10-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12-- GNU General Public License for more details.
13--
14
15with System;
16with HW.GFX.GMA;
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]17with HW.GFX.GMA.Config;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]18
19private package HW.GFX.GMA.Registers
20with
21 Abstract_State =>
22 ((Address_State with Part_Of => GMA.State),
23 (Register_State with External, Part_Of => GMA.Device_State),
24 (GTT_State with External, Part_Of => GMA.Device_State)),
25 Initializes => Address_State
26is
Nico Huber0b2329a2018-06-09 21:14:27 +0200[diff] [blame]27
28 MMIO_GTT_32_Size : constant := 16#20_0000#;
29 MMIO_GTT_32_Offset : constant := 16#20_0000#;
30
31 -- Limit Broadwell+ to 4MiB to have a stable
32 -- interface (i.e. same number of entries):
33 MMIO_GTT_64_Size : constant := 16#40_0000#;
34 MMIO_GTT_64_Offset : constant := 16#80_0000#;
35
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]36 type Registers_Invalid_Index is
37 (Invalid_Register, -- Allow a placeholder when access is not acceptable
38
39 RCS_RING_BUFFER_TAIL,
40 RCS_RING_BUFFER_HEAD,
41 RCS_RING_BUFFER_STRT,
42 RCS_RING_BUFFER_CTL,
43 QUIRK_02084,
44 QUIRK_02090,
45 HWSTAM,
46 MI_MODE,
47 INSTPM,
48 GT_MODE,
49 CACHE_MODE_0,
50 CTX_SIZE,
51 PP_DCLV_HIGH,
52 PP_DCLV_LOW,
53 GFX_MODE,
54 ARB_MODE,
55 HWS_PGA,
56 GAM_ECOCHK,
Arthur Heymans229ed1c2018-03-28 16:45:43 +0200[diff] [blame]57 GMCH_GMBUS0,
58 GMCH_GMBUS1,
59 GMCH_GMBUS2,
60 GMCH_GMBUS3,
61 GMCH_GMBUS4,
62 GMCH_GMBUS5,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]63 GMCH_DPLL_A,
64 GMCH_DPLL_B,
65 GMCH_FPA0,
66 GMCH_FPA1,
67 GMCH_FPB0,
68 GMCH_FPB1,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]69 MBCTL,
70 UCGCTL1,
71 UCGCTL2,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]72 GMCH_CLKCFG,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]73 VCS_RING_BUFFER_TAIL,
74 VCS_RING_BUFFER_HEAD,
75 VCS_RING_BUFFER_STRT,
76 VCS_RING_BUFFER_CTL,
77 SLEEP_PSMI_CONTROL,
78 VCS_HWSTAM,
79 VCS_PP_DCLV_HIGH,
80 VCS_PP_DCLV_LOW,
81 GAC_ECO_BITS,
82 BCS_RING_BUFFER_TAIL,
83 BCS_RING_BUFFER_HEAD,
84 BCS_RING_BUFFER_STRT,
85 BCS_RING_BUFFER_CTL,
86 BCS_HWSTAM,
87 BCS_PP_DCLV_HIGH,
88 BCS_PP_DCLV_LOW,
89 GAB_CTL_REG,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]90 CPU_VGACNTRL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]91 FUSE_STATUS,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]92 ILK_DISPLAY_CHICKEN2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]93 DSPCLK_GATE_D,
94 FBA_CFB_BASE,
95 FBC_CTL,
96 IPS_CTL,
97 DEISR,
98 DEIMR,
99 DEIIR,
100 DEIER,
101 GTISR,
102 GTIMR,
103 GTIIR,
104 GTIER,
105 IIR,
106 HOTPLUG_CTL,
107 ARB_CTL,
108 DBUF_CTL,
109 WM_PIPE_A,
110 WM_PIPE_B,
111 WM1_LP_ILK,
112 WM2_LP_ILK,
113 WM3_LP_ILK,
114 WM_PIPE_C,
115 WM_LINETIME_A,
116 WM_LINETIME_B,
117 WM_LINETIME_C,
118 PWR_WELL_CTL_BIOS,
119 PWR_WELL_CTL_DRIVER,
120 PWR_WELL_CTL_KVMR,
121 PWR_WELL_CTL_DEBUG,
122 PWR_WELL_CTL5,
123 PWR_WELL_CTL6,
124 CDCLK_CTL,
125 LCPLL1_CTL,
126 LCPLL2_CTL,
127 SPLL_CTL,
128 WRPLL_CTL_1,
129 WRPLL_CTL_2,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]130 BXT_DE_PLL_ENABLE,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]131 BXT_PORT_PLL_ENABLE_A,
132 BXT_PORT_PLL_ENABLE_B,
133 BXT_PORT_PLL_ENABLE_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]134 PORT_CLK_SEL_DDIA,
135 PORT_CLK_SEL_DDIB,
136 PORT_CLK_SEL_DDIC,
137 PORT_CLK_SEL_DDID,
138 PORT_CLK_SEL_DDIE,
139 TRANSA_CLK_SEL,
140 TRANSB_CLK_SEL,
141 TRANSC_CLK_SEL,
142 NDE_RSTWRN_OPT,
143 BLC_PWM_CPU_CTL2,
144 BLC_PWM_CPU_CTL,
145 HTOTAL_A,
146 HBLANK_A,
147 HSYNC_A,
148 VTOTAL_A,
149 VBLANK_A,
150 VSYNC_A,
151 PIPEASRC,
152 PIPE_VSYNCSHIFT_A,
153 PIPEA_DATA_M1,
154 PIPEA_DATA_N1,
155 PIPEA_LINK_M1,
156 PIPEA_LINK_N1,
157 FDI_TX_CTL_A,
158 PIPEA_DDI_FUNC_CTL,
159 PIPEA_MSA_MISC,
160 SRD_CTL_A,
161 SRD_STATUS_A,
162 HTOTAL_B,
163 HBLANK_B,
164 HSYNC_B,
165 VTOTAL_B,
166 VBLANK_B,
167 VSYNC_B,
168 PIPEBSRC,
169 PIPE_VSYNCSHIFT_B,
170 PIPEB_DATA_M1,
171 PIPEB_DATA_N1,
172 PIPEB_LINK_M1,
173 PIPEB_LINK_N1,
174 FDI_TX_CTL_B,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]175 PORT_HOTPLUG_EN,
176 PORT_HOTPLUG_STAT,
177 GMCH_SDVOB,
178 GMCH_SDVOC,
179 GMCH_LVDS,
Arthur Heymanse87d0d12018-03-28 17:02:49 +0200[diff] [blame]180 GMCH_PP_STATUS,
181 GMCH_PP_CONTROL,
182 GMCH_PP_ON_DELAYS,
183 GMCH_PP_OFF_DELAYS,
184 GMCH_PP_DIVISOR,
Arthur Heymansd5198442018-03-28 17:05:12 +0200[diff] [blame]185 GMCH_PFIT_CONTROL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]186 PIPEB_DDI_FUNC_CTL,
187 PIPEB_MSA_MISC,
188 SRD_CTL_B,
189 SRD_STATUS_B,
190 HTOTAL_C,
191 HBLANK_C,
192 HSYNC_C,
193 VTOTAL_C,
194 VBLANK_C,
195 VSYNC_C,
196 PIPECSRC,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]197 G4X_AUD_VID_DID,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]198 PIPE_VSYNCSHIFT_C,
199 PIPEC_DATA_M1,
200 PIPEC_DATA_N1,
201 PIPEC_LINK_M1,
202 PIPEC_LINK_N1,
203 FDI_TX_CTL_C,
204 PIPEC_DDI_FUNC_CTL,
205 PIPEC_MSA_MISC,
206 SRD_CTL_C,
207 SRD_STATUS_C,
208 DDI_BUF_CTL_A,
209 DDI_AUX_CTL_A,
210 DDI_AUX_DATA_A_1,
211 DDI_AUX_DATA_A_2,
212 DDI_AUX_DATA_A_3,
213 DDI_AUX_DATA_A_4,
214 DDI_AUX_DATA_A_5,
215 DDI_AUX_MUTEX_A,
216 DP_TP_CTL_A,
217 DDI_BUF_CTL_B,
218 DDI_AUX_CTL_B,
219 DDI_AUX_DATA_B_1,
220 DDI_AUX_DATA_B_2,
221 DDI_AUX_DATA_B_3,
222 DDI_AUX_DATA_B_4,
223 DDI_AUX_DATA_B_5,
224 DDI_AUX_MUTEX_B,
225 DP_TP_CTL_B,
226 DP_TP_STATUS_B,
227 DDI_BUF_CTL_C,
228 DDI_AUX_CTL_C,
229 DDI_AUX_DATA_C_1,
230 DDI_AUX_DATA_C_2,
231 DDI_AUX_DATA_C_3,
232 DDI_AUX_DATA_C_4,
233 DDI_AUX_DATA_C_5,
234 DDI_AUX_MUTEX_C,
235 DP_TP_CTL_C,
236 DP_TP_STATUS_C,
237 DDI_BUF_CTL_D,
238 DDI_AUX_CTL_D,
239 DDI_AUX_DATA_D_1,
240 DDI_AUX_DATA_D_2,
241 DDI_AUX_DATA_D_3,
242 DDI_AUX_DATA_D_4,
243 DDI_AUX_DATA_D_5,
244 DDI_AUX_MUTEX_D,
245 DP_TP_CTL_D,
246 DP_TP_STATUS_D,
247 DDI_BUF_CTL_E,
248 DP_TP_CTL_E,
249 DP_TP_STATUS_E,
250 SRD_CTL,
251 SRD_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]252 BXT_PHY_CTL_A,
253 BXT_PHY_CTL_B,
254 BXT_PHY_CTL_C,
255 BXT_PHY_CTL_FAM_EDP,
256 BXT_PHY_CTL_FAM_DDI,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]257 DDI_BUF_TRANS_A_S0T1,
258 DDI_BUF_TRANS_A_S0T2,
259 DDI_BUF_TRANS_A_S1T1,
260 DDI_BUF_TRANS_A_S1T2,
261 DDI_BUF_TRANS_A_S2T1,
262 DDI_BUF_TRANS_A_S2T2,
263 DDI_BUF_TRANS_A_S3T1,
264 DDI_BUF_TRANS_A_S3T2,
265 DDI_BUF_TRANS_A_S4T1,
266 DDI_BUF_TRANS_A_S4T2,
267 DDI_BUF_TRANS_A_S5T1,
268 DDI_BUF_TRANS_A_S5T2,
269 DDI_BUF_TRANS_A_S6T1,
270 DDI_BUF_TRANS_A_S6T2,
271 DDI_BUF_TRANS_A_S7T1,
272 DDI_BUF_TRANS_A_S7T2,
273 DDI_BUF_TRANS_A_S8T1,
274 DDI_BUF_TRANS_A_S8T2,
275 DDI_BUF_TRANS_A_S9T1,
276 DDI_BUF_TRANS_A_S9T2,
277 DDI_BUF_TRANS_B_S0T1,
278 DDI_BUF_TRANS_B_S0T2,
279 DDI_BUF_TRANS_B_S1T1,
280 DDI_BUF_TRANS_B_S1T2,
281 DDI_BUF_TRANS_B_S2T1,
282 DDI_BUF_TRANS_B_S2T2,
283 DDI_BUF_TRANS_B_S3T1,
284 DDI_BUF_TRANS_B_S3T2,
285 DDI_BUF_TRANS_B_S4T1,
286 DDI_BUF_TRANS_B_S4T2,
287 DDI_BUF_TRANS_B_S5T1,
288 DDI_BUF_TRANS_B_S5T2,
289 DDI_BUF_TRANS_B_S6T1,
290 DDI_BUF_TRANS_B_S6T2,
291 DDI_BUF_TRANS_B_S7T1,
292 DDI_BUF_TRANS_B_S7T2,
293 DDI_BUF_TRANS_B_S8T1,
294 DDI_BUF_TRANS_B_S8T2,
295 DDI_BUF_TRANS_B_S9T1,
296 DDI_BUF_TRANS_B_S9T2,
297 DDI_BUF_TRANS_C_S0T1,
298 DDI_BUF_TRANS_C_S0T2,
299 DDI_BUF_TRANS_C_S1T1,
300 DDI_BUF_TRANS_C_S1T2,
301 DDI_BUF_TRANS_C_S2T1,
302 DDI_BUF_TRANS_C_S2T2,
303 DDI_BUF_TRANS_C_S3T1,
304 DDI_BUF_TRANS_C_S3T2,
305 DDI_BUF_TRANS_C_S4T1,
306 DDI_BUF_TRANS_C_S4T2,
307 DDI_BUF_TRANS_C_S5T1,
308 DDI_BUF_TRANS_C_S5T2,
309 DDI_BUF_TRANS_C_S6T1,
310 DDI_BUF_TRANS_C_S6T2,
311 DDI_BUF_TRANS_C_S7T1,
312 DDI_BUF_TRANS_C_S7T2,
313 DDI_BUF_TRANS_C_S8T1,
314 DDI_BUF_TRANS_C_S8T2,
315 DDI_BUF_TRANS_C_S9T1,
316 DDI_BUF_TRANS_C_S9T2,
317 DDI_BUF_TRANS_D_S0T1,
318 DDI_BUF_TRANS_D_S0T2,
319 DDI_BUF_TRANS_D_S1T1,
320 DDI_BUF_TRANS_D_S1T2,
321 DDI_BUF_TRANS_D_S2T1,
322 DDI_BUF_TRANS_D_S2T2,
323 DDI_BUF_TRANS_D_S3T1,
324 DDI_BUF_TRANS_D_S3T2,
325 DDI_BUF_TRANS_D_S4T1,
326 DDI_BUF_TRANS_D_S4T2,
327 DDI_BUF_TRANS_D_S5T1,
328 DDI_BUF_TRANS_D_S5T2,
329 DDI_BUF_TRANS_D_S6T1,
330 DDI_BUF_TRANS_D_S6T2,
331 DDI_BUF_TRANS_D_S7T1,
332 DDI_BUF_TRANS_D_S7T2,
333 DDI_BUF_TRANS_D_S8T1,
334 DDI_BUF_TRANS_D_S8T2,
335 DDI_BUF_TRANS_D_S9T1,
336 DDI_BUF_TRANS_D_S9T2,
337 DDI_BUF_TRANS_E_S0T1,
338 DDI_BUF_TRANS_E_S0T2,
339 DDI_BUF_TRANS_E_S1T1,
340 DDI_BUF_TRANS_E_S1T2,
341 DDI_BUF_TRANS_E_S2T1,
342 DDI_BUF_TRANS_E_S2T2,
343 DDI_BUF_TRANS_E_S3T1,
344 DDI_BUF_TRANS_E_S3T2,
345 DDI_BUF_TRANS_E_S4T1,
346 DDI_BUF_TRANS_E_S4T2,
347 DDI_BUF_TRANS_E_S5T1,
348 DDI_BUF_TRANS_E_S5T2,
349 DDI_BUF_TRANS_E_S6T1,
350 DDI_BUF_TRANS_E_S6T2,
351 DDI_BUF_TRANS_E_S7T1,
352 DDI_BUF_TRANS_E_S7T2,
353 DDI_BUF_TRANS_E_S8T1,
354 DDI_BUF_TRANS_E_S8T2,
355 DDI_BUF_TRANS_E_S9T1,
356 DDI_BUF_TRANS_E_S9T2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]357 AUD_VID_DID,
358 PFA_WIN_POS,
359 PFA_WIN_SZ,
360 PFA_CTL_1,
361 PS_WIN_POS_1_A,
362 PS_WIN_SZ_1_A,
363 PS_CTRL_1_A,
364 PS_WIN_POS_2_A,
365 PS_WIN_SZ_2_A,
366 PS_CTRL_2_A,
367 PFB_WIN_POS,
368 PFB_WIN_SZ,
369 PFB_CTL_1,
370 PS_WIN_POS_1_B,
371 PS_WIN_SZ_1_B,
372 PS_CTRL_1_B,
373 PS_WIN_POS_2_B,
374 PS_WIN_SZ_2_B,
375 PS_CTRL_2_B,
376 PFC_WIN_POS,
377 PFC_WIN_SZ,
378 PFC_CTL_1,
379 PS_WIN_POS_1_C,
380 PS_WIN_SZ_1_C,
381 PS_CTRL_1_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]382 BXT_PORT_CL1CM_DW0_BC,
Nico Huber58afc202017-06-12 21:34:55 +0200[diff] [blame]383 DISPIO_CR_TX_BMU_CR0,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]384 BXT_PORT_CL1CM_DW9_BC,
385 BXT_PORT_CL1CM_DW10_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]386 BXT_PORT_PLL_EBB_0_B,
387 BXT_PORT_PLL_EBB_4_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]388 DPLL1_CFGR1,
389 DPLL1_CFGR2,
390 DPLL2_CFGR1,
391 DPLL2_CFGR2,
392 DPLL3_CFGR1,
393 DPLL3_CFGR2,
394 DPLL_CTRL1,
395 DPLL_CTRL2,
396 DPLL_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]397 BXT_PORT_CL1CM_DW28_BC,
398 BXT_PORT_CL1CM_DW30_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]399 BXT_PORT_PLL_0_B,
400 BXT_PORT_PLL_1_B,
401 BXT_PORT_PLL_2_B,
402 BXT_PORT_PLL_3_B,
403 BXT_PORT_PLL_6_B,
404 BXT_PORT_PLL_8_B,
405 BXT_PORT_PLL_9_B,
406 BXT_PORT_PLL_10_B,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]407 BXT_PORT_REF_DW3_BC,
408 BXT_PORT_REF_DW6_BC,
409 BXT_PORT_REF_DW8_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]410 BXT_PORT_PLL_EBB_0_C,
411 BXT_PORT_PLL_EBB_4_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]412 BXT_PORT_CL2CM_DW6_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]413 BXT_PORT_PLL_0_C,
414 BXT_PORT_PLL_1_C,
415 BXT_PORT_PLL_2_C,
416 BXT_PORT_PLL_3_C,
417 BXT_PORT_PLL_6_C,
418 BXT_PORT_PLL_8_C,
419 BXT_PORT_PLL_9_C,
420 BXT_PORT_PLL_10_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]421 BXT_PORT_PCS_DW10_01_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]422 BXT_PORT_PCS_DW12_01_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]423 BXT_PORT_TX_DW2_LN0_B,
424 BXT_PORT_TX_DW3_LN0_B,
425 BXT_PORT_TX_DW4_LN0_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]426 BXT_PORT_TX_DW14_LN0_B,
427 BXT_PORT_TX_DW14_LN1_B,
428 BXT_PORT_TX_DW14_LN2_B,
429 BXT_PORT_TX_DW14_LN3_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]430 BXT_PORT_PCS_DW10_01_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]431 BXT_PORT_PCS_DW12_01_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]432 BXT_PORT_TX_DW2_LN0_C,
433 BXT_PORT_TX_DW3_LN0_C,
434 BXT_PORT_TX_DW4_LN0_C,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]435 BXT_PORT_TX_DW14_LN0_C,
436 BXT_PORT_TX_DW14_LN1_C,
437 BXT_PORT_TX_DW14_LN2_C,
438 BXT_PORT_TX_DW14_LN3_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]439 BXT_PORT_PCS_DW10_GRP_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]440 BXT_PORT_PCS_DW12_GRP_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]441 BXT_PORT_TX_DW2_GRP_B,
442 BXT_PORT_TX_DW3_GRP_B,
443 BXT_PORT_TX_DW4_GRP_B,
444 BXT_PORT_PCS_DW10_GRP_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]445 BXT_PORT_PCS_DW12_GRP_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]446 BXT_PORT_TX_DW2_GRP_C,
447 BXT_PORT_TX_DW3_GRP_C,
448 BXT_PORT_TX_DW4_GRP_C,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]449 BXT_DE_PLL_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]450 HTOTAL_EDP,
451 HBLANK_EDP,
452 HSYNC_EDP,
453 VTOTAL_EDP,
454 VBLANK_EDP,
455 VSYNC_EDP,
456 PIPE_EDP_DATA_M1,
457 PIPE_EDP_DATA_N1,
458 PIPE_EDP_LINK_M1,
459 PIPE_EDP_LINK_N1,
460 PIPE_EDP_DDI_FUNC_CTL,
461 PIPE_EDP_MSA_MISC,
462 SRD_CTL_EDP,
463 SRD_STATUS_EDP,
464 PIPE_SCANLINE_A,
465 PIPEACONF,
466 PIPEAMISC,
467 PIPE_FRMCNT_A,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]468 PIPEA_GMCH_DATA_M,
469 PIPEA_GMCH_DATA_N,
470 PIPEA_GMCH_LINK_M,
471 PIPEA_GMCH_LINK_N,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]472 CUR_CTL_A,
473 CUR_BASE_A,
474 CUR_POS_A,
475 CUR_FBC_CTL_A,
Nico Huber75a707f2018-06-18 16:28:33 +0200[diff] [blame^]476 CURBCNTR,
477 CURBBASE,
478 CURBPOS,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]479 CUR_WM_A_0,
480 CUR_WM_A_1,
481 CUR_WM_A_2,
482 CUR_WM_A_3,
483 CUR_WM_A_4,
484 CUR_WM_A_5,
485 CUR_WM_A_6,
486 CUR_WM_A_7,
487 CUR_BUF_CFG_A,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]488 DSPACNTR,
489 DSPALINOFF,
490 DSPASTRIDE,
491 PLANE_POS_1_A,
492 PLANE_SIZE_1_A,
493 DSPASURF,
494 DSPATILEOFF,
495 PLANE_WM_1_A_0,
496 PLANE_WM_1_A_1,
497 PLANE_WM_1_A_2,
498 PLANE_WM_1_A_3,
499 PLANE_WM_1_A_4,
500 PLANE_WM_1_A_5,
501 PLANE_WM_1_A_6,
502 PLANE_WM_1_A_7,
503 PLANE_BUF_CFG_1_A,
504 SPACNTR,
505 PIPE_SCANLINE_B,
506 PIPEBCONF,
507 PIPEBMISC,
508 PIPE_FRMCNT_B,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]509 PIPEB_GMCH_DATA_M,
510 PIPEB_GMCH_DATA_N,
511 PIPEB_GMCH_LINK_M,
512 PIPEB_GMCH_LINK_N,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]513 CUR_CTL_B,
514 CUR_BASE_B,
515 CUR_POS_B,
516 CUR_FBC_CTL_B,
517 CUR_WM_B_0,
518 CUR_WM_B_1,
519 CUR_WM_B_2,
520 CUR_WM_B_3,
521 CUR_WM_B_4,
522 CUR_WM_B_5,
523 CUR_WM_B_6,
524 CUR_WM_B_7,
525 CUR_BUF_CFG_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]526 DSPBCNTR,
527 DSPBLINOFF,
528 DSPBSTRIDE,
529 PLANE_POS_1_B,
530 PLANE_SIZE_1_B,
531 DSPBSURF,
532 DSPBTILEOFF,
533 PLANE_WM_1_B_0,
534 PLANE_WM_1_B_1,
535 PLANE_WM_1_B_2,
536 PLANE_WM_1_B_3,
537 PLANE_WM_1_B_4,
538 PLANE_WM_1_B_5,
539 PLANE_WM_1_B_6,
540 PLANE_WM_1_B_7,
541 PLANE_BUF_CFG_1_B,
542 SPBCNTR,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]543 GMCH_VGACNTRL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]544 PIPE_SCANLINE_C,
545 PIPECCONF,
546 PIPECMISC,
547 PIPE_FRMCNT_C,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]548 CUR_CTL_C,
549 CUR_BASE_C,
550 CUR_POS_C,
551 CUR_FBC_CTL_C,
552 CUR_WM_C_0,
553 CUR_WM_C_1,
554 CUR_WM_C_2,
555 CUR_WM_C_3,
556 CUR_WM_C_4,
557 CUR_WM_C_5,
558 CUR_WM_C_6,
559 CUR_WM_C_7,
560 CUR_BUF_CFG_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]561 DSPCCNTR,
562 DSPCLINOFF,
563 DSPCSTRIDE,
564 PLANE_POS_1_C,
565 PLANE_SIZE_1_C,
566 DSPCSURF,
567 DSPCTILEOFF,
568 PLANE_WM_1_C_0,
569 PLANE_WM_1_C_1,
570 PLANE_WM_1_C_2,
571 PLANE_WM_1_C_3,
572 PLANE_WM_1_C_4,
573 PLANE_WM_1_C_5,
574 PLANE_WM_1_C_6,
575 PLANE_WM_1_C_7,
576 PLANE_BUF_CFG_1_C,
577 SPCCNTR,
578 PIPE_EDP_CONF,
579 PCH_FDI_CHICKEN_B_C,
580 QUIRK_C2004,
581 SFUSE_STRAP,
582 PCH_DSPCLK_GATE_D,
583 SDEISR,
584 SDEIMR,
585 SDEIIR,
586 SDEIER,
587 SHOTPLUG_CTL,
588 PCH_GMBUS0,
589 PCH_GMBUS1,
590 PCH_GMBUS2,
591 PCH_GMBUS3,
592 PCH_GMBUS4,
593 PCH_GMBUS5,
594 SBI_ADDR,
595 SBI_DATA,
596 SBI_CTL_STAT,
597 PCH_DPLL_A,
598 PCH_DPLL_B,
599 PCH_PIXCLK_GATE,
600 PCH_FPA0,
601 PCH_FPA1,
602 PCH_FPB0,
603 PCH_FPB1,
604 PCH_DREF_CONTROL,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]605 PCH_RAWCLK_FREQ,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]606 PCH_DPLL_SEL,
607 PCH_PP_STATUS,
608 PCH_PP_CONTROL,
609 PCH_PP_ON_DELAYS,
610 PCH_PP_OFF_DELAYS,
611 PCH_PP_DIVISOR,
612 BLC_PWM_PCH_CTL1,
613 BLC_PWM_PCH_CTL2,
614 TRANS_HTOTAL_A,
615 TRANS_HBLANK_A,
616 TRANS_HSYNC_A,
617 TRANS_VTOTAL_A,
618 TRANS_VBLANK_A,
619 TRANS_VSYNC_A,
620 TRANS_VSYNCSHIFT_A,
621 TRANSA_DATA_M1,
622 TRANSA_DATA_N1,
623 TRANSA_DP_LINK_M1,
624 TRANSA_DP_LINK_N1,
625 TRANS_DP_CTL_A,
626 TRANS_HTOTAL_B,
627 TRANS_HBLANK_B,
628 TRANS_HSYNC_B,
629 TRANS_VTOTAL_B,
630 TRANS_VBLANK_B,
631 TRANS_VSYNC_B,
632 TRANS_VSYNCSHIFT_B,
633 TRANSB_DATA_M1,
634 TRANSB_DATA_N1,
635 TRANSB_DP_LINK_M1,
636 TRANSB_DP_LINK_N1,
637 PCH_ADPA,
638 PCH_HDMIB,
639 PCH_HDMIC,
640 PCH_HDMID,
641 PCH_LVDS,
642 TRANS_DP_CTL_B,
643 TRANS_HTOTAL_C,
644 TRANS_HBLANK_C,
645 TRANS_HSYNC_C,
646 TRANS_VTOTAL_C,
647 TRANS_VBLANK_C,
648 TRANS_VSYNC_C,
649 TRANS_VSYNCSHIFT_C,
650 TRANSC_DATA_M1,
651 TRANSC_DATA_N1,
652 TRANSC_DP_LINK_M1,
653 TRANSC_DP_LINK_N1,
654 TRANS_DP_CTL_C,
655 PCH_DP_B,
656 PCH_DP_AUX_CTL_B,
657 PCH_DP_AUX_DATA_B_1,
658 PCH_DP_AUX_DATA_B_2,
659 PCH_DP_AUX_DATA_B_3,
660 PCH_DP_AUX_DATA_B_4,
661 PCH_DP_AUX_DATA_B_5,
662 PCH_DP_C,
663 PCH_DP_AUX_CTL_C,
664 PCH_DP_AUX_DATA_C_1,
665 PCH_DP_AUX_DATA_C_2,
666 PCH_DP_AUX_DATA_C_3,
667 PCH_DP_AUX_DATA_C_4,
668 PCH_DP_AUX_DATA_C_5,
669 PCH_DP_D,
670 PCH_DP_AUX_CTL_D,
671 PCH_DP_AUX_DATA_D_1,
672 PCH_DP_AUX_DATA_D_2,
673 PCH_DP_AUX_DATA_D_3,
674 PCH_DP_AUX_DATA_D_4,
675 PCH_DP_AUX_DATA_D_5,
676 AUD_CONFIG_A,
677 PCH_AUD_VID_DID,
678 AUD_HDMIW_HDMIEDID_A,
679 AUD_CNTL_ST_A,
680 AUD_CNTRL_ST2,
681 AUD_CONFIG_B,
682 AUD_HDMIW_HDMIEDID_B,
683 AUD_CNTL_ST_B,
684 AUD_CONFIG_C,
685 AUD_HDMIW_HDMIEDID_C,
686 AUD_CNTL_ST_C,
687 TRANSACONF,
688 FDI_RXA_CTL,
689 FDI_RX_MISC_A,
690 FDI_RXA_IIR,
691 FDI_RXA_IMR,
692 FDI_RXA_TUSIZE1,
693 QUIRK_F0060,
694 TRANSA_CHICKEN2,
695 TRANSBCONF,
696 FDI_RXB_CTL,
697 FDI_RX_MISC_B,
698 FDI_RXB_IIR,
699 FDI_RXB_IMR,
700 FDI_RXB_TUSIZE1,
701 QUIRK_F1060,
702 TRANSB_CHICKEN2,
703 TRANSCCONF,
704 FDI_RXC_CTL,
705 FDI_RX_MISC_C,
706 FDI_RXC_IIR,
707 FDI_RXC_IMR,
708 FDI_RXC_TUSIZE1,
709 QUIRK_F2060,
710 TRANSC_CHICKEN2,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]711 BXT_P_CR_GT_DISP_PWRON,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]712 GT_MAILBOX,
713 GT_MAILBOX_DATA,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]714 GT_MAILBOX_DATA_1,
715 BXT_PORT_CL1CM_DW0_A,
716 BXT_PORT_CL1CM_DW9_A,
717 BXT_PORT_CL1CM_DW10_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]718 BXT_PORT_PLL_EBB_0_A,
719 BXT_PORT_PLL_EBB_4_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]720 BXT_PORT_CL1CM_DW28_A,
721 BXT_PORT_CL1CM_DW30_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]722 BXT_PORT_PLL_0_A,
723 BXT_PORT_PLL_1_A,
724 BXT_PORT_PLL_2_A,
725 BXT_PORT_PLL_3_A,
726 BXT_PORT_PLL_6_A,
727 BXT_PORT_PLL_8_A,
728 BXT_PORT_PLL_9_A,
729 BXT_PORT_PLL_10_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]730 BXT_PORT_REF_DW3_A,
731 BXT_PORT_REF_DW6_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]732 BXT_PORT_REF_DW8_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]733 BXT_PORT_PCS_DW10_01_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]734 BXT_PORT_PCS_DW12_01_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]735 BXT_PORT_TX_DW2_LN0_A,
736 BXT_PORT_TX_DW3_LN0_A,
737 BXT_PORT_TX_DW4_LN0_A,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]738 BXT_PORT_TX_DW14_LN0_A,
739 BXT_PORT_TX_DW14_LN1_A,
740 BXT_PORT_TX_DW14_LN2_A,
741 BXT_PORT_TX_DW14_LN3_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]742 BXT_PORT_PCS_DW10_GRP_A,
743 BXT_PORT_PCS_DW12_GRP_A,
744 BXT_PORT_TX_DW2_GRP_A,
745 BXT_PORT_TX_DW3_GRP_A,
746 BXT_PORT_TX_DW4_GRP_A);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]747
748 pragma Warnings
749 (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)",
750 Reason => "TODO: Should it matter?");
751 pragma Keep_Names (Registers_Invalid_Index);
752 pragma Warnings
753 (GNATprove, On, "pragma ""KEEP_NAMES"" ignored *(not yet supported)");
754
755 Register_Width : constant := 4;
756
757 for Registers_Invalid_Index use
758 (Invalid_Register => 0,
759
760 ---------------------------------------------------------------------------
761 -- Pipe A registers
762 ---------------------------------------------------------------------------
763
764 -- pipe timing registers
765
766 HTOTAL_A => 16#06_0000# / Register_Width,
767 HBLANK_A => 16#06_0004# / Register_Width,
768 HSYNC_A => 16#06_0008# / Register_Width,
769 VTOTAL_A => 16#06_000c# / Register_Width,
770 VBLANK_A => 16#06_0010# / Register_Width,
771 VSYNC_A => 16#06_0014# / Register_Width,
772 PIPEASRC => 16#06_001c# / Register_Width,
773 PIPEACONF => 16#07_0008# / Register_Width,
774 PIPEAMISC => 16#07_0030# / Register_Width,
775 TRANS_HTOTAL_A => 16#0e_0000# / Register_Width,
776 TRANS_HBLANK_A => 16#0e_0004# / Register_Width,
777 TRANS_HSYNC_A => 16#0e_0008# / Register_Width,
778 TRANS_VTOTAL_A => 16#0e_000c# / Register_Width,
779 TRANS_VBLANK_A => 16#0e_0010# / Register_Width,
780 TRANS_VSYNC_A => 16#0e_0014# / Register_Width,
781 TRANSA_DATA_M1 => 16#0e_0030# / Register_Width,
782 TRANSA_DATA_N1 => 16#0e_0034# / Register_Width,
783 TRANSA_DP_LINK_M1 => 16#0e_0040# / Register_Width,
784 TRANSA_DP_LINK_N1 => 16#0e_0044# / Register_Width,
785 PIPEA_DATA_M1 => 16#06_0030# / Register_Width,
786 PIPEA_DATA_N1 => 16#06_0034# / Register_Width,
787 PIPEA_LINK_M1 => 16#06_0040# / Register_Width,
788 PIPEA_LINK_N1 => 16#06_0044# / Register_Width,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]789 PIPEA_GMCH_DATA_M => 16#07_0050# / Register_Width,
790 PIPEA_GMCH_DATA_N => 16#07_0054# / Register_Width,
791 PIPEA_GMCH_LINK_M => 16#07_0060# / Register_Width,
792 PIPEA_GMCH_LINK_N => 16#07_0064# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]793 PIPEA_DDI_FUNC_CTL => 16#06_0400# / Register_Width,
794 PIPEA_MSA_MISC => 16#06_0410# / Register_Width,
795
796 -- PCH sideband interface registers
797 SBI_ADDR => 16#0c_6000# / Register_Width,
798 SBI_DATA => 16#0c_6004# / Register_Width,
799 SBI_CTL_STAT => 16#0c_6008# / Register_Width,
800
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]801 -- GMCH clock registers
802 GMCH_DPLL_A => 16#00_6014# / Register_Width,
803 GMCH_FPA0 => 16#00_6040# / Register_Width,
804 GMCH_FPA1 => 16#00_6044# / Register_Width,
805
806 -- PCH clock registers
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]807 PCH_DPLL_A => 16#0c_6014# / Register_Width,
808 PCH_PIXCLK_GATE => 16#0c_6020# / Register_Width,
809 PCH_FPA0 => 16#0c_6040# / Register_Width,
810 PCH_FPA1 => 16#0c_6044# / Register_Width,
811
812 -- panel fitter
813 PFA_CTL_1 => 16#06_8080# / Register_Width,
814 PFA_WIN_POS => 16#06_8070# / Register_Width,
815 PFA_WIN_SZ => 16#06_8074# / Register_Width,
816 PS_WIN_POS_1_A => 16#06_8170# / Register_Width,
817 PS_WIN_SZ_1_A => 16#06_8174# / Register_Width,
818 PS_CTRL_1_A => 16#06_8180# / Register_Width,
819 PS_WIN_POS_2_A => 16#06_8270# / Register_Width,
820 PS_WIN_SZ_2_A => 16#06_8274# / Register_Width,
821 PS_CTRL_2_A => 16#06_8280# / Register_Width,
822
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]823 -- cursor control
824 CUR_CTL_A => 16#07_0080# / Register_Width,
825 CUR_BASE_A => 16#07_0084# / Register_Width,
826 CUR_POS_A => 16#07_0088# / Register_Width,
827 CUR_FBC_CTL_A => 16#07_00a0# / Register_Width,
828
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]829 -- display control
830 DSPACNTR => 16#07_0180# / Register_Width,
831 DSPALINOFF => 16#07_0184# / Register_Width,
832 DSPASTRIDE => 16#07_0188# / Register_Width,
833 PLANE_POS_1_A => 16#07_018c# / Register_Width,
834 PLANE_SIZE_1_A => 16#07_0190# / Register_Width,
835 DSPASURF => 16#07_019c# / Register_Width,
836 DSPATILEOFF => 16#07_01a4# / Register_Width,
837
838 -- sprite control
839 SPACNTR => 16#07_0280# / Register_Width,
840
841 -- FDI and PCH transcoder control
842 FDI_TX_CTL_A => 16#06_0100# / Register_Width,
843 FDI_RXA_CTL => 16#0f_000c# / Register_Width,
844 FDI_RX_MISC_A => 16#0f_0010# / Register_Width,
845 FDI_RXA_IIR => 16#0f_0014# / Register_Width,
846 FDI_RXA_IMR => 16#0f_0018# / Register_Width,
847 FDI_RXA_TUSIZE1 => 16#0f_0030# / Register_Width,
848 TRANSACONF => 16#0f_0008# / Register_Width,
849 TRANSA_CHICKEN2 => 16#0f_0064# / Register_Width,
850
851 -- watermark registers
852 WM_LINETIME_A => 16#04_5270# / Register_Width,
853 PLANE_WM_1_A_0 => 16#07_0240# / Register_Width,
854 PLANE_WM_1_A_1 => 16#07_0244# / Register_Width,
855 PLANE_WM_1_A_2 => 16#07_0248# / Register_Width,
856 PLANE_WM_1_A_3 => 16#07_024c# / Register_Width,
857 PLANE_WM_1_A_4 => 16#07_0250# / Register_Width,
858 PLANE_WM_1_A_5 => 16#07_0254# / Register_Width,
859 PLANE_WM_1_A_6 => 16#07_0258# / Register_Width,
860 PLANE_WM_1_A_7 => 16#07_025c# / Register_Width,
861 PLANE_BUF_CFG_1_A => 16#07_027c# / Register_Width,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]862 CUR_WM_A_0 => 16#07_0140# / Register_Width,
863 CUR_WM_A_1 => 16#07_0144# / Register_Width,
864 CUR_WM_A_2 => 16#07_0148# / Register_Width,
865 CUR_WM_A_3 => 16#07_014c# / Register_Width,
866 CUR_WM_A_4 => 16#07_0150# / Register_Width,
867 CUR_WM_A_5 => 16#07_0154# / Register_Width,
868 CUR_WM_A_6 => 16#07_0158# / Register_Width,
869 CUR_WM_A_7 => 16#07_015c# / Register_Width,
870 CUR_BUF_CFG_A => 16#07_017c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]871
872 -- CPU transcoder clock select
873 TRANSA_CLK_SEL => 16#04_6140# / Register_Width,
874
875 ---------------------------------------------------------------------------
876 -- Pipe B registers
877 ---------------------------------------------------------------------------
878
879 -- pipe timing registers
880
881 HTOTAL_B => 16#06_1000# / Register_Width,
882 HBLANK_B => 16#06_1004# / Register_Width,
883 HSYNC_B => 16#06_1008# / Register_Width,
884 VTOTAL_B => 16#06_100c# / Register_Width,
885 VBLANK_B => 16#06_1010# / Register_Width,
886 VSYNC_B => 16#06_1014# / Register_Width,
887 PIPEBSRC => 16#06_101c# / Register_Width,
888 PIPEBCONF => 16#07_1008# / Register_Width,
889 PIPEBMISC => 16#07_1030# / Register_Width,
890 TRANS_HTOTAL_B => 16#0e_1000# / Register_Width,
891 TRANS_HBLANK_B => 16#0e_1004# / Register_Width,
892 TRANS_HSYNC_B => 16#0e_1008# / Register_Width,
893 TRANS_VTOTAL_B => 16#0e_100c# / Register_Width,
894 TRANS_VBLANK_B => 16#0e_1010# / Register_Width,
895 TRANS_VSYNC_B => 16#0e_1014# / Register_Width,
896 TRANSB_DATA_M1 => 16#0e_1030# / Register_Width,
897 TRANSB_DATA_N1 => 16#0e_1034# / Register_Width,
898 TRANSB_DP_LINK_M1 => 16#0e_1040# / Register_Width,
899 TRANSB_DP_LINK_N1 => 16#0e_1044# / Register_Width,
900 PIPEB_DATA_M1 => 16#06_1030# / Register_Width,
901 PIPEB_DATA_N1 => 16#06_1034# / Register_Width,
902 PIPEB_LINK_M1 => 16#06_1040# / Register_Width,
903 PIPEB_LINK_N1 => 16#06_1044# / Register_Width,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]904 PIPEB_GMCH_DATA_M => 16#07_1050# / Register_Width,
905 PIPEB_GMCH_DATA_N => 16#07_1054# / Register_Width,
906 PIPEB_GMCH_LINK_M => 16#07_1060# / Register_Width,
907 PIPEB_GMCH_LINK_N => 16#07_1064# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]908 PIPEB_DDI_FUNC_CTL => 16#06_1400# / Register_Width,
909 PIPEB_MSA_MISC => 16#06_1410# / Register_Width,
910
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]911 -- GMCH clock registers
912 GMCH_DPLL_B => 16#00_6018# / Register_Width,
913 GMCH_FPB0 => 16#00_6048# / Register_Width,
914 GMCH_FPB1 => 16#00_604c# / Register_Width,
915
916 -- PCH clock registers
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]917 PCH_DPLL_B => 16#0c_6018# / Register_Width,
918 PCH_FPB0 => 16#0c_6048# / Register_Width,
919 PCH_FPB1 => 16#0c_604c# / Register_Width,
920
921 -- panel fitter
922 PFB_CTL_1 => 16#06_8880# / Register_Width,
923 PFB_WIN_POS => 16#06_8870# / Register_Width,
924 PFB_WIN_SZ => 16#06_8874# / Register_Width,
925 PS_WIN_POS_1_B => 16#06_8970# / Register_Width,
926 PS_WIN_SZ_1_B => 16#06_8974# / Register_Width,
927 PS_CTRL_1_B => 16#06_8980# / Register_Width,
928 PS_WIN_POS_2_B => 16#06_8a70# / Register_Width,
929 PS_WIN_SZ_2_B => 16#06_8a74# / Register_Width,
930 PS_CTRL_2_B => 16#06_8a80# / Register_Width,
931
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]932 -- cursor control
Nico Huber75a707f2018-06-18 16:28:33 +0200[diff] [blame^]933 CURBCNTR => 16#07_00c0# / Register_Width, -- <= SNB
934 CURBBASE => 16#07_00c4# / Register_Width, -- <= SNB
935 CURBPOS => 16#07_00c8# / Register_Width, -- <= SNB
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]936 CUR_CTL_B => 16#07_1080# / Register_Width,
937 CUR_BASE_B => 16#07_1084# / Register_Width,
938 CUR_POS_B => 16#07_1088# / Register_Width,
939 CUR_FBC_CTL_B => 16#07_10a0# / Register_Width,
940
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]941 -- display control
942 DSPBCNTR => 16#07_1180# / Register_Width,
943 DSPBLINOFF => 16#07_1184# / Register_Width,
944 DSPBSTRIDE => 16#07_1188# / Register_Width,
945 PLANE_POS_1_B => 16#07_118c# / Register_Width,
946 PLANE_SIZE_1_B => 16#07_1190# / Register_Width,
947 DSPBSURF => 16#07_119c# / Register_Width,
948 DSPBTILEOFF => 16#07_11a4# / Register_Width,
949
950 -- sprite control
951 SPBCNTR => 16#07_1280# / Register_Width,
952
953 -- FDI and PCH transcoder control
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]954 FDI_TX_CTL_B => 16#06_1100# / Register_Width, -- aliased by GMCH_ADPA
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]955 FDI_RXB_CTL => 16#0f_100c# / Register_Width,
956 FDI_RX_MISC_B => 16#0f_1010# / Register_Width,
957 FDI_RXB_IIR => 16#0f_1014# / Register_Width,
958 FDI_RXB_IMR => 16#0f_1018# / Register_Width,
959 FDI_RXB_TUSIZE1 => 16#0f_1030# / Register_Width,
960 TRANSBCONF => 16#0f_1008# / Register_Width,
961 TRANSB_CHICKEN2 => 16#0f_1064# / Register_Width,
962
963 -- watermark registers
964 WM_LINETIME_B => 16#04_5274# / Register_Width,
965 PLANE_WM_1_B_0 => 16#07_1240# / Register_Width,
966 PLANE_WM_1_B_1 => 16#07_1244# / Register_Width,
967 PLANE_WM_1_B_2 => 16#07_1248# / Register_Width,
968 PLANE_WM_1_B_3 => 16#07_124c# / Register_Width,
969 PLANE_WM_1_B_4 => 16#07_1250# / Register_Width,
970 PLANE_WM_1_B_5 => 16#07_1254# / Register_Width,
971 PLANE_WM_1_B_6 => 16#07_1258# / Register_Width,
972 PLANE_WM_1_B_7 => 16#07_125c# / Register_Width,
973 PLANE_BUF_CFG_1_B => 16#07_127c# / Register_Width,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]974 CUR_WM_B_0 => 16#07_1140# / Register_Width,
975 CUR_WM_B_1 => 16#07_1144# / Register_Width,
976 CUR_WM_B_2 => 16#07_1148# / Register_Width,
977 CUR_WM_B_3 => 16#07_114c# / Register_Width,
978 CUR_WM_B_4 => 16#07_1150# / Register_Width,
979 CUR_WM_B_5 => 16#07_1154# / Register_Width,
980 CUR_WM_B_6 => 16#07_1158# / Register_Width,
981 CUR_WM_B_7 => 16#07_115c# / Register_Width,
982 CUR_BUF_CFG_B => 16#07_117c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]983
984 -- CPU transcoder clock select
985 TRANSB_CLK_SEL => 16#04_6144# / Register_Width,
986
987 ---------------------------------------------------------------------------
988 -- Pipe C registers
989 ---------------------------------------------------------------------------
990
991 -- pipe timing registers
992
993 HTOTAL_C => 16#06_2000# / Register_Width,
994 HBLANK_C => 16#06_2004# / Register_Width,
995 HSYNC_C => 16#06_2008# / Register_Width,
996 VTOTAL_C => 16#06_200c# / Register_Width,
997 VBLANK_C => 16#06_2010# / Register_Width,
998 VSYNC_C => 16#06_2014# / Register_Width,
999 PIPECSRC => 16#06_201c# / Register_Width,
1000 PIPECCONF => 16#07_2008# / Register_Width,
1001 PIPECMISC => 16#07_2030# / Register_Width,
1002 TRANS_HTOTAL_C => 16#0e_2000# / Register_Width,
1003 TRANS_HBLANK_C => 16#0e_2004# / Register_Width,
1004 TRANS_HSYNC_C => 16#0e_2008# / Register_Width,
1005 TRANS_VTOTAL_C => 16#0e_200c# / Register_Width,
1006 TRANS_VBLANK_C => 16#0e_2010# / Register_Width,
1007 TRANS_VSYNC_C => 16#0e_2014# / Register_Width,
1008 TRANSC_DATA_M1 => 16#0e_2030# / Register_Width,
1009 TRANSC_DATA_N1 => 16#0e_2034# / Register_Width,
1010 TRANSC_DP_LINK_M1 => 16#0e_2040# / Register_Width,
1011 TRANSC_DP_LINK_N1 => 16#0e_2044# / Register_Width,
1012 PIPEC_DATA_M1 => 16#06_2030# / Register_Width,
1013 PIPEC_DATA_N1 => 16#06_2034# / Register_Width,
1014 PIPEC_LINK_M1 => 16#06_2040# / Register_Width,
1015 PIPEC_LINK_N1 => 16#06_2044# / Register_Width,
1016 PIPEC_DDI_FUNC_CTL => 16#06_2400# / Register_Width,
1017 PIPEC_MSA_MISC => 16#06_2410# / Register_Width,
1018
1019 -- panel fitter
1020 PFC_CTL_1 => 16#06_9080# / Register_Width,
1021 PFC_WIN_POS => 16#06_9070# / Register_Width,
1022 PFC_WIN_SZ => 16#06_9074# / Register_Width,
1023 PS_WIN_POS_1_C => 16#06_9170# / Register_Width,
1024 PS_WIN_SZ_1_C => 16#06_9174# / Register_Width,
1025 PS_CTRL_1_C => 16#06_9180# / Register_Width,
1026
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1027 -- cursor control
1028 CUR_CTL_C => 16#07_2080# / Register_Width,
1029 CUR_BASE_C => 16#07_2084# / Register_Width,
1030 CUR_POS_C => 16#07_2088# / Register_Width,
1031 CUR_FBC_CTL_C => 16#07_20a0# / Register_Width,
1032
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1033 -- display control
1034 DSPCCNTR => 16#07_2180# / Register_Width,
1035 DSPCLINOFF => 16#07_2184# / Register_Width,
1036 DSPCSTRIDE => 16#07_2188# / Register_Width,
1037 PLANE_POS_1_C => 16#07_218c# / Register_Width,
1038 PLANE_SIZE_1_C => 16#07_2190# / Register_Width,
1039 DSPCSURF => 16#07_219c# / Register_Width,
1040 DSPCTILEOFF => 16#07_21a4# / Register_Width,
1041
1042 -- sprite control
1043 SPCCNTR => 16#07_2280# / Register_Width,
1044
1045 -- PCH transcoder control
1046 FDI_TX_CTL_C => 16#06_2100# / Register_Width,
1047 FDI_RXC_CTL => 16#0f_200c# / Register_Width,
1048 FDI_RX_MISC_C => 16#0f_2010# / Register_Width,
1049 FDI_RXC_IIR => 16#0f_2014# / Register_Width,
1050 FDI_RXC_IMR => 16#0f_2018# / Register_Width,
1051 FDI_RXC_TUSIZE1 => 16#0f_2030# / Register_Width,
1052 TRANSCCONF => 16#0f_2008# / Register_Width,
1053 TRANSC_CHICKEN2 => 16#0f_2064# / Register_Width,
1054
1055 -- watermark registers
1056 WM_LINETIME_C => 16#04_5278# / Register_Width,
1057 PLANE_WM_1_C_0 => 16#07_2240# / Register_Width,
1058 PLANE_WM_1_C_1 => 16#07_2244# / Register_Width,
1059 PLANE_WM_1_C_2 => 16#07_2248# / Register_Width,
1060 PLANE_WM_1_C_3 => 16#07_224c# / Register_Width,
1061 PLANE_WM_1_C_4 => 16#07_2250# / Register_Width,
1062 PLANE_WM_1_C_5 => 16#07_2254# / Register_Width,
1063 PLANE_WM_1_C_6 => 16#07_2258# / Register_Width,
1064 PLANE_WM_1_C_7 => 16#07_225c# / Register_Width,
1065 PLANE_BUF_CFG_1_C => 16#07_227c# / Register_Width,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1066 CUR_WM_C_0 => 16#07_2140# / Register_Width,
1067 CUR_WM_C_1 => 16#07_2144# / Register_Width,
1068 CUR_WM_C_2 => 16#07_2148# / Register_Width,
1069 CUR_WM_C_3 => 16#07_214c# / Register_Width,
1070 CUR_WM_C_4 => 16#07_2150# / Register_Width,
1071 CUR_WM_C_5 => 16#07_2154# / Register_Width,
1072 CUR_WM_C_6 => 16#07_2158# / Register_Width,
1073 CUR_WM_C_7 => 16#07_215c# / Register_Width,
1074 CUR_BUF_CFG_C => 16#07_217c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1075
1076 -- CPU transcoder clock select
1077 TRANSC_CLK_SEL => 16#04_6148# / Register_Width,
1078
1079 ---------------------------------------------------------------------------
1080 -- Pipe EDP registers
1081 ---------------------------------------------------------------------------
1082
1083 -- pipe timing registers
1084
1085 HTOTAL_EDP => 16#06_f000# / Register_Width,
1086 HBLANK_EDP => 16#06_f004# / Register_Width,
1087 HSYNC_EDP => 16#06_f008# / Register_Width,
1088 VTOTAL_EDP => 16#06_f00c# / Register_Width,
1089 VBLANK_EDP => 16#06_f010# / Register_Width,
1090 VSYNC_EDP => 16#06_f014# / Register_Width,
1091 PIPE_EDP_CONF => 16#07_f008# / Register_Width,
1092 PIPE_EDP_DATA_M1 => 16#06_f030# / Register_Width,
1093 PIPE_EDP_DATA_N1 => 16#06_f034# / Register_Width,
1094 PIPE_EDP_LINK_M1 => 16#06_f040# / Register_Width,
1095 PIPE_EDP_LINK_N1 => 16#06_f044# / Register_Width,
1096 PIPE_EDP_DDI_FUNC_CTL => 16#06_f400# / Register_Width,
1097 PIPE_EDP_MSA_MISC => 16#06_f410# / Register_Width,
1098
1099 -- PSR registers
1100 SRD_CTL => 16#06_4800# / Register_Width,
1101 SRD_CTL_A => 16#06_0800# / Register_Width,
1102 SRD_CTL_B => 16#06_1800# / Register_Width,
1103 SRD_CTL_C => 16#06_2800# / Register_Width,
1104 SRD_CTL_EDP => 16#06_f800# / Register_Width,
1105 SRD_STATUS => 16#06_4840# / Register_Width,
1106 SRD_STATUS_A => 16#06_0840# / Register_Width,
1107 SRD_STATUS_B => 16#06_1840# / Register_Width,
1108 SRD_STATUS_C => 16#06_2840# / Register_Width,
1109 SRD_STATUS_EDP => 16#06_f840# / Register_Width,
1110
1111 -- DDI registers
1112 DDI_BUF_CTL_A => 16#06_4000# / Register_Width, -- aliased by DP_CTL_A
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1113 DDI_BUF_TRANS_A_S0T1 => 16#06_4e00# / Register_Width,
1114 DDI_BUF_TRANS_A_S0T2 => 16#06_4e04# / Register_Width,
1115 DDI_BUF_TRANS_A_S1T1 => 16#06_4e08# / Register_Width,
1116 DDI_BUF_TRANS_A_S1T2 => 16#06_4e0c# / Register_Width,
1117 DDI_BUF_TRANS_A_S2T1 => 16#06_4e10# / Register_Width,
1118 DDI_BUF_TRANS_A_S2T2 => 16#06_4e14# / Register_Width,
1119 DDI_BUF_TRANS_A_S3T1 => 16#06_4e18# / Register_Width,
1120 DDI_BUF_TRANS_A_S3T2 => 16#06_4e1c# / Register_Width,
1121 DDI_BUF_TRANS_A_S4T1 => 16#06_4e20# / Register_Width,
1122 DDI_BUF_TRANS_A_S4T2 => 16#06_4e24# / Register_Width,
1123 DDI_BUF_TRANS_A_S5T1 => 16#06_4e28# / Register_Width,
1124 DDI_BUF_TRANS_A_S5T2 => 16#06_4e2c# / Register_Width,
1125 DDI_BUF_TRANS_A_S6T1 => 16#06_4e30# / Register_Width,
1126 DDI_BUF_TRANS_A_S6T2 => 16#06_4e34# / Register_Width,
1127 DDI_BUF_TRANS_A_S7T1 => 16#06_4e38# / Register_Width,
1128 DDI_BUF_TRANS_A_S7T2 => 16#06_4e3c# / Register_Width,
1129 DDI_BUF_TRANS_A_S8T1 => 16#06_4e40# / Register_Width,
1130 DDI_BUF_TRANS_A_S8T2 => 16#06_4e44# / Register_Width,
1131 DDI_BUF_TRANS_A_S9T1 => 16#06_4e48# / Register_Width,
1132 DDI_BUF_TRANS_A_S9T2 => 16#06_4e4c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1133 DDI_AUX_CTL_A => 16#06_4010# / Register_Width, -- aliased by DP_AUX_CTL_A
1134 DDI_AUX_DATA_A_1 => 16#06_4014# / Register_Width, -- aliased by DP_AUX_DATA_A_1
1135 DDI_AUX_DATA_A_2 => 16#06_4018# / Register_Width, -- aliased by DP_AUX_DATA_A_2
1136 DDI_AUX_DATA_A_3 => 16#06_401c# / Register_Width, -- aliased by DP_AUX_DATA_A_3
1137 DDI_AUX_DATA_A_4 => 16#06_4020# / Register_Width, -- aliased by DP_AUX_DATA_A_4
1138 DDI_AUX_DATA_A_5 => 16#06_4024# / Register_Width, -- aliased by DP_AUX_DATA_A_5
1139 DDI_AUX_MUTEX_A => 16#06_402c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1140
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1141 DDI_BUF_CTL_B => 16#06_4100# / Register_Width, -- aliased by GMCH_DP_B
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1142 DDI_BUF_TRANS_B_S0T1 => 16#06_4e60# / Register_Width,
1143 DDI_BUF_TRANS_B_S0T2 => 16#06_4e64# / Register_Width,
1144 DDI_BUF_TRANS_B_S1T1 => 16#06_4e68# / Register_Width,
1145 DDI_BUF_TRANS_B_S1T2 => 16#06_4e6c# / Register_Width,
1146 DDI_BUF_TRANS_B_S2T1 => 16#06_4e70# / Register_Width,
1147 DDI_BUF_TRANS_B_S2T2 => 16#06_4e74# / Register_Width,
1148 DDI_BUF_TRANS_B_S3T1 => 16#06_4e78# / Register_Width,
1149 DDI_BUF_TRANS_B_S3T2 => 16#06_4e7c# / Register_Width,
1150 DDI_BUF_TRANS_B_S4T1 => 16#06_4e80# / Register_Width,
1151 DDI_BUF_TRANS_B_S4T2 => 16#06_4e84# / Register_Width,
1152 DDI_BUF_TRANS_B_S5T1 => 16#06_4e88# / Register_Width,
1153 DDI_BUF_TRANS_B_S5T2 => 16#06_4e8c# / Register_Width,
1154 DDI_BUF_TRANS_B_S6T1 => 16#06_4e90# / Register_Width,
1155 DDI_BUF_TRANS_B_S6T2 => 16#06_4e94# / Register_Width,
1156 DDI_BUF_TRANS_B_S7T1 => 16#06_4e98# / Register_Width,
1157 DDI_BUF_TRANS_B_S7T2 => 16#06_4e9c# / Register_Width,
1158 DDI_BUF_TRANS_B_S8T1 => 16#06_4ea0# / Register_Width,
1159 DDI_BUF_TRANS_B_S8T2 => 16#06_4ea4# / Register_Width,
1160 DDI_BUF_TRANS_B_S9T1 => 16#06_4ea8# / Register_Width,
1161 DDI_BUF_TRANS_B_S9T2 => 16#06_4eac# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1162 DDI_AUX_CTL_B => 16#06_4110# / Register_Width,
1163 DDI_AUX_DATA_B_1 => 16#06_4114# / Register_Width,
1164 DDI_AUX_DATA_B_2 => 16#06_4118# / Register_Width,
1165 DDI_AUX_DATA_B_3 => 16#06_411c# / Register_Width,
1166 DDI_AUX_DATA_B_4 => 16#06_4120# / Register_Width,
1167 DDI_AUX_DATA_B_5 => 16#06_4124# / Register_Width,
1168 DDI_AUX_MUTEX_B => 16#06_412c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1169
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1170 DDI_BUF_CTL_C => 16#06_4200# / Register_Width, -- aliased by GMCH_DP_C
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1171 DDI_BUF_TRANS_C_S0T1 => 16#06_4ec0# / Register_Width,
1172 DDI_BUF_TRANS_C_S0T2 => 16#06_4ec4# / Register_Width,
1173 DDI_BUF_TRANS_C_S1T1 => 16#06_4ec8# / Register_Width,
1174 DDI_BUF_TRANS_C_S1T2 => 16#06_4ecc# / Register_Width,
1175 DDI_BUF_TRANS_C_S2T1 => 16#06_4ed0# / Register_Width,
1176 DDI_BUF_TRANS_C_S2T2 => 16#06_4ed4# / Register_Width,
1177 DDI_BUF_TRANS_C_S3T1 => 16#06_4ed8# / Register_Width,
1178 DDI_BUF_TRANS_C_S3T2 => 16#06_4edc# / Register_Width,
1179 DDI_BUF_TRANS_C_S4T1 => 16#06_4ee0# / Register_Width,
1180 DDI_BUF_TRANS_C_S4T2 => 16#06_4ee4# / Register_Width,
1181 DDI_BUF_TRANS_C_S5T1 => 16#06_4ee8# / Register_Width,
1182 DDI_BUF_TRANS_C_S5T2 => 16#06_4eec# / Register_Width,
1183 DDI_BUF_TRANS_C_S6T1 => 16#06_4ef0# / Register_Width,
1184 DDI_BUF_TRANS_C_S6T2 => 16#06_4ef4# / Register_Width,
1185 DDI_BUF_TRANS_C_S7T1 => 16#06_4ef8# / Register_Width,
1186 DDI_BUF_TRANS_C_S7T2 => 16#06_4efc# / Register_Width,
1187 DDI_BUF_TRANS_C_S8T1 => 16#06_4f00# / Register_Width,
1188 DDI_BUF_TRANS_C_S8T2 => 16#06_4f04# / Register_Width,
1189 DDI_BUF_TRANS_C_S9T1 => 16#06_4f08# / Register_Width,
1190 DDI_BUF_TRANS_C_S9T2 => 16#06_4f0c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1191 DDI_AUX_CTL_C => 16#06_4210# / Register_Width,
1192 DDI_AUX_DATA_C_1 => 16#06_4214# / Register_Width,
1193 DDI_AUX_DATA_C_2 => 16#06_4218# / Register_Width,
1194 DDI_AUX_DATA_C_3 => 16#06_421c# / Register_Width,
1195 DDI_AUX_DATA_C_4 => 16#06_4220# / Register_Width,
1196 DDI_AUX_DATA_C_5 => 16#06_4224# / Register_Width,
1197 DDI_AUX_MUTEX_C => 16#06_422c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1198
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1199 DDI_BUF_CTL_D => 16#06_4300# / Register_Width, -- aliased by GMCH_DP_D
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1200 DDI_BUF_TRANS_D_S0T1 => 16#06_4f20# / Register_Width,
1201 DDI_BUF_TRANS_D_S0T2 => 16#06_4f24# / Register_Width,
1202 DDI_BUF_TRANS_D_S1T1 => 16#06_4f28# / Register_Width,
1203 DDI_BUF_TRANS_D_S1T2 => 16#06_4f2c# / Register_Width,
1204 DDI_BUF_TRANS_D_S2T1 => 16#06_4f30# / Register_Width,
1205 DDI_BUF_TRANS_D_S2T2 => 16#06_4f34# / Register_Width,
1206 DDI_BUF_TRANS_D_S3T1 => 16#06_4f38# / Register_Width,
1207 DDI_BUF_TRANS_D_S3T2 => 16#06_4f3c# / Register_Width,
1208 DDI_BUF_TRANS_D_S4T1 => 16#06_4f40# / Register_Width,
1209 DDI_BUF_TRANS_D_S4T2 => 16#06_4f44# / Register_Width,
1210 DDI_BUF_TRANS_D_S5T1 => 16#06_4f48# / Register_Width,
1211 DDI_BUF_TRANS_D_S5T2 => 16#06_4f4c# / Register_Width,
1212 DDI_BUF_TRANS_D_S6T1 => 16#06_4f50# / Register_Width,
1213 DDI_BUF_TRANS_D_S6T2 => 16#06_4f54# / Register_Width,
1214 DDI_BUF_TRANS_D_S7T1 => 16#06_4f58# / Register_Width,
1215 DDI_BUF_TRANS_D_S7T2 => 16#06_4f5c# / Register_Width,
1216 DDI_BUF_TRANS_D_S8T1 => 16#06_4f60# / Register_Width,
1217 DDI_BUF_TRANS_D_S8T2 => 16#06_4f64# / Register_Width,
1218 DDI_BUF_TRANS_D_S9T1 => 16#06_4f68# / Register_Width,
1219 DDI_BUF_TRANS_D_S9T2 => 16#06_4f6c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1220 DDI_AUX_CTL_D => 16#06_4310# / Register_Width,
1221 DDI_AUX_DATA_D_1 => 16#06_4314# / Register_Width,
1222 DDI_AUX_DATA_D_2 => 16#06_4318# / Register_Width,
1223 DDI_AUX_DATA_D_3 => 16#06_431c# / Register_Width,
1224 DDI_AUX_DATA_D_4 => 16#06_4320# / Register_Width,
1225 DDI_AUX_DATA_D_5 => 16#06_4324# / Register_Width,
1226 DDI_AUX_MUTEX_D => 16#06_432c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1227
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1228 DDI_BUF_CTL_E => 16#06_4400# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1229 DDI_BUF_TRANS_E_S0T1 => 16#06_4f80# / Register_Width,
1230 DDI_BUF_TRANS_E_S0T2 => 16#06_4f84# / Register_Width,
1231 DDI_BUF_TRANS_E_S1T1 => 16#06_4f88# / Register_Width,
1232 DDI_BUF_TRANS_E_S1T2 => 16#06_4f8c# / Register_Width,
1233 DDI_BUF_TRANS_E_S2T1 => 16#06_4f90# / Register_Width,
1234 DDI_BUF_TRANS_E_S2T2 => 16#06_4f94# / Register_Width,
1235 DDI_BUF_TRANS_E_S3T1 => 16#06_4f98# / Register_Width,
1236 DDI_BUF_TRANS_E_S3T2 => 16#06_4f9c# / Register_Width,
1237 DDI_BUF_TRANS_E_S4T1 => 16#06_4fa0# / Register_Width,
1238 DDI_BUF_TRANS_E_S4T2 => 16#06_4fa4# / Register_Width,
1239 DDI_BUF_TRANS_E_S5T1 => 16#06_4fa8# / Register_Width,
1240 DDI_BUF_TRANS_E_S5T2 => 16#06_4fac# / Register_Width,
1241 DDI_BUF_TRANS_E_S6T1 => 16#06_4fb0# / Register_Width,
1242 DDI_BUF_TRANS_E_S6T2 => 16#06_4fb4# / Register_Width,
1243 DDI_BUF_TRANS_E_S7T1 => 16#06_4fb8# / Register_Width,
1244 DDI_BUF_TRANS_E_S7T2 => 16#06_4fbc# / Register_Width,
1245 DDI_BUF_TRANS_E_S8T1 => 16#06_4fc0# / Register_Width,
1246 DDI_BUF_TRANS_E_S8T2 => 16#06_4fc4# / Register_Width,
1247 DDI_BUF_TRANS_E_S9T1 => 16#06_4fc8# / Register_Width,
1248 DDI_BUF_TRANS_E_S9T2 => 16#06_4fcc# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1249 DP_TP_CTL_A => 16#06_4040# / Register_Width,
1250 DP_TP_CTL_B => 16#06_4140# / Register_Width,
1251 DP_TP_CTL_C => 16#06_4240# / Register_Width,
1252 DP_TP_CTL_D => 16#06_4340# / Register_Width,
1253 DP_TP_CTL_E => 16#06_4440# / Register_Width,
1254 DP_TP_STATUS_B => 16#06_4144# / Register_Width,
1255 DP_TP_STATUS_C => 16#06_4244# / Register_Width,
1256 DP_TP_STATUS_D => 16#06_4344# / Register_Width,
1257 DP_TP_STATUS_E => 16#06_4444# / Register_Width,
1258 PORT_CLK_SEL_DDIA => 16#04_6100# / Register_Width,
1259 PORT_CLK_SEL_DDIB => 16#04_6104# / Register_Width,
1260 PORT_CLK_SEL_DDIC => 16#04_6108# / Register_Width,
1261 PORT_CLK_SEL_DDID => 16#04_610c# / Register_Width,
1262 PORT_CLK_SEL_DDIE => 16#04_6110# / Register_Width,
1263
Nico Huber58afc202017-06-12 21:34:55 +0200[diff] [blame]1264 -- Skylake I_boost configuration
1265 DISPIO_CR_TX_BMU_CR0 => 16#06_c00c# / Register_Width,
1266
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1267 -- Skylake DPLL registers
1268 DPLL1_CFGR1 => 16#06_c040# / Register_Width,
1269 DPLL1_CFGR2 => 16#06_c044# / Register_Width,
1270 DPLL2_CFGR1 => 16#06_c048# / Register_Width,
1271 DPLL2_CFGR2 => 16#06_c04c# / Register_Width,
1272 DPLL3_CFGR1 => 16#06_c050# / Register_Width,
1273 DPLL3_CFGR2 => 16#06_c054# / Register_Width,
1274 DPLL_CTRL1 => 16#06_c058# / Register_Width,
1275 DPLL_CTRL2 => 16#06_c05c# / Register_Width,
1276 DPLL_STATUS => 16#06_c060# / Register_Width,
1277
1278 -- CD CLK register
1279 CDCLK_CTL => 16#04_6000# / Register_Width,
1280
1281 -- Skylake LCPLL registers
1282 LCPLL1_CTL => 16#04_6010# / Register_Width,
1283 LCPLL2_CTL => 16#04_6014# / Register_Width,
1284
1285 -- SPLL register
1286 SPLL_CTL => 16#04_6020# / Register_Width,
1287
1288 -- WRPLL registers
1289 WRPLL_CTL_1 => 16#04_6040# / Register_Width,
1290 WRPLL_CTL_2 => 16#04_6060# / Register_Width,
1291
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]1292 -- Broxton Display Engine PLL registers
1293 BXT_DE_PLL_CTL => 16#06_d000# / Register_Width,
1294 BXT_DE_PLL_ENABLE => 16#04_6070# / Register_Width,
1295
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1296 -- Broxton DDI PHY PLL registers
1297 BXT_PORT_PLL_ENABLE_A => 16#04_6074# / Register_Width,
1298 BXT_PORT_PLL_ENABLE_B => 16#04_6078# / Register_Width,
1299 BXT_PORT_PLL_ENABLE_C => 16#04_607c# / Register_Width,
1300 BXT_PORT_PLL_EBB_0_A => 16#16_2034# / Register_Width,
1301 BXT_PORT_PLL_EBB_4_A => 16#16_2038# / Register_Width,
1302 BXT_PORT_PLL_0_A => 16#16_2100# / Register_Width,
1303 BXT_PORT_PLL_1_A => 16#16_2104# / Register_Width,
1304 BXT_PORT_PLL_2_A => 16#16_2108# / Register_Width,
1305 BXT_PORT_PLL_3_A => 16#16_210c# / Register_Width,
1306 BXT_PORT_PLL_6_A => 16#16_2118# / Register_Width,
1307 BXT_PORT_PLL_8_A => 16#16_2120# / Register_Width,
1308 BXT_PORT_PLL_9_A => 16#16_2124# / Register_Width,
1309 BXT_PORT_PLL_10_A => 16#16_2128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1310 BXT_PORT_PLL_EBB_0_B => 16#06_c034# / Register_Width,
1311 BXT_PORT_PLL_EBB_4_B => 16#06_c038# / Register_Width,
1312 BXT_PORT_PLL_0_B => 16#06_c100# / Register_Width,
1313 BXT_PORT_PLL_1_B => 16#06_c104# / Register_Width,
1314 BXT_PORT_PLL_2_B => 16#06_c108# / Register_Width,
1315 BXT_PORT_PLL_3_B => 16#06_c10c# / Register_Width,
1316 BXT_PORT_PLL_6_B => 16#06_c118# / Register_Width,
1317 BXT_PORT_PLL_8_B => 16#06_c120# / Register_Width,
1318 BXT_PORT_PLL_9_B => 16#06_c124# / Register_Width,
1319 BXT_PORT_PLL_10_B => 16#06_c128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1320 BXT_PORT_PLL_EBB_0_C => 16#06_c340# / Register_Width,
1321 BXT_PORT_PLL_EBB_4_C => 16#06_c344# / Register_Width,
1322 BXT_PORT_PLL_0_C => 16#06_c380# / Register_Width,
1323 BXT_PORT_PLL_1_C => 16#06_c384# / Register_Width,
1324 BXT_PORT_PLL_2_C => 16#06_c388# / Register_Width,
1325 BXT_PORT_PLL_3_C => 16#06_c38c# / Register_Width,
1326 BXT_PORT_PLL_6_C => 16#06_c398# / Register_Width,
1327 BXT_PORT_PLL_8_C => 16#06_c3a0# / Register_Width,
1328 BXT_PORT_PLL_9_C => 16#06_c3a4# / Register_Width,
1329 BXT_PORT_PLL_10_C => 16#06_c3a8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1330
1331 -- Broxton DDI PHY PCS? registers
1332 BXT_PORT_PCS_DW10_01_A => 16#16_2428# / Register_Width,
1333 BXT_PORT_PCS_DW12_01_A => 16#16_2430# / Register_Width,
1334 BXT_PORT_PCS_DW10_GRP_A => 16#16_2c28# / Register_Width,
1335 BXT_PORT_PCS_DW12_GRP_A => 16#16_2c30# / Register_Width,
1336 BXT_PORT_PCS_DW10_01_B => 16#06_c428# / Register_Width,
1337 BXT_PORT_PCS_DW12_01_B => 16#06_c430# / Register_Width,
1338 BXT_PORT_PCS_DW10_01_C => 16#06_c828# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1339 BXT_PORT_PCS_DW12_01_C => 16#06_c830# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1340 BXT_PORT_PCS_DW10_GRP_B => 16#06_cc28# / Register_Width,
1341 BXT_PORT_PCS_DW12_GRP_B => 16#06_cc30# / Register_Width,
1342 BXT_PORT_PCS_DW10_GRP_C => 16#06_ce28# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1343 BXT_PORT_PCS_DW12_GRP_C => 16#06_ce30# / Register_Width,
1344
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]1345 -- Broxton DDI PHY registers
1346 BXT_P_CR_GT_DISP_PWRON => 16#13_8090# / Register_Width,
1347 BXT_PHY_CTL_A => 16#06_4c00# / Register_Width,
1348 BXT_PHY_CTL_B => 16#06_4c10# / Register_Width,
1349 BXT_PHY_CTL_C => 16#06_4c20# / Register_Width,
1350 BXT_PHY_CTL_FAM_EDP => 16#06_4c80# / Register_Width,
1351 BXT_PHY_CTL_FAM_DDI => 16#06_4c90# / Register_Width,
1352
1353 -- Broxton DDI PHY common lane registers
1354 BXT_PORT_CL1CM_DW0_A => 16#16_2000# / Register_Width,
1355 BXT_PORT_CL1CM_DW0_BC => 16#06_c000# / Register_Width,
1356 BXT_PORT_CL1CM_DW9_A => 16#16_2024# / Register_Width,
1357 BXT_PORT_CL1CM_DW9_BC => 16#06_c024# / Register_Width,
1358 BXT_PORT_CL1CM_DW10_A => 16#16_2028# / Register_Width,
1359 BXT_PORT_CL1CM_DW10_BC => 16#06_c028# / Register_Width,
1360 BXT_PORT_CL1CM_DW28_A => 16#16_2070# / Register_Width,
1361 BXT_PORT_CL1CM_DW28_BC => 16#06_c070# / Register_Width,
1362 BXT_PORT_CL1CM_DW30_A => 16#16_2078# / Register_Width,
1363 BXT_PORT_CL1CM_DW30_BC => 16#06_c078# / Register_Width,
1364 BXT_PORT_CL2CM_DW6_BC => 16#06_c358# / Register_Width,
1365
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1366 -- Broxton DDI PHY TX lane registers
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1367 BXT_PORT_TX_DW2_LN0_A => 16#16_2508# / Register_Width,
1368 BXT_PORT_TX_DW3_LN0_A => 16#16_250c# / Register_Width,
1369 BXT_PORT_TX_DW4_LN0_A => 16#16_2510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1370 BXT_PORT_TX_DW14_LN0_A => 16#16_2538# / Register_Width,
1371 BXT_PORT_TX_DW14_LN1_A => 16#16_25b8# / Register_Width,
1372 BXT_PORT_TX_DW14_LN2_A => 16#16_2738# / Register_Width,
1373 BXT_PORT_TX_DW14_LN3_A => 16#16_27b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1374 BXT_PORT_TX_DW2_GRP_A => 16#16_2d08# / Register_Width,
1375 BXT_PORT_TX_DW3_GRP_A => 16#16_2d0c# / Register_Width,
1376 BXT_PORT_TX_DW4_GRP_A => 16#16_2d10# / Register_Width,
1377 BXT_PORT_TX_DW2_LN0_B => 16#06_c508# / Register_Width,
1378 BXT_PORT_TX_DW3_LN0_B => 16#06_c50c# / Register_Width,
1379 BXT_PORT_TX_DW4_LN0_B => 16#06_c510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1380 BXT_PORT_TX_DW14_LN0_B => 16#06_c538# / Register_Width,
1381 BXT_PORT_TX_DW14_LN1_B => 16#06_c5b8# / Register_Width,
1382 BXT_PORT_TX_DW14_LN2_B => 16#06_c738# / Register_Width,
1383 BXT_PORT_TX_DW14_LN3_B => 16#06_c7b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1384 BXT_PORT_TX_DW2_GRP_B => 16#06_cd08# / Register_Width,
1385 BXT_PORT_TX_DW3_GRP_B => 16#06_cd0c# / Register_Width,
1386 BXT_PORT_TX_DW4_GRP_B => 16#06_cd10# / Register_Width,
1387 BXT_PORT_TX_DW2_LN0_C => 16#06_c908# / Register_Width,
1388 BXT_PORT_TX_DW3_LN0_C => 16#06_c90c# / Register_Width,
1389 BXT_PORT_TX_DW4_LN0_C => 16#06_c910# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1390 BXT_PORT_TX_DW14_LN0_C => 16#06_c938# / Register_Width,
1391 BXT_PORT_TX_DW14_LN1_C => 16#06_c9b8# / Register_Width,
1392 BXT_PORT_TX_DW14_LN2_C => 16#06_cb38# / Register_Width,
1393 BXT_PORT_TX_DW14_LN3_C => 16#06_cbb8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1394 BXT_PORT_TX_DW2_GRP_C => 16#06_cf08# / Register_Width,
1395 BXT_PORT_TX_DW3_GRP_C => 16#06_cf0c# / Register_Width,
1396 BXT_PORT_TX_DW4_GRP_C => 16#06_cf10# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1397
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]1398 -- Broxton DDI PHY ref registers
1399 BXT_PORT_REF_DW3_A => 16#16_218c# / Register_Width,
1400 BXT_PORT_REF_DW3_BC => 16#06_c18c# / Register_Width,
1401 BXT_PORT_REF_DW6_A => 16#16_2198# / Register_Width,
1402 BXT_PORT_REF_DW6_BC => 16#06_c198# / Register_Width,
1403 BXT_PORT_REF_DW8_A => 16#16_21a0# / Register_Width,
1404 BXT_PORT_REF_DW8_BC => 16#06_c1a0# / Register_Width,
1405
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1406 -- Power Down Well registers
1407 PWR_WELL_CTL_BIOS => 16#04_5400# / Register_Width,
1408 PWR_WELL_CTL_DRIVER => 16#04_5404# / Register_Width,
1409 PWR_WELL_CTL_KVMR => 16#04_5408# / Register_Width,
1410 PWR_WELL_CTL_DEBUG => 16#04_540c# / Register_Width,
1411 PWR_WELL_CTL5 => 16#04_5410# / Register_Width,
1412 PWR_WELL_CTL6 => 16#04_5414# / Register_Width,
1413
1414 -- class Panel registers
Arthur Heymanse87d0d12018-03-28 17:02:49 +0200[diff] [blame]1415 GMCH_PP_STATUS => 16#06_1200# / Register_Width,
1416 GMCH_PP_CONTROL => 16#06_1204# / Register_Width,
1417 GMCH_PP_ON_DELAYS => 16#06_1208# / Register_Width,
1418 GMCH_PP_OFF_DELAYS => 16#06_120c# / Register_Width,
1419 GMCH_PP_DIVISOR => 16#06_1210# / Register_Width,
Arthur Heymansd5198442018-03-28 17:05:12 +0200[diff] [blame]1420 GMCH_PFIT_CONTROL => 16#06_1230# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1421 PCH_PP_STATUS => 16#0c_7200# / Register_Width,
1422 PCH_PP_CONTROL => 16#0c_7204# / Register_Width,
1423 PCH_PP_ON_DELAYS => 16#0c_7208# / Register_Width,
1424 PCH_PP_OFF_DELAYS => 16#0c_720c# / Register_Width,
1425 PCH_PP_DIVISOR => 16#0c_7210# / Register_Width,
1426 BLC_PWM_CPU_CTL => 16#04_8254# / Register_Width,
1427 BLC_PWM_PCH_CTL2 => 16#0c_8254# / Register_Width,
1428
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1429 -- GMCH LVDS Connector Registers
1430 GMCH_LVDS => 16#06_1180# / Register_Width,
1431
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1432 -- PCH LVDS Connector Registers
1433 PCH_LVDS => 16#0e_1180# / Register_Width,
1434
1435 -- PCH ADPA Connector Registers
1436 PCH_ADPA => 16#0e_1100# / Register_Width,
1437
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1438 -- GMCH DVOB Connector Registers
1439 GMCH_SDVOB => 16#06_1140# / Register_Width,
1440
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1441 -- PCH HDMIB Connector Registers
1442 PCH_HDMIB => 16#0e_1140# / Register_Width,
1443
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1444 -- GMCH DVOC Connector Registers
1445 GMCH_SDVOC => 16#06_1160# / Register_Width,
1446
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1447 -- PCH HDMIC Connector Registers
1448 PCH_HDMIC => 16#0e_1150# / Register_Width,
1449
1450 -- PCH HDMID Connector Registers
1451 PCH_HDMID => 16#0e_1160# / Register_Width,
1452
1453 -- Intel Registers
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]1454 CPU_VGACNTRL => 16#04_1000# / Register_Width,
1455 GMCH_VGACNTRL => 16#07_1400# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1456 FUSE_STATUS => 16#04_2000# / Register_Width,
1457 FBA_CFB_BASE => 16#04_3200# / Register_Width,
1458 IPS_CTL => 16#04_3408# / Register_Width,
1459 ARB_CTL => 16#04_5000# / Register_Width,
1460 DBUF_CTL => 16#04_5008# / Register_Width,
1461 NDE_RSTWRN_OPT => 16#04_6408# / Register_Width,
1462 PCH_DREF_CONTROL => 16#0c_6200# / Register_Width,
1463 BLC_PWM_PCH_CTL1 => 16#0c_8250# / Register_Width,
1464 BLC_PWM_CPU_CTL2 => 16#04_8250# / Register_Width,
1465 PCH_DPLL_SEL => 16#0c_7000# / Register_Width,
1466 GT_MAILBOX => 16#13_8124# / Register_Width,
1467 GT_MAILBOX_DATA => 16#13_8128# / Register_Width,
1468 GT_MAILBOX_DATA_1 => 16#13_812c# / Register_Width,
1469
1470 PCH_DP_B => 16#0e_4100# / Register_Width,
1471 PCH_DP_AUX_CTL_B => 16#0e_4110# / Register_Width,
1472 PCH_DP_AUX_DATA_B_1 => 16#0e_4114# / Register_Width,
1473 PCH_DP_AUX_DATA_B_2 => 16#0e_4118# / Register_Width,
1474 PCH_DP_AUX_DATA_B_3 => 16#0e_411c# / Register_Width,
1475 PCH_DP_AUX_DATA_B_4 => 16#0e_4120# / Register_Width,
1476 PCH_DP_AUX_DATA_B_5 => 16#0e_4124# / Register_Width,
1477 PCH_DP_C => 16#0e_4200# / Register_Width,
1478 PCH_DP_AUX_CTL_C => 16#0e_4210# / Register_Width,
1479 PCH_DP_AUX_DATA_C_1 => 16#0e_4214# / Register_Width,
1480 PCH_DP_AUX_DATA_C_2 => 16#0e_4218# / Register_Width,
1481 PCH_DP_AUX_DATA_C_3 => 16#0e_421c# / Register_Width,
1482 PCH_DP_AUX_DATA_C_4 => 16#0e_4220# / Register_Width,
1483 PCH_DP_AUX_DATA_C_5 => 16#0e_4224# / Register_Width,
1484 PCH_DP_D => 16#0e_4300# / Register_Width,
1485 PCH_DP_AUX_CTL_D => 16#0e_4310# / Register_Width,
1486 PCH_DP_AUX_DATA_D_1 => 16#0e_4314# / Register_Width,
1487 PCH_DP_AUX_DATA_D_2 => 16#0e_4318# / Register_Width,
1488 PCH_DP_AUX_DATA_D_3 => 16#0e_431c# / Register_Width,
1489 PCH_DP_AUX_DATA_D_4 => 16#0e_4320# / Register_Width,
1490 PCH_DP_AUX_DATA_D_5 => 16#0e_4324# / Register_Width,
1491
1492 -- watermark registers
1493 WM1_LP_ILK => 16#04_5108# / Register_Width,
1494 WM2_LP_ILK => 16#04_510c# / Register_Width,
1495 WM3_LP_ILK => 16#04_5110# / Register_Width,
1496
1497 -- audio VID/DID
1498 AUD_VID_DID => 16#06_5020# / Register_Width,
1499 PCH_AUD_VID_DID => 16#0e_5020# / Register_Width,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1500 G4X_AUD_VID_DID => 16#06_2020# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1501
1502 -- interrupt registers
1503 DEISR => 16#04_4000# / Register_Width,
1504 DEIMR => 16#04_4004# / Register_Width,
1505 DEIIR => 16#04_4008# / Register_Width,
1506 DEIER => 16#04_400c# / Register_Width,
1507 GTISR => 16#04_4010# / Register_Width,
1508 GTIMR => 16#04_4014# / Register_Width,
1509 GTIIR => 16#04_4018# / Register_Width,
1510 GTIER => 16#04_401c# / Register_Width,
1511 SDEISR => 16#0c_4000# / Register_Width,
1512 SDEIMR => 16#0c_4004# / Register_Width,
1513 SDEIIR => 16#0c_4008# / Register_Width,
1514 SDEIER => 16#0c_400c# / Register_Width,
1515
1516 -- I2C stuff
Arthur Heymans229ed1c2018-03-28 16:45:43 +0200[diff] [blame]1517 GMCH_GMBUS0 => 16#00_5100# / Register_Width,
1518 GMCH_GMBUS1 => 16#00_5104# / Register_Width,
1519 GMCH_GMBUS2 => 16#00_5108# / Register_Width,
1520 GMCH_GMBUS3 => 16#00_510c# / Register_Width,
1521 GMCH_GMBUS4 => 16#00_5110# / Register_Width,
1522 GMCH_GMBUS5 => 16#00_5120# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1523 PCH_GMBUS0 => 16#0c_5100# / Register_Width,
1524 PCH_GMBUS1 => 16#0c_5104# / Register_Width,
1525 PCH_GMBUS2 => 16#0c_5108# / Register_Width,
1526 PCH_GMBUS3 => 16#0c_510c# / Register_Width,
1527 PCH_GMBUS4 => 16#0c_5110# / Register_Width,
1528 PCH_GMBUS5 => 16#0c_5120# / Register_Width,
1529
1530 -- clock gating -- maybe have to touch this
1531 DSPCLK_GATE_D => 16#04_2020# / Register_Width,
1532 PCH_FDI_CHICKEN_B_C => 16#0c_2000# / Register_Width,
1533 PCH_DSPCLK_GATE_D => 16#0c_2020# / Register_Width,
1534
1535 -- hotplug and initial detection
1536 HOTPLUG_CTL => 16#04_4030# / Register_Width,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1537 PORT_HOTPLUG_EN => 16#06_1110# / Register_Width,
1538 PORT_HOTPLUG_STAT => 16#06_1114# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1539 SHOTPLUG_CTL => 16#0c_4030# / Register_Width,
1540 SFUSE_STRAP => 16#0c_2014# / Register_Width,
1541
1542 -- Render Engine Command Streamer
1543 ARB_MODE => 16#00_4030# / Register_Width,
1544 HWS_PGA => 16#00_4080# / Register_Width,
1545 RCS_RING_BUFFER_TAIL => 16#00_2030# / Register_Width,
1546 VCS_RING_BUFFER_TAIL => 16#01_2030# / Register_Width,
1547 BCS_RING_BUFFER_TAIL => 16#02_2030# / Register_Width,
1548 RCS_RING_BUFFER_HEAD => 16#00_2034# / Register_Width,
1549 VCS_RING_BUFFER_HEAD => 16#01_2034# / Register_Width,
1550 BCS_RING_BUFFER_HEAD => 16#02_2034# / Register_Width,
1551 RCS_RING_BUFFER_STRT => 16#00_2038# / Register_Width,
1552 VCS_RING_BUFFER_STRT => 16#01_2038# / Register_Width,
1553 BCS_RING_BUFFER_STRT => 16#02_2038# / Register_Width,
1554 RCS_RING_BUFFER_CTL => 16#00_203c# / Register_Width,
1555 VCS_RING_BUFFER_CTL => 16#01_203c# / Register_Width,
1556 BCS_RING_BUFFER_CTL => 16#02_203c# / Register_Width,
1557 MI_MODE => 16#00_209c# / Register_Width,
1558 INSTPM => 16#00_20c0# / Register_Width,
1559 GAB_CTL_REG => 16#02_4000# / Register_Width,
1560 PP_DCLV_HIGH => 16#00_2220# / Register_Width,
1561 PP_DCLV_LOW => 16#00_2228# / Register_Width,
1562 VCS_PP_DCLV_HIGH => 16#01_2220# / Register_Width,
1563 VCS_PP_DCLV_LOW => 16#01_2228# / Register_Width,
1564 BCS_PP_DCLV_HIGH => 16#02_2220# / Register_Width,
1565 BCS_PP_DCLV_LOW => 16#02_2228# / Register_Width,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1566 ILK_DISPLAY_CHICKEN2 => 16#04_2004# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1567 UCGCTL1 => 16#00_9400# / Register_Width,
1568 UCGCTL2 => 16#00_9404# / Register_Width,
1569 MBCTL => 16#00_907c# / Register_Width,
1570 HWSTAM => 16#00_2098# / Register_Width,
1571 VCS_HWSTAM => 16#01_2098# / Register_Width,
1572 BCS_HWSTAM => 16#02_2098# / Register_Width,
1573 IIR => 16#04_4028# / Register_Width,
1574 PIPE_FRMCNT_A => 16#07_0040# / Register_Width,
1575 PIPE_FRMCNT_B => 16#07_1040# / Register_Width,
1576 PIPE_FRMCNT_C => 16#07_2040# / Register_Width,
1577 FBC_CTL => 16#04_3208# / Register_Width,
1578 PIPE_VSYNCSHIFT_A => 16#06_0028# / Register_Width,
1579 PIPE_VSYNCSHIFT_B => 16#06_1028# / Register_Width,
1580 PIPE_VSYNCSHIFT_C => 16#06_2028# / Register_Width,
1581 WM_PIPE_A => 16#04_5100# / Register_Width,
1582 WM_PIPE_B => 16#04_5104# / Register_Width,
1583 WM_PIPE_C => 16#04_5200# / Register_Width,
1584 PIPE_SCANLINE_A => 16#07_0000# / Register_Width,
1585 PIPE_SCANLINE_B => 16#07_1000# / Register_Width,
1586 PIPE_SCANLINE_C => 16#07_2000# / Register_Width,
1587 GFX_MODE => 16#00_2520# / Register_Width,
1588 CACHE_MODE_0 => 16#00_2120# / Register_Width,
1589 SLEEP_PSMI_CONTROL => 16#01_2050# / Register_Width,
1590 CTX_SIZE => 16#00_21a0# / Register_Width,
1591 GAC_ECO_BITS => 16#01_4090# / Register_Width,
1592 GAM_ECOCHK => 16#00_4090# / Register_Width,
1593 QUIRK_02084 => 16#00_2084# / Register_Width,
1594 QUIRK_02090 => 16#00_2090# / Register_Width,
1595 GT_MODE => 16#00_20d0# / Register_Width,
1596 QUIRK_F0060 => 16#0f_0060# / Register_Width,
1597 QUIRK_F1060 => 16#0f_1060# / Register_Width,
1598 QUIRK_F2060 => 16#0f_2060# / Register_Width,
1599 AUD_CNTRL_ST2 => 16#0e_50c0# / Register_Width,
1600 AUD_CNTL_ST_A => 16#0e_50b4# / Register_Width,
1601 AUD_CNTL_ST_B => 16#0e_51b4# / Register_Width,
1602 AUD_CNTL_ST_C => 16#0e_52b4# / Register_Width,
1603 AUD_HDMIW_HDMIEDID_A => 16#0e_5050# / Register_Width,
1604 AUD_HDMIW_HDMIEDID_B => 16#0e_5150# / Register_Width,
1605 AUD_HDMIW_HDMIEDID_C => 16#0e_5250# / Register_Width,
1606 AUD_CONFIG_A => 16#0e_5000# / Register_Width,
1607 AUD_CONFIG_B => 16#0e_5100# / Register_Width,
1608 AUD_CONFIG_C => 16#0e_5200# / Register_Width,
1609 TRANS_DP_CTL_A => 16#0e_0300# / Register_Width,
1610 TRANS_DP_CTL_B => 16#0e_1300# / Register_Width,
1611 TRANS_DP_CTL_C => 16#0e_2300# / Register_Width,
1612 TRANS_VSYNCSHIFT_A => 16#0e_0028# / Register_Width,
1613 TRANS_VSYNCSHIFT_B => 16#0e_1028# / Register_Width,
1614 TRANS_VSYNCSHIFT_C => 16#0e_2028# / Register_Width,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]1615 PCH_RAWCLK_FREQ => 16#0c_6204# / Register_Width,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1616 QUIRK_C2004 => 16#0c_2004# / Register_Width,
1617
1618 -- MCHBAR Mirror
1619
1620 GMCH_CLKCFG => 16#01_0c00# / Register_Width);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1621
1622 subtype Registers_Index is Registers_Invalid_Index range
1623 Registers_Invalid_Index'Succ (Invalid_Register) ..
1624 Registers_Invalid_Index'Last;
1625
1626 -- aliased registers
1627 DP_CTL_A : constant Registers_Index := DDI_BUF_CTL_A;
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1628 GMCH_DP_B : constant Registers_Index := DDI_BUF_CTL_B;
1629 GMCH_DP_C : constant Registers_Index := DDI_BUF_CTL_C;
1630 GMCH_DP_D : constant Registers_Index := DDI_BUF_CTL_D;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1631 DP_AUX_CTL_A : constant Registers_Index := DDI_AUX_CTL_A;
1632 DP_AUX_DATA_A_1 : constant Registers_Index := DDI_AUX_DATA_A_1;
1633 DP_AUX_DATA_A_2 : constant Registers_Index := DDI_AUX_DATA_A_2;
1634 DP_AUX_DATA_A_3 : constant Registers_Index := DDI_AUX_DATA_A_3;
1635 DP_AUX_DATA_A_4 : constant Registers_Index := DDI_AUX_DATA_A_4;
1636 DP_AUX_DATA_A_5 : constant Registers_Index := DDI_AUX_DATA_A_5;
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1637 ILK_DISPLAY_CHICKEN1 : constant Registers_Index := FUSE_STATUS;
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1638 GMCH_ADPA : constant Registers_Index := FDI_TX_CTL_B;
1639 GMCH_HDMIB : constant Registers_Index := GMCH_SDVOB;
1640 GMCH_HDMIC : constant Registers_Index := GMCH_SDVOC;
Nico Huber75a707f2018-06-18 16:28:33 +0200[diff] [blame^]1641 CURACNTR : constant Registers_Index := CUR_CTL_A;
1642 CURABASE : constant Registers_Index := CUR_BASE_A;
1643 CURAPOS : constant Registers_Index := CUR_POS_A;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1644
1645 ---------------------------------------------------------------------------
1646
1647 Default_Timeout_MS : constant := 10;
1648
1649 ---------------------------------------------------------------------------
1650
1651 procedure Posting_Read
1652 (Register : in Registers_Index)
1653 with
1654 Global => (In_Out => Register_State),
1655 Depends => (Register_State =>+ (Register)),
1656 Pre => True,
1657 Post => True;
1658
1659 pragma Warnings (GNATprove, Off, "unused variable ""Verbose""",
1660 Reason => "Only used on debugging path");
1661 procedure Read
1662 (Register : in Registers_Index;
1663 Value : out Word32;
1664 Verbose : in Boolean := True)
1665 with
1666 Global => (In_Out => Register_State),
1667 Depends => ((Value, Register_State) => (Register, Register_State),
1668 null => Verbose),
1669 Pre => True,
1670 Post => True;
1671 pragma Warnings (GNATprove, On, "unused variable ""Verbose""");
1672
1673 procedure Write
1674 (Register : Registers_Index;
1675 Value : Word32)
1676 with
1677 Global => (In_Out => Register_State),
1678 Depends => (Register_State => (Register, Register_State, Value)),
1679 Pre => True,
1680 Post => True;
1681
1682 procedure Is_Set_Mask
1683 (Register : in Registers_Index;
1684 Mask : in Word32;
1685 Result : out Boolean);
1686
1687 pragma Warnings (GNATprove, Off, "unused initial value of ""Verbose""",
1688 Reason => "Only used on debugging path");
Nico Huberbcb2c472017-02-02 16:39:26 +0100[diff] [blame]1689 procedure Wait
1690 (Register : Registers_Index;
1691 Mask : Word32;
1692 Value : Word32;
1693 TOut_MS : Natural := Default_Timeout_MS;
1694 Verbose : Boolean := False);
1695
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1696 procedure Wait_Set_Mask
1697 (Register : Registers_Index;
1698 Mask : Word32;
1699 TOut_MS : Natural := Default_Timeout_MS;
1700 Verbose : Boolean := False);
1701
1702 procedure Wait_Unset_Mask
1703 (Register : Registers_Index;
1704 Mask : Word32;
1705 TOut_MS : Natural := Default_Timeout_MS;
1706 Verbose : Boolean := False);
1707 pragma Warnings (GNATprove, On, "unused initial value of ""Verbose""");
1708
1709 procedure Set_Mask
1710 (Register : Registers_Index;
1711 Mask : Word32);
1712
1713 procedure Unset_Mask
1714 (Register : Registers_Index;
1715 Mask : Word32);
1716
1717 procedure Unset_And_Set_Mask
1718 (Register : Registers_Index;
1719 Mask_Unset : Word32;
1720 Mask_Set : Word32);
1721
Nico Huber17d64b62017-07-15 20:51:25 +0200[diff] [blame]1722 procedure Clear_Fences;
1723
Nico Huberb03c8f12017-08-25 13:29:08 +0200[diff] [blame]1724 procedure Add_Fence
1725 (First_Page : in GTT_Range;
1726 Last_Page : in GTT_Range;
1727 Tiling : in XY_Tiling;
1728 Pitch : in Natural;
1729 Success : out Boolean);
1730
1731 procedure Remove_Fence (First_Page, Last_Page : GTT_Range);
1732
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]1733 pragma Warnings (GNATprove, Off, "no check message justified by this",
1734 Reason => "see Annotate aspects.");
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1735 procedure Write_GTT
1736 (GTT_Page : GTT_Range;
1737 Device_Address : GTT_Address_Type;
1738 Valid : Boolean)
1739 with
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]1740 Global =>
1741 (Input => Config.Variable,
1742 In_Out => GTT_State),
1743 Depends =>
1744 (GTT_State =>+ (Config.Variable, GTT_Page, Device_Address, Valid)),
1745 Annotate =>
1746 (GNATprove, Intentional,
1747 """GMA.Config_State"" of ""Write_GTT"" not read",
1748 "Reading of Config_State depends on the platform configuration.");
Nico Huberceda17d2018-06-09 22:00:29 +0200[diff] [blame]1749
1750 procedure Read_GTT
1751 (Device_Address : out GTT_Address_Type;
1752 Valid : out Boolean;
1753 GTT_Page : in GTT_Range)
1754 with
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]1755 Global =>
1756 (Input => Config.Variable,
1757 In_Out => GTT_State),
1758 Depends =>
1759 ((Device_Address, Valid, GTT_State) =>
1760 (Config.Variable, GTT_State, GTT_Page)),
1761 Annotate =>
1762 (GNATprove, Intentional,
1763 """GMA.Config_State"" of ""Read_GTT"" not read",
1764 "Reading of Config_State depends on the platform configuration.");
1765 pragma Warnings (GNATprove, On, "no check message justified by this");
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1766
Nico Huber2b6f6992017-07-09 18:11:34 +0200[diff] [blame]1767 procedure Set_Register_Base (Base : Word64; GTT_Base : Word64 := 0)
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1768 with
1769 Global => (Output => Address_State),
Nico Huber2b6f6992017-07-09 18:11:34 +0200[diff] [blame]1770 Depends => (Address_State => (Base, GTT_Base)),
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1771 Pre => True,
1772 Post => True;
1773
1774end HW.GFX.GMA.Registers;