Gitiles
Code Review Sign In
review.sourcearcade.org / libgfxinit / 408204409b3324ae6ae7043826ee5ab7bb45bb2f / . / common / hw-gfx-gma-registers.ads
blob: 814dd11a2b01ff1b745d77e2a88eaaa0848b17f3 [file] [log] [blame]
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1--
2-- Copyright (C) 2015-2016 secunet Security Networks AG
3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
Nico Huber125a29e2016-10-18 00:23:54 +0200[diff] [blame]6-- the Free Software Foundation; either version 2 of the License, or
7-- (at your option) any later version.
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]8--
9-- This program is distributed in the hope that it will be useful,
10-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12-- GNU General Public License for more details.
13--
14
15with System;
16with HW.GFX.GMA;
17with HW.GFX.GMA.Config;
18
19private package HW.GFX.GMA.Registers
20with
21 Abstract_State =>
22 ((Address_State with Part_Of => GMA.State),
23 (Register_State with External, Part_Of => GMA.Device_State),
24 (GTT_State with External, Part_Of => GMA.Device_State)),
25 Initializes => Address_State
26is
27 type Registers_Invalid_Index is
28 (Invalid_Register, -- Allow a placeholder when access is not acceptable
29
30 RCS_RING_BUFFER_TAIL,
31 RCS_RING_BUFFER_HEAD,
32 RCS_RING_BUFFER_STRT,
33 RCS_RING_BUFFER_CTL,
34 QUIRK_02084,
35 QUIRK_02090,
36 HWSTAM,
37 MI_MODE,
38 INSTPM,
39 GT_MODE,
40 CACHE_MODE_0,
41 CTX_SIZE,
42 PP_DCLV_HIGH,
43 PP_DCLV_LOW,
44 GFX_MODE,
45 ARB_MODE,
46 HWS_PGA,
47 GAM_ECOCHK,
48 MBCTL,
49 UCGCTL1,
50 UCGCTL2,
51 VCS_RING_BUFFER_TAIL,
52 VCS_RING_BUFFER_HEAD,
53 VCS_RING_BUFFER_STRT,
54 VCS_RING_BUFFER_CTL,
55 SLEEP_PSMI_CONTROL,
56 VCS_HWSTAM,
57 VCS_PP_DCLV_HIGH,
58 VCS_PP_DCLV_LOW,
59 GAC_ECO_BITS,
60 BCS_RING_BUFFER_TAIL,
61 BCS_RING_BUFFER_HEAD,
62 BCS_RING_BUFFER_STRT,
63 BCS_RING_BUFFER_CTL,
64 BCS_HWSTAM,
65 BCS_PP_DCLV_HIGH,
66 BCS_PP_DCLV_LOW,
67 GAB_CTL_REG,
68 VGACNTRL,
69 FUSE_STATUS,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]70 ILK_DISPLAY_CHICKEN2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]71 DSPCLK_GATE_D,
72 FBA_CFB_BASE,
73 FBC_CTL,
74 IPS_CTL,
75 DEISR,
76 DEIMR,
77 DEIIR,
78 DEIER,
79 GTISR,
80 GTIMR,
81 GTIIR,
82 GTIER,
83 IIR,
84 HOTPLUG_CTL,
85 ARB_CTL,
86 DBUF_CTL,
87 WM_PIPE_A,
88 WM_PIPE_B,
89 WM1_LP_ILK,
90 WM2_LP_ILK,
91 WM3_LP_ILK,
92 WM_PIPE_C,
93 WM_LINETIME_A,
94 WM_LINETIME_B,
95 WM_LINETIME_C,
96 PWR_WELL_CTL_BIOS,
97 PWR_WELL_CTL_DRIVER,
98 PWR_WELL_CTL_KVMR,
99 PWR_WELL_CTL_DEBUG,
100 PWR_WELL_CTL5,
101 PWR_WELL_CTL6,
102 CDCLK_CTL,
103 LCPLL1_CTL,
104 LCPLL2_CTL,
105 SPLL_CTL,
106 WRPLL_CTL_1,
107 WRPLL_CTL_2,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame^]108 BXT_DE_PLL_ENABLE,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]109 PORT_CLK_SEL_DDIA,
110 PORT_CLK_SEL_DDIB,
111 PORT_CLK_SEL_DDIC,
112 PORT_CLK_SEL_DDID,
113 PORT_CLK_SEL_DDIE,
114 TRANSA_CLK_SEL,
115 TRANSB_CLK_SEL,
116 TRANSC_CLK_SEL,
117 NDE_RSTWRN_OPT,
118 BLC_PWM_CPU_CTL2,
119 BLC_PWM_CPU_CTL,
120 HTOTAL_A,
121 HBLANK_A,
122 HSYNC_A,
123 VTOTAL_A,
124 VBLANK_A,
125 VSYNC_A,
126 PIPEASRC,
127 PIPE_VSYNCSHIFT_A,
128 PIPEA_DATA_M1,
129 PIPEA_DATA_N1,
130 PIPEA_LINK_M1,
131 PIPEA_LINK_N1,
132 FDI_TX_CTL_A,
133 PIPEA_DDI_FUNC_CTL,
134 PIPEA_MSA_MISC,
135 SRD_CTL_A,
136 SRD_STATUS_A,
137 HTOTAL_B,
138 HBLANK_B,
139 HSYNC_B,
140 VTOTAL_B,
141 VBLANK_B,
142 VSYNC_B,
143 PIPEBSRC,
144 PIPE_VSYNCSHIFT_B,
145 PIPEB_DATA_M1,
146 PIPEB_DATA_N1,
147 PIPEB_LINK_M1,
148 PIPEB_LINK_N1,
149 FDI_TX_CTL_B,
150 PIPEB_DDI_FUNC_CTL,
151 PIPEB_MSA_MISC,
152 SRD_CTL_B,
153 SRD_STATUS_B,
154 HTOTAL_C,
155 HBLANK_C,
156 HSYNC_C,
157 VTOTAL_C,
158 VBLANK_C,
159 VSYNC_C,
160 PIPECSRC,
161 PIPE_VSYNCSHIFT_C,
162 PIPEC_DATA_M1,
163 PIPEC_DATA_N1,
164 PIPEC_LINK_M1,
165 PIPEC_LINK_N1,
166 FDI_TX_CTL_C,
167 PIPEC_DDI_FUNC_CTL,
168 PIPEC_MSA_MISC,
169 SRD_CTL_C,
170 SRD_STATUS_C,
171 DDI_BUF_CTL_A,
172 DDI_AUX_CTL_A,
173 DDI_AUX_DATA_A_1,
174 DDI_AUX_DATA_A_2,
175 DDI_AUX_DATA_A_3,
176 DDI_AUX_DATA_A_4,
177 DDI_AUX_DATA_A_5,
178 DDI_AUX_MUTEX_A,
179 DP_TP_CTL_A,
180 DDI_BUF_CTL_B,
181 DDI_AUX_CTL_B,
182 DDI_AUX_DATA_B_1,
183 DDI_AUX_DATA_B_2,
184 DDI_AUX_DATA_B_3,
185 DDI_AUX_DATA_B_4,
186 DDI_AUX_DATA_B_5,
187 DDI_AUX_MUTEX_B,
188 DP_TP_CTL_B,
189 DP_TP_STATUS_B,
190 DDI_BUF_CTL_C,
191 DDI_AUX_CTL_C,
192 DDI_AUX_DATA_C_1,
193 DDI_AUX_DATA_C_2,
194 DDI_AUX_DATA_C_3,
195 DDI_AUX_DATA_C_4,
196 DDI_AUX_DATA_C_5,
197 DDI_AUX_MUTEX_C,
198 DP_TP_CTL_C,
199 DP_TP_STATUS_C,
200 DDI_BUF_CTL_D,
201 DDI_AUX_CTL_D,
202 DDI_AUX_DATA_D_1,
203 DDI_AUX_DATA_D_2,
204 DDI_AUX_DATA_D_3,
205 DDI_AUX_DATA_D_4,
206 DDI_AUX_DATA_D_5,
207 DDI_AUX_MUTEX_D,
208 DP_TP_CTL_D,
209 DP_TP_STATUS_D,
210 DDI_BUF_CTL_E,
211 DP_TP_CTL_E,
212 DP_TP_STATUS_E,
213 SRD_CTL,
214 SRD_STATUS,
215 AUD_VID_DID,
216 PFA_WIN_POS,
217 PFA_WIN_SZ,
218 PFA_CTL_1,
219 PS_WIN_POS_1_A,
220 PS_WIN_SZ_1_A,
221 PS_CTRL_1_A,
222 PS_WIN_POS_2_A,
223 PS_WIN_SZ_2_A,
224 PS_CTRL_2_A,
225 PFB_WIN_POS,
226 PFB_WIN_SZ,
227 PFB_CTL_1,
228 PS_WIN_POS_1_B,
229 PS_WIN_SZ_1_B,
230 PS_CTRL_1_B,
231 PS_WIN_POS_2_B,
232 PS_WIN_SZ_2_B,
233 PS_CTRL_2_B,
234 PFC_WIN_POS,
235 PFC_WIN_SZ,
236 PFC_CTL_1,
237 PS_WIN_POS_1_C,
238 PS_WIN_SZ_1_C,
239 PS_CTRL_1_C,
240 DPLL1_CFGR1,
241 DPLL1_CFGR2,
242 DPLL2_CFGR1,
243 DPLL2_CFGR2,
244 DPLL3_CFGR1,
245 DPLL3_CFGR2,
246 DPLL_CTRL1,
247 DPLL_CTRL2,
248 DPLL_STATUS,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame^]249 BXT_DE_PLL_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]250 HTOTAL_EDP,
251 HBLANK_EDP,
252 HSYNC_EDP,
253 VTOTAL_EDP,
254 VBLANK_EDP,
255 VSYNC_EDP,
256 PIPE_EDP_DATA_M1,
257 PIPE_EDP_DATA_N1,
258 PIPE_EDP_LINK_M1,
259 PIPE_EDP_LINK_N1,
260 PIPE_EDP_DDI_FUNC_CTL,
261 PIPE_EDP_MSA_MISC,
262 SRD_CTL_EDP,
263 SRD_STATUS_EDP,
264 PIPE_SCANLINE_A,
265 PIPEACONF,
266 PIPEAMISC,
267 PIPE_FRMCNT_A,
268 DSPACNTR,
269 DSPALINOFF,
270 DSPASTRIDE,
271 PLANE_POS_1_A,
272 PLANE_SIZE_1_A,
273 DSPASURF,
274 DSPATILEOFF,
275 PLANE_WM_1_A_0,
276 PLANE_WM_1_A_1,
277 PLANE_WM_1_A_2,
278 PLANE_WM_1_A_3,
279 PLANE_WM_1_A_4,
280 PLANE_WM_1_A_5,
281 PLANE_WM_1_A_6,
282 PLANE_WM_1_A_7,
283 PLANE_BUF_CFG_1_A,
284 SPACNTR,
285 PIPE_SCANLINE_B,
286 PIPEBCONF,
287 PIPEBMISC,
288 PIPE_FRMCNT_B,
289 DSPBCNTR,
290 DSPBLINOFF,
291 DSPBSTRIDE,
292 PLANE_POS_1_B,
293 PLANE_SIZE_1_B,
294 DSPBSURF,
295 DSPBTILEOFF,
296 PLANE_WM_1_B_0,
297 PLANE_WM_1_B_1,
298 PLANE_WM_1_B_2,
299 PLANE_WM_1_B_3,
300 PLANE_WM_1_B_4,
301 PLANE_WM_1_B_5,
302 PLANE_WM_1_B_6,
303 PLANE_WM_1_B_7,
304 PLANE_BUF_CFG_1_B,
305 SPBCNTR,
306 PIPE_SCANLINE_C,
307 PIPECCONF,
308 PIPECMISC,
309 PIPE_FRMCNT_C,
310 DSPCCNTR,
311 DSPCLINOFF,
312 DSPCSTRIDE,
313 PLANE_POS_1_C,
314 PLANE_SIZE_1_C,
315 DSPCSURF,
316 DSPCTILEOFF,
317 PLANE_WM_1_C_0,
318 PLANE_WM_1_C_1,
319 PLANE_WM_1_C_2,
320 PLANE_WM_1_C_3,
321 PLANE_WM_1_C_4,
322 PLANE_WM_1_C_5,
323 PLANE_WM_1_C_6,
324 PLANE_WM_1_C_7,
325 PLANE_BUF_CFG_1_C,
326 SPCCNTR,
327 PIPE_EDP_CONF,
328 PCH_FDI_CHICKEN_B_C,
329 QUIRK_C2004,
330 SFUSE_STRAP,
331 PCH_DSPCLK_GATE_D,
332 SDEISR,
333 SDEIMR,
334 SDEIIR,
335 SDEIER,
336 SHOTPLUG_CTL,
337 PCH_GMBUS0,
338 PCH_GMBUS1,
339 PCH_GMBUS2,
340 PCH_GMBUS3,
341 PCH_GMBUS4,
342 PCH_GMBUS5,
343 SBI_ADDR,
344 SBI_DATA,
345 SBI_CTL_STAT,
346 PCH_DPLL_A,
347 PCH_DPLL_B,
348 PCH_PIXCLK_GATE,
349 PCH_FPA0,
350 PCH_FPA1,
351 PCH_FPB0,
352 PCH_FPB1,
353 PCH_DREF_CONTROL,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]354 PCH_RAWCLK_FREQ,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]355 PCH_DPLL_SEL,
356 PCH_PP_STATUS,
357 PCH_PP_CONTROL,
358 PCH_PP_ON_DELAYS,
359 PCH_PP_OFF_DELAYS,
360 PCH_PP_DIVISOR,
361 BLC_PWM_PCH_CTL1,
362 BLC_PWM_PCH_CTL2,
363 TRANS_HTOTAL_A,
364 TRANS_HBLANK_A,
365 TRANS_HSYNC_A,
366 TRANS_VTOTAL_A,
367 TRANS_VBLANK_A,
368 TRANS_VSYNC_A,
369 TRANS_VSYNCSHIFT_A,
370 TRANSA_DATA_M1,
371 TRANSA_DATA_N1,
372 TRANSA_DP_LINK_M1,
373 TRANSA_DP_LINK_N1,
374 TRANS_DP_CTL_A,
375 TRANS_HTOTAL_B,
376 TRANS_HBLANK_B,
377 TRANS_HSYNC_B,
378 TRANS_VTOTAL_B,
379 TRANS_VBLANK_B,
380 TRANS_VSYNC_B,
381 TRANS_VSYNCSHIFT_B,
382 TRANSB_DATA_M1,
383 TRANSB_DATA_N1,
384 TRANSB_DP_LINK_M1,
385 TRANSB_DP_LINK_N1,
386 PCH_ADPA,
387 PCH_HDMIB,
388 PCH_HDMIC,
389 PCH_HDMID,
390 PCH_LVDS,
391 TRANS_DP_CTL_B,
392 TRANS_HTOTAL_C,
393 TRANS_HBLANK_C,
394 TRANS_HSYNC_C,
395 TRANS_VTOTAL_C,
396 TRANS_VBLANK_C,
397 TRANS_VSYNC_C,
398 TRANS_VSYNCSHIFT_C,
399 TRANSC_DATA_M1,
400 TRANSC_DATA_N1,
401 TRANSC_DP_LINK_M1,
402 TRANSC_DP_LINK_N1,
403 TRANS_DP_CTL_C,
404 PCH_DP_B,
405 PCH_DP_AUX_CTL_B,
406 PCH_DP_AUX_DATA_B_1,
407 PCH_DP_AUX_DATA_B_2,
408 PCH_DP_AUX_DATA_B_3,
409 PCH_DP_AUX_DATA_B_4,
410 PCH_DP_AUX_DATA_B_5,
411 PCH_DP_C,
412 PCH_DP_AUX_CTL_C,
413 PCH_DP_AUX_DATA_C_1,
414 PCH_DP_AUX_DATA_C_2,
415 PCH_DP_AUX_DATA_C_3,
416 PCH_DP_AUX_DATA_C_4,
417 PCH_DP_AUX_DATA_C_5,
418 PCH_DP_D,
419 PCH_DP_AUX_CTL_D,
420 PCH_DP_AUX_DATA_D_1,
421 PCH_DP_AUX_DATA_D_2,
422 PCH_DP_AUX_DATA_D_3,
423 PCH_DP_AUX_DATA_D_4,
424 PCH_DP_AUX_DATA_D_5,
425 AUD_CONFIG_A,
426 PCH_AUD_VID_DID,
427 AUD_HDMIW_HDMIEDID_A,
428 AUD_CNTL_ST_A,
429 AUD_CNTRL_ST2,
430 AUD_CONFIG_B,
431 AUD_HDMIW_HDMIEDID_B,
432 AUD_CNTL_ST_B,
433 AUD_CONFIG_C,
434 AUD_HDMIW_HDMIEDID_C,
435 AUD_CNTL_ST_C,
436 TRANSACONF,
437 FDI_RXA_CTL,
438 FDI_RX_MISC_A,
439 FDI_RXA_IIR,
440 FDI_RXA_IMR,
441 FDI_RXA_TUSIZE1,
442 QUIRK_F0060,
443 TRANSA_CHICKEN2,
444 TRANSBCONF,
445 FDI_RXB_CTL,
446 FDI_RX_MISC_B,
447 FDI_RXB_IIR,
448 FDI_RXB_IMR,
449 FDI_RXB_TUSIZE1,
450 QUIRK_F1060,
451 TRANSB_CHICKEN2,
452 TRANSCCONF,
453 FDI_RXC_CTL,
454 FDI_RX_MISC_C,
455 FDI_RXC_IIR,
456 FDI_RXC_IMR,
457 FDI_RXC_TUSIZE1,
458 QUIRK_F2060,
459 TRANSC_CHICKEN2,
460 GT_MAILBOX,
461 GT_MAILBOX_DATA,
462 GT_MAILBOX_DATA_1);
463
464 pragma Warnings
465 (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)",
466 Reason => "TODO: Should it matter?");
467 pragma Keep_Names (Registers_Invalid_Index);
468 pragma Warnings
469 (GNATprove, On, "pragma ""KEEP_NAMES"" ignored *(not yet supported)");
470
471 Register_Width : constant := 4;
472
473 for Registers_Invalid_Index use
474 (Invalid_Register => 0,
475
476 ---------------------------------------------------------------------------
477 -- Pipe A registers
478 ---------------------------------------------------------------------------
479
480 -- pipe timing registers
481
482 HTOTAL_A => 16#06_0000# / Register_Width,
483 HBLANK_A => 16#06_0004# / Register_Width,
484 HSYNC_A => 16#06_0008# / Register_Width,
485 VTOTAL_A => 16#06_000c# / Register_Width,
486 VBLANK_A => 16#06_0010# / Register_Width,
487 VSYNC_A => 16#06_0014# / Register_Width,
488 PIPEASRC => 16#06_001c# / Register_Width,
489 PIPEACONF => 16#07_0008# / Register_Width,
490 PIPEAMISC => 16#07_0030# / Register_Width,
491 TRANS_HTOTAL_A => 16#0e_0000# / Register_Width,
492 TRANS_HBLANK_A => 16#0e_0004# / Register_Width,
493 TRANS_HSYNC_A => 16#0e_0008# / Register_Width,
494 TRANS_VTOTAL_A => 16#0e_000c# / Register_Width,
495 TRANS_VBLANK_A => 16#0e_0010# / Register_Width,
496 TRANS_VSYNC_A => 16#0e_0014# / Register_Width,
497 TRANSA_DATA_M1 => 16#0e_0030# / Register_Width,
498 TRANSA_DATA_N1 => 16#0e_0034# / Register_Width,
499 TRANSA_DP_LINK_M1 => 16#0e_0040# / Register_Width,
500 TRANSA_DP_LINK_N1 => 16#0e_0044# / Register_Width,
501 PIPEA_DATA_M1 => 16#06_0030# / Register_Width,
502 PIPEA_DATA_N1 => 16#06_0034# / Register_Width,
503 PIPEA_LINK_M1 => 16#06_0040# / Register_Width,
504 PIPEA_LINK_N1 => 16#06_0044# / Register_Width,
505 PIPEA_DDI_FUNC_CTL => 16#06_0400# / Register_Width,
506 PIPEA_MSA_MISC => 16#06_0410# / Register_Width,
507
508 -- PCH sideband interface registers
509 SBI_ADDR => 16#0c_6000# / Register_Width,
510 SBI_DATA => 16#0c_6004# / Register_Width,
511 SBI_CTL_STAT => 16#0c_6008# / Register_Width,
512
513 -- clock registers
514 PCH_DPLL_A => 16#0c_6014# / Register_Width,
515 PCH_PIXCLK_GATE => 16#0c_6020# / Register_Width,
516 PCH_FPA0 => 16#0c_6040# / Register_Width,
517 PCH_FPA1 => 16#0c_6044# / Register_Width,
518
519 -- panel fitter
520 PFA_CTL_1 => 16#06_8080# / Register_Width,
521 PFA_WIN_POS => 16#06_8070# / Register_Width,
522 PFA_WIN_SZ => 16#06_8074# / Register_Width,
523 PS_WIN_POS_1_A => 16#06_8170# / Register_Width,
524 PS_WIN_SZ_1_A => 16#06_8174# / Register_Width,
525 PS_CTRL_1_A => 16#06_8180# / Register_Width,
526 PS_WIN_POS_2_A => 16#06_8270# / Register_Width,
527 PS_WIN_SZ_2_A => 16#06_8274# / Register_Width,
528 PS_CTRL_2_A => 16#06_8280# / Register_Width,
529
530 -- display control
531 DSPACNTR => 16#07_0180# / Register_Width,
532 DSPALINOFF => 16#07_0184# / Register_Width,
533 DSPASTRIDE => 16#07_0188# / Register_Width,
534 PLANE_POS_1_A => 16#07_018c# / Register_Width,
535 PLANE_SIZE_1_A => 16#07_0190# / Register_Width,
536 DSPASURF => 16#07_019c# / Register_Width,
537 DSPATILEOFF => 16#07_01a4# / Register_Width,
538
539 -- sprite control
540 SPACNTR => 16#07_0280# / Register_Width,
541
542 -- FDI and PCH transcoder control
543 FDI_TX_CTL_A => 16#06_0100# / Register_Width,
544 FDI_RXA_CTL => 16#0f_000c# / Register_Width,
545 FDI_RX_MISC_A => 16#0f_0010# / Register_Width,
546 FDI_RXA_IIR => 16#0f_0014# / Register_Width,
547 FDI_RXA_IMR => 16#0f_0018# / Register_Width,
548 FDI_RXA_TUSIZE1 => 16#0f_0030# / Register_Width,
549 TRANSACONF => 16#0f_0008# / Register_Width,
550 TRANSA_CHICKEN2 => 16#0f_0064# / Register_Width,
551
552 -- watermark registers
553 WM_LINETIME_A => 16#04_5270# / Register_Width,
554 PLANE_WM_1_A_0 => 16#07_0240# / Register_Width,
555 PLANE_WM_1_A_1 => 16#07_0244# / Register_Width,
556 PLANE_WM_1_A_2 => 16#07_0248# / Register_Width,
557 PLANE_WM_1_A_3 => 16#07_024c# / Register_Width,
558 PLANE_WM_1_A_4 => 16#07_0250# / Register_Width,
559 PLANE_WM_1_A_5 => 16#07_0254# / Register_Width,
560 PLANE_WM_1_A_6 => 16#07_0258# / Register_Width,
561 PLANE_WM_1_A_7 => 16#07_025c# / Register_Width,
562 PLANE_BUF_CFG_1_A => 16#07_027c# / Register_Width,
563
564 -- CPU transcoder clock select
565 TRANSA_CLK_SEL => 16#04_6140# / Register_Width,
566
567 ---------------------------------------------------------------------------
568 -- Pipe B registers
569 ---------------------------------------------------------------------------
570
571 -- pipe timing registers
572
573 HTOTAL_B => 16#06_1000# / Register_Width,
574 HBLANK_B => 16#06_1004# / Register_Width,
575 HSYNC_B => 16#06_1008# / Register_Width,
576 VTOTAL_B => 16#06_100c# / Register_Width,
577 VBLANK_B => 16#06_1010# / Register_Width,
578 VSYNC_B => 16#06_1014# / Register_Width,
579 PIPEBSRC => 16#06_101c# / Register_Width,
580 PIPEBCONF => 16#07_1008# / Register_Width,
581 PIPEBMISC => 16#07_1030# / Register_Width,
582 TRANS_HTOTAL_B => 16#0e_1000# / Register_Width,
583 TRANS_HBLANK_B => 16#0e_1004# / Register_Width,
584 TRANS_HSYNC_B => 16#0e_1008# / Register_Width,
585 TRANS_VTOTAL_B => 16#0e_100c# / Register_Width,
586 TRANS_VBLANK_B => 16#0e_1010# / Register_Width,
587 TRANS_VSYNC_B => 16#0e_1014# / Register_Width,
588 TRANSB_DATA_M1 => 16#0e_1030# / Register_Width,
589 TRANSB_DATA_N1 => 16#0e_1034# / Register_Width,
590 TRANSB_DP_LINK_M1 => 16#0e_1040# / Register_Width,
591 TRANSB_DP_LINK_N1 => 16#0e_1044# / Register_Width,
592 PIPEB_DATA_M1 => 16#06_1030# / Register_Width,
593 PIPEB_DATA_N1 => 16#06_1034# / Register_Width,
594 PIPEB_LINK_M1 => 16#06_1040# / Register_Width,
595 PIPEB_LINK_N1 => 16#06_1044# / Register_Width,
596 PIPEB_DDI_FUNC_CTL => 16#06_1400# / Register_Width,
597 PIPEB_MSA_MISC => 16#06_1410# / Register_Width,
598
599 -- clock registers
600 PCH_DPLL_B => 16#0c_6018# / Register_Width,
601 PCH_FPB0 => 16#0c_6048# / Register_Width,
602 PCH_FPB1 => 16#0c_604c# / Register_Width,
603
604 -- panel fitter
605 PFB_CTL_1 => 16#06_8880# / Register_Width,
606 PFB_WIN_POS => 16#06_8870# / Register_Width,
607 PFB_WIN_SZ => 16#06_8874# / Register_Width,
608 PS_WIN_POS_1_B => 16#06_8970# / Register_Width,
609 PS_WIN_SZ_1_B => 16#06_8974# / Register_Width,
610 PS_CTRL_1_B => 16#06_8980# / Register_Width,
611 PS_WIN_POS_2_B => 16#06_8a70# / Register_Width,
612 PS_WIN_SZ_2_B => 16#06_8a74# / Register_Width,
613 PS_CTRL_2_B => 16#06_8a80# / Register_Width,
614
615 -- display control
616 DSPBCNTR => 16#07_1180# / Register_Width,
617 DSPBLINOFF => 16#07_1184# / Register_Width,
618 DSPBSTRIDE => 16#07_1188# / Register_Width,
619 PLANE_POS_1_B => 16#07_118c# / Register_Width,
620 PLANE_SIZE_1_B => 16#07_1190# / Register_Width,
621 DSPBSURF => 16#07_119c# / Register_Width,
622 DSPBTILEOFF => 16#07_11a4# / Register_Width,
623
624 -- sprite control
625 SPBCNTR => 16#07_1280# / Register_Width,
626
627 -- FDI and PCH transcoder control
628 FDI_TX_CTL_B => 16#06_1100# / Register_Width,
629 FDI_RXB_CTL => 16#0f_100c# / Register_Width,
630 FDI_RX_MISC_B => 16#0f_1010# / Register_Width,
631 FDI_RXB_IIR => 16#0f_1014# / Register_Width,
632 FDI_RXB_IMR => 16#0f_1018# / Register_Width,
633 FDI_RXB_TUSIZE1 => 16#0f_1030# / Register_Width,
634 TRANSBCONF => 16#0f_1008# / Register_Width,
635 TRANSB_CHICKEN2 => 16#0f_1064# / Register_Width,
636
637 -- watermark registers
638 WM_LINETIME_B => 16#04_5274# / Register_Width,
639 PLANE_WM_1_B_0 => 16#07_1240# / Register_Width,
640 PLANE_WM_1_B_1 => 16#07_1244# / Register_Width,
641 PLANE_WM_1_B_2 => 16#07_1248# / Register_Width,
642 PLANE_WM_1_B_3 => 16#07_124c# / Register_Width,
643 PLANE_WM_1_B_4 => 16#07_1250# / Register_Width,
644 PLANE_WM_1_B_5 => 16#07_1254# / Register_Width,
645 PLANE_WM_1_B_6 => 16#07_1258# / Register_Width,
646 PLANE_WM_1_B_7 => 16#07_125c# / Register_Width,
647 PLANE_BUF_CFG_1_B => 16#07_127c# / Register_Width,
648
649 -- CPU transcoder clock select
650 TRANSB_CLK_SEL => 16#04_6144# / Register_Width,
651
652 ---------------------------------------------------------------------------
653 -- Pipe C registers
654 ---------------------------------------------------------------------------
655
656 -- pipe timing registers
657
658 HTOTAL_C => 16#06_2000# / Register_Width,
659 HBLANK_C => 16#06_2004# / Register_Width,
660 HSYNC_C => 16#06_2008# / Register_Width,
661 VTOTAL_C => 16#06_200c# / Register_Width,
662 VBLANK_C => 16#06_2010# / Register_Width,
663 VSYNC_C => 16#06_2014# / Register_Width,
664 PIPECSRC => 16#06_201c# / Register_Width,
665 PIPECCONF => 16#07_2008# / Register_Width,
666 PIPECMISC => 16#07_2030# / Register_Width,
667 TRANS_HTOTAL_C => 16#0e_2000# / Register_Width,
668 TRANS_HBLANK_C => 16#0e_2004# / Register_Width,
669 TRANS_HSYNC_C => 16#0e_2008# / Register_Width,
670 TRANS_VTOTAL_C => 16#0e_200c# / Register_Width,
671 TRANS_VBLANK_C => 16#0e_2010# / Register_Width,
672 TRANS_VSYNC_C => 16#0e_2014# / Register_Width,
673 TRANSC_DATA_M1 => 16#0e_2030# / Register_Width,
674 TRANSC_DATA_N1 => 16#0e_2034# / Register_Width,
675 TRANSC_DP_LINK_M1 => 16#0e_2040# / Register_Width,
676 TRANSC_DP_LINK_N1 => 16#0e_2044# / Register_Width,
677 PIPEC_DATA_M1 => 16#06_2030# / Register_Width,
678 PIPEC_DATA_N1 => 16#06_2034# / Register_Width,
679 PIPEC_LINK_M1 => 16#06_2040# / Register_Width,
680 PIPEC_LINK_N1 => 16#06_2044# / Register_Width,
681 PIPEC_DDI_FUNC_CTL => 16#06_2400# / Register_Width,
682 PIPEC_MSA_MISC => 16#06_2410# / Register_Width,
683
684 -- panel fitter
685 PFC_CTL_1 => 16#06_9080# / Register_Width,
686 PFC_WIN_POS => 16#06_9070# / Register_Width,
687 PFC_WIN_SZ => 16#06_9074# / Register_Width,
688 PS_WIN_POS_1_C => 16#06_9170# / Register_Width,
689 PS_WIN_SZ_1_C => 16#06_9174# / Register_Width,
690 PS_CTRL_1_C => 16#06_9180# / Register_Width,
691
692 -- display control
693 DSPCCNTR => 16#07_2180# / Register_Width,
694 DSPCLINOFF => 16#07_2184# / Register_Width,
695 DSPCSTRIDE => 16#07_2188# / Register_Width,
696 PLANE_POS_1_C => 16#07_218c# / Register_Width,
697 PLANE_SIZE_1_C => 16#07_2190# / Register_Width,
698 DSPCSURF => 16#07_219c# / Register_Width,
699 DSPCTILEOFF => 16#07_21a4# / Register_Width,
700
701 -- sprite control
702 SPCCNTR => 16#07_2280# / Register_Width,
703
704 -- PCH transcoder control
705 FDI_TX_CTL_C => 16#06_2100# / Register_Width,
706 FDI_RXC_CTL => 16#0f_200c# / Register_Width,
707 FDI_RX_MISC_C => 16#0f_2010# / Register_Width,
708 FDI_RXC_IIR => 16#0f_2014# / Register_Width,
709 FDI_RXC_IMR => 16#0f_2018# / Register_Width,
710 FDI_RXC_TUSIZE1 => 16#0f_2030# / Register_Width,
711 TRANSCCONF => 16#0f_2008# / Register_Width,
712 TRANSC_CHICKEN2 => 16#0f_2064# / Register_Width,
713
714 -- watermark registers
715 WM_LINETIME_C => 16#04_5278# / Register_Width,
716 PLANE_WM_1_C_0 => 16#07_2240# / Register_Width,
717 PLANE_WM_1_C_1 => 16#07_2244# / Register_Width,
718 PLANE_WM_1_C_2 => 16#07_2248# / Register_Width,
719 PLANE_WM_1_C_3 => 16#07_224c# / Register_Width,
720 PLANE_WM_1_C_4 => 16#07_2250# / Register_Width,
721 PLANE_WM_1_C_5 => 16#07_2254# / Register_Width,
722 PLANE_WM_1_C_6 => 16#07_2258# / Register_Width,
723 PLANE_WM_1_C_7 => 16#07_225c# / Register_Width,
724 PLANE_BUF_CFG_1_C => 16#07_227c# / Register_Width,
725
726 -- CPU transcoder clock select
727 TRANSC_CLK_SEL => 16#04_6148# / Register_Width,
728
729 ---------------------------------------------------------------------------
730 -- Pipe EDP registers
731 ---------------------------------------------------------------------------
732
733 -- pipe timing registers
734
735 HTOTAL_EDP => 16#06_f000# / Register_Width,
736 HBLANK_EDP => 16#06_f004# / Register_Width,
737 HSYNC_EDP => 16#06_f008# / Register_Width,
738 VTOTAL_EDP => 16#06_f00c# / Register_Width,
739 VBLANK_EDP => 16#06_f010# / Register_Width,
740 VSYNC_EDP => 16#06_f014# / Register_Width,
741 PIPE_EDP_CONF => 16#07_f008# / Register_Width,
742 PIPE_EDP_DATA_M1 => 16#06_f030# / Register_Width,
743 PIPE_EDP_DATA_N1 => 16#06_f034# / Register_Width,
744 PIPE_EDP_LINK_M1 => 16#06_f040# / Register_Width,
745 PIPE_EDP_LINK_N1 => 16#06_f044# / Register_Width,
746 PIPE_EDP_DDI_FUNC_CTL => 16#06_f400# / Register_Width,
747 PIPE_EDP_MSA_MISC => 16#06_f410# / Register_Width,
748
749 -- PSR registers
750 SRD_CTL => 16#06_4800# / Register_Width,
751 SRD_CTL_A => 16#06_0800# / Register_Width,
752 SRD_CTL_B => 16#06_1800# / Register_Width,
753 SRD_CTL_C => 16#06_2800# / Register_Width,
754 SRD_CTL_EDP => 16#06_f800# / Register_Width,
755 SRD_STATUS => 16#06_4840# / Register_Width,
756 SRD_STATUS_A => 16#06_0840# / Register_Width,
757 SRD_STATUS_B => 16#06_1840# / Register_Width,
758 SRD_STATUS_C => 16#06_2840# / Register_Width,
759 SRD_STATUS_EDP => 16#06_f840# / Register_Width,
760
761 -- DDI registers
762 DDI_BUF_CTL_A => 16#06_4000# / Register_Width, -- aliased by DP_CTL_A
763 DDI_AUX_CTL_A => 16#06_4010# / Register_Width, -- aliased by DP_AUX_CTL_A
764 DDI_AUX_DATA_A_1 => 16#06_4014# / Register_Width, -- aliased by DP_AUX_DATA_A_1
765 DDI_AUX_DATA_A_2 => 16#06_4018# / Register_Width, -- aliased by DP_AUX_DATA_A_2
766 DDI_AUX_DATA_A_3 => 16#06_401c# / Register_Width, -- aliased by DP_AUX_DATA_A_3
767 DDI_AUX_DATA_A_4 => 16#06_4020# / Register_Width, -- aliased by DP_AUX_DATA_A_4
768 DDI_AUX_DATA_A_5 => 16#06_4024# / Register_Width, -- aliased by DP_AUX_DATA_A_5
769 DDI_AUX_MUTEX_A => 16#06_402c# / Register_Width,
770 DDI_BUF_CTL_B => 16#06_4100# / Register_Width,
771 DDI_AUX_CTL_B => 16#06_4110# / Register_Width,
772 DDI_AUX_DATA_B_1 => 16#06_4114# / Register_Width,
773 DDI_AUX_DATA_B_2 => 16#06_4118# / Register_Width,
774 DDI_AUX_DATA_B_3 => 16#06_411c# / Register_Width,
775 DDI_AUX_DATA_B_4 => 16#06_4120# / Register_Width,
776 DDI_AUX_DATA_B_5 => 16#06_4124# / Register_Width,
777 DDI_AUX_MUTEX_B => 16#06_412c# / Register_Width,
778 DDI_BUF_CTL_C => 16#06_4200# / Register_Width,
779 DDI_AUX_CTL_C => 16#06_4210# / Register_Width,
780 DDI_AUX_DATA_C_1 => 16#06_4214# / Register_Width,
781 DDI_AUX_DATA_C_2 => 16#06_4218# / Register_Width,
782 DDI_AUX_DATA_C_3 => 16#06_421c# / Register_Width,
783 DDI_AUX_DATA_C_4 => 16#06_4220# / Register_Width,
784 DDI_AUX_DATA_C_5 => 16#06_4224# / Register_Width,
785 DDI_AUX_MUTEX_C => 16#06_422c# / Register_Width,
786 DDI_BUF_CTL_D => 16#06_4300# / Register_Width,
787 DDI_AUX_CTL_D => 16#06_4310# / Register_Width,
788 DDI_AUX_DATA_D_1 => 16#06_4314# / Register_Width,
789 DDI_AUX_DATA_D_2 => 16#06_4318# / Register_Width,
790 DDI_AUX_DATA_D_3 => 16#06_431c# / Register_Width,
791 DDI_AUX_DATA_D_4 => 16#06_4320# / Register_Width,
792 DDI_AUX_DATA_D_5 => 16#06_4324# / Register_Width,
793 DDI_AUX_MUTEX_D => 16#06_432c# / Register_Width,
794 DDI_BUF_CTL_E => 16#06_4400# / Register_Width,
795 DP_TP_CTL_A => 16#06_4040# / Register_Width,
796 DP_TP_CTL_B => 16#06_4140# / Register_Width,
797 DP_TP_CTL_C => 16#06_4240# / Register_Width,
798 DP_TP_CTL_D => 16#06_4340# / Register_Width,
799 DP_TP_CTL_E => 16#06_4440# / Register_Width,
800 DP_TP_STATUS_B => 16#06_4144# / Register_Width,
801 DP_TP_STATUS_C => 16#06_4244# / Register_Width,
802 DP_TP_STATUS_D => 16#06_4344# / Register_Width,
803 DP_TP_STATUS_E => 16#06_4444# / Register_Width,
804 PORT_CLK_SEL_DDIA => 16#04_6100# / Register_Width,
805 PORT_CLK_SEL_DDIB => 16#04_6104# / Register_Width,
806 PORT_CLK_SEL_DDIC => 16#04_6108# / Register_Width,
807 PORT_CLK_SEL_DDID => 16#04_610c# / Register_Width,
808 PORT_CLK_SEL_DDIE => 16#04_6110# / Register_Width,
809
810 -- Skylake DPLL registers
811 DPLL1_CFGR1 => 16#06_c040# / Register_Width,
812 DPLL1_CFGR2 => 16#06_c044# / Register_Width,
813 DPLL2_CFGR1 => 16#06_c048# / Register_Width,
814 DPLL2_CFGR2 => 16#06_c04c# / Register_Width,
815 DPLL3_CFGR1 => 16#06_c050# / Register_Width,
816 DPLL3_CFGR2 => 16#06_c054# / Register_Width,
817 DPLL_CTRL1 => 16#06_c058# / Register_Width,
818 DPLL_CTRL2 => 16#06_c05c# / Register_Width,
819 DPLL_STATUS => 16#06_c060# / Register_Width,
820
821 -- CD CLK register
822 CDCLK_CTL => 16#04_6000# / Register_Width,
823
824 -- Skylake LCPLL registers
825 LCPLL1_CTL => 16#04_6010# / Register_Width,
826 LCPLL2_CTL => 16#04_6014# / Register_Width,
827
828 -- SPLL register
829 SPLL_CTL => 16#04_6020# / Register_Width,
830
831 -- WRPLL registers
832 WRPLL_CTL_1 => 16#04_6040# / Register_Width,
833 WRPLL_CTL_2 => 16#04_6060# / Register_Width,
834
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame^]835 -- Broxton Display Engine PLL registers
836 BXT_DE_PLL_CTL => 16#06_d000# / Register_Width,
837 BXT_DE_PLL_ENABLE => 16#04_6070# / Register_Width,
838
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]839 -- Power Down Well registers
840 PWR_WELL_CTL_BIOS => 16#04_5400# / Register_Width,
841 PWR_WELL_CTL_DRIVER => 16#04_5404# / Register_Width,
842 PWR_WELL_CTL_KVMR => 16#04_5408# / Register_Width,
843 PWR_WELL_CTL_DEBUG => 16#04_540c# / Register_Width,
844 PWR_WELL_CTL5 => 16#04_5410# / Register_Width,
845 PWR_WELL_CTL6 => 16#04_5414# / Register_Width,
846
847 -- class Panel registers
848 PCH_PP_STATUS => 16#0c_7200# / Register_Width,
849 PCH_PP_CONTROL => 16#0c_7204# / Register_Width,
850 PCH_PP_ON_DELAYS => 16#0c_7208# / Register_Width,
851 PCH_PP_OFF_DELAYS => 16#0c_720c# / Register_Width,
852 PCH_PP_DIVISOR => 16#0c_7210# / Register_Width,
853 BLC_PWM_CPU_CTL => 16#04_8254# / Register_Width,
854 BLC_PWM_PCH_CTL2 => 16#0c_8254# / Register_Width,
855
856 -- PCH LVDS Connector Registers
857 PCH_LVDS => 16#0e_1180# / Register_Width,
858
859 -- PCH ADPA Connector Registers
860 PCH_ADPA => 16#0e_1100# / Register_Width,
861
862 -- PCH HDMIB Connector Registers
863 PCH_HDMIB => 16#0e_1140# / Register_Width,
864
865 -- PCH HDMIC Connector Registers
866 PCH_HDMIC => 16#0e_1150# / Register_Width,
867
868 -- PCH HDMID Connector Registers
869 PCH_HDMID => 16#0e_1160# / Register_Width,
870
871 -- Intel Registers
872 VGACNTRL => 16#04_1000# / Register_Width,
873 FUSE_STATUS => 16#04_2000# / Register_Width,
874 FBA_CFB_BASE => 16#04_3200# / Register_Width,
875 IPS_CTL => 16#04_3408# / Register_Width,
876 ARB_CTL => 16#04_5000# / Register_Width,
877 DBUF_CTL => 16#04_5008# / Register_Width,
878 NDE_RSTWRN_OPT => 16#04_6408# / Register_Width,
879 PCH_DREF_CONTROL => 16#0c_6200# / Register_Width,
880 BLC_PWM_PCH_CTL1 => 16#0c_8250# / Register_Width,
881 BLC_PWM_CPU_CTL2 => 16#04_8250# / Register_Width,
882 PCH_DPLL_SEL => 16#0c_7000# / Register_Width,
883 GT_MAILBOX => 16#13_8124# / Register_Width,
884 GT_MAILBOX_DATA => 16#13_8128# / Register_Width,
885 GT_MAILBOX_DATA_1 => 16#13_812c# / Register_Width,
886
887 PCH_DP_B => 16#0e_4100# / Register_Width,
888 PCH_DP_AUX_CTL_B => 16#0e_4110# / Register_Width,
889 PCH_DP_AUX_DATA_B_1 => 16#0e_4114# / Register_Width,
890 PCH_DP_AUX_DATA_B_2 => 16#0e_4118# / Register_Width,
891 PCH_DP_AUX_DATA_B_3 => 16#0e_411c# / Register_Width,
892 PCH_DP_AUX_DATA_B_4 => 16#0e_4120# / Register_Width,
893 PCH_DP_AUX_DATA_B_5 => 16#0e_4124# / Register_Width,
894 PCH_DP_C => 16#0e_4200# / Register_Width,
895 PCH_DP_AUX_CTL_C => 16#0e_4210# / Register_Width,
896 PCH_DP_AUX_DATA_C_1 => 16#0e_4214# / Register_Width,
897 PCH_DP_AUX_DATA_C_2 => 16#0e_4218# / Register_Width,
898 PCH_DP_AUX_DATA_C_3 => 16#0e_421c# / Register_Width,
899 PCH_DP_AUX_DATA_C_4 => 16#0e_4220# / Register_Width,
900 PCH_DP_AUX_DATA_C_5 => 16#0e_4224# / Register_Width,
901 PCH_DP_D => 16#0e_4300# / Register_Width,
902 PCH_DP_AUX_CTL_D => 16#0e_4310# / Register_Width,
903 PCH_DP_AUX_DATA_D_1 => 16#0e_4314# / Register_Width,
904 PCH_DP_AUX_DATA_D_2 => 16#0e_4318# / Register_Width,
905 PCH_DP_AUX_DATA_D_3 => 16#0e_431c# / Register_Width,
906 PCH_DP_AUX_DATA_D_4 => 16#0e_4320# / Register_Width,
907 PCH_DP_AUX_DATA_D_5 => 16#0e_4324# / Register_Width,
908
909 -- watermark registers
910 WM1_LP_ILK => 16#04_5108# / Register_Width,
911 WM2_LP_ILK => 16#04_510c# / Register_Width,
912 WM3_LP_ILK => 16#04_5110# / Register_Width,
913
914 -- audio VID/DID
915 AUD_VID_DID => 16#06_5020# / Register_Width,
916 PCH_AUD_VID_DID => 16#0e_5020# / Register_Width,
917
918 -- interrupt registers
919 DEISR => 16#04_4000# / Register_Width,
920 DEIMR => 16#04_4004# / Register_Width,
921 DEIIR => 16#04_4008# / Register_Width,
922 DEIER => 16#04_400c# / Register_Width,
923 GTISR => 16#04_4010# / Register_Width,
924 GTIMR => 16#04_4014# / Register_Width,
925 GTIIR => 16#04_4018# / Register_Width,
926 GTIER => 16#04_401c# / Register_Width,
927 SDEISR => 16#0c_4000# / Register_Width,
928 SDEIMR => 16#0c_4004# / Register_Width,
929 SDEIIR => 16#0c_4008# / Register_Width,
930 SDEIER => 16#0c_400c# / Register_Width,
931
932 -- I2C stuff
933 PCH_GMBUS0 => 16#0c_5100# / Register_Width,
934 PCH_GMBUS1 => 16#0c_5104# / Register_Width,
935 PCH_GMBUS2 => 16#0c_5108# / Register_Width,
936 PCH_GMBUS3 => 16#0c_510c# / Register_Width,
937 PCH_GMBUS4 => 16#0c_5110# / Register_Width,
938 PCH_GMBUS5 => 16#0c_5120# / Register_Width,
939
940 -- clock gating -- maybe have to touch this
941 DSPCLK_GATE_D => 16#04_2020# / Register_Width,
942 PCH_FDI_CHICKEN_B_C => 16#0c_2000# / Register_Width,
943 PCH_DSPCLK_GATE_D => 16#0c_2020# / Register_Width,
944
945 -- hotplug and initial detection
946 HOTPLUG_CTL => 16#04_4030# / Register_Width,
947 SHOTPLUG_CTL => 16#0c_4030# / Register_Width,
948 SFUSE_STRAP => 16#0c_2014# / Register_Width,
949
950 -- Render Engine Command Streamer
951 ARB_MODE => 16#00_4030# / Register_Width,
952 HWS_PGA => 16#00_4080# / Register_Width,
953 RCS_RING_BUFFER_TAIL => 16#00_2030# / Register_Width,
954 VCS_RING_BUFFER_TAIL => 16#01_2030# / Register_Width,
955 BCS_RING_BUFFER_TAIL => 16#02_2030# / Register_Width,
956 RCS_RING_BUFFER_HEAD => 16#00_2034# / Register_Width,
957 VCS_RING_BUFFER_HEAD => 16#01_2034# / Register_Width,
958 BCS_RING_BUFFER_HEAD => 16#02_2034# / Register_Width,
959 RCS_RING_BUFFER_STRT => 16#00_2038# / Register_Width,
960 VCS_RING_BUFFER_STRT => 16#01_2038# / Register_Width,
961 BCS_RING_BUFFER_STRT => 16#02_2038# / Register_Width,
962 RCS_RING_BUFFER_CTL => 16#00_203c# / Register_Width,
963 VCS_RING_BUFFER_CTL => 16#01_203c# / Register_Width,
964 BCS_RING_BUFFER_CTL => 16#02_203c# / Register_Width,
965 MI_MODE => 16#00_209c# / Register_Width,
966 INSTPM => 16#00_20c0# / Register_Width,
967 GAB_CTL_REG => 16#02_4000# / Register_Width,
968 PP_DCLV_HIGH => 16#00_2220# / Register_Width,
969 PP_DCLV_LOW => 16#00_2228# / Register_Width,
970 VCS_PP_DCLV_HIGH => 16#01_2220# / Register_Width,
971 VCS_PP_DCLV_LOW => 16#01_2228# / Register_Width,
972 BCS_PP_DCLV_HIGH => 16#02_2220# / Register_Width,
973 BCS_PP_DCLV_LOW => 16#02_2228# / Register_Width,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]974 ILK_DISPLAY_CHICKEN2 => 16#04_2004# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]975 UCGCTL1 => 16#00_9400# / Register_Width,
976 UCGCTL2 => 16#00_9404# / Register_Width,
977 MBCTL => 16#00_907c# / Register_Width,
978 HWSTAM => 16#00_2098# / Register_Width,
979 VCS_HWSTAM => 16#01_2098# / Register_Width,
980 BCS_HWSTAM => 16#02_2098# / Register_Width,
981 IIR => 16#04_4028# / Register_Width,
982 PIPE_FRMCNT_A => 16#07_0040# / Register_Width,
983 PIPE_FRMCNT_B => 16#07_1040# / Register_Width,
984 PIPE_FRMCNT_C => 16#07_2040# / Register_Width,
985 FBC_CTL => 16#04_3208# / Register_Width,
986 PIPE_VSYNCSHIFT_A => 16#06_0028# / Register_Width,
987 PIPE_VSYNCSHIFT_B => 16#06_1028# / Register_Width,
988 PIPE_VSYNCSHIFT_C => 16#06_2028# / Register_Width,
989 WM_PIPE_A => 16#04_5100# / Register_Width,
990 WM_PIPE_B => 16#04_5104# / Register_Width,
991 WM_PIPE_C => 16#04_5200# / Register_Width,
992 PIPE_SCANLINE_A => 16#07_0000# / Register_Width,
993 PIPE_SCANLINE_B => 16#07_1000# / Register_Width,
994 PIPE_SCANLINE_C => 16#07_2000# / Register_Width,
995 GFX_MODE => 16#00_2520# / Register_Width,
996 CACHE_MODE_0 => 16#00_2120# / Register_Width,
997 SLEEP_PSMI_CONTROL => 16#01_2050# / Register_Width,
998 CTX_SIZE => 16#00_21a0# / Register_Width,
999 GAC_ECO_BITS => 16#01_4090# / Register_Width,
1000 GAM_ECOCHK => 16#00_4090# / Register_Width,
1001 QUIRK_02084 => 16#00_2084# / Register_Width,
1002 QUIRK_02090 => 16#00_2090# / Register_Width,
1003 GT_MODE => 16#00_20d0# / Register_Width,
1004 QUIRK_F0060 => 16#0f_0060# / Register_Width,
1005 QUIRK_F1060 => 16#0f_1060# / Register_Width,
1006 QUIRK_F2060 => 16#0f_2060# / Register_Width,
1007 AUD_CNTRL_ST2 => 16#0e_50c0# / Register_Width,
1008 AUD_CNTL_ST_A => 16#0e_50b4# / Register_Width,
1009 AUD_CNTL_ST_B => 16#0e_51b4# / Register_Width,
1010 AUD_CNTL_ST_C => 16#0e_52b4# / Register_Width,
1011 AUD_HDMIW_HDMIEDID_A => 16#0e_5050# / Register_Width,
1012 AUD_HDMIW_HDMIEDID_B => 16#0e_5150# / Register_Width,
1013 AUD_HDMIW_HDMIEDID_C => 16#0e_5250# / Register_Width,
1014 AUD_CONFIG_A => 16#0e_5000# / Register_Width,
1015 AUD_CONFIG_B => 16#0e_5100# / Register_Width,
1016 AUD_CONFIG_C => 16#0e_5200# / Register_Width,
1017 TRANS_DP_CTL_A => 16#0e_0300# / Register_Width,
1018 TRANS_DP_CTL_B => 16#0e_1300# / Register_Width,
1019 TRANS_DP_CTL_C => 16#0e_2300# / Register_Width,
1020 TRANS_VSYNCSHIFT_A => 16#0e_0028# / Register_Width,
1021 TRANS_VSYNCSHIFT_B => 16#0e_1028# / Register_Width,
1022 TRANS_VSYNCSHIFT_C => 16#0e_2028# / Register_Width,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]1023 PCH_RAWCLK_FREQ => 16#0c_6204# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1024 QUIRK_C2004 => 16#0c_2004# / Register_Width);
1025
1026 subtype Registers_Index is Registers_Invalid_Index range
1027 Registers_Invalid_Index'Succ (Invalid_Register) ..
1028 Registers_Invalid_Index'Last;
1029
1030 -- aliased registers
1031 DP_CTL_A : constant Registers_Index := DDI_BUF_CTL_A;
1032 DP_AUX_CTL_A : constant Registers_Index := DDI_AUX_CTL_A;
1033 DP_AUX_DATA_A_1 : constant Registers_Index := DDI_AUX_DATA_A_1;
1034 DP_AUX_DATA_A_2 : constant Registers_Index := DDI_AUX_DATA_A_2;
1035 DP_AUX_DATA_A_3 : constant Registers_Index := DDI_AUX_DATA_A_3;
1036 DP_AUX_DATA_A_4 : constant Registers_Index := DDI_AUX_DATA_A_4;
1037 DP_AUX_DATA_A_5 : constant Registers_Index := DDI_AUX_DATA_A_5;
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1038 ILK_DISPLAY_CHICKEN1 : constant Registers_Index := FUSE_STATUS;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1039
1040 ---------------------------------------------------------------------------
1041
1042 Default_Timeout_MS : constant := 10;
1043
1044 ---------------------------------------------------------------------------
1045
1046 procedure Posting_Read
1047 (Register : in Registers_Index)
1048 with
1049 Global => (In_Out => Register_State),
1050 Depends => (Register_State =>+ (Register)),
1051 Pre => True,
1052 Post => True;
1053
1054 pragma Warnings (GNATprove, Off, "unused variable ""Verbose""",
1055 Reason => "Only used on debugging path");
1056 procedure Read
1057 (Register : in Registers_Index;
1058 Value : out Word32;
1059 Verbose : in Boolean := True)
1060 with
1061 Global => (In_Out => Register_State),
1062 Depends => ((Value, Register_State) => (Register, Register_State),
1063 null => Verbose),
1064 Pre => True,
1065 Post => True;
1066 pragma Warnings (GNATprove, On, "unused variable ""Verbose""");
1067
1068 procedure Write
1069 (Register : Registers_Index;
1070 Value : Word32)
1071 with
1072 Global => (In_Out => Register_State),
1073 Depends => (Register_State => (Register, Register_State, Value)),
1074 Pre => True,
1075 Post => True;
1076
1077 procedure Is_Set_Mask
1078 (Register : in Registers_Index;
1079 Mask : in Word32;
1080 Result : out Boolean);
1081
1082 pragma Warnings (GNATprove, Off, "unused initial value of ""Verbose""",
1083 Reason => "Only used on debugging path");
Nico Huberbcb2c472017-02-02 16:39:26 +0100[diff] [blame]1084 procedure Wait
1085 (Register : Registers_Index;
1086 Mask : Word32;
1087 Value : Word32;
1088 TOut_MS : Natural := Default_Timeout_MS;
1089 Verbose : Boolean := False);
1090
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1091 procedure Wait_Set_Mask
1092 (Register : Registers_Index;
1093 Mask : Word32;
1094 TOut_MS : Natural := Default_Timeout_MS;
1095 Verbose : Boolean := False);
1096
1097 procedure Wait_Unset_Mask
1098 (Register : Registers_Index;
1099 Mask : Word32;
1100 TOut_MS : Natural := Default_Timeout_MS;
1101 Verbose : Boolean := False);
1102 pragma Warnings (GNATprove, On, "unused initial value of ""Verbose""");
1103
1104 procedure Set_Mask
1105 (Register : Registers_Index;
1106 Mask : Word32);
1107
1108 procedure Unset_Mask
1109 (Register : Registers_Index;
1110 Mask : Word32);
1111
1112 procedure Unset_And_Set_Mask
1113 (Register : Registers_Index;
1114 Mask_Unset : Word32;
1115 Mask_Set : Word32);
1116
1117 pragma Warnings (Off, "declaration of ""Write_GTT"" hides one at *");
1118 procedure Write_GTT
1119 (GTT_Page : GTT_Range;
1120 Device_Address : GTT_Address_Type;
1121 Valid : Boolean)
1122 with
1123 Global => (In_Out => GTT_State),
1124 Depends => (GTT_State =>+ (GTT_Page, Device_Address, Valid)),
1125 Pre => True,
1126 Post => True;
1127 pragma Warnings (On, "declaration of ""Write_GTT"" hides one at *");
1128
1129 procedure Set_Register_Base (Base : Word64)
1130 with
1131 Global => (Output => Address_State),
1132 Depends => (Address_State => Base),
1133 Pre => True,
1134 Post => True;
1135
1136end HW.GFX.GMA.Registers;