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review.sourcearcade.org / libgfxinit / f6266004f9c8dcbb7493b409de02048ef209387e / . / common / hw-gfx-gma-registers.ads
blob: cb558d72a266a8278eaf795db5769846be4b5e05 [file] [log] [blame]
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1--
2-- Copyright (C) 2015-2016 secunet Security Networks AG
3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
Nico Huber125a29e2016-10-18 00:23:54 +0200[diff] [blame]6-- the Free Software Foundation; either version 2 of the License, or
7-- (at your option) any later version.
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]8--
9-- This program is distributed in the hope that it will be useful,
10-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12-- GNU General Public License for more details.
13--
14
15with System;
16with HW.GFX.GMA;
17with HW.GFX.GMA.Config;
18
19private package HW.GFX.GMA.Registers
20with
21 Abstract_State =>
22 ((Address_State with Part_Of => GMA.State),
23 (Register_State with External, Part_Of => GMA.Device_State),
24 (GTT_State with External, Part_Of => GMA.Device_State)),
25 Initializes => Address_State
26is
27 type Registers_Invalid_Index is
28 (Invalid_Register, -- Allow a placeholder when access is not acceptable
29
30 RCS_RING_BUFFER_TAIL,
31 RCS_RING_BUFFER_HEAD,
32 RCS_RING_BUFFER_STRT,
33 RCS_RING_BUFFER_CTL,
34 QUIRK_02084,
35 QUIRK_02090,
36 HWSTAM,
37 MI_MODE,
38 INSTPM,
39 GT_MODE,
40 CACHE_MODE_0,
41 CTX_SIZE,
42 PP_DCLV_HIGH,
43 PP_DCLV_LOW,
44 GFX_MODE,
45 ARB_MODE,
46 HWS_PGA,
47 GAM_ECOCHK,
48 MBCTL,
49 UCGCTL1,
50 UCGCTL2,
51 VCS_RING_BUFFER_TAIL,
52 VCS_RING_BUFFER_HEAD,
53 VCS_RING_BUFFER_STRT,
54 VCS_RING_BUFFER_CTL,
55 SLEEP_PSMI_CONTROL,
56 VCS_HWSTAM,
57 VCS_PP_DCLV_HIGH,
58 VCS_PP_DCLV_LOW,
59 GAC_ECO_BITS,
60 BCS_RING_BUFFER_TAIL,
61 BCS_RING_BUFFER_HEAD,
62 BCS_RING_BUFFER_STRT,
63 BCS_RING_BUFFER_CTL,
64 BCS_HWSTAM,
65 BCS_PP_DCLV_HIGH,
66 BCS_PP_DCLV_LOW,
67 GAB_CTL_REG,
68 VGACNTRL,
69 FUSE_STATUS,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]70 ILK_DISPLAY_CHICKEN2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]71 DSPCLK_GATE_D,
72 FBA_CFB_BASE,
73 FBC_CTL,
74 IPS_CTL,
75 DEISR,
76 DEIMR,
77 DEIIR,
78 DEIER,
79 GTISR,
80 GTIMR,
81 GTIIR,
82 GTIER,
83 IIR,
84 HOTPLUG_CTL,
85 ARB_CTL,
86 DBUF_CTL,
87 WM_PIPE_A,
88 WM_PIPE_B,
89 WM1_LP_ILK,
90 WM2_LP_ILK,
91 WM3_LP_ILK,
92 WM_PIPE_C,
93 WM_LINETIME_A,
94 WM_LINETIME_B,
95 WM_LINETIME_C,
96 PWR_WELL_CTL_BIOS,
97 PWR_WELL_CTL_DRIVER,
98 PWR_WELL_CTL_KVMR,
99 PWR_WELL_CTL_DEBUG,
100 PWR_WELL_CTL5,
101 PWR_WELL_CTL6,
102 CDCLK_CTL,
103 LCPLL1_CTL,
104 LCPLL2_CTL,
105 SPLL_CTL,
106 WRPLL_CTL_1,
107 WRPLL_CTL_2,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]108 BXT_DE_PLL_ENABLE,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]109 PORT_CLK_SEL_DDIA,
110 PORT_CLK_SEL_DDIB,
111 PORT_CLK_SEL_DDIC,
112 PORT_CLK_SEL_DDID,
113 PORT_CLK_SEL_DDIE,
114 TRANSA_CLK_SEL,
115 TRANSB_CLK_SEL,
116 TRANSC_CLK_SEL,
117 NDE_RSTWRN_OPT,
118 BLC_PWM_CPU_CTL2,
119 BLC_PWM_CPU_CTL,
120 HTOTAL_A,
121 HBLANK_A,
122 HSYNC_A,
123 VTOTAL_A,
124 VBLANK_A,
125 VSYNC_A,
126 PIPEASRC,
127 PIPE_VSYNCSHIFT_A,
128 PIPEA_DATA_M1,
129 PIPEA_DATA_N1,
130 PIPEA_LINK_M1,
131 PIPEA_LINK_N1,
132 FDI_TX_CTL_A,
133 PIPEA_DDI_FUNC_CTL,
134 PIPEA_MSA_MISC,
135 SRD_CTL_A,
136 SRD_STATUS_A,
137 HTOTAL_B,
138 HBLANK_B,
139 HSYNC_B,
140 VTOTAL_B,
141 VBLANK_B,
142 VSYNC_B,
143 PIPEBSRC,
144 PIPE_VSYNCSHIFT_B,
145 PIPEB_DATA_M1,
146 PIPEB_DATA_N1,
147 PIPEB_LINK_M1,
148 PIPEB_LINK_N1,
149 FDI_TX_CTL_B,
150 PIPEB_DDI_FUNC_CTL,
151 PIPEB_MSA_MISC,
152 SRD_CTL_B,
153 SRD_STATUS_B,
154 HTOTAL_C,
155 HBLANK_C,
156 HSYNC_C,
157 VTOTAL_C,
158 VBLANK_C,
159 VSYNC_C,
160 PIPECSRC,
161 PIPE_VSYNCSHIFT_C,
162 PIPEC_DATA_M1,
163 PIPEC_DATA_N1,
164 PIPEC_LINK_M1,
165 PIPEC_LINK_N1,
166 FDI_TX_CTL_C,
167 PIPEC_DDI_FUNC_CTL,
168 PIPEC_MSA_MISC,
169 SRD_CTL_C,
170 SRD_STATUS_C,
171 DDI_BUF_CTL_A,
172 DDI_AUX_CTL_A,
173 DDI_AUX_DATA_A_1,
174 DDI_AUX_DATA_A_2,
175 DDI_AUX_DATA_A_3,
176 DDI_AUX_DATA_A_4,
177 DDI_AUX_DATA_A_5,
178 DDI_AUX_MUTEX_A,
179 DP_TP_CTL_A,
180 DDI_BUF_CTL_B,
181 DDI_AUX_CTL_B,
182 DDI_AUX_DATA_B_1,
183 DDI_AUX_DATA_B_2,
184 DDI_AUX_DATA_B_3,
185 DDI_AUX_DATA_B_4,
186 DDI_AUX_DATA_B_5,
187 DDI_AUX_MUTEX_B,
188 DP_TP_CTL_B,
189 DP_TP_STATUS_B,
190 DDI_BUF_CTL_C,
191 DDI_AUX_CTL_C,
192 DDI_AUX_DATA_C_1,
193 DDI_AUX_DATA_C_2,
194 DDI_AUX_DATA_C_3,
195 DDI_AUX_DATA_C_4,
196 DDI_AUX_DATA_C_5,
197 DDI_AUX_MUTEX_C,
198 DP_TP_CTL_C,
199 DP_TP_STATUS_C,
200 DDI_BUF_CTL_D,
201 DDI_AUX_CTL_D,
202 DDI_AUX_DATA_D_1,
203 DDI_AUX_DATA_D_2,
204 DDI_AUX_DATA_D_3,
205 DDI_AUX_DATA_D_4,
206 DDI_AUX_DATA_D_5,
207 DDI_AUX_MUTEX_D,
208 DP_TP_CTL_D,
209 DP_TP_STATUS_D,
210 DDI_BUF_CTL_E,
211 DP_TP_CTL_E,
212 DP_TP_STATUS_E,
213 SRD_CTL,
214 SRD_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame^]215 BXT_PHY_CTL_A,
216 BXT_PHY_CTL_B,
217 BXT_PHY_CTL_C,
218 BXT_PHY_CTL_FAM_EDP,
219 BXT_PHY_CTL_FAM_DDI,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]220 AUD_VID_DID,
221 PFA_WIN_POS,
222 PFA_WIN_SZ,
223 PFA_CTL_1,
224 PS_WIN_POS_1_A,
225 PS_WIN_SZ_1_A,
226 PS_CTRL_1_A,
227 PS_WIN_POS_2_A,
228 PS_WIN_SZ_2_A,
229 PS_CTRL_2_A,
230 PFB_WIN_POS,
231 PFB_WIN_SZ,
232 PFB_CTL_1,
233 PS_WIN_POS_1_B,
234 PS_WIN_SZ_1_B,
235 PS_CTRL_1_B,
236 PS_WIN_POS_2_B,
237 PS_WIN_SZ_2_B,
238 PS_CTRL_2_B,
239 PFC_WIN_POS,
240 PFC_WIN_SZ,
241 PFC_CTL_1,
242 PS_WIN_POS_1_C,
243 PS_WIN_SZ_1_C,
244 PS_CTRL_1_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame^]245 BXT_PORT_CL1CM_DW0_BC,
246 BXT_PORT_CL1CM_DW9_BC,
247 BXT_PORT_CL1CM_DW10_BC,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]248 DPLL1_CFGR1,
249 DPLL1_CFGR2,
250 DPLL2_CFGR1,
251 DPLL2_CFGR2,
252 DPLL3_CFGR1,
253 DPLL3_CFGR2,
254 DPLL_CTRL1,
255 DPLL_CTRL2,
256 DPLL_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame^]257 BXT_PORT_CL1CM_DW28_BC,
258 BXT_PORT_CL1CM_DW30_BC,
259 BXT_PORT_REF_DW3_BC,
260 BXT_PORT_REF_DW6_BC,
261 BXT_PORT_REF_DW8_BC,
262 BXT_PORT_CL2CM_DW6_BC,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]263 BXT_DE_PLL_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]264 HTOTAL_EDP,
265 HBLANK_EDP,
266 HSYNC_EDP,
267 VTOTAL_EDP,
268 VBLANK_EDP,
269 VSYNC_EDP,
270 PIPE_EDP_DATA_M1,
271 PIPE_EDP_DATA_N1,
272 PIPE_EDP_LINK_M1,
273 PIPE_EDP_LINK_N1,
274 PIPE_EDP_DDI_FUNC_CTL,
275 PIPE_EDP_MSA_MISC,
276 SRD_CTL_EDP,
277 SRD_STATUS_EDP,
278 PIPE_SCANLINE_A,
279 PIPEACONF,
280 PIPEAMISC,
281 PIPE_FRMCNT_A,
282 DSPACNTR,
283 DSPALINOFF,
284 DSPASTRIDE,
285 PLANE_POS_1_A,
286 PLANE_SIZE_1_A,
287 DSPASURF,
288 DSPATILEOFF,
289 PLANE_WM_1_A_0,
290 PLANE_WM_1_A_1,
291 PLANE_WM_1_A_2,
292 PLANE_WM_1_A_3,
293 PLANE_WM_1_A_4,
294 PLANE_WM_1_A_5,
295 PLANE_WM_1_A_6,
296 PLANE_WM_1_A_7,
297 PLANE_BUF_CFG_1_A,
298 SPACNTR,
299 PIPE_SCANLINE_B,
300 PIPEBCONF,
301 PIPEBMISC,
302 PIPE_FRMCNT_B,
303 DSPBCNTR,
304 DSPBLINOFF,
305 DSPBSTRIDE,
306 PLANE_POS_1_B,
307 PLANE_SIZE_1_B,
308 DSPBSURF,
309 DSPBTILEOFF,
310 PLANE_WM_1_B_0,
311 PLANE_WM_1_B_1,
312 PLANE_WM_1_B_2,
313 PLANE_WM_1_B_3,
314 PLANE_WM_1_B_4,
315 PLANE_WM_1_B_5,
316 PLANE_WM_1_B_6,
317 PLANE_WM_1_B_7,
318 PLANE_BUF_CFG_1_B,
319 SPBCNTR,
320 PIPE_SCANLINE_C,
321 PIPECCONF,
322 PIPECMISC,
323 PIPE_FRMCNT_C,
324 DSPCCNTR,
325 DSPCLINOFF,
326 DSPCSTRIDE,
327 PLANE_POS_1_C,
328 PLANE_SIZE_1_C,
329 DSPCSURF,
330 DSPCTILEOFF,
331 PLANE_WM_1_C_0,
332 PLANE_WM_1_C_1,
333 PLANE_WM_1_C_2,
334 PLANE_WM_1_C_3,
335 PLANE_WM_1_C_4,
336 PLANE_WM_1_C_5,
337 PLANE_WM_1_C_6,
338 PLANE_WM_1_C_7,
339 PLANE_BUF_CFG_1_C,
340 SPCCNTR,
341 PIPE_EDP_CONF,
342 PCH_FDI_CHICKEN_B_C,
343 QUIRK_C2004,
344 SFUSE_STRAP,
345 PCH_DSPCLK_GATE_D,
346 SDEISR,
347 SDEIMR,
348 SDEIIR,
349 SDEIER,
350 SHOTPLUG_CTL,
351 PCH_GMBUS0,
352 PCH_GMBUS1,
353 PCH_GMBUS2,
354 PCH_GMBUS3,
355 PCH_GMBUS4,
356 PCH_GMBUS5,
357 SBI_ADDR,
358 SBI_DATA,
359 SBI_CTL_STAT,
360 PCH_DPLL_A,
361 PCH_DPLL_B,
362 PCH_PIXCLK_GATE,
363 PCH_FPA0,
364 PCH_FPA1,
365 PCH_FPB0,
366 PCH_FPB1,
367 PCH_DREF_CONTROL,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]368 PCH_RAWCLK_FREQ,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]369 PCH_DPLL_SEL,
370 PCH_PP_STATUS,
371 PCH_PP_CONTROL,
372 PCH_PP_ON_DELAYS,
373 PCH_PP_OFF_DELAYS,
374 PCH_PP_DIVISOR,
375 BLC_PWM_PCH_CTL1,
376 BLC_PWM_PCH_CTL2,
377 TRANS_HTOTAL_A,
378 TRANS_HBLANK_A,
379 TRANS_HSYNC_A,
380 TRANS_VTOTAL_A,
381 TRANS_VBLANK_A,
382 TRANS_VSYNC_A,
383 TRANS_VSYNCSHIFT_A,
384 TRANSA_DATA_M1,
385 TRANSA_DATA_N1,
386 TRANSA_DP_LINK_M1,
387 TRANSA_DP_LINK_N1,
388 TRANS_DP_CTL_A,
389 TRANS_HTOTAL_B,
390 TRANS_HBLANK_B,
391 TRANS_HSYNC_B,
392 TRANS_VTOTAL_B,
393 TRANS_VBLANK_B,
394 TRANS_VSYNC_B,
395 TRANS_VSYNCSHIFT_B,
396 TRANSB_DATA_M1,
397 TRANSB_DATA_N1,
398 TRANSB_DP_LINK_M1,
399 TRANSB_DP_LINK_N1,
400 PCH_ADPA,
401 PCH_HDMIB,
402 PCH_HDMIC,
403 PCH_HDMID,
404 PCH_LVDS,
405 TRANS_DP_CTL_B,
406 TRANS_HTOTAL_C,
407 TRANS_HBLANK_C,
408 TRANS_HSYNC_C,
409 TRANS_VTOTAL_C,
410 TRANS_VBLANK_C,
411 TRANS_VSYNC_C,
412 TRANS_VSYNCSHIFT_C,
413 TRANSC_DATA_M1,
414 TRANSC_DATA_N1,
415 TRANSC_DP_LINK_M1,
416 TRANSC_DP_LINK_N1,
417 TRANS_DP_CTL_C,
418 PCH_DP_B,
419 PCH_DP_AUX_CTL_B,
420 PCH_DP_AUX_DATA_B_1,
421 PCH_DP_AUX_DATA_B_2,
422 PCH_DP_AUX_DATA_B_3,
423 PCH_DP_AUX_DATA_B_4,
424 PCH_DP_AUX_DATA_B_5,
425 PCH_DP_C,
426 PCH_DP_AUX_CTL_C,
427 PCH_DP_AUX_DATA_C_1,
428 PCH_DP_AUX_DATA_C_2,
429 PCH_DP_AUX_DATA_C_3,
430 PCH_DP_AUX_DATA_C_4,
431 PCH_DP_AUX_DATA_C_5,
432 PCH_DP_D,
433 PCH_DP_AUX_CTL_D,
434 PCH_DP_AUX_DATA_D_1,
435 PCH_DP_AUX_DATA_D_2,
436 PCH_DP_AUX_DATA_D_3,
437 PCH_DP_AUX_DATA_D_4,
438 PCH_DP_AUX_DATA_D_5,
439 AUD_CONFIG_A,
440 PCH_AUD_VID_DID,
441 AUD_HDMIW_HDMIEDID_A,
442 AUD_CNTL_ST_A,
443 AUD_CNTRL_ST2,
444 AUD_CONFIG_B,
445 AUD_HDMIW_HDMIEDID_B,
446 AUD_CNTL_ST_B,
447 AUD_CONFIG_C,
448 AUD_HDMIW_HDMIEDID_C,
449 AUD_CNTL_ST_C,
450 TRANSACONF,
451 FDI_RXA_CTL,
452 FDI_RX_MISC_A,
453 FDI_RXA_IIR,
454 FDI_RXA_IMR,
455 FDI_RXA_TUSIZE1,
456 QUIRK_F0060,
457 TRANSA_CHICKEN2,
458 TRANSBCONF,
459 FDI_RXB_CTL,
460 FDI_RX_MISC_B,
461 FDI_RXB_IIR,
462 FDI_RXB_IMR,
463 FDI_RXB_TUSIZE1,
464 QUIRK_F1060,
465 TRANSB_CHICKEN2,
466 TRANSCCONF,
467 FDI_RXC_CTL,
468 FDI_RX_MISC_C,
469 FDI_RXC_IIR,
470 FDI_RXC_IMR,
471 FDI_RXC_TUSIZE1,
472 QUIRK_F2060,
473 TRANSC_CHICKEN2,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame^]474 BXT_P_CR_GT_DISP_PWRON,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]475 GT_MAILBOX,
476 GT_MAILBOX_DATA,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame^]477 GT_MAILBOX_DATA_1,
478 BXT_PORT_CL1CM_DW0_A,
479 BXT_PORT_CL1CM_DW9_A,
480 BXT_PORT_CL1CM_DW10_A,
481 BXT_PORT_CL1CM_DW28_A,
482 BXT_PORT_CL1CM_DW30_A,
483 BXT_PORT_REF_DW3_A,
484 BXT_PORT_REF_DW6_A,
485 BXT_PORT_REF_DW8_A);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]486
487 pragma Warnings
488 (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)",
489 Reason => "TODO: Should it matter?");
490 pragma Keep_Names (Registers_Invalid_Index);
491 pragma Warnings
492 (GNATprove, On, "pragma ""KEEP_NAMES"" ignored *(not yet supported)");
493
494 Register_Width : constant := 4;
495
496 for Registers_Invalid_Index use
497 (Invalid_Register => 0,
498
499 ---------------------------------------------------------------------------
500 -- Pipe A registers
501 ---------------------------------------------------------------------------
502
503 -- pipe timing registers
504
505 HTOTAL_A => 16#06_0000# / Register_Width,
506 HBLANK_A => 16#06_0004# / Register_Width,
507 HSYNC_A => 16#06_0008# / Register_Width,
508 VTOTAL_A => 16#06_000c# / Register_Width,
509 VBLANK_A => 16#06_0010# / Register_Width,
510 VSYNC_A => 16#06_0014# / Register_Width,
511 PIPEASRC => 16#06_001c# / Register_Width,
512 PIPEACONF => 16#07_0008# / Register_Width,
513 PIPEAMISC => 16#07_0030# / Register_Width,
514 TRANS_HTOTAL_A => 16#0e_0000# / Register_Width,
515 TRANS_HBLANK_A => 16#0e_0004# / Register_Width,
516 TRANS_HSYNC_A => 16#0e_0008# / Register_Width,
517 TRANS_VTOTAL_A => 16#0e_000c# / Register_Width,
518 TRANS_VBLANK_A => 16#0e_0010# / Register_Width,
519 TRANS_VSYNC_A => 16#0e_0014# / Register_Width,
520 TRANSA_DATA_M1 => 16#0e_0030# / Register_Width,
521 TRANSA_DATA_N1 => 16#0e_0034# / Register_Width,
522 TRANSA_DP_LINK_M1 => 16#0e_0040# / Register_Width,
523 TRANSA_DP_LINK_N1 => 16#0e_0044# / Register_Width,
524 PIPEA_DATA_M1 => 16#06_0030# / Register_Width,
525 PIPEA_DATA_N1 => 16#06_0034# / Register_Width,
526 PIPEA_LINK_M1 => 16#06_0040# / Register_Width,
527 PIPEA_LINK_N1 => 16#06_0044# / Register_Width,
528 PIPEA_DDI_FUNC_CTL => 16#06_0400# / Register_Width,
529 PIPEA_MSA_MISC => 16#06_0410# / Register_Width,
530
531 -- PCH sideband interface registers
532 SBI_ADDR => 16#0c_6000# / Register_Width,
533 SBI_DATA => 16#0c_6004# / Register_Width,
534 SBI_CTL_STAT => 16#0c_6008# / Register_Width,
535
536 -- clock registers
537 PCH_DPLL_A => 16#0c_6014# / Register_Width,
538 PCH_PIXCLK_GATE => 16#0c_6020# / Register_Width,
539 PCH_FPA0 => 16#0c_6040# / Register_Width,
540 PCH_FPA1 => 16#0c_6044# / Register_Width,
541
542 -- panel fitter
543 PFA_CTL_1 => 16#06_8080# / Register_Width,
544 PFA_WIN_POS => 16#06_8070# / Register_Width,
545 PFA_WIN_SZ => 16#06_8074# / Register_Width,
546 PS_WIN_POS_1_A => 16#06_8170# / Register_Width,
547 PS_WIN_SZ_1_A => 16#06_8174# / Register_Width,
548 PS_CTRL_1_A => 16#06_8180# / Register_Width,
549 PS_WIN_POS_2_A => 16#06_8270# / Register_Width,
550 PS_WIN_SZ_2_A => 16#06_8274# / Register_Width,
551 PS_CTRL_2_A => 16#06_8280# / Register_Width,
552
553 -- display control
554 DSPACNTR => 16#07_0180# / Register_Width,
555 DSPALINOFF => 16#07_0184# / Register_Width,
556 DSPASTRIDE => 16#07_0188# / Register_Width,
557 PLANE_POS_1_A => 16#07_018c# / Register_Width,
558 PLANE_SIZE_1_A => 16#07_0190# / Register_Width,
559 DSPASURF => 16#07_019c# / Register_Width,
560 DSPATILEOFF => 16#07_01a4# / Register_Width,
561
562 -- sprite control
563 SPACNTR => 16#07_0280# / Register_Width,
564
565 -- FDI and PCH transcoder control
566 FDI_TX_CTL_A => 16#06_0100# / Register_Width,
567 FDI_RXA_CTL => 16#0f_000c# / Register_Width,
568 FDI_RX_MISC_A => 16#0f_0010# / Register_Width,
569 FDI_RXA_IIR => 16#0f_0014# / Register_Width,
570 FDI_RXA_IMR => 16#0f_0018# / Register_Width,
571 FDI_RXA_TUSIZE1 => 16#0f_0030# / Register_Width,
572 TRANSACONF => 16#0f_0008# / Register_Width,
573 TRANSA_CHICKEN2 => 16#0f_0064# / Register_Width,
574
575 -- watermark registers
576 WM_LINETIME_A => 16#04_5270# / Register_Width,
577 PLANE_WM_1_A_0 => 16#07_0240# / Register_Width,
578 PLANE_WM_1_A_1 => 16#07_0244# / Register_Width,
579 PLANE_WM_1_A_2 => 16#07_0248# / Register_Width,
580 PLANE_WM_1_A_3 => 16#07_024c# / Register_Width,
581 PLANE_WM_1_A_4 => 16#07_0250# / Register_Width,
582 PLANE_WM_1_A_5 => 16#07_0254# / Register_Width,
583 PLANE_WM_1_A_6 => 16#07_0258# / Register_Width,
584 PLANE_WM_1_A_7 => 16#07_025c# / Register_Width,
585 PLANE_BUF_CFG_1_A => 16#07_027c# / Register_Width,
586
587 -- CPU transcoder clock select
588 TRANSA_CLK_SEL => 16#04_6140# / Register_Width,
589
590 ---------------------------------------------------------------------------
591 -- Pipe B registers
592 ---------------------------------------------------------------------------
593
594 -- pipe timing registers
595
596 HTOTAL_B => 16#06_1000# / Register_Width,
597 HBLANK_B => 16#06_1004# / Register_Width,
598 HSYNC_B => 16#06_1008# / Register_Width,
599 VTOTAL_B => 16#06_100c# / Register_Width,
600 VBLANK_B => 16#06_1010# / Register_Width,
601 VSYNC_B => 16#06_1014# / Register_Width,
602 PIPEBSRC => 16#06_101c# / Register_Width,
603 PIPEBCONF => 16#07_1008# / Register_Width,
604 PIPEBMISC => 16#07_1030# / Register_Width,
605 TRANS_HTOTAL_B => 16#0e_1000# / Register_Width,
606 TRANS_HBLANK_B => 16#0e_1004# / Register_Width,
607 TRANS_HSYNC_B => 16#0e_1008# / Register_Width,
608 TRANS_VTOTAL_B => 16#0e_100c# / Register_Width,
609 TRANS_VBLANK_B => 16#0e_1010# / Register_Width,
610 TRANS_VSYNC_B => 16#0e_1014# / Register_Width,
611 TRANSB_DATA_M1 => 16#0e_1030# / Register_Width,
612 TRANSB_DATA_N1 => 16#0e_1034# / Register_Width,
613 TRANSB_DP_LINK_M1 => 16#0e_1040# / Register_Width,
614 TRANSB_DP_LINK_N1 => 16#0e_1044# / Register_Width,
615 PIPEB_DATA_M1 => 16#06_1030# / Register_Width,
616 PIPEB_DATA_N1 => 16#06_1034# / Register_Width,
617 PIPEB_LINK_M1 => 16#06_1040# / Register_Width,
618 PIPEB_LINK_N1 => 16#06_1044# / Register_Width,
619 PIPEB_DDI_FUNC_CTL => 16#06_1400# / Register_Width,
620 PIPEB_MSA_MISC => 16#06_1410# / Register_Width,
621
622 -- clock registers
623 PCH_DPLL_B => 16#0c_6018# / Register_Width,
624 PCH_FPB0 => 16#0c_6048# / Register_Width,
625 PCH_FPB1 => 16#0c_604c# / Register_Width,
626
627 -- panel fitter
628 PFB_CTL_1 => 16#06_8880# / Register_Width,
629 PFB_WIN_POS => 16#06_8870# / Register_Width,
630 PFB_WIN_SZ => 16#06_8874# / Register_Width,
631 PS_WIN_POS_1_B => 16#06_8970# / Register_Width,
632 PS_WIN_SZ_1_B => 16#06_8974# / Register_Width,
633 PS_CTRL_1_B => 16#06_8980# / Register_Width,
634 PS_WIN_POS_2_B => 16#06_8a70# / Register_Width,
635 PS_WIN_SZ_2_B => 16#06_8a74# / Register_Width,
636 PS_CTRL_2_B => 16#06_8a80# / Register_Width,
637
638 -- display control
639 DSPBCNTR => 16#07_1180# / Register_Width,
640 DSPBLINOFF => 16#07_1184# / Register_Width,
641 DSPBSTRIDE => 16#07_1188# / Register_Width,
642 PLANE_POS_1_B => 16#07_118c# / Register_Width,
643 PLANE_SIZE_1_B => 16#07_1190# / Register_Width,
644 DSPBSURF => 16#07_119c# / Register_Width,
645 DSPBTILEOFF => 16#07_11a4# / Register_Width,
646
647 -- sprite control
648 SPBCNTR => 16#07_1280# / Register_Width,
649
650 -- FDI and PCH transcoder control
651 FDI_TX_CTL_B => 16#06_1100# / Register_Width,
652 FDI_RXB_CTL => 16#0f_100c# / Register_Width,
653 FDI_RX_MISC_B => 16#0f_1010# / Register_Width,
654 FDI_RXB_IIR => 16#0f_1014# / Register_Width,
655 FDI_RXB_IMR => 16#0f_1018# / Register_Width,
656 FDI_RXB_TUSIZE1 => 16#0f_1030# / Register_Width,
657 TRANSBCONF => 16#0f_1008# / Register_Width,
658 TRANSB_CHICKEN2 => 16#0f_1064# / Register_Width,
659
660 -- watermark registers
661 WM_LINETIME_B => 16#04_5274# / Register_Width,
662 PLANE_WM_1_B_0 => 16#07_1240# / Register_Width,
663 PLANE_WM_1_B_1 => 16#07_1244# / Register_Width,
664 PLANE_WM_1_B_2 => 16#07_1248# / Register_Width,
665 PLANE_WM_1_B_3 => 16#07_124c# / Register_Width,
666 PLANE_WM_1_B_4 => 16#07_1250# / Register_Width,
667 PLANE_WM_1_B_5 => 16#07_1254# / Register_Width,
668 PLANE_WM_1_B_6 => 16#07_1258# / Register_Width,
669 PLANE_WM_1_B_7 => 16#07_125c# / Register_Width,
670 PLANE_BUF_CFG_1_B => 16#07_127c# / Register_Width,
671
672 -- CPU transcoder clock select
673 TRANSB_CLK_SEL => 16#04_6144# / Register_Width,
674
675 ---------------------------------------------------------------------------
676 -- Pipe C registers
677 ---------------------------------------------------------------------------
678
679 -- pipe timing registers
680
681 HTOTAL_C => 16#06_2000# / Register_Width,
682 HBLANK_C => 16#06_2004# / Register_Width,
683 HSYNC_C => 16#06_2008# / Register_Width,
684 VTOTAL_C => 16#06_200c# / Register_Width,
685 VBLANK_C => 16#06_2010# / Register_Width,
686 VSYNC_C => 16#06_2014# / Register_Width,
687 PIPECSRC => 16#06_201c# / Register_Width,
688 PIPECCONF => 16#07_2008# / Register_Width,
689 PIPECMISC => 16#07_2030# / Register_Width,
690 TRANS_HTOTAL_C => 16#0e_2000# / Register_Width,
691 TRANS_HBLANK_C => 16#0e_2004# / Register_Width,
692 TRANS_HSYNC_C => 16#0e_2008# / Register_Width,
693 TRANS_VTOTAL_C => 16#0e_200c# / Register_Width,
694 TRANS_VBLANK_C => 16#0e_2010# / Register_Width,
695 TRANS_VSYNC_C => 16#0e_2014# / Register_Width,
696 TRANSC_DATA_M1 => 16#0e_2030# / Register_Width,
697 TRANSC_DATA_N1 => 16#0e_2034# / Register_Width,
698 TRANSC_DP_LINK_M1 => 16#0e_2040# / Register_Width,
699 TRANSC_DP_LINK_N1 => 16#0e_2044# / Register_Width,
700 PIPEC_DATA_M1 => 16#06_2030# / Register_Width,
701 PIPEC_DATA_N1 => 16#06_2034# / Register_Width,
702 PIPEC_LINK_M1 => 16#06_2040# / Register_Width,
703 PIPEC_LINK_N1 => 16#06_2044# / Register_Width,
704 PIPEC_DDI_FUNC_CTL => 16#06_2400# / Register_Width,
705 PIPEC_MSA_MISC => 16#06_2410# / Register_Width,
706
707 -- panel fitter
708 PFC_CTL_1 => 16#06_9080# / Register_Width,
709 PFC_WIN_POS => 16#06_9070# / Register_Width,
710 PFC_WIN_SZ => 16#06_9074# / Register_Width,
711 PS_WIN_POS_1_C => 16#06_9170# / Register_Width,
712 PS_WIN_SZ_1_C => 16#06_9174# / Register_Width,
713 PS_CTRL_1_C => 16#06_9180# / Register_Width,
714
715 -- display control
716 DSPCCNTR => 16#07_2180# / Register_Width,
717 DSPCLINOFF => 16#07_2184# / Register_Width,
718 DSPCSTRIDE => 16#07_2188# / Register_Width,
719 PLANE_POS_1_C => 16#07_218c# / Register_Width,
720 PLANE_SIZE_1_C => 16#07_2190# / Register_Width,
721 DSPCSURF => 16#07_219c# / Register_Width,
722 DSPCTILEOFF => 16#07_21a4# / Register_Width,
723
724 -- sprite control
725 SPCCNTR => 16#07_2280# / Register_Width,
726
727 -- PCH transcoder control
728 FDI_TX_CTL_C => 16#06_2100# / Register_Width,
729 FDI_RXC_CTL => 16#0f_200c# / Register_Width,
730 FDI_RX_MISC_C => 16#0f_2010# / Register_Width,
731 FDI_RXC_IIR => 16#0f_2014# / Register_Width,
732 FDI_RXC_IMR => 16#0f_2018# / Register_Width,
733 FDI_RXC_TUSIZE1 => 16#0f_2030# / Register_Width,
734 TRANSCCONF => 16#0f_2008# / Register_Width,
735 TRANSC_CHICKEN2 => 16#0f_2064# / Register_Width,
736
737 -- watermark registers
738 WM_LINETIME_C => 16#04_5278# / Register_Width,
739 PLANE_WM_1_C_0 => 16#07_2240# / Register_Width,
740 PLANE_WM_1_C_1 => 16#07_2244# / Register_Width,
741 PLANE_WM_1_C_2 => 16#07_2248# / Register_Width,
742 PLANE_WM_1_C_3 => 16#07_224c# / Register_Width,
743 PLANE_WM_1_C_4 => 16#07_2250# / Register_Width,
744 PLANE_WM_1_C_5 => 16#07_2254# / Register_Width,
745 PLANE_WM_1_C_6 => 16#07_2258# / Register_Width,
746 PLANE_WM_1_C_7 => 16#07_225c# / Register_Width,
747 PLANE_BUF_CFG_1_C => 16#07_227c# / Register_Width,
748
749 -- CPU transcoder clock select
750 TRANSC_CLK_SEL => 16#04_6148# / Register_Width,
751
752 ---------------------------------------------------------------------------
753 -- Pipe EDP registers
754 ---------------------------------------------------------------------------
755
756 -- pipe timing registers
757
758 HTOTAL_EDP => 16#06_f000# / Register_Width,
759 HBLANK_EDP => 16#06_f004# / Register_Width,
760 HSYNC_EDP => 16#06_f008# / Register_Width,
761 VTOTAL_EDP => 16#06_f00c# / Register_Width,
762 VBLANK_EDP => 16#06_f010# / Register_Width,
763 VSYNC_EDP => 16#06_f014# / Register_Width,
764 PIPE_EDP_CONF => 16#07_f008# / Register_Width,
765 PIPE_EDP_DATA_M1 => 16#06_f030# / Register_Width,
766 PIPE_EDP_DATA_N1 => 16#06_f034# / Register_Width,
767 PIPE_EDP_LINK_M1 => 16#06_f040# / Register_Width,
768 PIPE_EDP_LINK_N1 => 16#06_f044# / Register_Width,
769 PIPE_EDP_DDI_FUNC_CTL => 16#06_f400# / Register_Width,
770 PIPE_EDP_MSA_MISC => 16#06_f410# / Register_Width,
771
772 -- PSR registers
773 SRD_CTL => 16#06_4800# / Register_Width,
774 SRD_CTL_A => 16#06_0800# / Register_Width,
775 SRD_CTL_B => 16#06_1800# / Register_Width,
776 SRD_CTL_C => 16#06_2800# / Register_Width,
777 SRD_CTL_EDP => 16#06_f800# / Register_Width,
778 SRD_STATUS => 16#06_4840# / Register_Width,
779 SRD_STATUS_A => 16#06_0840# / Register_Width,
780 SRD_STATUS_B => 16#06_1840# / Register_Width,
781 SRD_STATUS_C => 16#06_2840# / Register_Width,
782 SRD_STATUS_EDP => 16#06_f840# / Register_Width,
783
784 -- DDI registers
785 DDI_BUF_CTL_A => 16#06_4000# / Register_Width, -- aliased by DP_CTL_A
786 DDI_AUX_CTL_A => 16#06_4010# / Register_Width, -- aliased by DP_AUX_CTL_A
787 DDI_AUX_DATA_A_1 => 16#06_4014# / Register_Width, -- aliased by DP_AUX_DATA_A_1
788 DDI_AUX_DATA_A_2 => 16#06_4018# / Register_Width, -- aliased by DP_AUX_DATA_A_2
789 DDI_AUX_DATA_A_3 => 16#06_401c# / Register_Width, -- aliased by DP_AUX_DATA_A_3
790 DDI_AUX_DATA_A_4 => 16#06_4020# / Register_Width, -- aliased by DP_AUX_DATA_A_4
791 DDI_AUX_DATA_A_5 => 16#06_4024# / Register_Width, -- aliased by DP_AUX_DATA_A_5
792 DDI_AUX_MUTEX_A => 16#06_402c# / Register_Width,
793 DDI_BUF_CTL_B => 16#06_4100# / Register_Width,
794 DDI_AUX_CTL_B => 16#06_4110# / Register_Width,
795 DDI_AUX_DATA_B_1 => 16#06_4114# / Register_Width,
796 DDI_AUX_DATA_B_2 => 16#06_4118# / Register_Width,
797 DDI_AUX_DATA_B_3 => 16#06_411c# / Register_Width,
798 DDI_AUX_DATA_B_4 => 16#06_4120# / Register_Width,
799 DDI_AUX_DATA_B_5 => 16#06_4124# / Register_Width,
800 DDI_AUX_MUTEX_B => 16#06_412c# / Register_Width,
801 DDI_BUF_CTL_C => 16#06_4200# / Register_Width,
802 DDI_AUX_CTL_C => 16#06_4210# / Register_Width,
803 DDI_AUX_DATA_C_1 => 16#06_4214# / Register_Width,
804 DDI_AUX_DATA_C_2 => 16#06_4218# / Register_Width,
805 DDI_AUX_DATA_C_3 => 16#06_421c# / Register_Width,
806 DDI_AUX_DATA_C_4 => 16#06_4220# / Register_Width,
807 DDI_AUX_DATA_C_5 => 16#06_4224# / Register_Width,
808 DDI_AUX_MUTEX_C => 16#06_422c# / Register_Width,
809 DDI_BUF_CTL_D => 16#06_4300# / Register_Width,
810 DDI_AUX_CTL_D => 16#06_4310# / Register_Width,
811 DDI_AUX_DATA_D_1 => 16#06_4314# / Register_Width,
812 DDI_AUX_DATA_D_2 => 16#06_4318# / Register_Width,
813 DDI_AUX_DATA_D_3 => 16#06_431c# / Register_Width,
814 DDI_AUX_DATA_D_4 => 16#06_4320# / Register_Width,
815 DDI_AUX_DATA_D_5 => 16#06_4324# / Register_Width,
816 DDI_AUX_MUTEX_D => 16#06_432c# / Register_Width,
817 DDI_BUF_CTL_E => 16#06_4400# / Register_Width,
818 DP_TP_CTL_A => 16#06_4040# / Register_Width,
819 DP_TP_CTL_B => 16#06_4140# / Register_Width,
820 DP_TP_CTL_C => 16#06_4240# / Register_Width,
821 DP_TP_CTL_D => 16#06_4340# / Register_Width,
822 DP_TP_CTL_E => 16#06_4440# / Register_Width,
823 DP_TP_STATUS_B => 16#06_4144# / Register_Width,
824 DP_TP_STATUS_C => 16#06_4244# / Register_Width,
825 DP_TP_STATUS_D => 16#06_4344# / Register_Width,
826 DP_TP_STATUS_E => 16#06_4444# / Register_Width,
827 PORT_CLK_SEL_DDIA => 16#04_6100# / Register_Width,
828 PORT_CLK_SEL_DDIB => 16#04_6104# / Register_Width,
829 PORT_CLK_SEL_DDIC => 16#04_6108# / Register_Width,
830 PORT_CLK_SEL_DDID => 16#04_610c# / Register_Width,
831 PORT_CLK_SEL_DDIE => 16#04_6110# / Register_Width,
832
833 -- Skylake DPLL registers
834 DPLL1_CFGR1 => 16#06_c040# / Register_Width,
835 DPLL1_CFGR2 => 16#06_c044# / Register_Width,
836 DPLL2_CFGR1 => 16#06_c048# / Register_Width,
837 DPLL2_CFGR2 => 16#06_c04c# / Register_Width,
838 DPLL3_CFGR1 => 16#06_c050# / Register_Width,
839 DPLL3_CFGR2 => 16#06_c054# / Register_Width,
840 DPLL_CTRL1 => 16#06_c058# / Register_Width,
841 DPLL_CTRL2 => 16#06_c05c# / Register_Width,
842 DPLL_STATUS => 16#06_c060# / Register_Width,
843
844 -- CD CLK register
845 CDCLK_CTL => 16#04_6000# / Register_Width,
846
847 -- Skylake LCPLL registers
848 LCPLL1_CTL => 16#04_6010# / Register_Width,
849 LCPLL2_CTL => 16#04_6014# / Register_Width,
850
851 -- SPLL register
852 SPLL_CTL => 16#04_6020# / Register_Width,
853
854 -- WRPLL registers
855 WRPLL_CTL_1 => 16#04_6040# / Register_Width,
856 WRPLL_CTL_2 => 16#04_6060# / Register_Width,
857
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]858 -- Broxton Display Engine PLL registers
859 BXT_DE_PLL_CTL => 16#06_d000# / Register_Width,
860 BXT_DE_PLL_ENABLE => 16#04_6070# / Register_Width,
861
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame^]862 -- Broxton DDI PHY registers
863 BXT_P_CR_GT_DISP_PWRON => 16#13_8090# / Register_Width,
864 BXT_PHY_CTL_A => 16#06_4c00# / Register_Width,
865 BXT_PHY_CTL_B => 16#06_4c10# / Register_Width,
866 BXT_PHY_CTL_C => 16#06_4c20# / Register_Width,
867 BXT_PHY_CTL_FAM_EDP => 16#06_4c80# / Register_Width,
868 BXT_PHY_CTL_FAM_DDI => 16#06_4c90# / Register_Width,
869
870 -- Broxton DDI PHY common lane registers
871 BXT_PORT_CL1CM_DW0_A => 16#16_2000# / Register_Width,
872 BXT_PORT_CL1CM_DW0_BC => 16#06_c000# / Register_Width,
873 BXT_PORT_CL1CM_DW9_A => 16#16_2024# / Register_Width,
874 BXT_PORT_CL1CM_DW9_BC => 16#06_c024# / Register_Width,
875 BXT_PORT_CL1CM_DW10_A => 16#16_2028# / Register_Width,
876 BXT_PORT_CL1CM_DW10_BC => 16#06_c028# / Register_Width,
877 BXT_PORT_CL1CM_DW28_A => 16#16_2070# / Register_Width,
878 BXT_PORT_CL1CM_DW28_BC => 16#06_c070# / Register_Width,
879 BXT_PORT_CL1CM_DW30_A => 16#16_2078# / Register_Width,
880 BXT_PORT_CL1CM_DW30_BC => 16#06_c078# / Register_Width,
881 BXT_PORT_CL2CM_DW6_BC => 16#06_c358# / Register_Width,
882
883 -- Broxton DDI PHY ref registers
884 BXT_PORT_REF_DW3_A => 16#16_218c# / Register_Width,
885 BXT_PORT_REF_DW3_BC => 16#06_c18c# / Register_Width,
886 BXT_PORT_REF_DW6_A => 16#16_2198# / Register_Width,
887 BXT_PORT_REF_DW6_BC => 16#06_c198# / Register_Width,
888 BXT_PORT_REF_DW8_A => 16#16_21a0# / Register_Width,
889 BXT_PORT_REF_DW8_BC => 16#06_c1a0# / Register_Width,
890
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]891 -- Power Down Well registers
892 PWR_WELL_CTL_BIOS => 16#04_5400# / Register_Width,
893 PWR_WELL_CTL_DRIVER => 16#04_5404# / Register_Width,
894 PWR_WELL_CTL_KVMR => 16#04_5408# / Register_Width,
895 PWR_WELL_CTL_DEBUG => 16#04_540c# / Register_Width,
896 PWR_WELL_CTL5 => 16#04_5410# / Register_Width,
897 PWR_WELL_CTL6 => 16#04_5414# / Register_Width,
898
899 -- class Panel registers
900 PCH_PP_STATUS => 16#0c_7200# / Register_Width,
901 PCH_PP_CONTROL => 16#0c_7204# / Register_Width,
902 PCH_PP_ON_DELAYS => 16#0c_7208# / Register_Width,
903 PCH_PP_OFF_DELAYS => 16#0c_720c# / Register_Width,
904 PCH_PP_DIVISOR => 16#0c_7210# / Register_Width,
905 BLC_PWM_CPU_CTL => 16#04_8254# / Register_Width,
906 BLC_PWM_PCH_CTL2 => 16#0c_8254# / Register_Width,
907
908 -- PCH LVDS Connector Registers
909 PCH_LVDS => 16#0e_1180# / Register_Width,
910
911 -- PCH ADPA Connector Registers
912 PCH_ADPA => 16#0e_1100# / Register_Width,
913
914 -- PCH HDMIB Connector Registers
915 PCH_HDMIB => 16#0e_1140# / Register_Width,
916
917 -- PCH HDMIC Connector Registers
918 PCH_HDMIC => 16#0e_1150# / Register_Width,
919
920 -- PCH HDMID Connector Registers
921 PCH_HDMID => 16#0e_1160# / Register_Width,
922
923 -- Intel Registers
924 VGACNTRL => 16#04_1000# / Register_Width,
925 FUSE_STATUS => 16#04_2000# / Register_Width,
926 FBA_CFB_BASE => 16#04_3200# / Register_Width,
927 IPS_CTL => 16#04_3408# / Register_Width,
928 ARB_CTL => 16#04_5000# / Register_Width,
929 DBUF_CTL => 16#04_5008# / Register_Width,
930 NDE_RSTWRN_OPT => 16#04_6408# / Register_Width,
931 PCH_DREF_CONTROL => 16#0c_6200# / Register_Width,
932 BLC_PWM_PCH_CTL1 => 16#0c_8250# / Register_Width,
933 BLC_PWM_CPU_CTL2 => 16#04_8250# / Register_Width,
934 PCH_DPLL_SEL => 16#0c_7000# / Register_Width,
935 GT_MAILBOX => 16#13_8124# / Register_Width,
936 GT_MAILBOX_DATA => 16#13_8128# / Register_Width,
937 GT_MAILBOX_DATA_1 => 16#13_812c# / Register_Width,
938
939 PCH_DP_B => 16#0e_4100# / Register_Width,
940 PCH_DP_AUX_CTL_B => 16#0e_4110# / Register_Width,
941 PCH_DP_AUX_DATA_B_1 => 16#0e_4114# / Register_Width,
942 PCH_DP_AUX_DATA_B_2 => 16#0e_4118# / Register_Width,
943 PCH_DP_AUX_DATA_B_3 => 16#0e_411c# / Register_Width,
944 PCH_DP_AUX_DATA_B_4 => 16#0e_4120# / Register_Width,
945 PCH_DP_AUX_DATA_B_5 => 16#0e_4124# / Register_Width,
946 PCH_DP_C => 16#0e_4200# / Register_Width,
947 PCH_DP_AUX_CTL_C => 16#0e_4210# / Register_Width,
948 PCH_DP_AUX_DATA_C_1 => 16#0e_4214# / Register_Width,
949 PCH_DP_AUX_DATA_C_2 => 16#0e_4218# / Register_Width,
950 PCH_DP_AUX_DATA_C_3 => 16#0e_421c# / Register_Width,
951 PCH_DP_AUX_DATA_C_4 => 16#0e_4220# / Register_Width,
952 PCH_DP_AUX_DATA_C_5 => 16#0e_4224# / Register_Width,
953 PCH_DP_D => 16#0e_4300# / Register_Width,
954 PCH_DP_AUX_CTL_D => 16#0e_4310# / Register_Width,
955 PCH_DP_AUX_DATA_D_1 => 16#0e_4314# / Register_Width,
956 PCH_DP_AUX_DATA_D_2 => 16#0e_4318# / Register_Width,
957 PCH_DP_AUX_DATA_D_3 => 16#0e_431c# / Register_Width,
958 PCH_DP_AUX_DATA_D_4 => 16#0e_4320# / Register_Width,
959 PCH_DP_AUX_DATA_D_5 => 16#0e_4324# / Register_Width,
960
961 -- watermark registers
962 WM1_LP_ILK => 16#04_5108# / Register_Width,
963 WM2_LP_ILK => 16#04_510c# / Register_Width,
964 WM3_LP_ILK => 16#04_5110# / Register_Width,
965
966 -- audio VID/DID
967 AUD_VID_DID => 16#06_5020# / Register_Width,
968 PCH_AUD_VID_DID => 16#0e_5020# / Register_Width,
969
970 -- interrupt registers
971 DEISR => 16#04_4000# / Register_Width,
972 DEIMR => 16#04_4004# / Register_Width,
973 DEIIR => 16#04_4008# / Register_Width,
974 DEIER => 16#04_400c# / Register_Width,
975 GTISR => 16#04_4010# / Register_Width,
976 GTIMR => 16#04_4014# / Register_Width,
977 GTIIR => 16#04_4018# / Register_Width,
978 GTIER => 16#04_401c# / Register_Width,
979 SDEISR => 16#0c_4000# / Register_Width,
980 SDEIMR => 16#0c_4004# / Register_Width,
981 SDEIIR => 16#0c_4008# / Register_Width,
982 SDEIER => 16#0c_400c# / Register_Width,
983
984 -- I2C stuff
985 PCH_GMBUS0 => 16#0c_5100# / Register_Width,
986 PCH_GMBUS1 => 16#0c_5104# / Register_Width,
987 PCH_GMBUS2 => 16#0c_5108# / Register_Width,
988 PCH_GMBUS3 => 16#0c_510c# / Register_Width,
989 PCH_GMBUS4 => 16#0c_5110# / Register_Width,
990 PCH_GMBUS5 => 16#0c_5120# / Register_Width,
991
992 -- clock gating -- maybe have to touch this
993 DSPCLK_GATE_D => 16#04_2020# / Register_Width,
994 PCH_FDI_CHICKEN_B_C => 16#0c_2000# / Register_Width,
995 PCH_DSPCLK_GATE_D => 16#0c_2020# / Register_Width,
996
997 -- hotplug and initial detection
998 HOTPLUG_CTL => 16#04_4030# / Register_Width,
999 SHOTPLUG_CTL => 16#0c_4030# / Register_Width,
1000 SFUSE_STRAP => 16#0c_2014# / Register_Width,
1001
1002 -- Render Engine Command Streamer
1003 ARB_MODE => 16#00_4030# / Register_Width,
1004 HWS_PGA => 16#00_4080# / Register_Width,
1005 RCS_RING_BUFFER_TAIL => 16#00_2030# / Register_Width,
1006 VCS_RING_BUFFER_TAIL => 16#01_2030# / Register_Width,
1007 BCS_RING_BUFFER_TAIL => 16#02_2030# / Register_Width,
1008 RCS_RING_BUFFER_HEAD => 16#00_2034# / Register_Width,
1009 VCS_RING_BUFFER_HEAD => 16#01_2034# / Register_Width,
1010 BCS_RING_BUFFER_HEAD => 16#02_2034# / Register_Width,
1011 RCS_RING_BUFFER_STRT => 16#00_2038# / Register_Width,
1012 VCS_RING_BUFFER_STRT => 16#01_2038# / Register_Width,
1013 BCS_RING_BUFFER_STRT => 16#02_2038# / Register_Width,
1014 RCS_RING_BUFFER_CTL => 16#00_203c# / Register_Width,
1015 VCS_RING_BUFFER_CTL => 16#01_203c# / Register_Width,
1016 BCS_RING_BUFFER_CTL => 16#02_203c# / Register_Width,
1017 MI_MODE => 16#00_209c# / Register_Width,
1018 INSTPM => 16#00_20c0# / Register_Width,
1019 GAB_CTL_REG => 16#02_4000# / Register_Width,
1020 PP_DCLV_HIGH => 16#00_2220# / Register_Width,
1021 PP_DCLV_LOW => 16#00_2228# / Register_Width,
1022 VCS_PP_DCLV_HIGH => 16#01_2220# / Register_Width,
1023 VCS_PP_DCLV_LOW => 16#01_2228# / Register_Width,
1024 BCS_PP_DCLV_HIGH => 16#02_2220# / Register_Width,
1025 BCS_PP_DCLV_LOW => 16#02_2228# / Register_Width,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1026 ILK_DISPLAY_CHICKEN2 => 16#04_2004# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1027 UCGCTL1 => 16#00_9400# / Register_Width,
1028 UCGCTL2 => 16#00_9404# / Register_Width,
1029 MBCTL => 16#00_907c# / Register_Width,
1030 HWSTAM => 16#00_2098# / Register_Width,
1031 VCS_HWSTAM => 16#01_2098# / Register_Width,
1032 BCS_HWSTAM => 16#02_2098# / Register_Width,
1033 IIR => 16#04_4028# / Register_Width,
1034 PIPE_FRMCNT_A => 16#07_0040# / Register_Width,
1035 PIPE_FRMCNT_B => 16#07_1040# / Register_Width,
1036 PIPE_FRMCNT_C => 16#07_2040# / Register_Width,
1037 FBC_CTL => 16#04_3208# / Register_Width,
1038 PIPE_VSYNCSHIFT_A => 16#06_0028# / Register_Width,
1039 PIPE_VSYNCSHIFT_B => 16#06_1028# / Register_Width,
1040 PIPE_VSYNCSHIFT_C => 16#06_2028# / Register_Width,
1041 WM_PIPE_A => 16#04_5100# / Register_Width,
1042 WM_PIPE_B => 16#04_5104# / Register_Width,
1043 WM_PIPE_C => 16#04_5200# / Register_Width,
1044 PIPE_SCANLINE_A => 16#07_0000# / Register_Width,
1045 PIPE_SCANLINE_B => 16#07_1000# / Register_Width,
1046 PIPE_SCANLINE_C => 16#07_2000# / Register_Width,
1047 GFX_MODE => 16#00_2520# / Register_Width,
1048 CACHE_MODE_0 => 16#00_2120# / Register_Width,
1049 SLEEP_PSMI_CONTROL => 16#01_2050# / Register_Width,
1050 CTX_SIZE => 16#00_21a0# / Register_Width,
1051 GAC_ECO_BITS => 16#01_4090# / Register_Width,
1052 GAM_ECOCHK => 16#00_4090# / Register_Width,
1053 QUIRK_02084 => 16#00_2084# / Register_Width,
1054 QUIRK_02090 => 16#00_2090# / Register_Width,
1055 GT_MODE => 16#00_20d0# / Register_Width,
1056 QUIRK_F0060 => 16#0f_0060# / Register_Width,
1057 QUIRK_F1060 => 16#0f_1060# / Register_Width,
1058 QUIRK_F2060 => 16#0f_2060# / Register_Width,
1059 AUD_CNTRL_ST2 => 16#0e_50c0# / Register_Width,
1060 AUD_CNTL_ST_A => 16#0e_50b4# / Register_Width,
1061 AUD_CNTL_ST_B => 16#0e_51b4# / Register_Width,
1062 AUD_CNTL_ST_C => 16#0e_52b4# / Register_Width,
1063 AUD_HDMIW_HDMIEDID_A => 16#0e_5050# / Register_Width,
1064 AUD_HDMIW_HDMIEDID_B => 16#0e_5150# / Register_Width,
1065 AUD_HDMIW_HDMIEDID_C => 16#0e_5250# / Register_Width,
1066 AUD_CONFIG_A => 16#0e_5000# / Register_Width,
1067 AUD_CONFIG_B => 16#0e_5100# / Register_Width,
1068 AUD_CONFIG_C => 16#0e_5200# / Register_Width,
1069 TRANS_DP_CTL_A => 16#0e_0300# / Register_Width,
1070 TRANS_DP_CTL_B => 16#0e_1300# / Register_Width,
1071 TRANS_DP_CTL_C => 16#0e_2300# / Register_Width,
1072 TRANS_VSYNCSHIFT_A => 16#0e_0028# / Register_Width,
1073 TRANS_VSYNCSHIFT_B => 16#0e_1028# / Register_Width,
1074 TRANS_VSYNCSHIFT_C => 16#0e_2028# / Register_Width,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]1075 PCH_RAWCLK_FREQ => 16#0c_6204# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1076 QUIRK_C2004 => 16#0c_2004# / Register_Width);
1077
1078 subtype Registers_Index is Registers_Invalid_Index range
1079 Registers_Invalid_Index'Succ (Invalid_Register) ..
1080 Registers_Invalid_Index'Last;
1081
1082 -- aliased registers
1083 DP_CTL_A : constant Registers_Index := DDI_BUF_CTL_A;
1084 DP_AUX_CTL_A : constant Registers_Index := DDI_AUX_CTL_A;
1085 DP_AUX_DATA_A_1 : constant Registers_Index := DDI_AUX_DATA_A_1;
1086 DP_AUX_DATA_A_2 : constant Registers_Index := DDI_AUX_DATA_A_2;
1087 DP_AUX_DATA_A_3 : constant Registers_Index := DDI_AUX_DATA_A_3;
1088 DP_AUX_DATA_A_4 : constant Registers_Index := DDI_AUX_DATA_A_4;
1089 DP_AUX_DATA_A_5 : constant Registers_Index := DDI_AUX_DATA_A_5;
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1090 ILK_DISPLAY_CHICKEN1 : constant Registers_Index := FUSE_STATUS;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1091
1092 ---------------------------------------------------------------------------
1093
1094 Default_Timeout_MS : constant := 10;
1095
1096 ---------------------------------------------------------------------------
1097
1098 procedure Posting_Read
1099 (Register : in Registers_Index)
1100 with
1101 Global => (In_Out => Register_State),
1102 Depends => (Register_State =>+ (Register)),
1103 Pre => True,
1104 Post => True;
1105
1106 pragma Warnings (GNATprove, Off, "unused variable ""Verbose""",
1107 Reason => "Only used on debugging path");
1108 procedure Read
1109 (Register : in Registers_Index;
1110 Value : out Word32;
1111 Verbose : in Boolean := True)
1112 with
1113 Global => (In_Out => Register_State),
1114 Depends => ((Value, Register_State) => (Register, Register_State),
1115 null => Verbose),
1116 Pre => True,
1117 Post => True;
1118 pragma Warnings (GNATprove, On, "unused variable ""Verbose""");
1119
1120 procedure Write
1121 (Register : Registers_Index;
1122 Value : Word32)
1123 with
1124 Global => (In_Out => Register_State),
1125 Depends => (Register_State => (Register, Register_State, Value)),
1126 Pre => True,
1127 Post => True;
1128
1129 procedure Is_Set_Mask
1130 (Register : in Registers_Index;
1131 Mask : in Word32;
1132 Result : out Boolean);
1133
1134 pragma Warnings (GNATprove, Off, "unused initial value of ""Verbose""",
1135 Reason => "Only used on debugging path");
Nico Huberbcb2c472017-02-02 16:39:26 +0100[diff] [blame]1136 procedure Wait
1137 (Register : Registers_Index;
1138 Mask : Word32;
1139 Value : Word32;
1140 TOut_MS : Natural := Default_Timeout_MS;
1141 Verbose : Boolean := False);
1142
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1143 procedure Wait_Set_Mask
1144 (Register : Registers_Index;
1145 Mask : Word32;
1146 TOut_MS : Natural := Default_Timeout_MS;
1147 Verbose : Boolean := False);
1148
1149 procedure Wait_Unset_Mask
1150 (Register : Registers_Index;
1151 Mask : Word32;
1152 TOut_MS : Natural := Default_Timeout_MS;
1153 Verbose : Boolean := False);
1154 pragma Warnings (GNATprove, On, "unused initial value of ""Verbose""");
1155
1156 procedure Set_Mask
1157 (Register : Registers_Index;
1158 Mask : Word32);
1159
1160 procedure Unset_Mask
1161 (Register : Registers_Index;
1162 Mask : Word32);
1163
1164 procedure Unset_And_Set_Mask
1165 (Register : Registers_Index;
1166 Mask_Unset : Word32;
1167 Mask_Set : Word32);
1168
1169 pragma Warnings (Off, "declaration of ""Write_GTT"" hides one at *");
1170 procedure Write_GTT
1171 (GTT_Page : GTT_Range;
1172 Device_Address : GTT_Address_Type;
1173 Valid : Boolean)
1174 with
1175 Global => (In_Out => GTT_State),
1176 Depends => (GTT_State =>+ (GTT_Page, Device_Address, Valid)),
1177 Pre => True,
1178 Post => True;
1179 pragma Warnings (On, "declaration of ""Write_GTT"" hides one at *");
1180
1181 procedure Set_Register_Base (Base : Word64)
1182 with
1183 Global => (Output => Address_State),
1184 Depends => (Address_State => Base),
1185 Pre => True,
1186 Post => True;
1187
1188end HW.GFX.GMA.Registers;