commit 6b4678d6aad8c9025c6e5b649a6af36cfe0b3d61
author Nico Huber <nico.h@gmx.de> Sun Sep 22 21:31:52 2019 +0200
committer Nico Huber <nico.h@gmx.de> Fri Oct 18 12:34:06 2019 +0000
tree 642ab6f35aabf09d76c6bcbd77587611c408a8b1
parent d0f84b9acd65e047876c36b4571f1e4da17c4b23

gma skl: Implement CDClk switching

Flow is roughly the same as for Broadwell. Maximum CDClk is now
completely controlled by fuses, though. The same frequencies are
supported and dot clocks can run at full CDClk speed.

Change-Id: Ic14cf5981540d36d3f337a43bbec3574be0d3c99
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/35614
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

common/hw-gfx-gma-registers.ads

diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads
index 4eb2c04..767284c 100644
--- a/common/hw-gfx-gma-registers.ads
+++ b/common/hw-gfx-gma-registers.ads
@@ -146,6 +146,7 @@
       NDE_RSTWRN_OPT,
       BLC_PWM_CPU_CTL2,
       BLC_PWM_CPU_CTL,
+      DFSM,
       HTOTAL_A,
       HBLANK_A,
       HSYNC_A,
@@ -1460,6 +1461,7 @@
       PCH_HDMID             => 16#0e_1160# / Register_Width,
 
       -- Intel Registers
+      DFSM                  => 16#05_1000# / Register_Width,
       CPU_VGACNTRL          => 16#04_1000# / Register_Width,
       GMCH_VGACNTRL         => 16#07_1400# / Register_Width,
       FUSE_STATUS           => 16#04_2000# / Register_Width,