commit 408204409b3324ae6ae7043826ee5ab7bb45bb2f
author Nico Huber <nico.huber@secunet.com> Fri Jan 20 14:00:53 2017 +0100
committer Nico Huber <nico.h@gmx.de> Sat Jun 03 15:22:31 2017 +0200
tree 771cd2b63dc548d61a0d3a42f7bce72c7ed3acd6
parent 21da5741378af7c9f8db23b55aa316a905ae9183

gma broxton: Start off with power domains and CDClk

It's close to the respective code for Skylake but still different
enough for a separate implementation. We start with a default CDClk
of 288MHz which is enough for resolutions up to 2560x1600.

Change-Id: I44364191236f421b2b89c9a019a50713f7c20525
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18243
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

common/hw-gfx-gma-registers.ads

diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads
index 9b32c63..814dd11 100644
--- a/common/hw-gfx-gma-registers.ads
+++ b/common/hw-gfx-gma-registers.ads
@@ -105,6 +105,7 @@
       SPLL_CTL,
       WRPLL_CTL_1,
       WRPLL_CTL_2,
+      BXT_DE_PLL_ENABLE,
       PORT_CLK_SEL_DDIA,
       PORT_CLK_SEL_DDIB,
       PORT_CLK_SEL_DDIC,
@@ -245,6 +246,7 @@
       DPLL_CTRL1,
       DPLL_CTRL2,
       DPLL_STATUS,
+      BXT_DE_PLL_CTL,
       HTOTAL_EDP,
       HBLANK_EDP,
       HSYNC_EDP,
@@ -830,6 +832,10 @@
       WRPLL_CTL_1           => 16#04_6040# / Register_Width,
       WRPLL_CTL_2           => 16#04_6060# / Register_Width,
 
+      -- Broxton Display Engine PLL registers
+      BXT_DE_PLL_CTL        => 16#06_d000# / Register_Width,
+      BXT_DE_PLL_ENABLE     => 16#04_6070# / Register_Width,
+
       -- Power Down Well registers
       PWR_WELL_CTL_BIOS     => 16#04_5400# / Register_Width,
       PWR_WELL_CTL_DRIVER   => 16#04_5404# / Register_Width,