gma registers: Update for Tiger Lake and Alder Lake
Add all of the necessary registers at once, so they do not distract
from the rest of the patches.
Change-Id: I32102b58018b62874d708b31621c3ca8f676ca02
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/70890
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads
index c8ada33..498cb53 100644
--- a/common/hw-gfx-gma-registers.ads
+++ b/common/hw-gfx-gma-registers.ads
@@ -106,13 +106,27 @@
GTIER,
IIR,
HOTPLUG_CTL,
+ TC_HOTPLUG_CTL,
+ DISPLAY_ERR_FATAL_MASK,
+ DBUF_CTL_S2,
+ DBUF_CTL_S3,
+ MBUS_CTL,
+ GEN11_DE_HPD_ISR,
+ DBUF_CTL_S1,
ARB_CTL,
- DBUF_CTL,
+ DBUF_CTL_S0,
+ MBUS_ABOX_CTL,
+ MBUS_ABOX1_CTL,
+ MBUS_ABOX2_CTL,
WM_PIPE_A,
WM_PIPE_B,
WM1_LP_ILK,
WM2_LP_ILK,
WM3_LP_ILK,
+ BW_BUDDY1_CTL,
+ BW_BUDDY1_PAGE_MASK,
+ BW_BUDDY2_CTL,
+ BW_BUDDY2_PAGE_MASK,
WM_PIPE_C,
WM_LINETIME_A,
WM_LINETIME_B,
@@ -123,11 +137,24 @@
PWR_WELL_CTL_DEBUG,
PWR_WELL_CTL5,
PWR_WELL_CTL6,
+ PWR_AUX_CTL_BIOS,
+ PWR_AUX_CTL_DRIVER,
+ PWR_DDI_CTL_BIOS,
+ PWR_DDI_CTL_DRIVER,
CDCLK_CTL,
LCPLL1_CTL,
LCPLL2_CTL,
+ DPLL_4_ENABLE,
SPLL_CTL,
+ MGPLL1_ENABLE,
+ MGPLL2_ENABLE,
+ MGPLL3_ENABLE,
+ MGPLL4_ENABLE,
WRPLL_CTL_1,
+ MGPLL6_ENABLE,
+ PORTTC3_PLL1_ENABLE,
+ PORTTC4_PLL0_ENABLE,
+ PORTTC4_PLL1_ENABLE,
WRPLL_CTL_2,
BXT_DE_PLL_ENABLE,
BXT_PORT_PLL_ENABLE_A,
@@ -138,15 +165,24 @@
PORT_CLK_SEL_DDIC,
PORT_CLK_SEL_DDID,
PORT_CLK_SEL_DDIE,
+ DDI_CLK_SEL_USBC3,
+ DDI_CLK_SEL_USBC4,
+ DDI_CLK_SEL_USBC5,
+ DDI_CLK_SEL_USBC6,
TRANSA_CLK_SEL,
TRANSB_CLK_SEL,
TRANSC_CLK_SEL,
CDCLK_FREQ,
NDE_RSTWRN_OPT,
GEN8_CHICKEN_DCPR_1,
+ GEN11_CHICKEN_DCPR_2,
+ GEN9_CLKGATE_DIS_0,
+ GEN9_CHICKEN_DPCR_3,
+ GEN9_CLKGATE_DIS_5,
BLC_PWM_CPU_CTL2,
BLC_PWM_CPU_CTL,
DFSM,
+ DSSM,
HTOTAL_A,
HBLANK_A,
HSYNC_A,
@@ -162,6 +198,8 @@
FDI_TX_CTL_A,
PIPEA_DDI_FUNC_CTL,
PIPEA_MSA_MISC,
+ TGL_DP_TP_CTL_A,
+ TGL_DP_TP_STATUS_A,
SRD_CTL_A,
SRD_STATUS_A,
HTOTAL_B,
@@ -190,6 +228,8 @@
GMCH_PFIT_CONTROL,
PIPEB_DDI_FUNC_CTL,
PIPEB_MSA_MISC,
+ TGL_DP_TP_CTL_B,
+ TGL_DP_TP_STATUS_B,
SRD_CTL_B,
SRD_STATUS_B,
HTOTAL_C,
@@ -208,6 +248,8 @@
FDI_TX_CTL_C,
PIPEC_DDI_FUNC_CTL,
PIPEC_MSA_MISC,
+ TGL_DP_TP_CTL_C,
+ TGL_DP_TP_STATUS_C,
SRD_CTL_C,
SRD_STATUS_C,
DDI_BUF_CTL_A,
@@ -250,11 +292,46 @@
DP_TP_CTL_D,
DP_TP_STATUS_D,
DDI_BUF_CTL_E,
+ DDI_AUX_CTL_USBC2,
+ DDI_AUX_DATA_USBC2_1,
+ DDI_AUX_DATA_USBC2_2,
+ DDI_AUX_DATA_USBC2_3,
+ DDI_AUX_DATA_USBC2_4,
+ DDI_AUX_DATA_USBC2_5,
DP_TP_CTL_E,
DP_TP_STATUS_E,
+ DDI_BUF_CTL_USBC3,
+ DDI_AUX_CTL_USBC3,
+ DDI_AUX_DATA_USBC3_1,
+ DDI_AUX_DATA_USBC3_2,
+ DDI_AUX_DATA_USBC3_3,
+ DDI_AUX_DATA_USBC3_4,
+ DDI_AUX_DATA_USBC3_5,
+ DDI_BUF_CTL_USBC4,
+ DDI_AUX_CTL_USBC4,
+ DDI_AUX_DATA_USBC4_1,
+ DDI_AUX_DATA_USBC4_2,
+ DDI_AUX_DATA_USBC4_3,
+ DDI_AUX_DATA_USBC4_4,
+ DDI_AUX_DATA_USBC4_5,
+ DDI_BUF_CTL_USBC5,
+ DDI_AUX_CTL_USBC5,
+ DDI_AUX_DATA_USBC5_1,
+ DDI_AUX_DATA_USBC5_2,
+ DDI_AUX_DATA_USBC5_3,
+ DDI_AUX_DATA_USBC5_4,
+ DDI_AUX_DATA_USBC5_5,
SRD_CTL,
+ DDI_AUX_CTL_USBC6,
+ DDI_AUX_DATA_USBC6_1,
+ DDI_AUX_DATA_USBC6_2,
+ DDI_AUX_DATA_USBC6_3,
+ DDI_AUX_DATA_USBC6_4,
+ DDI_AUX_DATA_USBC6_5,
SRD_STATUS,
BXT_PHY_CTL_A,
+ PHY_MISC_B,
+ PHY_MISC_C,
BXT_PHY_CTL_B,
BXT_PHY_CTL_C,
BXT_PHY_CTL_FAM_EDP,
@@ -386,6 +463,7 @@
PS_CTRL_1_C,
BXT_PORT_CL1CM_DW0_BC,
DISPIO_CR_TX_BMU_CR0,
+ PORT_CL_DW5_B,
BXT_PORT_CL1CM_DW9_BC,
BXT_PORT_CL1CM_DW10_BC,
BXT_PORT_PLL_EBB_0_B,
@@ -430,16 +508,31 @@
BXT_PORT_TX_DW4_LN0_B,
BXT_PORT_TX_DW14_LN0_B,
BXT_PORT_TX_DW14_LN1_B,
+ PORT_PCS_DW1_GRP_B,
+ PORT_TX_DW2_GRP_B,
+ PORT_TX_DW4_GRP_B,
+ PORT_TX_DW5_GRP_B,
+ PORT_TX_DW7_GRP_B,
+ PORT_TX_DW8_GRP_B,
BXT_PORT_TX_DW14_LN2_B,
BXT_PORT_TX_DW14_LN3_B,
+ PORT_PCS_DW1_LN0_B,
BXT_PORT_PCS_DW10_01_C,
BXT_PORT_PCS_DW12_01_C,
+ PORT_TX_DW2_LN0_B,
+ PORT_TX_DW4_LN0_B,
+ PORT_TX_DW5_LN0_B,
+ PORT_TX_DW7_LN0_B,
+ PORT_TX_DW8_LN0_B,
BXT_PORT_TX_DW2_LN0_C,
BXT_PORT_TX_DW3_LN0_C,
BXT_PORT_TX_DW4_LN0_C,
BXT_PORT_TX_DW14_LN0_C,
+ PORT_TX_DW4_LN1_B,
BXT_PORT_TX_DW14_LN1_C,
+ PORT_TX_DW4_LN2_B,
BXT_PORT_TX_DW14_LN2_C,
+ PORT_TX_DW4_LN3_B,
BXT_PORT_TX_DW14_LN3_C,
BXT_PORT_PCS_DW10_GRP_B,
BXT_PORT_PCS_DW12_GRP_B,
@@ -468,7 +561,10 @@
SRD_STATUS_EDP,
PIPE_SCANLINE_A,
PIPEACONF,
+ PIPEA_ARB_CTL,
PIPEAMISC,
+ PIPEA_CHICKEN,
+ PIPE_MBUS_DBOX_CTL_A,
PIPE_FRMCNT_A,
PIPEA_GMCH_DATA_M,
PIPEA_GMCH_DATA_N,
@@ -497,6 +593,8 @@
PLANE_SIZE_1_A,
DSPASURF,
DSPATILEOFF,
+ PLANE_AUX_DIST_1_A,
+ PLANE_COLOR_CTL_1_A,
PLANE_WM_1_A_0,
PLANE_WM_1_A_1,
PLANE_WM_1_A_2,
@@ -509,7 +607,10 @@
SPACNTR,
PIPE_SCANLINE_B,
PIPEBCONF,
+ PIPEB_ARB_CTL,
PIPEBMISC,
+ PIPEB_CHICKEN,
+ PIPE_MBUS_DBOX_CTL_B,
PIPE_FRMCNT_B,
PIPEB_GMCH_DATA_M,
PIPEB_GMCH_DATA_N,
@@ -535,6 +636,8 @@
PLANE_SIZE_1_B,
DSPBSURF,
DSPBTILEOFF,
+ PLANE_AUX_DIST_1_B,
+ PLANE_COLOR_CTL_1_B,
PLANE_WM_1_B_0,
PLANE_WM_1_B_1,
PLANE_WM_1_B_2,
@@ -548,7 +651,10 @@
GMCH_VGACNTRL,
PIPE_SCANLINE_C,
PIPECCONF,
+ PIPEC_ARB_CTL,
PIPECMISC,
+ PIPEC_CHICKEN,
+ PIPE_MBUS_DBOX_CTL_C,
PIPE_FRMCNT_C,
CUR_CTL_C,
CUR_BASE_C,
@@ -570,6 +676,8 @@
PLANE_SIZE_1_C,
DSPCSURF,
DSPCTILEOFF,
+ PLANE_AUX_DIST_1_C,
+ PLANE_COLOR_CTL_1_C,
PLANE_WM_1_C_0,
PLANE_WM_1_C_1,
PLANE_WM_1_C_2,
@@ -590,6 +698,8 @@
SDEIIR,
SDEIER,
SHOTPLUG_CTL,
+ SHOTPLUG_CTL_TC,
+ SHPD_FILTER_CNT,
PCH_GMBUS0,
PCH_GMBUS1,
PCH_GMBUS2,
@@ -721,12 +831,42 @@
FDI_RXC_TUSIZE1,
QUIRK_F2060,
TRANSC_CHICKEN2,
+ HIP_INDEX_REG0,
+ HIP_INDEX_REG1,
LCPLL_CTL,
BXT_P_CR_GT_DISP_PWRON,
GT_MAILBOX,
GT_MAILBOX_DATA,
GT_MAILBOX_DATA_1,
+ PORT_CL_DW5_C,
+ PORT_CL_DW10_C,
+ PORT_COMP_DW0_C,
+ PORT_COMP_DW1_C,
+ PORT_COMP_DW3_C,
+ PORT_COMP_DW8_C,
+ PORT_COMP_DW9_C,
+ PORT_COMP_DW10_C,
+ PORT_PCS_DW1_GRP_C,
+ PORT_TX_DW2_GRP_C,
+ PORT_TX_DW4_GRP_C,
+ PORT_TX_DW5_GRP_C,
+ PORT_TX_DW7_GRP_C,
+ PORT_TX_DW8_GRP_C,
+ PORT_PCS_DW1_LN0_C,
+ PORT_TX_DW2_LN0_C,
+ PORT_TX_DW4_LN0_C,
+ PORT_TX_DW5_LN0_C,
+ PORT_TX_DW7_LN0_C,
+ PORT_TX_DW8_LN0_C,
+ PORT_TX_DW4_LN1_C,
+ PORT_TX_DW4_LN2_C,
+ PORT_TX_DW4_LN3_C,
+ TCSS_DDI_STATUS_1,
+ TCSS_DDI_STATUS_2,
+ TCSS_DDI_STATUS_3,
+ TCSS_DDI_STATUS_4,
BXT_PORT_CL1CM_DW0_A,
+ PORT_CL_DW5_A,
BXT_PORT_CL1CM_DW9_A,
BXT_PORT_CL1CM_DW10_A,
BXT_PORT_PLL_EBB_0_A,
@@ -751,14 +891,141 @@
BXT_PORT_TX_DW4_LN0_A,
BXT_PORT_TX_DW14_LN0_A,
BXT_PORT_TX_DW14_LN1_A,
+ PORT_PCS_DW1_GRP_A,
+ PORT_TX_DW2_GRP_A,
+ PORT_TX_DW4_GRP_A,
+ PORT_TX_DW5_GRP_A,
+ PORT_TX_DW7_GRP_A,
+ PORT_TX_DW8_GRP_A,
BXT_PORT_TX_DW14_LN2_A,
BXT_PORT_TX_DW14_LN3_A,
+ PORT_PCS_DW1_LN0_A,
+ PORT_TX_DW2_LN0_A,
+ PORT_TX_DW4_LN0_A,
+ PORT_TX_DW5_LN0_A,
+ PORT_TX_DW7_LN0_A,
+ PORT_TX_DW8_LN0_A,
+ PORT_TX_DW4_LN1_A,
+ PORT_TX_DW4_LN2_A,
+ PORT_TX_DW4_LN3_A,
BXT_PORT_PCS_DW10_GRP_A,
BXT_PORT_PCS_DW12_GRP_A,
BXT_PORT_TX_DW2_GRP_A,
BXT_PORT_TX_DW3_GRP_A,
- BXT_PORT_TX_DW4_GRP_A);
-
+ BXT_PORT_TX_DW4_GRP_A,
+ PORT_TX_DFLEXPA1_FIA1,
+ PORT_TX_DFLEXDPPMS_FIA1,
+ PORT_TX_DFLEXDPCSSS_FIA1,
+ PORT_TX_DFLEXDPSP_FIA1,
+ PORT_TX_DFLEXDPMLE1_FIA1,
+ DPCLKA_CFGCR0,
+ DPLL_0_CFGCR0,
+ DPLL_0_CFGCR1,
+ DPLL_1_CFGCR0,
+ DPLL_1_CFGCR1,
+ DPLL_4_CFGCR0,
+ DPLL_4_CFGCR1,
+ DPLL_0_SSC,
+ DPLL_1_SSC,
+ DPLL_4_SSC,
+ DKL_PCS_DW5_1,
+ DKL_DP_MODE_1,
+ DKL_CLKTOP2_HSCC_1,
+ DKL_CLKTOP2_CCC1_1,
+ DKL_REFCLKIN_CTL_1,
+ DKL_PLL_DIV0_1,
+ DKL_PLL_DIV1_1,
+ DKL_PLL_SSC_1,
+ DKL_PLL_BIAS_1,
+ DKL_PLL_COLDST_BIAS_1,
+ DKL_TX_DPCNTL0_1,
+ DKL_TX_DPCNTL1_1,
+ DKL_TX_DPCNTL2_1,
+ DKL_CMN_UC_DW_27_1,
+ DKL_TX_PMD_LANE_SUS_1,
+ DKL_PCS_DW5_2,
+ DKL_DP_MODE_2,
+ DKL_CLKTOP2_HSCC_2,
+ DKL_CLKTOP2_CCC1_2,
+ DKL_REFCLKIN_CTL_2,
+ DKL_PLL_DIV0_2,
+ DKL_PLL_DIV1_2,
+ DKL_PLL_SSC_2,
+ DKL_PLL_BIAS_2,
+ DKL_PLL_COLDST_BIAS_2,
+ DKL_TX_DPCNTL0_2,
+ DKL_TX_DPCNTL1_2,
+ DKL_TX_DPCNTL2_2,
+ DKL_CMN_UC_DW_27_2,
+ DKL_TX_PMD_LANE_SUS_2,
+ DKL_PCS_DW5_3,
+ DKL_DP_MODE_3,
+ DKL_CLKTOP2_HSCC_3,
+ DKL_CLKTOP2_CCC1_3,
+ DKL_REFCLKIN_CTL_3,
+ DKL_PLL_DIV0_3,
+ DKL_PLL_DIV1_3,
+ DKL_PLL_SSC_3,
+ DKL_PLL_BIAS_3,
+ DKL_PLL_COLDST_BIAS_3,
+ DKL_TX_DPCNTL0_3,
+ DKL_TX_DPCNTL1_3,
+ DKL_TX_DPCNTL2_3,
+ DKL_CMN_UC_DW_27_3,
+ DKL_TX_PMD_LANE_SUS_3,
+ DKL_PCS_DW5_4,
+ DKL_DP_MODE_4,
+ DKL_CLKTOP2_HSCC_4,
+ DKL_CLKTOP2_CCC1_4,
+ DKL_REFCLKIN_CTL_4,
+ DKL_PLL_DIV0_4,
+ DKL_PLL_DIV1_4,
+ DKL_PLL_SSC_4,
+ DKL_PLL_BIAS_4,
+ DKL_PLL_COLDST_BIAS_4,
+ DKL_TX_DPCNTL0_4,
+ DKL_TX_DPCNTL1_4,
+ DKL_TX_DPCNTL2_4,
+ DKL_CMN_UC_DW_27_4,
+ DKL_TX_PMD_LANE_SUS_4,
+ DKL_DP_MODE_5,
+ DKL_CLKTOP2_HSCC_5,
+ DKL_CLKTOP2_CCC1_5,
+ DKL_REFCLKIN_CTL_5,
+ DKL_PLL_DIV0_5,
+ DKL_PLL_DIV1_5,
+ DKL_PLL_SSC_5,
+ DKL_PLL_BIAS_5,
+ DKL_PLL_COLDST_BIAS_5,
+ DKL_TX_DPCNTL0_5,
+ DKL_TX_DPCNTL1_5,
+ DKL_TX_DPCNTL2_5,
+ DKL_CMN_UC_DW_27_5,
+ DKL_TX_PMD_LANE_SUS_5,
+ DKL_DP_MODE_6,
+ DKL_CLKTOP2_HSCC_6,
+ DKL_CLKTOP2_CCC1_6,
+ DKL_REFCLKIN_CTL_6,
+ DKL_PLL_DIV0_6,
+ DKL_PLL_DIV1_6,
+ DKL_PLL_SSC_6,
+ DKL_PLL_BIAS_6,
+ DKL_PLL_COLDST_BIAS_6,
+ DKL_TX_DPCNTL0_6,
+ DKL_TX_DPCNTL1_6,
+ DKL_TX_DPCNTL2_6,
+ DKL_CMN_UC_DW_27_6,
+ DKL_TX_PMD_LANE_SUS_6,
+ PORT_TX_DFLEXPA1_FIA2,
+ PORT_TX_DFLEXDPPMS_FIA2,
+ PORT_TX_DFLEXDPCSSS_FIA2,
+ PORT_TX_DFLEXDPSP_FIA2,
+ PORT_TX_DFLEXDPMLE1_FIA2,
+ PORT_TX_DFLEXPA1_FIA3,
+ PORT_TX_DFLEXDPPMS_FIA3,
+ PORT_TX_DFLEXDPCSSS_FIA3,
+ PORT_TX_DFLEXDPSP_FIA3,
+ PORT_TX_DFLEXDPMLE1_FIA3);
pragma Warnings
(GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)",
Reason => "TODO: Should it matter?");
@@ -785,7 +1052,9 @@
VSYNC_A => 16#06_0014# / Register_Width,
PIPEASRC => 16#06_001c# / Register_Width,
PIPEACONF => 16#07_0008# / Register_Width,
+ PIPEA_ARB_CTL => 16#07_0028# / Register_Width,
PIPEAMISC => 16#07_0030# / Register_Width,
+ PIPEA_CHICKEN => 16#07_0038# / Register_Width,
TRANS_HTOTAL_A => 16#0e_0000# / Register_Width,
TRANS_HBLANK_A => 16#0e_0004# / Register_Width,
TRANS_HSYNC_A => 16#0e_0008# / Register_Width,
@@ -900,7 +1169,9 @@
VSYNC_B => 16#06_1014# / Register_Width,
PIPEBSRC => 16#06_101c# / Register_Width,
PIPEBCONF => 16#07_1008# / Register_Width,
+ PIPEB_ARB_CTL => 16#07_1028# / Register_Width,
PIPEBMISC => 16#07_1030# / Register_Width,
+ PIPEB_CHICKEN => 16#07_1038# / Register_Width,
TRANS_HTOTAL_B => 16#0e_1000# / Register_Width,
TRANS_HBLANK_B => 16#0e_1004# / Register_Width,
TRANS_HSYNC_B => 16#0e_1008# / Register_Width,
@@ -1012,7 +1283,9 @@
VSYNC_C => 16#06_2014# / Register_Width,
PIPECSRC => 16#06_201c# / Register_Width,
PIPECCONF => 16#07_2008# / Register_Width,
+ PIPEC_ARB_CTL => 16#07_2028# / Register_Width,
PIPECMISC => 16#07_2030# / Register_Width,
+ PIPEC_CHICKEN => 16#07_2038# / Register_Width,
TRANS_HTOTAL_C => 16#0e_2000# / Register_Width,
TRANS_HBLANK_C => 16#0e_2004# / Register_Width,
TRANS_HSYNC_C => 16#0e_2008# / Register_Width,
@@ -1239,6 +1512,38 @@
DDI_AUX_DATA_D_5 => 16#06_4324# / Register_Width,
DDI_AUX_MUTEX_D => 16#06_432c# / Register_Width,
+ -- USB-C AUX control and data
+ DDI_AUX_CTL_USBC2 => 16#06_4410# / Register_Width,
+ DDI_AUX_DATA_USBC2_1 => 16#06_4414# / Register_Width,
+ DDI_AUX_DATA_USBC2_2 => 16#06_4418# / Register_Width,
+ DDI_AUX_DATA_USBC2_3 => 16#06_441c# / Register_Width,
+ DDI_AUX_DATA_USBC2_4 => 16#06_4420# / Register_Width,
+ DDI_AUX_DATA_USBC2_5 => 16#06_4424# / Register_Width,
+ DDI_AUX_CTL_USBC3 => 16#06_4510# / Register_Width,
+ DDI_AUX_DATA_USBC3_1 => 16#06_4514# / Register_Width,
+ DDI_AUX_DATA_USBC3_2 => 16#06_4518# / Register_Width,
+ DDI_AUX_DATA_USBC3_3 => 16#06_451c# / Register_Width,
+ DDI_AUX_DATA_USBC3_4 => 16#06_4520# / Register_Width,
+ DDI_AUX_DATA_USBC3_5 => 16#06_4524# / Register_Width,
+ DDI_AUX_CTL_USBC4 => 16#06_4610# / Register_Width,
+ DDI_AUX_DATA_USBC4_1 => 16#06_4614# / Register_Width,
+ DDI_AUX_DATA_USBC4_2 => 16#06_4618# / Register_Width,
+ DDI_AUX_DATA_USBC4_3 => 16#06_461c# / Register_Width,
+ DDI_AUX_DATA_USBC4_4 => 16#06_4620# / Register_Width,
+ DDI_AUX_DATA_USBC4_5 => 16#06_4624# / Register_Width,
+ DDI_AUX_CTL_USBC5 => 16#06_4710# / Register_Width,
+ DDI_AUX_DATA_USBC5_1 => 16#06_4714# / Register_Width,
+ DDI_AUX_DATA_USBC5_2 => 16#06_4718# / Register_Width,
+ DDI_AUX_DATA_USBC5_3 => 16#06_471c# / Register_Width,
+ DDI_AUX_DATA_USBC5_4 => 16#06_4720# / Register_Width,
+ DDI_AUX_DATA_USBC5_5 => 16#06_4724# / Register_Width,
+ DDI_AUX_CTL_USBC6 => 16#06_4810# / Register_Width,
+ DDI_AUX_DATA_USBC6_1 => 16#06_4814# / Register_Width,
+ DDI_AUX_DATA_USBC6_2 => 16#06_4818# / Register_Width,
+ DDI_AUX_DATA_USBC6_3 => 16#06_481c# / Register_Width,
+ DDI_AUX_DATA_USBC6_4 => 16#06_4820# / Register_Width,
+ DDI_AUX_DATA_USBC6_5 => 16#06_4824# / Register_Width,
+
DDI_BUF_CTL_E => 16#06_4400# / Register_Width,
DDI_BUF_TRANS_E_S0T1 => 16#06_4f80# / Register_Width,
DDI_BUF_TRANS_E_S0T2 => 16#06_4f84# / Register_Width,
@@ -1429,6 +1734,11 @@
PWR_WELL_CTL5 => 16#04_5410# / Register_Width,
PWR_WELL_CTL6 => 16#04_5414# / Register_Width,
+ PWR_AUX_CTL_BIOS => 16#04_5440# / Register_Width,
+ PWR_AUX_CTL_DRIVER => 16#04_5444# / Register_Width,
+ PWR_DDI_CTL_BIOS => 16#04_5450# / Register_Width,
+ PWR_DDI_CTL_DRIVER => 16#04_5454# / Register_Width,
+
-- class Panel registers
GMCH_PP_STATUS => 16#06_1200# / Register_Width,
GMCH_PP_CONTROL => 16#06_1204# / Register_Width,
@@ -1480,6 +1790,7 @@
-- Intel Registers
DFSM => 16#05_1000# / Register_Width,
+ DSSM => 16#05_1004# / Register_Width,
CPU_VGACNTRL => 16#04_1000# / Register_Width,
GMCH_VGACNTRL => 16#07_1400# / Register_Width,
FUSE_STATUS => 16#04_2000# / Register_Width,
@@ -1487,9 +1798,16 @@
FBA_CFB_BASE => 16#04_3200# / Register_Width,
IPS_CTL => 16#04_3408# / Register_Width,
ARB_CTL => 16#04_5000# / Register_Width,
- DBUF_CTL => 16#04_5008# / Register_Width,
+ DBUF_CTL_S0 => 16#04_5008# / Register_Width,
+ DBUF_CTL_S1 => 16#04_4fe8# / Register_Width,
+ DBUF_CTL_S2 => 16#04_4300# / Register_Width,
+ DBUF_CTL_S3 => 16#04_4304# / Register_Width,
NDE_RSTWRN_OPT => 16#04_6408# / Register_Width,
GEN8_CHICKEN_DCPR_1 => 16#04_6430# / Register_Width,
+ GEN11_CHICKEN_DCPR_2 => 16#04_6434# / Register_Width,
+ GEN9_CLKGATE_DIS_0 => 16#04_6530# / Register_Width,
+ GEN9_CLKGATE_DIS_5 => 16#04_6540# / Register_Width,
+ GEN9_CHICKEN_DPCR_3 => 16#04_6538# / Register_Width,
PCH_DREF_CONTROL => 16#0c_6200# / Register_Width,
PCH_DPLL_SEL => 16#0c_7000# / Register_Width,
GT_MAILBOX => 16#13_8124# / Register_Width,
@@ -1563,10 +1881,14 @@
-- hotplug and initial detection
HOTPLUG_CTL => 16#04_4030# / Register_Width,
+ TC_HOTPLUG_CTL => 16#04_4038# / Register_Width,
PORT_HOTPLUG_EN => 16#06_1110# / Register_Width,
PORT_HOTPLUG_STAT => 16#06_1114# / Register_Width,
SHOTPLUG_CTL => 16#0c_4030# / Register_Width,
+ SHOTPLUG_CTL_TC => 16#0c_4034# / Register_Width,
+ SHPD_FILTER_CNT => 16#0c_4038# / Register_Width,
SFUSE_STRAP => 16#0c_2014# / Register_Width,
+ GEN11_DE_HPD_ISR => 16#04_4470# / Register_Width,
-- Render Engine Command Streamer
ARB_MODE => 16#00_4030# / Register_Width,
@@ -1648,7 +1970,267 @@
GMCH_CLKCFG => 16#01_0c00# / Register_Width,
GMCH_HPLLVCO_MOBILE => 16#01_0c0f# / Register_Width,
- GMCH_HPLLVCO => 16#01_0c38# / Register_Width);
+ GMCH_HPLLVCO => 16#01_0c38# / Register_Width,
+
+ -- Combo Phy Registers (Tigerlake on)
+
+ PHY_MISC_B => 16#06_4c04# / Register_Width,
+ PHY_MISC_C => 16#06_4c08# / Register_Width,
+ PORT_CL_DW5_A => 16#16_2014# / Register_Width,
+ PORT_CL_DW5_B => 16#06_c014# / Register_Width,
+ PORT_CL_DW5_C => 16#16_0014# / Register_Width,
+ PORT_COMP_DW0_C => 16#16_0100# / Register_Width,
+ PORT_COMP_DW1_C => 16#16_0104# / Register_Width,
+ PORT_COMP_DW3_C => 16#16_010c# / Register_Width,
+ PORT_COMP_DW8_C => 16#16_0120# / Register_Width,
+ PORT_COMP_DW9_C => 16#16_0124# / Register_Width,
+ PORT_COMP_DW10_C => 16#16_0128# / Register_Width,
+ PORT_TX_DW8_LN0_A => 16#16_28a0# / Register_Width,
+ PORT_TX_DW8_LN0_B => 16#06_c8a0# / Register_Width,
+ PORT_TX_DW8_LN0_C => 16#16_08a0# / Register_Width,
+ PORT_TX_DW8_GRP_A => 16#16_26a0# / Register_Width,
+ PORT_TX_DW8_GRP_B => 16#06_c6a0# / Register_Width,
+ PORT_TX_DW8_GRP_C => 16#16_06a0# / Register_Width,
+ PORT_PCS_DW1_LN0_A => 16#16_2804# / Register_Width,
+ PORT_PCS_DW1_LN0_B => 16#06_c804# / Register_Width,
+ PORT_PCS_DW1_LN0_C => 16#16_0804# / Register_Width,
+ PORT_PCS_DW1_GRP_A => 16#16_2604# / Register_Width,
+ PORT_PCS_DW1_GRP_B => 16#06_c604# / Register_Width,
+ PORT_PCS_DW1_GRP_C => 16#16_0604# / Register_Width,
+ MBUS_ABOX_CTL => 16#04_5038# / Register_Width,
+ MBUS_ABOX1_CTL => 16#04_5048# / Register_Width,
+ MBUS_ABOX2_CTL => 16#04_504c# / Register_Width,
+ BW_BUDDY1_PAGE_MASK => 16#04_5144# / Register_Width,
+ BW_BUDDY2_PAGE_MASK => 16#04_5154# / Register_Width,
+ BW_BUDDY1_CTL => 16#04_5140# / Register_Width,
+ BW_BUDDY2_CTL => 16#04_5150# / Register_Width,
+
+ -- TGL DKL PHY registers
+ HIP_INDEX_REG0 => 16#10_10a0# / Register_Width,
+ HIP_INDEX_REG1 => 16#10_10a4# / Register_Width,
+ -- Each type-C port PHY is addressed through a 4KB
+ -- aperture. Each PHY has more than 4KB of register space, so a
+ -- separate index is programmed in HIP_INDEX_REG0 or
+ -- HIP_INDEX_REG1, based on the port number, to set the upper 2
+ -- address bits that point the 4KB window into the full PHY
+ -- register space.
+ -- The registers below assumes index 2 has been programmed.
+
+ -- 16_8*** registers for DKL PHY 1
+ DKL_CLKTOP2_HSCC_1 => 16#16_80d4# / Register_Width,
+ DKL_CLKTOP2_CCC1_1 => 16#16_80d8# / Register_Width,
+ DKL_REFCLKIN_CTL_1 => 16#16_812c# / Register_Width,
+ DKL_PLL_DIV0_1 => 16#16_8200# / Register_Width,
+ DKL_PLL_DIV1_1 => 16#16_8204# / Register_Width,
+ DKL_PLL_SSC_1 => 16#16_8210# / Register_Width,
+ DKL_PLL_BIAS_1 => 16#16_8214# / Register_Width,
+ DKL_PLL_COLDST_BIAS_1 => 16#16_8218# / Register_Width,
+ DKL_CMN_UC_DW_27_1 => 16#16_836c# / Register_Width,
+ DKL_DP_MODE_1 => 16#16_80a0# / Register_Width,
+ -- 16_9*** registers for DKL PHY 2
+ DKL_CLKTOP2_HSCC_2 => 16#16_90d4# / Register_Width,
+ DKL_CLKTOP2_CCC1_2 => 16#16_90d8# / Register_Width,
+ DKL_REFCLKIN_CTL_2 => 16#16_912c# / Register_Width,
+ DKL_PLL_DIV0_2 => 16#16_9200# / Register_Width,
+ DKL_PLL_DIV1_2 => 16#16_9204# / Register_Width,
+ DKL_PLL_SSC_2 => 16#16_9210# / Register_Width,
+ DKL_PLL_BIAS_2 => 16#16_9214# / Register_Width,
+ DKL_PLL_COLDST_BIAS_2 => 16#16_9218# / Register_Width,
+ DKL_CMN_UC_DW_27_2 => 16#16_936c# / Register_Width,
+ DKL_DP_MODE_2 => 16#16_90a0# / Register_Width,
+ -- 16_a*** registers for DKL PHY 3
+ DKL_CLKTOP2_HSCC_3 => 16#16_a0d4# / Register_Width,
+ DKL_CLKTOP2_CCC1_3 => 16#16_a0d8# / Register_Width,
+ DKL_REFCLKIN_CTL_3 => 16#16_a12c# / Register_Width,
+ DKL_PLL_DIV0_3 => 16#16_a200# / Register_Width,
+ DKL_PLL_DIV1_3 => 16#16_a204# / Register_Width,
+ DKL_PLL_SSC_3 => 16#16_a210# / Register_Width,
+ DKL_PLL_BIAS_3 => 16#16_a214# / Register_Width,
+ DKL_PLL_COLDST_BIAS_3 => 16#16_a218# / Register_Width,
+ DKL_CMN_UC_DW_27_3 => 16#16_a36c# / Register_Width,
+ DKL_DP_MODE_3 => 16#16_a0a0# / Register_Width,
+ -- 16_b*** registers for DKL PHY 4
+ DKL_CLKTOP2_HSCC_4 => 16#16_b0d4# / Register_Width,
+ DKL_CLKTOP2_CCC1_4 => 16#16_b0d8# / Register_Width,
+ DKL_REFCLKIN_CTL_4 => 16#16_b12c# / Register_Width,
+ DKL_PLL_DIV0_4 => 16#16_b200# / Register_Width,
+ DKL_PLL_DIV1_4 => 16#16_b204# / Register_Width,
+ DKL_PLL_SSC_4 => 16#16_b210# / Register_Width,
+ DKL_PLL_BIAS_4 => 16#16_b214# / Register_Width,
+ DKL_PLL_COLDST_BIAS_4 => 16#16_b218# / Register_Width,
+ DKL_CMN_UC_DW_27_4 => 16#16_b36c# / Register_Width,
+ DKL_DP_MODE_4 => 16#16_b0a0# / Register_Width,
+ -- 16_c*** registers for DKL PHY 5
+ DKL_CLKTOP2_HSCC_5 => 16#16_c0d4# / Register_Width,
+ DKL_CLKTOP2_CCC1_5 => 16#16_c0d8# / Register_Width,
+ DKL_REFCLKIN_CTL_5 => 16#16_c12c# / Register_Width,
+ DKL_PLL_DIV0_5 => 16#16_c200# / Register_Width,
+ DKL_PLL_DIV1_5 => 16#16_c204# / Register_Width,
+ DKL_PLL_SSC_5 => 16#16_c210# / Register_Width,
+ DKL_PLL_BIAS_5 => 16#16_c214# / Register_Width,
+ DKL_PLL_COLDST_BIAS_5 => 16#16_c218# / Register_Width,
+ DKL_CMN_UC_DW_27_5 => 16#16_c36c# / Register_Width,
+ DKL_DP_MODE_5 => 16#16_c0a0# / Register_Width,
+ -- 16_d*** registers for DKL PHY 6
+ DKL_CLKTOP2_HSCC_6 => 16#16_d0d4# / Register_Width,
+ DKL_CLKTOP2_CCC1_6 => 16#16_d0d8# / Register_Width,
+ DKL_REFCLKIN_CTL_6 => 16#16_d12c# / Register_Width,
+ DKL_PLL_DIV0_6 => 16#16_d200# / Register_Width,
+ DKL_PLL_DIV1_6 => 16#16_d204# / Register_Width,
+ DKL_PLL_SSC_6 => 16#16_d210# / Register_Width,
+ DKL_PLL_BIAS_6 => 16#16_d214# / Register_Width,
+ DKL_PLL_COLDST_BIAS_6 => 16#16_d218# / Register_Width,
+ DKL_CMN_UC_DW_27_6 => 16#16_d36c# / Register_Width,
+ DKL_DP_MODE_6 => 16#16_d0a0# / Register_Width,
+
+ -- TGL DPLL registers
+ DPLL_4_ENABLE => 16#04_6018# / Register_Width,
+ DPLL_0_CFGCR0 => 16#16_4284# / Register_Width,
+ DPLL_0_CFGCR1 => 16#16_4288# / Register_Width,
+ DPLL_1_CFGCR0 => 16#16_428c# / Register_Width,
+ DPLL_1_CFGCR1 => 16#16_4290# / Register_Width,
+ DPLL_4_CFGCR0 => 16#16_4294# / Register_Width,
+ DPLL_4_CFGCR1 => 16#16_4298# / Register_Width,
+ DPLL_0_SSC => 16#16_4b10# / Register_Width,
+ DPLL_1_SSC => 16#16_4c10# / Register_Width,
+ DPLL_4_SSC => 16#16_4e10# / Register_Width,
+
+ -- TGL DDI registers (some aliases too)
+ DDI_BUF_CTL_USBC3 => 16#06_4500# / Register_Width,
+ DDI_BUF_CTL_USBC4 => 16#06_4600# / Register_Width,
+ DDI_BUF_CTL_USBC5 => 16#06_4700# / Register_Width,
+ PORT_TX_DW2_LN0_A => 16#16_2888# / Register_Width,
+ PORT_TX_DW2_LN0_B => 16#06_c888# / Register_Width,
+ PORT_TX_DW2_LN0_C => 16#16_0888# / Register_Width,
+ PORT_TX_DW2_GRP_A => 16#16_2688# / Register_Width,
+ PORT_TX_DW2_GRP_B => 16#06_c688# / Register_Width,
+ PORT_TX_DW2_GRP_C => 16#16_0688# / Register_Width,
+ PORT_TX_DW4_LN0_A => 16#16_2890# / Register_Width,
+ PORT_TX_DW4_LN1_A => 16#16_2990# / Register_Width,
+ PORT_TX_DW4_LN2_A => 16#16_2a90# / Register_Width,
+ PORT_TX_DW4_LN3_A => 16#16_2b90# / Register_Width,
+ PORT_TX_DW4_LN0_B => 16#06_c890# / Register_Width,
+ PORT_TX_DW4_LN1_B => 16#06_c990# / Register_Width,
+ PORT_TX_DW4_LN2_B => 16#06_ca90# / Register_Width,
+ PORT_TX_DW4_LN3_B => 16#06_cb90# / Register_Width,
+ PORT_TX_DW4_LN0_C => 16#16_0890# / Register_Width,
+ PORT_TX_DW4_LN1_C => 16#16_0990# / Register_Width,
+ PORT_TX_DW4_LN2_C => 16#16_0a90# / Register_Width,
+ PORT_TX_DW4_LN3_C => 16#16_0b90# / Register_Width,
+ PORT_TX_DW4_GRP_A => 16#16_2690# / Register_Width,
+ PORT_TX_DW4_GRP_B => 16#06_c690# / Register_Width,
+ PORT_TX_DW4_GRP_C => 16#16_0690# / Register_Width,
+ PORT_TX_DW5_LN0_A => 16#16_2894# / Register_Width,
+ PORT_TX_DW5_LN0_B => 16#06_c894# / Register_Width,
+ PORT_TX_DW5_LN0_C => 16#16_0894# / Register_Width,
+ PORT_TX_DW5_GRP_A => 16#16_2694# / Register_Width,
+ PORT_TX_DW5_GRP_B => 16#06_c694# / Register_Width,
+ PORT_TX_DW5_GRP_C => 16#16_0694# / Register_Width,
+ PORT_TX_DW7_LN0_A => 16#16_289c# / Register_Width,
+ PORT_TX_DW7_LN0_B => 16#06_c89c# / Register_Width,
+ PORT_TX_DW7_LN0_C => 16#16_089c# / Register_Width,
+ PORT_TX_DW7_GRP_A => 16#16_269c# / Register_Width,
+ PORT_TX_DW7_GRP_B => 16#06_c69c# / Register_Width,
+ PORT_TX_DW7_GRP_C => 16#16_069c# / Register_Width,
+
+ -- TGL DisplayPort transport
+ TGL_DP_TP_CTL_A => 16#06_0540# / Register_Width,
+ TGL_DP_TP_CTL_B => 16#06_1540# / Register_Width,
+ TGL_DP_TP_CTL_C => 16#06_2540# / Register_Width,
+ TGL_DP_TP_STATUS_A => 16#06_0544# / Register_Width,
+ TGL_DP_TP_STATUS_B => 16#06_1544# / Register_Width,
+ TGL_DP_TP_STATUS_C => 16#06_2544# / Register_Width,
+ DPCLKA_CFGCR0 => 16#16_4280# / Register_Width,
+ PORT_CL_DW10_C => 16#16_0028# / Register_Width,
+
+ -- MBUS DBOX
+ PIPE_MBUS_DBOX_CTL_A => 16#07_003c# / Register_Width,
+ PIPE_MBUS_DBOX_CTL_B => 16#07_103c# / Register_Width,
+ PIPE_MBUS_DBOX_CTL_C => 16#07_203c# / Register_Width,
+
+ -- TGL+ new plane control registers
+ PLANE_AUX_DIST_1_A => 16#07_01c0# / Register_Width,
+ PLANE_AUX_DIST_1_B => 16#07_11c0# / Register_Width,
+ PLANE_AUX_DIST_1_C => 16#07_21c0# / Register_Width,
+ PLANE_COLOR_CTL_1_A => 16#07_01cc# / Register_Width,
+ PLANE_COLOR_CTL_1_B => 16#07_11cc# / Register_Width,
+ PLANE_COLOR_CTL_1_C => 16#07_21cc# / Register_Width,
+
+ -- TGL FIA registers
+ PORT_TX_DFLEXDPCSSS_FIA1 => 16#16_3894# / Register_Width,
+ PORT_TX_DFLEXDPMLE1_FIA1 => 16#16_38c0# / Register_Width,
+ PORT_TX_DFLEXDPPMS_FIA1 => 16#16_3890# / Register_Width,
+ PORT_TX_DFLEXDPSP_FIA1 => 16#16_38a0# / Register_Width,
+ PORT_TX_DFLEXPA1_FIA1 => 16#16_3880# / Register_Width,
+ PORT_TX_DFLEXDPCSSS_FIA2 => 16#16_e894# / Register_Width,
+ PORT_TX_DFLEXDPMLE1_FIA2 => 16#16_e8c0# / Register_Width,
+ PORT_TX_DFLEXDPPMS_FIA2 => 16#16_e890# / Register_Width,
+ PORT_TX_DFLEXDPSP_FIA2 => 16#16_e8a0# / Register_Width,
+ PORT_TX_DFLEXPA1_FIA2 => 16#16_e880# / Register_Width,
+ PORT_TX_DFLEXDPCSSS_FIA3 => 16#16_f894# / Register_Width,
+ PORT_TX_DFLEXDPMLE1_FIA3 => 16#16_f8c0# / Register_Width,
+ PORT_TX_DFLEXDPPMS_FIA3 => 16#16_f890# / Register_Width,
+ PORT_TX_DFLEXDPSP_FIA3 => 16#16_f8a0# / Register_Width,
+ PORT_TX_DFLEXPA1_FIA3 => 16#16_f880# / Register_Width,
+
+ -- TGL DDI clock select
+ DDI_CLK_SEL_USBC3 => 16#04_6114# / Register_Width,
+ DDI_CLK_SEL_USBC4 => 16#04_6118# / Register_Width,
+ DDI_CLK_SEL_USBC5 => 16#04_611c# / Register_Width,
+ DDI_CLK_SEL_USBC6 => 16#04_6120# / Register_Width,
+
+ -- TGL DKL PLLs
+ MGPLL1_ENABLE => 16#04_6030# / Register_Width,
+ MGPLL2_ENABLE => 16#04_6034# / Register_Width,
+ MGPLL3_ENABLE => 16#04_6038# / Register_Width,
+ MGPLL4_ENABLE => 16#04_603c# / Register_Width,
+ MGPLL6_ENABLE => 16#04_6044# / Register_Width,
+
+ -- ADL-P DKL PLLs
+ PORTTC3_PLL1_ENABLE => 16#04_6048# / Register_Width,
+ PORTTC4_PLL0_ENABLE => 16#04_604c# / Register_Width,
+ PORTTC4_PLL1_ENABLE => 16#04_6050# / Register_Width,
+
+ -- TGL DKL Vswing
+ DKL_TX_PMD_LANE_SUS_1 => 16#16_8d00# / Register_Width,
+ DKL_TX_PMD_LANE_SUS_2 => 16#16_9d00# / Register_Width,
+ DKL_TX_PMD_LANE_SUS_3 => 16#16_ad00# / Register_Width,
+ DKL_TX_PMD_LANE_SUS_4 => 16#16_bd00# / Register_Width,
+ DKL_TX_PMD_LANE_SUS_5 => 16#16_cd00# / Register_Width,
+ DKL_TX_PMD_LANE_SUS_6 => 16#16_dd00# / Register_Width,
+ DKL_TX_DPCNTL0_1 => 16#16_82c0# / Register_Width,
+ DKL_TX_DPCNTL0_2 => 16#16_92c0# / Register_Width,
+ DKL_TX_DPCNTL0_3 => 16#16_a2c0# / Register_Width,
+ DKL_TX_DPCNTL0_4 => 16#16_b2c0# / Register_Width,
+ DKL_TX_DPCNTL0_5 => 16#16_c2c0# / Register_Width,
+ DKL_TX_DPCNTL0_6 => 16#16_d2c0# / Register_Width,
+ DKL_TX_DPCNTL1_1 => 16#16_82c4# / Register_Width,
+ DKL_TX_DPCNTL1_2 => 16#16_92c4# / Register_Width,
+ DKL_TX_DPCNTL1_3 => 16#16_a2c4# / Register_Width,
+ DKL_TX_DPCNTL1_4 => 16#16_b2c4# / Register_Width,
+ DKL_TX_DPCNTL1_5 => 16#16_c2c4# / Register_Width,
+ DKL_TX_DPCNTL1_6 => 16#16_d2c4# / Register_Width,
+ DKL_TX_DPCNTL2_1 => 16#16_82c8# / Register_Width,
+ DKL_TX_DPCNTL2_2 => 16#16_92c8# / Register_Width,
+ DKL_TX_DPCNTL2_3 => 16#16_a2c8# / Register_Width,
+ DKL_TX_DPCNTL2_4 => 16#16_b2c8# / Register_Width,
+ DKL_TX_DPCNTL2_5 => 16#16_c2c8# / Register_Width,
+ DKL_TX_DPCNTL2_6 => 16#16_d2c8# / Register_Width,
+
+ -- ADL-P DKL registers
+ DKL_PCS_DW5_1 => 16#16_8014# / Register_Width,
+ DKL_PCS_DW5_2 => 16#16_9014# / Register_Width,
+ DKL_PCS_DW5_3 => 16#16_a014# / Register_Width,
+ DKL_PCS_DW5_4 => 16#16_b014# / Register_Width,
+
+ -- ADL-P DDI status
+ TCSS_DDI_STATUS_1 => 16#16_1500# / Register_Width,
+ TCSS_DDI_STATUS_2 => 16#16_1504# / Register_Width,
+ TCSS_DDI_STATUS_3 => 16#16_1508# / Register_Width,
+ TCSS_DDI_STATUS_4 => 16#16_150c# / Register_Width,
+
+ DISPLAY_ERR_FATAL_MASK => 16#04_421c# / Register_Width,
+ MBUS_CTL => 16#04_438c# / Register_Width);
subtype Registers_Index is Registers_Invalid_Index range
Registers_Invalid_Index'Succ (Invalid_Register) ..
@@ -1674,6 +2256,41 @@
CURAPOS : constant Registers_Index := CUR_POS_A;
BXT_BLC_PWM_CTL_1 : constant Registers_Index := BLC_PWM_PCH_CTL1;
BXT_BLC_PWM_FREQ_1 : constant Registers_Index := BLC_PWM_PCH_CTL2;
+ PHY_MISC_A : constant Registers_Index := BXT_PHY_CTL_A;
+ PORT_COMP_DW0_B : constant Registers_Index := BXT_PORT_PLL_0_B;
+ PORT_COMP_DW1_B : constant Registers_Index := BXT_PORT_PLL_1_B;
+ PORT_COMP_DW3_B : constant Registers_Index := BXT_PORT_PLL_3_B;
+ PORT_COMP_DW0_A : constant Registers_Index := BXT_PORT_PLL_0_A;
+ PORT_COMP_DW1_A : constant Registers_Index := BXT_PORT_PLL_1_A;
+ PORT_COMP_DW3_A : constant Registers_Index := BXT_PORT_PLL_3_A;
+ PORT_COMP_DW9_A : constant Registers_Index := BXT_PORT_PLL_9_A;
+ PORT_COMP_DW9_B : constant Registers_Index := BXT_PORT_PLL_9_B;
+ PORT_COMP_DW8_A : constant Registers_Index := BXT_PORT_PLL_8_A;
+ PORT_COMP_DW8_B : constant Registers_Index := BXT_PORT_PLL_8_B;
+ PORT_COMP_DW10_A : constant Registers_Index := BXT_PORT_PLL_10_A;
+ PORT_COMP_DW10_B : constant Registers_Index := BXT_PORT_PLL_10_B;
+ CDCLK_PLL_ENABLE : constant Registers_Index := BXT_DE_PLL_ENABLE;
+ DDI_AUX_CTL_USBC1 : constant Registers_Index := DDI_AUX_CTL_D;
+ DDI_AUX_DATA_USBC1_1 : constant Registers_Index := DDI_AUX_DATA_D_1;
+ DDI_AUX_DATA_USBC1_2 : constant Registers_Index := DDI_AUX_DATA_D_2;
+ DDI_AUX_DATA_USBC1_3 : constant Registers_Index := DDI_AUX_DATA_D_3;
+ DDI_AUX_DATA_USBC1_4 : constant Registers_Index := DDI_AUX_DATA_D_4;
+ DDI_AUX_DATA_USBC1_5 : constant Registers_Index := DDI_AUX_DATA_D_5;
+ DPLL_0_ENABLE : constant Registers_Index := LCPLL1_CTL;
+ DPLL_1_ENABLE : constant Registers_Index := LCPLL2_CTL;
+ PORT_CL_DW10_A : constant Registers_Index := BXT_PORT_CL1CM_DW10_A;
+ PORT_CL_DW10_B : constant Registers_Index := BXT_PORT_CL1CM_DW10_BC;
+ DDI_CLK_SEL_USBC1 : constant Registers_Index := PORT_CLK_SEL_DDID;
+ DDI_CLK_SEL_USBC2 : constant Registers_Index := PORT_CLK_SEL_DDIE;
+ MGPLL5_ENABLE : constant Registers_Index := WRPLL_CTL_1;
+ DDI_BUF_CTL_USBC1 : constant Registers_Index := DDI_BUF_CTL_D;
+ DDI_BUF_CTL_USBC2 : constant Registers_Index := DDI_BUF_CTL_E;
+ DDI_BUF_CTL_USBC6 : constant Registers_Index := SRD_CTL;
+ PORTTC1_PLL0_ENABLE : constant Registers_Index := MGPLL2_ENABLE;
+ PORTTC1_PLL1_ENABLE : constant Registers_Index := MGPLL3_ENABLE;
+ PORTTC2_PLL0_ENABLE : constant Registers_Index := MGPLL4_ENABLE;
+ PORTTC2_PLL1_ENABLE : constant Registers_Index := WRPLL_CTL_1;
+ PORTTC3_PLL0_ENABLE : constant Registers_Index := MGPLL6_ENABLE;
---------------------------------------------------------------------------