commit afadcace9e96289e3aff808c4fac5830c11bdc6c
author Nico Huber <nico.huber@secunet.com> Wed Feb 08 13:41:38 2017 +0100
committer Nico Huber <nico.h@gmx.de> Sat Jun 03 15:23:51 2017 +0200
tree 9cb10bccb194c7504a14c6f7e6f7fd7d97d3e0e6
parent 4b0239f549c99b1c393f099fe21c7055860fbe7a

gma broxton: Implement pre-PLL setup for DDI PHYs

Some lane configuration that's supposed to happen before enabling
the display PLL.

Change-Id: I08ec3ac26164061b19d695ab600d6bb9eeadd7ad
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18424
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

common/hw-gfx-gma-registers.ads

diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads
index 84caefc..4e58651 100644
--- a/common/hw-gfx-gma-registers.ads
+++ b/common/hw-gfx-gma-registers.ads
@@ -284,7 +284,15 @@
       BXT_PORT_PLL_9_C,
       BXT_PORT_PLL_10_C,
       BXT_PORT_PCS_DW12_01_B,
+      BXT_PORT_TX_DW14_LN0_B,
+      BXT_PORT_TX_DW14_LN1_B,
+      BXT_PORT_TX_DW14_LN2_B,
+      BXT_PORT_TX_DW14_LN3_B,
       BXT_PORT_PCS_DW12_01_C,
+      BXT_PORT_TX_DW14_LN0_C,
+      BXT_PORT_TX_DW14_LN1_C,
+      BXT_PORT_TX_DW14_LN2_C,
+      BXT_PORT_TX_DW14_LN3_C,
       BXT_PORT_PCS_DW12_GRP_B,
       BXT_PORT_PCS_DW12_GRP_C,
       BXT_DE_PLL_CTL,
@@ -521,6 +529,10 @@
       BXT_PORT_REF_DW6_A,
       BXT_PORT_REF_DW8_A,
       BXT_PORT_PCS_DW12_01_A,
+      BXT_PORT_TX_DW14_LN0_A,
+      BXT_PORT_TX_DW14_LN1_A,
+      BXT_PORT_TX_DW14_LN2_A,
+      BXT_PORT_TX_DW14_LN3_A,
       BXT_PORT_PCS_DW12_GRP_A);
 
    pragma Warnings
@@ -960,6 +972,20 @@
       BXT_PORT_CL1CM_DW30_BC  => 16#06_c078# / Register_Width,
       BXT_PORT_CL2CM_DW6_BC   => 16#06_c358# / Register_Width,
 
+      -- Broxton DDI PHY TX lane registers
+      BXT_PORT_TX_DW14_LN0_A  => 16#16_2538# / Register_Width,
+      BXT_PORT_TX_DW14_LN1_A  => 16#16_25b8# / Register_Width,
+      BXT_PORT_TX_DW14_LN2_A  => 16#16_2738# / Register_Width,
+      BXT_PORT_TX_DW14_LN3_A  => 16#16_27b8# / Register_Width,
+      BXT_PORT_TX_DW14_LN0_B  => 16#06_c538# / Register_Width,
+      BXT_PORT_TX_DW14_LN1_B  => 16#06_c5b8# / Register_Width,
+      BXT_PORT_TX_DW14_LN2_B  => 16#06_c738# / Register_Width,
+      BXT_PORT_TX_DW14_LN3_B  => 16#06_c7b8# / Register_Width,
+      BXT_PORT_TX_DW14_LN0_C  => 16#06_c938# / Register_Width,
+      BXT_PORT_TX_DW14_LN1_C  => 16#06_c9b8# / Register_Width,
+      BXT_PORT_TX_DW14_LN2_C  => 16#06_cb38# / Register_Width,
+      BXT_PORT_TX_DW14_LN3_C  => 16#06_cbb8# / Register_Width,
+
       -- Broxton DDI PHY ref registers
       BXT_PORT_REF_DW3_A      => 16#16_218c# / Register_Width,
       BXT_PORT_REF_DW3_BC     => 16#06_c18c# / Register_Width,