Gitiles
Code Review Sign In
review.sourcearcade.org / libgfxinit / 229ed1c7bfb6c372b6247a6be6f002066feaf43e / . / common / hw-gfx-gma-registers.ads
blob: 37e62e823212da0526db0fa8bb93b7d10e0400ce [file] [log] [blame]
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1--
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]2-- Copyright (C) 2015-2017 secunet Security Networks AG
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
Nico Huber125a29e2016-10-18 00:23:54 +0200[diff] [blame]6-- the Free Software Foundation; either version 2 of the License, or
7-- (at your option) any later version.
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]8--
9-- This program is distributed in the hope that it will be useful,
10-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12-- GNU General Public License for more details.
13--
14
15with System;
16with HW.GFX.GMA;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]17
18private package HW.GFX.GMA.Registers
19with
20 Abstract_State =>
21 ((Address_State with Part_Of => GMA.State),
22 (Register_State with External, Part_Of => GMA.Device_State),
23 (GTT_State with External, Part_Of => GMA.Device_State)),
24 Initializes => Address_State
25is
26 type Registers_Invalid_Index is
27 (Invalid_Register, -- Allow a placeholder when access is not acceptable
28
29 RCS_RING_BUFFER_TAIL,
30 RCS_RING_BUFFER_HEAD,
31 RCS_RING_BUFFER_STRT,
32 RCS_RING_BUFFER_CTL,
33 QUIRK_02084,
34 QUIRK_02090,
35 HWSTAM,
36 MI_MODE,
37 INSTPM,
38 GT_MODE,
39 CACHE_MODE_0,
40 CTX_SIZE,
41 PP_DCLV_HIGH,
42 PP_DCLV_LOW,
43 GFX_MODE,
44 ARB_MODE,
45 HWS_PGA,
46 GAM_ECOCHK,
Arthur Heymans229ed1c2018-03-28 16:45:43 +0200[diff] [blame^]47 GMCH_GMBUS0,
48 GMCH_GMBUS1,
49 GMCH_GMBUS2,
50 GMCH_GMBUS3,
51 GMCH_GMBUS4,
52 GMCH_GMBUS5,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]53 MBCTL,
54 UCGCTL1,
55 UCGCTL2,
56 VCS_RING_BUFFER_TAIL,
57 VCS_RING_BUFFER_HEAD,
58 VCS_RING_BUFFER_STRT,
59 VCS_RING_BUFFER_CTL,
60 SLEEP_PSMI_CONTROL,
61 VCS_HWSTAM,
62 VCS_PP_DCLV_HIGH,
63 VCS_PP_DCLV_LOW,
64 GAC_ECO_BITS,
65 BCS_RING_BUFFER_TAIL,
66 BCS_RING_BUFFER_HEAD,
67 BCS_RING_BUFFER_STRT,
68 BCS_RING_BUFFER_CTL,
69 BCS_HWSTAM,
70 BCS_PP_DCLV_HIGH,
71 BCS_PP_DCLV_LOW,
72 GAB_CTL_REG,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]73 CPU_VGACNTRL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]74 FUSE_STATUS,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]75 ILK_DISPLAY_CHICKEN2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]76 DSPCLK_GATE_D,
77 FBA_CFB_BASE,
78 FBC_CTL,
79 IPS_CTL,
80 DEISR,
81 DEIMR,
82 DEIIR,
83 DEIER,
84 GTISR,
85 GTIMR,
86 GTIIR,
87 GTIER,
88 IIR,
89 HOTPLUG_CTL,
90 ARB_CTL,
91 DBUF_CTL,
92 WM_PIPE_A,
93 WM_PIPE_B,
94 WM1_LP_ILK,
95 WM2_LP_ILK,
96 WM3_LP_ILK,
97 WM_PIPE_C,
98 WM_LINETIME_A,
99 WM_LINETIME_B,
100 WM_LINETIME_C,
101 PWR_WELL_CTL_BIOS,
102 PWR_WELL_CTL_DRIVER,
103 PWR_WELL_CTL_KVMR,
104 PWR_WELL_CTL_DEBUG,
105 PWR_WELL_CTL5,
106 PWR_WELL_CTL6,
107 CDCLK_CTL,
108 LCPLL1_CTL,
109 LCPLL2_CTL,
110 SPLL_CTL,
111 WRPLL_CTL_1,
112 WRPLL_CTL_2,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]113 BXT_DE_PLL_ENABLE,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]114 BXT_PORT_PLL_ENABLE_A,
115 BXT_PORT_PLL_ENABLE_B,
116 BXT_PORT_PLL_ENABLE_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]117 PORT_CLK_SEL_DDIA,
118 PORT_CLK_SEL_DDIB,
119 PORT_CLK_SEL_DDIC,
120 PORT_CLK_SEL_DDID,
121 PORT_CLK_SEL_DDIE,
122 TRANSA_CLK_SEL,
123 TRANSB_CLK_SEL,
124 TRANSC_CLK_SEL,
125 NDE_RSTWRN_OPT,
126 BLC_PWM_CPU_CTL2,
127 BLC_PWM_CPU_CTL,
128 HTOTAL_A,
129 HBLANK_A,
130 HSYNC_A,
131 VTOTAL_A,
132 VBLANK_A,
133 VSYNC_A,
134 PIPEASRC,
135 PIPE_VSYNCSHIFT_A,
136 PIPEA_DATA_M1,
137 PIPEA_DATA_N1,
138 PIPEA_LINK_M1,
139 PIPEA_LINK_N1,
140 FDI_TX_CTL_A,
141 PIPEA_DDI_FUNC_CTL,
142 PIPEA_MSA_MISC,
143 SRD_CTL_A,
144 SRD_STATUS_A,
145 HTOTAL_B,
146 HBLANK_B,
147 HSYNC_B,
148 VTOTAL_B,
149 VBLANK_B,
150 VSYNC_B,
151 PIPEBSRC,
152 PIPE_VSYNCSHIFT_B,
153 PIPEB_DATA_M1,
154 PIPEB_DATA_N1,
155 PIPEB_LINK_M1,
156 PIPEB_LINK_N1,
157 FDI_TX_CTL_B,
158 PIPEB_DDI_FUNC_CTL,
159 PIPEB_MSA_MISC,
160 SRD_CTL_B,
161 SRD_STATUS_B,
162 HTOTAL_C,
163 HBLANK_C,
164 HSYNC_C,
165 VTOTAL_C,
166 VBLANK_C,
167 VSYNC_C,
168 PIPECSRC,
169 PIPE_VSYNCSHIFT_C,
170 PIPEC_DATA_M1,
171 PIPEC_DATA_N1,
172 PIPEC_LINK_M1,
173 PIPEC_LINK_N1,
174 FDI_TX_CTL_C,
175 PIPEC_DDI_FUNC_CTL,
176 PIPEC_MSA_MISC,
177 SRD_CTL_C,
178 SRD_STATUS_C,
179 DDI_BUF_CTL_A,
180 DDI_AUX_CTL_A,
181 DDI_AUX_DATA_A_1,
182 DDI_AUX_DATA_A_2,
183 DDI_AUX_DATA_A_3,
184 DDI_AUX_DATA_A_4,
185 DDI_AUX_DATA_A_5,
186 DDI_AUX_MUTEX_A,
187 DP_TP_CTL_A,
188 DDI_BUF_CTL_B,
189 DDI_AUX_CTL_B,
190 DDI_AUX_DATA_B_1,
191 DDI_AUX_DATA_B_2,
192 DDI_AUX_DATA_B_3,
193 DDI_AUX_DATA_B_4,
194 DDI_AUX_DATA_B_5,
195 DDI_AUX_MUTEX_B,
196 DP_TP_CTL_B,
197 DP_TP_STATUS_B,
198 DDI_BUF_CTL_C,
199 DDI_AUX_CTL_C,
200 DDI_AUX_DATA_C_1,
201 DDI_AUX_DATA_C_2,
202 DDI_AUX_DATA_C_3,
203 DDI_AUX_DATA_C_4,
204 DDI_AUX_DATA_C_5,
205 DDI_AUX_MUTEX_C,
206 DP_TP_CTL_C,
207 DP_TP_STATUS_C,
208 DDI_BUF_CTL_D,
209 DDI_AUX_CTL_D,
210 DDI_AUX_DATA_D_1,
211 DDI_AUX_DATA_D_2,
212 DDI_AUX_DATA_D_3,
213 DDI_AUX_DATA_D_4,
214 DDI_AUX_DATA_D_5,
215 DDI_AUX_MUTEX_D,
216 DP_TP_CTL_D,
217 DP_TP_STATUS_D,
218 DDI_BUF_CTL_E,
219 DP_TP_CTL_E,
220 DP_TP_STATUS_E,
221 SRD_CTL,
222 SRD_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]223 BXT_PHY_CTL_A,
224 BXT_PHY_CTL_B,
225 BXT_PHY_CTL_C,
226 BXT_PHY_CTL_FAM_EDP,
227 BXT_PHY_CTL_FAM_DDI,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]228 DDI_BUF_TRANS_A_S0T1,
229 DDI_BUF_TRANS_A_S0T2,
230 DDI_BUF_TRANS_A_S1T1,
231 DDI_BUF_TRANS_A_S1T2,
232 DDI_BUF_TRANS_A_S2T1,
233 DDI_BUF_TRANS_A_S2T2,
234 DDI_BUF_TRANS_A_S3T1,
235 DDI_BUF_TRANS_A_S3T2,
236 DDI_BUF_TRANS_A_S4T1,
237 DDI_BUF_TRANS_A_S4T2,
238 DDI_BUF_TRANS_A_S5T1,
239 DDI_BUF_TRANS_A_S5T2,
240 DDI_BUF_TRANS_A_S6T1,
241 DDI_BUF_TRANS_A_S6T2,
242 DDI_BUF_TRANS_A_S7T1,
243 DDI_BUF_TRANS_A_S7T2,
244 DDI_BUF_TRANS_A_S8T1,
245 DDI_BUF_TRANS_A_S8T2,
246 DDI_BUF_TRANS_A_S9T1,
247 DDI_BUF_TRANS_A_S9T2,
248 DDI_BUF_TRANS_B_S0T1,
249 DDI_BUF_TRANS_B_S0T2,
250 DDI_BUF_TRANS_B_S1T1,
251 DDI_BUF_TRANS_B_S1T2,
252 DDI_BUF_TRANS_B_S2T1,
253 DDI_BUF_TRANS_B_S2T2,
254 DDI_BUF_TRANS_B_S3T1,
255 DDI_BUF_TRANS_B_S3T2,
256 DDI_BUF_TRANS_B_S4T1,
257 DDI_BUF_TRANS_B_S4T2,
258 DDI_BUF_TRANS_B_S5T1,
259 DDI_BUF_TRANS_B_S5T2,
260 DDI_BUF_TRANS_B_S6T1,
261 DDI_BUF_TRANS_B_S6T2,
262 DDI_BUF_TRANS_B_S7T1,
263 DDI_BUF_TRANS_B_S7T2,
264 DDI_BUF_TRANS_B_S8T1,
265 DDI_BUF_TRANS_B_S8T2,
266 DDI_BUF_TRANS_B_S9T1,
267 DDI_BUF_TRANS_B_S9T2,
268 DDI_BUF_TRANS_C_S0T1,
269 DDI_BUF_TRANS_C_S0T2,
270 DDI_BUF_TRANS_C_S1T1,
271 DDI_BUF_TRANS_C_S1T2,
272 DDI_BUF_TRANS_C_S2T1,
273 DDI_BUF_TRANS_C_S2T2,
274 DDI_BUF_TRANS_C_S3T1,
275 DDI_BUF_TRANS_C_S3T2,
276 DDI_BUF_TRANS_C_S4T1,
277 DDI_BUF_TRANS_C_S4T2,
278 DDI_BUF_TRANS_C_S5T1,
279 DDI_BUF_TRANS_C_S5T2,
280 DDI_BUF_TRANS_C_S6T1,
281 DDI_BUF_TRANS_C_S6T2,
282 DDI_BUF_TRANS_C_S7T1,
283 DDI_BUF_TRANS_C_S7T2,
284 DDI_BUF_TRANS_C_S8T1,
285 DDI_BUF_TRANS_C_S8T2,
286 DDI_BUF_TRANS_C_S9T1,
287 DDI_BUF_TRANS_C_S9T2,
288 DDI_BUF_TRANS_D_S0T1,
289 DDI_BUF_TRANS_D_S0T2,
290 DDI_BUF_TRANS_D_S1T1,
291 DDI_BUF_TRANS_D_S1T2,
292 DDI_BUF_TRANS_D_S2T1,
293 DDI_BUF_TRANS_D_S2T2,
294 DDI_BUF_TRANS_D_S3T1,
295 DDI_BUF_TRANS_D_S3T2,
296 DDI_BUF_TRANS_D_S4T1,
297 DDI_BUF_TRANS_D_S4T2,
298 DDI_BUF_TRANS_D_S5T1,
299 DDI_BUF_TRANS_D_S5T2,
300 DDI_BUF_TRANS_D_S6T1,
301 DDI_BUF_TRANS_D_S6T2,
302 DDI_BUF_TRANS_D_S7T1,
303 DDI_BUF_TRANS_D_S7T2,
304 DDI_BUF_TRANS_D_S8T1,
305 DDI_BUF_TRANS_D_S8T2,
306 DDI_BUF_TRANS_D_S9T1,
307 DDI_BUF_TRANS_D_S9T2,
308 DDI_BUF_TRANS_E_S0T1,
309 DDI_BUF_TRANS_E_S0T2,
310 DDI_BUF_TRANS_E_S1T1,
311 DDI_BUF_TRANS_E_S1T2,
312 DDI_BUF_TRANS_E_S2T1,
313 DDI_BUF_TRANS_E_S2T2,
314 DDI_BUF_TRANS_E_S3T1,
315 DDI_BUF_TRANS_E_S3T2,
316 DDI_BUF_TRANS_E_S4T1,
317 DDI_BUF_TRANS_E_S4T2,
318 DDI_BUF_TRANS_E_S5T1,
319 DDI_BUF_TRANS_E_S5T2,
320 DDI_BUF_TRANS_E_S6T1,
321 DDI_BUF_TRANS_E_S6T2,
322 DDI_BUF_TRANS_E_S7T1,
323 DDI_BUF_TRANS_E_S7T2,
324 DDI_BUF_TRANS_E_S8T1,
325 DDI_BUF_TRANS_E_S8T2,
326 DDI_BUF_TRANS_E_S9T1,
327 DDI_BUF_TRANS_E_S9T2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]328 AUD_VID_DID,
329 PFA_WIN_POS,
330 PFA_WIN_SZ,
331 PFA_CTL_1,
332 PS_WIN_POS_1_A,
333 PS_WIN_SZ_1_A,
334 PS_CTRL_1_A,
335 PS_WIN_POS_2_A,
336 PS_WIN_SZ_2_A,
337 PS_CTRL_2_A,
338 PFB_WIN_POS,
339 PFB_WIN_SZ,
340 PFB_CTL_1,
341 PS_WIN_POS_1_B,
342 PS_WIN_SZ_1_B,
343 PS_CTRL_1_B,
344 PS_WIN_POS_2_B,
345 PS_WIN_SZ_2_B,
346 PS_CTRL_2_B,
347 PFC_WIN_POS,
348 PFC_WIN_SZ,
349 PFC_CTL_1,
350 PS_WIN_POS_1_C,
351 PS_WIN_SZ_1_C,
352 PS_CTRL_1_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]353 BXT_PORT_CL1CM_DW0_BC,
Nico Huber58afc202017-06-12 21:34:55 +0200[diff] [blame]354 DISPIO_CR_TX_BMU_CR0,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]355 BXT_PORT_CL1CM_DW9_BC,
356 BXT_PORT_CL1CM_DW10_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]357 BXT_PORT_PLL_EBB_0_B,
358 BXT_PORT_PLL_EBB_4_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]359 DPLL1_CFGR1,
360 DPLL1_CFGR2,
361 DPLL2_CFGR1,
362 DPLL2_CFGR2,
363 DPLL3_CFGR1,
364 DPLL3_CFGR2,
365 DPLL_CTRL1,
366 DPLL_CTRL2,
367 DPLL_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]368 BXT_PORT_CL1CM_DW28_BC,
369 BXT_PORT_CL1CM_DW30_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]370 BXT_PORT_PLL_0_B,
371 BXT_PORT_PLL_1_B,
372 BXT_PORT_PLL_2_B,
373 BXT_PORT_PLL_3_B,
374 BXT_PORT_PLL_6_B,
375 BXT_PORT_PLL_8_B,
376 BXT_PORT_PLL_9_B,
377 BXT_PORT_PLL_10_B,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]378 BXT_PORT_REF_DW3_BC,
379 BXT_PORT_REF_DW6_BC,
380 BXT_PORT_REF_DW8_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]381 BXT_PORT_PLL_EBB_0_C,
382 BXT_PORT_PLL_EBB_4_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]383 BXT_PORT_CL2CM_DW6_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]384 BXT_PORT_PLL_0_C,
385 BXT_PORT_PLL_1_C,
386 BXT_PORT_PLL_2_C,
387 BXT_PORT_PLL_3_C,
388 BXT_PORT_PLL_6_C,
389 BXT_PORT_PLL_8_C,
390 BXT_PORT_PLL_9_C,
391 BXT_PORT_PLL_10_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]392 BXT_PORT_PCS_DW10_01_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]393 BXT_PORT_PCS_DW12_01_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]394 BXT_PORT_TX_DW2_LN0_B,
395 BXT_PORT_TX_DW3_LN0_B,
396 BXT_PORT_TX_DW4_LN0_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]397 BXT_PORT_TX_DW14_LN0_B,
398 BXT_PORT_TX_DW14_LN1_B,
399 BXT_PORT_TX_DW14_LN2_B,
400 BXT_PORT_TX_DW14_LN3_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]401 BXT_PORT_PCS_DW10_01_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]402 BXT_PORT_PCS_DW12_01_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]403 BXT_PORT_TX_DW2_LN0_C,
404 BXT_PORT_TX_DW3_LN0_C,
405 BXT_PORT_TX_DW4_LN0_C,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]406 BXT_PORT_TX_DW14_LN0_C,
407 BXT_PORT_TX_DW14_LN1_C,
408 BXT_PORT_TX_DW14_LN2_C,
409 BXT_PORT_TX_DW14_LN3_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]410 BXT_PORT_PCS_DW10_GRP_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]411 BXT_PORT_PCS_DW12_GRP_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]412 BXT_PORT_TX_DW2_GRP_B,
413 BXT_PORT_TX_DW3_GRP_B,
414 BXT_PORT_TX_DW4_GRP_B,
415 BXT_PORT_PCS_DW10_GRP_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]416 BXT_PORT_PCS_DW12_GRP_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]417 BXT_PORT_TX_DW2_GRP_C,
418 BXT_PORT_TX_DW3_GRP_C,
419 BXT_PORT_TX_DW4_GRP_C,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]420 BXT_DE_PLL_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]421 HTOTAL_EDP,
422 HBLANK_EDP,
423 HSYNC_EDP,
424 VTOTAL_EDP,
425 VBLANK_EDP,
426 VSYNC_EDP,
427 PIPE_EDP_DATA_M1,
428 PIPE_EDP_DATA_N1,
429 PIPE_EDP_LINK_M1,
430 PIPE_EDP_LINK_N1,
431 PIPE_EDP_DDI_FUNC_CTL,
432 PIPE_EDP_MSA_MISC,
433 SRD_CTL_EDP,
434 SRD_STATUS_EDP,
435 PIPE_SCANLINE_A,
436 PIPEACONF,
437 PIPEAMISC,
438 PIPE_FRMCNT_A,
439 DSPACNTR,
440 DSPALINOFF,
441 DSPASTRIDE,
442 PLANE_POS_1_A,
443 PLANE_SIZE_1_A,
444 DSPASURF,
445 DSPATILEOFF,
446 PLANE_WM_1_A_0,
447 PLANE_WM_1_A_1,
448 PLANE_WM_1_A_2,
449 PLANE_WM_1_A_3,
450 PLANE_WM_1_A_4,
451 PLANE_WM_1_A_5,
452 PLANE_WM_1_A_6,
453 PLANE_WM_1_A_7,
454 PLANE_BUF_CFG_1_A,
455 SPACNTR,
456 PIPE_SCANLINE_B,
457 PIPEBCONF,
458 PIPEBMISC,
459 PIPE_FRMCNT_B,
460 DSPBCNTR,
461 DSPBLINOFF,
462 DSPBSTRIDE,
463 PLANE_POS_1_B,
464 PLANE_SIZE_1_B,
465 DSPBSURF,
466 DSPBTILEOFF,
467 PLANE_WM_1_B_0,
468 PLANE_WM_1_B_1,
469 PLANE_WM_1_B_2,
470 PLANE_WM_1_B_3,
471 PLANE_WM_1_B_4,
472 PLANE_WM_1_B_5,
473 PLANE_WM_1_B_6,
474 PLANE_WM_1_B_7,
475 PLANE_BUF_CFG_1_B,
476 SPBCNTR,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]477 GMCH_VGACNTRL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]478 PIPE_SCANLINE_C,
479 PIPECCONF,
480 PIPECMISC,
481 PIPE_FRMCNT_C,
482 DSPCCNTR,
483 DSPCLINOFF,
484 DSPCSTRIDE,
485 PLANE_POS_1_C,
486 PLANE_SIZE_1_C,
487 DSPCSURF,
488 DSPCTILEOFF,
489 PLANE_WM_1_C_0,
490 PLANE_WM_1_C_1,
491 PLANE_WM_1_C_2,
492 PLANE_WM_1_C_3,
493 PLANE_WM_1_C_4,
494 PLANE_WM_1_C_5,
495 PLANE_WM_1_C_6,
496 PLANE_WM_1_C_7,
497 PLANE_BUF_CFG_1_C,
498 SPCCNTR,
499 PIPE_EDP_CONF,
500 PCH_FDI_CHICKEN_B_C,
501 QUIRK_C2004,
502 SFUSE_STRAP,
503 PCH_DSPCLK_GATE_D,
504 SDEISR,
505 SDEIMR,
506 SDEIIR,
507 SDEIER,
508 SHOTPLUG_CTL,
509 PCH_GMBUS0,
510 PCH_GMBUS1,
511 PCH_GMBUS2,
512 PCH_GMBUS3,
513 PCH_GMBUS4,
514 PCH_GMBUS5,
515 SBI_ADDR,
516 SBI_DATA,
517 SBI_CTL_STAT,
518 PCH_DPLL_A,
519 PCH_DPLL_B,
520 PCH_PIXCLK_GATE,
521 PCH_FPA0,
522 PCH_FPA1,
523 PCH_FPB0,
524 PCH_FPB1,
525 PCH_DREF_CONTROL,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]526 PCH_RAWCLK_FREQ,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]527 PCH_DPLL_SEL,
528 PCH_PP_STATUS,
529 PCH_PP_CONTROL,
530 PCH_PP_ON_DELAYS,
531 PCH_PP_OFF_DELAYS,
532 PCH_PP_DIVISOR,
533 BLC_PWM_PCH_CTL1,
534 BLC_PWM_PCH_CTL2,
535 TRANS_HTOTAL_A,
536 TRANS_HBLANK_A,
537 TRANS_HSYNC_A,
538 TRANS_VTOTAL_A,
539 TRANS_VBLANK_A,
540 TRANS_VSYNC_A,
541 TRANS_VSYNCSHIFT_A,
542 TRANSA_DATA_M1,
543 TRANSA_DATA_N1,
544 TRANSA_DP_LINK_M1,
545 TRANSA_DP_LINK_N1,
546 TRANS_DP_CTL_A,
547 TRANS_HTOTAL_B,
548 TRANS_HBLANK_B,
549 TRANS_HSYNC_B,
550 TRANS_VTOTAL_B,
551 TRANS_VBLANK_B,
552 TRANS_VSYNC_B,
553 TRANS_VSYNCSHIFT_B,
554 TRANSB_DATA_M1,
555 TRANSB_DATA_N1,
556 TRANSB_DP_LINK_M1,
557 TRANSB_DP_LINK_N1,
558 PCH_ADPA,
559 PCH_HDMIB,
560 PCH_HDMIC,
561 PCH_HDMID,
562 PCH_LVDS,
563 TRANS_DP_CTL_B,
564 TRANS_HTOTAL_C,
565 TRANS_HBLANK_C,
566 TRANS_HSYNC_C,
567 TRANS_VTOTAL_C,
568 TRANS_VBLANK_C,
569 TRANS_VSYNC_C,
570 TRANS_VSYNCSHIFT_C,
571 TRANSC_DATA_M1,
572 TRANSC_DATA_N1,
573 TRANSC_DP_LINK_M1,
574 TRANSC_DP_LINK_N1,
575 TRANS_DP_CTL_C,
576 PCH_DP_B,
577 PCH_DP_AUX_CTL_B,
578 PCH_DP_AUX_DATA_B_1,
579 PCH_DP_AUX_DATA_B_2,
580 PCH_DP_AUX_DATA_B_3,
581 PCH_DP_AUX_DATA_B_4,
582 PCH_DP_AUX_DATA_B_5,
583 PCH_DP_C,
584 PCH_DP_AUX_CTL_C,
585 PCH_DP_AUX_DATA_C_1,
586 PCH_DP_AUX_DATA_C_2,
587 PCH_DP_AUX_DATA_C_3,
588 PCH_DP_AUX_DATA_C_4,
589 PCH_DP_AUX_DATA_C_5,
590 PCH_DP_D,
591 PCH_DP_AUX_CTL_D,
592 PCH_DP_AUX_DATA_D_1,
593 PCH_DP_AUX_DATA_D_2,
594 PCH_DP_AUX_DATA_D_3,
595 PCH_DP_AUX_DATA_D_4,
596 PCH_DP_AUX_DATA_D_5,
597 AUD_CONFIG_A,
598 PCH_AUD_VID_DID,
599 AUD_HDMIW_HDMIEDID_A,
600 AUD_CNTL_ST_A,
601 AUD_CNTRL_ST2,
602 AUD_CONFIG_B,
603 AUD_HDMIW_HDMIEDID_B,
604 AUD_CNTL_ST_B,
605 AUD_CONFIG_C,
606 AUD_HDMIW_HDMIEDID_C,
607 AUD_CNTL_ST_C,
608 TRANSACONF,
609 FDI_RXA_CTL,
610 FDI_RX_MISC_A,
611 FDI_RXA_IIR,
612 FDI_RXA_IMR,
613 FDI_RXA_TUSIZE1,
614 QUIRK_F0060,
615 TRANSA_CHICKEN2,
616 TRANSBCONF,
617 FDI_RXB_CTL,
618 FDI_RX_MISC_B,
619 FDI_RXB_IIR,
620 FDI_RXB_IMR,
621 FDI_RXB_TUSIZE1,
622 QUIRK_F1060,
623 TRANSB_CHICKEN2,
624 TRANSCCONF,
625 FDI_RXC_CTL,
626 FDI_RX_MISC_C,
627 FDI_RXC_IIR,
628 FDI_RXC_IMR,
629 FDI_RXC_TUSIZE1,
630 QUIRK_F2060,
631 TRANSC_CHICKEN2,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]632 BXT_P_CR_GT_DISP_PWRON,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]633 GT_MAILBOX,
634 GT_MAILBOX_DATA,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]635 GT_MAILBOX_DATA_1,
636 BXT_PORT_CL1CM_DW0_A,
637 BXT_PORT_CL1CM_DW9_A,
638 BXT_PORT_CL1CM_DW10_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]639 BXT_PORT_PLL_EBB_0_A,
640 BXT_PORT_PLL_EBB_4_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]641 BXT_PORT_CL1CM_DW28_A,
642 BXT_PORT_CL1CM_DW30_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]643 BXT_PORT_PLL_0_A,
644 BXT_PORT_PLL_1_A,
645 BXT_PORT_PLL_2_A,
646 BXT_PORT_PLL_3_A,
647 BXT_PORT_PLL_6_A,
648 BXT_PORT_PLL_8_A,
649 BXT_PORT_PLL_9_A,
650 BXT_PORT_PLL_10_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]651 BXT_PORT_REF_DW3_A,
652 BXT_PORT_REF_DW6_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]653 BXT_PORT_REF_DW8_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]654 BXT_PORT_PCS_DW10_01_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]655 BXT_PORT_PCS_DW12_01_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]656 BXT_PORT_TX_DW2_LN0_A,
657 BXT_PORT_TX_DW3_LN0_A,
658 BXT_PORT_TX_DW4_LN0_A,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]659 BXT_PORT_TX_DW14_LN0_A,
660 BXT_PORT_TX_DW14_LN1_A,
661 BXT_PORT_TX_DW14_LN2_A,
662 BXT_PORT_TX_DW14_LN3_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]663 BXT_PORT_PCS_DW10_GRP_A,
664 BXT_PORT_PCS_DW12_GRP_A,
665 BXT_PORT_TX_DW2_GRP_A,
666 BXT_PORT_TX_DW3_GRP_A,
667 BXT_PORT_TX_DW4_GRP_A);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]668
669 pragma Warnings
670 (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)",
671 Reason => "TODO: Should it matter?");
672 pragma Keep_Names (Registers_Invalid_Index);
673 pragma Warnings
674 (GNATprove, On, "pragma ""KEEP_NAMES"" ignored *(not yet supported)");
675
676 Register_Width : constant := 4;
677
678 for Registers_Invalid_Index use
679 (Invalid_Register => 0,
680
681 ---------------------------------------------------------------------------
682 -- Pipe A registers
683 ---------------------------------------------------------------------------
684
685 -- pipe timing registers
686
687 HTOTAL_A => 16#06_0000# / Register_Width,
688 HBLANK_A => 16#06_0004# / Register_Width,
689 HSYNC_A => 16#06_0008# / Register_Width,
690 VTOTAL_A => 16#06_000c# / Register_Width,
691 VBLANK_A => 16#06_0010# / Register_Width,
692 VSYNC_A => 16#06_0014# / Register_Width,
693 PIPEASRC => 16#06_001c# / Register_Width,
694 PIPEACONF => 16#07_0008# / Register_Width,
695 PIPEAMISC => 16#07_0030# / Register_Width,
696 TRANS_HTOTAL_A => 16#0e_0000# / Register_Width,
697 TRANS_HBLANK_A => 16#0e_0004# / Register_Width,
698 TRANS_HSYNC_A => 16#0e_0008# / Register_Width,
699 TRANS_VTOTAL_A => 16#0e_000c# / Register_Width,
700 TRANS_VBLANK_A => 16#0e_0010# / Register_Width,
701 TRANS_VSYNC_A => 16#0e_0014# / Register_Width,
702 TRANSA_DATA_M1 => 16#0e_0030# / Register_Width,
703 TRANSA_DATA_N1 => 16#0e_0034# / Register_Width,
704 TRANSA_DP_LINK_M1 => 16#0e_0040# / Register_Width,
705 TRANSA_DP_LINK_N1 => 16#0e_0044# / Register_Width,
706 PIPEA_DATA_M1 => 16#06_0030# / Register_Width,
707 PIPEA_DATA_N1 => 16#06_0034# / Register_Width,
708 PIPEA_LINK_M1 => 16#06_0040# / Register_Width,
709 PIPEA_LINK_N1 => 16#06_0044# / Register_Width,
710 PIPEA_DDI_FUNC_CTL => 16#06_0400# / Register_Width,
711 PIPEA_MSA_MISC => 16#06_0410# / Register_Width,
712
713 -- PCH sideband interface registers
714 SBI_ADDR => 16#0c_6000# / Register_Width,
715 SBI_DATA => 16#0c_6004# / Register_Width,
716 SBI_CTL_STAT => 16#0c_6008# / Register_Width,
717
718 -- clock registers
719 PCH_DPLL_A => 16#0c_6014# / Register_Width,
720 PCH_PIXCLK_GATE => 16#0c_6020# / Register_Width,
721 PCH_FPA0 => 16#0c_6040# / Register_Width,
722 PCH_FPA1 => 16#0c_6044# / Register_Width,
723
724 -- panel fitter
725 PFA_CTL_1 => 16#06_8080# / Register_Width,
726 PFA_WIN_POS => 16#06_8070# / Register_Width,
727 PFA_WIN_SZ => 16#06_8074# / Register_Width,
728 PS_WIN_POS_1_A => 16#06_8170# / Register_Width,
729 PS_WIN_SZ_1_A => 16#06_8174# / Register_Width,
730 PS_CTRL_1_A => 16#06_8180# / Register_Width,
731 PS_WIN_POS_2_A => 16#06_8270# / Register_Width,
732 PS_WIN_SZ_2_A => 16#06_8274# / Register_Width,
733 PS_CTRL_2_A => 16#06_8280# / Register_Width,
734
735 -- display control
736 DSPACNTR => 16#07_0180# / Register_Width,
737 DSPALINOFF => 16#07_0184# / Register_Width,
738 DSPASTRIDE => 16#07_0188# / Register_Width,
739 PLANE_POS_1_A => 16#07_018c# / Register_Width,
740 PLANE_SIZE_1_A => 16#07_0190# / Register_Width,
741 DSPASURF => 16#07_019c# / Register_Width,
742 DSPATILEOFF => 16#07_01a4# / Register_Width,
743
744 -- sprite control
745 SPACNTR => 16#07_0280# / Register_Width,
746
747 -- FDI and PCH transcoder control
748 FDI_TX_CTL_A => 16#06_0100# / Register_Width,
749 FDI_RXA_CTL => 16#0f_000c# / Register_Width,
750 FDI_RX_MISC_A => 16#0f_0010# / Register_Width,
751 FDI_RXA_IIR => 16#0f_0014# / Register_Width,
752 FDI_RXA_IMR => 16#0f_0018# / Register_Width,
753 FDI_RXA_TUSIZE1 => 16#0f_0030# / Register_Width,
754 TRANSACONF => 16#0f_0008# / Register_Width,
755 TRANSA_CHICKEN2 => 16#0f_0064# / Register_Width,
756
757 -- watermark registers
758 WM_LINETIME_A => 16#04_5270# / Register_Width,
759 PLANE_WM_1_A_0 => 16#07_0240# / Register_Width,
760 PLANE_WM_1_A_1 => 16#07_0244# / Register_Width,
761 PLANE_WM_1_A_2 => 16#07_0248# / Register_Width,
762 PLANE_WM_1_A_3 => 16#07_024c# / Register_Width,
763 PLANE_WM_1_A_4 => 16#07_0250# / Register_Width,
764 PLANE_WM_1_A_5 => 16#07_0254# / Register_Width,
765 PLANE_WM_1_A_6 => 16#07_0258# / Register_Width,
766 PLANE_WM_1_A_7 => 16#07_025c# / Register_Width,
767 PLANE_BUF_CFG_1_A => 16#07_027c# / Register_Width,
768
769 -- CPU transcoder clock select
770 TRANSA_CLK_SEL => 16#04_6140# / Register_Width,
771
772 ---------------------------------------------------------------------------
773 -- Pipe B registers
774 ---------------------------------------------------------------------------
775
776 -- pipe timing registers
777
778 HTOTAL_B => 16#06_1000# / Register_Width,
779 HBLANK_B => 16#06_1004# / Register_Width,
780 HSYNC_B => 16#06_1008# / Register_Width,
781 VTOTAL_B => 16#06_100c# / Register_Width,
782 VBLANK_B => 16#06_1010# / Register_Width,
783 VSYNC_B => 16#06_1014# / Register_Width,
784 PIPEBSRC => 16#06_101c# / Register_Width,
785 PIPEBCONF => 16#07_1008# / Register_Width,
786 PIPEBMISC => 16#07_1030# / Register_Width,
787 TRANS_HTOTAL_B => 16#0e_1000# / Register_Width,
788 TRANS_HBLANK_B => 16#0e_1004# / Register_Width,
789 TRANS_HSYNC_B => 16#0e_1008# / Register_Width,
790 TRANS_VTOTAL_B => 16#0e_100c# / Register_Width,
791 TRANS_VBLANK_B => 16#0e_1010# / Register_Width,
792 TRANS_VSYNC_B => 16#0e_1014# / Register_Width,
793 TRANSB_DATA_M1 => 16#0e_1030# / Register_Width,
794 TRANSB_DATA_N1 => 16#0e_1034# / Register_Width,
795 TRANSB_DP_LINK_M1 => 16#0e_1040# / Register_Width,
796 TRANSB_DP_LINK_N1 => 16#0e_1044# / Register_Width,
797 PIPEB_DATA_M1 => 16#06_1030# / Register_Width,
798 PIPEB_DATA_N1 => 16#06_1034# / Register_Width,
799 PIPEB_LINK_M1 => 16#06_1040# / Register_Width,
800 PIPEB_LINK_N1 => 16#06_1044# / Register_Width,
801 PIPEB_DDI_FUNC_CTL => 16#06_1400# / Register_Width,
802 PIPEB_MSA_MISC => 16#06_1410# / Register_Width,
803
804 -- clock registers
805 PCH_DPLL_B => 16#0c_6018# / Register_Width,
806 PCH_FPB0 => 16#0c_6048# / Register_Width,
807 PCH_FPB1 => 16#0c_604c# / Register_Width,
808
809 -- panel fitter
810 PFB_CTL_1 => 16#06_8880# / Register_Width,
811 PFB_WIN_POS => 16#06_8870# / Register_Width,
812 PFB_WIN_SZ => 16#06_8874# / Register_Width,
813 PS_WIN_POS_1_B => 16#06_8970# / Register_Width,
814 PS_WIN_SZ_1_B => 16#06_8974# / Register_Width,
815 PS_CTRL_1_B => 16#06_8980# / Register_Width,
816 PS_WIN_POS_2_B => 16#06_8a70# / Register_Width,
817 PS_WIN_SZ_2_B => 16#06_8a74# / Register_Width,
818 PS_CTRL_2_B => 16#06_8a80# / Register_Width,
819
820 -- display control
821 DSPBCNTR => 16#07_1180# / Register_Width,
822 DSPBLINOFF => 16#07_1184# / Register_Width,
823 DSPBSTRIDE => 16#07_1188# / Register_Width,
824 PLANE_POS_1_B => 16#07_118c# / Register_Width,
825 PLANE_SIZE_1_B => 16#07_1190# / Register_Width,
826 DSPBSURF => 16#07_119c# / Register_Width,
827 DSPBTILEOFF => 16#07_11a4# / Register_Width,
828
829 -- sprite control
830 SPBCNTR => 16#07_1280# / Register_Width,
831
832 -- FDI and PCH transcoder control
833 FDI_TX_CTL_B => 16#06_1100# / Register_Width,
834 FDI_RXB_CTL => 16#0f_100c# / Register_Width,
835 FDI_RX_MISC_B => 16#0f_1010# / Register_Width,
836 FDI_RXB_IIR => 16#0f_1014# / Register_Width,
837 FDI_RXB_IMR => 16#0f_1018# / Register_Width,
838 FDI_RXB_TUSIZE1 => 16#0f_1030# / Register_Width,
839 TRANSBCONF => 16#0f_1008# / Register_Width,
840 TRANSB_CHICKEN2 => 16#0f_1064# / Register_Width,
841
842 -- watermark registers
843 WM_LINETIME_B => 16#04_5274# / Register_Width,
844 PLANE_WM_1_B_0 => 16#07_1240# / Register_Width,
845 PLANE_WM_1_B_1 => 16#07_1244# / Register_Width,
846 PLANE_WM_1_B_2 => 16#07_1248# / Register_Width,
847 PLANE_WM_1_B_3 => 16#07_124c# / Register_Width,
848 PLANE_WM_1_B_4 => 16#07_1250# / Register_Width,
849 PLANE_WM_1_B_5 => 16#07_1254# / Register_Width,
850 PLANE_WM_1_B_6 => 16#07_1258# / Register_Width,
851 PLANE_WM_1_B_7 => 16#07_125c# / Register_Width,
852 PLANE_BUF_CFG_1_B => 16#07_127c# / Register_Width,
853
854 -- CPU transcoder clock select
855 TRANSB_CLK_SEL => 16#04_6144# / Register_Width,
856
857 ---------------------------------------------------------------------------
858 -- Pipe C registers
859 ---------------------------------------------------------------------------
860
861 -- pipe timing registers
862
863 HTOTAL_C => 16#06_2000# / Register_Width,
864 HBLANK_C => 16#06_2004# / Register_Width,
865 HSYNC_C => 16#06_2008# / Register_Width,
866 VTOTAL_C => 16#06_200c# / Register_Width,
867 VBLANK_C => 16#06_2010# / Register_Width,
868 VSYNC_C => 16#06_2014# / Register_Width,
869 PIPECSRC => 16#06_201c# / Register_Width,
870 PIPECCONF => 16#07_2008# / Register_Width,
871 PIPECMISC => 16#07_2030# / Register_Width,
872 TRANS_HTOTAL_C => 16#0e_2000# / Register_Width,
873 TRANS_HBLANK_C => 16#0e_2004# / Register_Width,
874 TRANS_HSYNC_C => 16#0e_2008# / Register_Width,
875 TRANS_VTOTAL_C => 16#0e_200c# / Register_Width,
876 TRANS_VBLANK_C => 16#0e_2010# / Register_Width,
877 TRANS_VSYNC_C => 16#0e_2014# / Register_Width,
878 TRANSC_DATA_M1 => 16#0e_2030# / Register_Width,
879 TRANSC_DATA_N1 => 16#0e_2034# / Register_Width,
880 TRANSC_DP_LINK_M1 => 16#0e_2040# / Register_Width,
881 TRANSC_DP_LINK_N1 => 16#0e_2044# / Register_Width,
882 PIPEC_DATA_M1 => 16#06_2030# / Register_Width,
883 PIPEC_DATA_N1 => 16#06_2034# / Register_Width,
884 PIPEC_LINK_M1 => 16#06_2040# / Register_Width,
885 PIPEC_LINK_N1 => 16#06_2044# / Register_Width,
886 PIPEC_DDI_FUNC_CTL => 16#06_2400# / Register_Width,
887 PIPEC_MSA_MISC => 16#06_2410# / Register_Width,
888
889 -- panel fitter
890 PFC_CTL_1 => 16#06_9080# / Register_Width,
891 PFC_WIN_POS => 16#06_9070# / Register_Width,
892 PFC_WIN_SZ => 16#06_9074# / Register_Width,
893 PS_WIN_POS_1_C => 16#06_9170# / Register_Width,
894 PS_WIN_SZ_1_C => 16#06_9174# / Register_Width,
895 PS_CTRL_1_C => 16#06_9180# / Register_Width,
896
897 -- display control
898 DSPCCNTR => 16#07_2180# / Register_Width,
899 DSPCLINOFF => 16#07_2184# / Register_Width,
900 DSPCSTRIDE => 16#07_2188# / Register_Width,
901 PLANE_POS_1_C => 16#07_218c# / Register_Width,
902 PLANE_SIZE_1_C => 16#07_2190# / Register_Width,
903 DSPCSURF => 16#07_219c# / Register_Width,
904 DSPCTILEOFF => 16#07_21a4# / Register_Width,
905
906 -- sprite control
907 SPCCNTR => 16#07_2280# / Register_Width,
908
909 -- PCH transcoder control
910 FDI_TX_CTL_C => 16#06_2100# / Register_Width,
911 FDI_RXC_CTL => 16#0f_200c# / Register_Width,
912 FDI_RX_MISC_C => 16#0f_2010# / Register_Width,
913 FDI_RXC_IIR => 16#0f_2014# / Register_Width,
914 FDI_RXC_IMR => 16#0f_2018# / Register_Width,
915 FDI_RXC_TUSIZE1 => 16#0f_2030# / Register_Width,
916 TRANSCCONF => 16#0f_2008# / Register_Width,
917 TRANSC_CHICKEN2 => 16#0f_2064# / Register_Width,
918
919 -- watermark registers
920 WM_LINETIME_C => 16#04_5278# / Register_Width,
921 PLANE_WM_1_C_0 => 16#07_2240# / Register_Width,
922 PLANE_WM_1_C_1 => 16#07_2244# / Register_Width,
923 PLANE_WM_1_C_2 => 16#07_2248# / Register_Width,
924 PLANE_WM_1_C_3 => 16#07_224c# / Register_Width,
925 PLANE_WM_1_C_4 => 16#07_2250# / Register_Width,
926 PLANE_WM_1_C_5 => 16#07_2254# / Register_Width,
927 PLANE_WM_1_C_6 => 16#07_2258# / Register_Width,
928 PLANE_WM_1_C_7 => 16#07_225c# / Register_Width,
929 PLANE_BUF_CFG_1_C => 16#07_227c# / Register_Width,
930
931 -- CPU transcoder clock select
932 TRANSC_CLK_SEL => 16#04_6148# / Register_Width,
933
934 ---------------------------------------------------------------------------
935 -- Pipe EDP registers
936 ---------------------------------------------------------------------------
937
938 -- pipe timing registers
939
940 HTOTAL_EDP => 16#06_f000# / Register_Width,
941 HBLANK_EDP => 16#06_f004# / Register_Width,
942 HSYNC_EDP => 16#06_f008# / Register_Width,
943 VTOTAL_EDP => 16#06_f00c# / Register_Width,
944 VBLANK_EDP => 16#06_f010# / Register_Width,
945 VSYNC_EDP => 16#06_f014# / Register_Width,
946 PIPE_EDP_CONF => 16#07_f008# / Register_Width,
947 PIPE_EDP_DATA_M1 => 16#06_f030# / Register_Width,
948 PIPE_EDP_DATA_N1 => 16#06_f034# / Register_Width,
949 PIPE_EDP_LINK_M1 => 16#06_f040# / Register_Width,
950 PIPE_EDP_LINK_N1 => 16#06_f044# / Register_Width,
951 PIPE_EDP_DDI_FUNC_CTL => 16#06_f400# / Register_Width,
952 PIPE_EDP_MSA_MISC => 16#06_f410# / Register_Width,
953
954 -- PSR registers
955 SRD_CTL => 16#06_4800# / Register_Width,
956 SRD_CTL_A => 16#06_0800# / Register_Width,
957 SRD_CTL_B => 16#06_1800# / Register_Width,
958 SRD_CTL_C => 16#06_2800# / Register_Width,
959 SRD_CTL_EDP => 16#06_f800# / Register_Width,
960 SRD_STATUS => 16#06_4840# / Register_Width,
961 SRD_STATUS_A => 16#06_0840# / Register_Width,
962 SRD_STATUS_B => 16#06_1840# / Register_Width,
963 SRD_STATUS_C => 16#06_2840# / Register_Width,
964 SRD_STATUS_EDP => 16#06_f840# / Register_Width,
965
966 -- DDI registers
967 DDI_BUF_CTL_A => 16#06_4000# / Register_Width, -- aliased by DP_CTL_A
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]968 DDI_BUF_TRANS_A_S0T1 => 16#06_4e00# / Register_Width,
969 DDI_BUF_TRANS_A_S0T2 => 16#06_4e04# / Register_Width,
970 DDI_BUF_TRANS_A_S1T1 => 16#06_4e08# / Register_Width,
971 DDI_BUF_TRANS_A_S1T2 => 16#06_4e0c# / Register_Width,
972 DDI_BUF_TRANS_A_S2T1 => 16#06_4e10# / Register_Width,
973 DDI_BUF_TRANS_A_S2T2 => 16#06_4e14# / Register_Width,
974 DDI_BUF_TRANS_A_S3T1 => 16#06_4e18# / Register_Width,
975 DDI_BUF_TRANS_A_S3T2 => 16#06_4e1c# / Register_Width,
976 DDI_BUF_TRANS_A_S4T1 => 16#06_4e20# / Register_Width,
977 DDI_BUF_TRANS_A_S4T2 => 16#06_4e24# / Register_Width,
978 DDI_BUF_TRANS_A_S5T1 => 16#06_4e28# / Register_Width,
979 DDI_BUF_TRANS_A_S5T2 => 16#06_4e2c# / Register_Width,
980 DDI_BUF_TRANS_A_S6T1 => 16#06_4e30# / Register_Width,
981 DDI_BUF_TRANS_A_S6T2 => 16#06_4e34# / Register_Width,
982 DDI_BUF_TRANS_A_S7T1 => 16#06_4e38# / Register_Width,
983 DDI_BUF_TRANS_A_S7T2 => 16#06_4e3c# / Register_Width,
984 DDI_BUF_TRANS_A_S8T1 => 16#06_4e40# / Register_Width,
985 DDI_BUF_TRANS_A_S8T2 => 16#06_4e44# / Register_Width,
986 DDI_BUF_TRANS_A_S9T1 => 16#06_4e48# / Register_Width,
987 DDI_BUF_TRANS_A_S9T2 => 16#06_4e4c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]988 DDI_AUX_CTL_A => 16#06_4010# / Register_Width, -- aliased by DP_AUX_CTL_A
989 DDI_AUX_DATA_A_1 => 16#06_4014# / Register_Width, -- aliased by DP_AUX_DATA_A_1
990 DDI_AUX_DATA_A_2 => 16#06_4018# / Register_Width, -- aliased by DP_AUX_DATA_A_2
991 DDI_AUX_DATA_A_3 => 16#06_401c# / Register_Width, -- aliased by DP_AUX_DATA_A_3
992 DDI_AUX_DATA_A_4 => 16#06_4020# / Register_Width, -- aliased by DP_AUX_DATA_A_4
993 DDI_AUX_DATA_A_5 => 16#06_4024# / Register_Width, -- aliased by DP_AUX_DATA_A_5
994 DDI_AUX_MUTEX_A => 16#06_402c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]995
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]996 DDI_BUF_CTL_B => 16#06_4100# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]997 DDI_BUF_TRANS_B_S0T1 => 16#06_4e60# / Register_Width,
998 DDI_BUF_TRANS_B_S0T2 => 16#06_4e64# / Register_Width,
999 DDI_BUF_TRANS_B_S1T1 => 16#06_4e68# / Register_Width,
1000 DDI_BUF_TRANS_B_S1T2 => 16#06_4e6c# / Register_Width,
1001 DDI_BUF_TRANS_B_S2T1 => 16#06_4e70# / Register_Width,
1002 DDI_BUF_TRANS_B_S2T2 => 16#06_4e74# / Register_Width,
1003 DDI_BUF_TRANS_B_S3T1 => 16#06_4e78# / Register_Width,
1004 DDI_BUF_TRANS_B_S3T2 => 16#06_4e7c# / Register_Width,
1005 DDI_BUF_TRANS_B_S4T1 => 16#06_4e80# / Register_Width,
1006 DDI_BUF_TRANS_B_S4T2 => 16#06_4e84# / Register_Width,
1007 DDI_BUF_TRANS_B_S5T1 => 16#06_4e88# / Register_Width,
1008 DDI_BUF_TRANS_B_S5T2 => 16#06_4e8c# / Register_Width,
1009 DDI_BUF_TRANS_B_S6T1 => 16#06_4e90# / Register_Width,
1010 DDI_BUF_TRANS_B_S6T2 => 16#06_4e94# / Register_Width,
1011 DDI_BUF_TRANS_B_S7T1 => 16#06_4e98# / Register_Width,
1012 DDI_BUF_TRANS_B_S7T2 => 16#06_4e9c# / Register_Width,
1013 DDI_BUF_TRANS_B_S8T1 => 16#06_4ea0# / Register_Width,
1014 DDI_BUF_TRANS_B_S8T2 => 16#06_4ea4# / Register_Width,
1015 DDI_BUF_TRANS_B_S9T1 => 16#06_4ea8# / Register_Width,
1016 DDI_BUF_TRANS_B_S9T2 => 16#06_4eac# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1017 DDI_AUX_CTL_B => 16#06_4110# / Register_Width,
1018 DDI_AUX_DATA_B_1 => 16#06_4114# / Register_Width,
1019 DDI_AUX_DATA_B_2 => 16#06_4118# / Register_Width,
1020 DDI_AUX_DATA_B_3 => 16#06_411c# / Register_Width,
1021 DDI_AUX_DATA_B_4 => 16#06_4120# / Register_Width,
1022 DDI_AUX_DATA_B_5 => 16#06_4124# / Register_Width,
1023 DDI_AUX_MUTEX_B => 16#06_412c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1024
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1025 DDI_BUF_CTL_C => 16#06_4200# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1026 DDI_BUF_TRANS_C_S0T1 => 16#06_4ec0# / Register_Width,
1027 DDI_BUF_TRANS_C_S0T2 => 16#06_4ec4# / Register_Width,
1028 DDI_BUF_TRANS_C_S1T1 => 16#06_4ec8# / Register_Width,
1029 DDI_BUF_TRANS_C_S1T2 => 16#06_4ecc# / Register_Width,
1030 DDI_BUF_TRANS_C_S2T1 => 16#06_4ed0# / Register_Width,
1031 DDI_BUF_TRANS_C_S2T2 => 16#06_4ed4# / Register_Width,
1032 DDI_BUF_TRANS_C_S3T1 => 16#06_4ed8# / Register_Width,
1033 DDI_BUF_TRANS_C_S3T2 => 16#06_4edc# / Register_Width,
1034 DDI_BUF_TRANS_C_S4T1 => 16#06_4ee0# / Register_Width,
1035 DDI_BUF_TRANS_C_S4T2 => 16#06_4ee4# / Register_Width,
1036 DDI_BUF_TRANS_C_S5T1 => 16#06_4ee8# / Register_Width,
1037 DDI_BUF_TRANS_C_S5T2 => 16#06_4eec# / Register_Width,
1038 DDI_BUF_TRANS_C_S6T1 => 16#06_4ef0# / Register_Width,
1039 DDI_BUF_TRANS_C_S6T2 => 16#06_4ef4# / Register_Width,
1040 DDI_BUF_TRANS_C_S7T1 => 16#06_4ef8# / Register_Width,
1041 DDI_BUF_TRANS_C_S7T2 => 16#06_4efc# / Register_Width,
1042 DDI_BUF_TRANS_C_S8T1 => 16#06_4f00# / Register_Width,
1043 DDI_BUF_TRANS_C_S8T2 => 16#06_4f04# / Register_Width,
1044 DDI_BUF_TRANS_C_S9T1 => 16#06_4f08# / Register_Width,
1045 DDI_BUF_TRANS_C_S9T2 => 16#06_4f0c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1046 DDI_AUX_CTL_C => 16#06_4210# / Register_Width,
1047 DDI_AUX_DATA_C_1 => 16#06_4214# / Register_Width,
1048 DDI_AUX_DATA_C_2 => 16#06_4218# / Register_Width,
1049 DDI_AUX_DATA_C_3 => 16#06_421c# / Register_Width,
1050 DDI_AUX_DATA_C_4 => 16#06_4220# / Register_Width,
1051 DDI_AUX_DATA_C_5 => 16#06_4224# / Register_Width,
1052 DDI_AUX_MUTEX_C => 16#06_422c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1053
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1054 DDI_BUF_CTL_D => 16#06_4300# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1055 DDI_BUF_TRANS_D_S0T1 => 16#06_4f20# / Register_Width,
1056 DDI_BUF_TRANS_D_S0T2 => 16#06_4f24# / Register_Width,
1057 DDI_BUF_TRANS_D_S1T1 => 16#06_4f28# / Register_Width,
1058 DDI_BUF_TRANS_D_S1T2 => 16#06_4f2c# / Register_Width,
1059 DDI_BUF_TRANS_D_S2T1 => 16#06_4f30# / Register_Width,
1060 DDI_BUF_TRANS_D_S2T2 => 16#06_4f34# / Register_Width,
1061 DDI_BUF_TRANS_D_S3T1 => 16#06_4f38# / Register_Width,
1062 DDI_BUF_TRANS_D_S3T2 => 16#06_4f3c# / Register_Width,
1063 DDI_BUF_TRANS_D_S4T1 => 16#06_4f40# / Register_Width,
1064 DDI_BUF_TRANS_D_S4T2 => 16#06_4f44# / Register_Width,
1065 DDI_BUF_TRANS_D_S5T1 => 16#06_4f48# / Register_Width,
1066 DDI_BUF_TRANS_D_S5T2 => 16#06_4f4c# / Register_Width,
1067 DDI_BUF_TRANS_D_S6T1 => 16#06_4f50# / Register_Width,
1068 DDI_BUF_TRANS_D_S6T2 => 16#06_4f54# / Register_Width,
1069 DDI_BUF_TRANS_D_S7T1 => 16#06_4f58# / Register_Width,
1070 DDI_BUF_TRANS_D_S7T2 => 16#06_4f5c# / Register_Width,
1071 DDI_BUF_TRANS_D_S8T1 => 16#06_4f60# / Register_Width,
1072 DDI_BUF_TRANS_D_S8T2 => 16#06_4f64# / Register_Width,
1073 DDI_BUF_TRANS_D_S9T1 => 16#06_4f68# / Register_Width,
1074 DDI_BUF_TRANS_D_S9T2 => 16#06_4f6c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1075 DDI_AUX_CTL_D => 16#06_4310# / Register_Width,
1076 DDI_AUX_DATA_D_1 => 16#06_4314# / Register_Width,
1077 DDI_AUX_DATA_D_2 => 16#06_4318# / Register_Width,
1078 DDI_AUX_DATA_D_3 => 16#06_431c# / Register_Width,
1079 DDI_AUX_DATA_D_4 => 16#06_4320# / Register_Width,
1080 DDI_AUX_DATA_D_5 => 16#06_4324# / Register_Width,
1081 DDI_AUX_MUTEX_D => 16#06_432c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1082
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1083 DDI_BUF_CTL_E => 16#06_4400# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1084 DDI_BUF_TRANS_E_S0T1 => 16#06_4f80# / Register_Width,
1085 DDI_BUF_TRANS_E_S0T2 => 16#06_4f84# / Register_Width,
1086 DDI_BUF_TRANS_E_S1T1 => 16#06_4f88# / Register_Width,
1087 DDI_BUF_TRANS_E_S1T2 => 16#06_4f8c# / Register_Width,
1088 DDI_BUF_TRANS_E_S2T1 => 16#06_4f90# / Register_Width,
1089 DDI_BUF_TRANS_E_S2T2 => 16#06_4f94# / Register_Width,
1090 DDI_BUF_TRANS_E_S3T1 => 16#06_4f98# / Register_Width,
1091 DDI_BUF_TRANS_E_S3T2 => 16#06_4f9c# / Register_Width,
1092 DDI_BUF_TRANS_E_S4T1 => 16#06_4fa0# / Register_Width,
1093 DDI_BUF_TRANS_E_S4T2 => 16#06_4fa4# / Register_Width,
1094 DDI_BUF_TRANS_E_S5T1 => 16#06_4fa8# / Register_Width,
1095 DDI_BUF_TRANS_E_S5T2 => 16#06_4fac# / Register_Width,
1096 DDI_BUF_TRANS_E_S6T1 => 16#06_4fb0# / Register_Width,
1097 DDI_BUF_TRANS_E_S6T2 => 16#06_4fb4# / Register_Width,
1098 DDI_BUF_TRANS_E_S7T1 => 16#06_4fb8# / Register_Width,
1099 DDI_BUF_TRANS_E_S7T2 => 16#06_4fbc# / Register_Width,
1100 DDI_BUF_TRANS_E_S8T1 => 16#06_4fc0# / Register_Width,
1101 DDI_BUF_TRANS_E_S8T2 => 16#06_4fc4# / Register_Width,
1102 DDI_BUF_TRANS_E_S9T1 => 16#06_4fc8# / Register_Width,
1103 DDI_BUF_TRANS_E_S9T2 => 16#06_4fcc# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1104 DP_TP_CTL_A => 16#06_4040# / Register_Width,
1105 DP_TP_CTL_B => 16#06_4140# / Register_Width,
1106 DP_TP_CTL_C => 16#06_4240# / Register_Width,
1107 DP_TP_CTL_D => 16#06_4340# / Register_Width,
1108 DP_TP_CTL_E => 16#06_4440# / Register_Width,
1109 DP_TP_STATUS_B => 16#06_4144# / Register_Width,
1110 DP_TP_STATUS_C => 16#06_4244# / Register_Width,
1111 DP_TP_STATUS_D => 16#06_4344# / Register_Width,
1112 DP_TP_STATUS_E => 16#06_4444# / Register_Width,
1113 PORT_CLK_SEL_DDIA => 16#04_6100# / Register_Width,
1114 PORT_CLK_SEL_DDIB => 16#04_6104# / Register_Width,
1115 PORT_CLK_SEL_DDIC => 16#04_6108# / Register_Width,
1116 PORT_CLK_SEL_DDID => 16#04_610c# / Register_Width,
1117 PORT_CLK_SEL_DDIE => 16#04_6110# / Register_Width,
1118
Nico Huber58afc202017-06-12 21:34:55 +0200[diff] [blame]1119 -- Skylake I_boost configuration
1120 DISPIO_CR_TX_BMU_CR0 => 16#06_c00c# / Register_Width,
1121
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1122 -- Skylake DPLL registers
1123 DPLL1_CFGR1 => 16#06_c040# / Register_Width,
1124 DPLL1_CFGR2 => 16#06_c044# / Register_Width,
1125 DPLL2_CFGR1 => 16#06_c048# / Register_Width,
1126 DPLL2_CFGR2 => 16#06_c04c# / Register_Width,
1127 DPLL3_CFGR1 => 16#06_c050# / Register_Width,
1128 DPLL3_CFGR2 => 16#06_c054# / Register_Width,
1129 DPLL_CTRL1 => 16#06_c058# / Register_Width,
1130 DPLL_CTRL2 => 16#06_c05c# / Register_Width,
1131 DPLL_STATUS => 16#06_c060# / Register_Width,
1132
1133 -- CD CLK register
1134 CDCLK_CTL => 16#04_6000# / Register_Width,
1135
1136 -- Skylake LCPLL registers
1137 LCPLL1_CTL => 16#04_6010# / Register_Width,
1138 LCPLL2_CTL => 16#04_6014# / Register_Width,
1139
1140 -- SPLL register
1141 SPLL_CTL => 16#04_6020# / Register_Width,
1142
1143 -- WRPLL registers
1144 WRPLL_CTL_1 => 16#04_6040# / Register_Width,
1145 WRPLL_CTL_2 => 16#04_6060# / Register_Width,
1146
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]1147 -- Broxton Display Engine PLL registers
1148 BXT_DE_PLL_CTL => 16#06_d000# / Register_Width,
1149 BXT_DE_PLL_ENABLE => 16#04_6070# / Register_Width,
1150
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1151 -- Broxton DDI PHY PLL registers
1152 BXT_PORT_PLL_ENABLE_A => 16#04_6074# / Register_Width,
1153 BXT_PORT_PLL_ENABLE_B => 16#04_6078# / Register_Width,
1154 BXT_PORT_PLL_ENABLE_C => 16#04_607c# / Register_Width,
1155 BXT_PORT_PLL_EBB_0_A => 16#16_2034# / Register_Width,
1156 BXT_PORT_PLL_EBB_4_A => 16#16_2038# / Register_Width,
1157 BXT_PORT_PLL_0_A => 16#16_2100# / Register_Width,
1158 BXT_PORT_PLL_1_A => 16#16_2104# / Register_Width,
1159 BXT_PORT_PLL_2_A => 16#16_2108# / Register_Width,
1160 BXT_PORT_PLL_3_A => 16#16_210c# / Register_Width,
1161 BXT_PORT_PLL_6_A => 16#16_2118# / Register_Width,
1162 BXT_PORT_PLL_8_A => 16#16_2120# / Register_Width,
1163 BXT_PORT_PLL_9_A => 16#16_2124# / Register_Width,
1164 BXT_PORT_PLL_10_A => 16#16_2128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1165 BXT_PORT_PLL_EBB_0_B => 16#06_c034# / Register_Width,
1166 BXT_PORT_PLL_EBB_4_B => 16#06_c038# / Register_Width,
1167 BXT_PORT_PLL_0_B => 16#06_c100# / Register_Width,
1168 BXT_PORT_PLL_1_B => 16#06_c104# / Register_Width,
1169 BXT_PORT_PLL_2_B => 16#06_c108# / Register_Width,
1170 BXT_PORT_PLL_3_B => 16#06_c10c# / Register_Width,
1171 BXT_PORT_PLL_6_B => 16#06_c118# / Register_Width,
1172 BXT_PORT_PLL_8_B => 16#06_c120# / Register_Width,
1173 BXT_PORT_PLL_9_B => 16#06_c124# / Register_Width,
1174 BXT_PORT_PLL_10_B => 16#06_c128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1175 BXT_PORT_PLL_EBB_0_C => 16#06_c340# / Register_Width,
1176 BXT_PORT_PLL_EBB_4_C => 16#06_c344# / Register_Width,
1177 BXT_PORT_PLL_0_C => 16#06_c380# / Register_Width,
1178 BXT_PORT_PLL_1_C => 16#06_c384# / Register_Width,
1179 BXT_PORT_PLL_2_C => 16#06_c388# / Register_Width,
1180 BXT_PORT_PLL_3_C => 16#06_c38c# / Register_Width,
1181 BXT_PORT_PLL_6_C => 16#06_c398# / Register_Width,
1182 BXT_PORT_PLL_8_C => 16#06_c3a0# / Register_Width,
1183 BXT_PORT_PLL_9_C => 16#06_c3a4# / Register_Width,
1184 BXT_PORT_PLL_10_C => 16#06_c3a8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1185
1186 -- Broxton DDI PHY PCS? registers
1187 BXT_PORT_PCS_DW10_01_A => 16#16_2428# / Register_Width,
1188 BXT_PORT_PCS_DW12_01_A => 16#16_2430# / Register_Width,
1189 BXT_PORT_PCS_DW10_GRP_A => 16#16_2c28# / Register_Width,
1190 BXT_PORT_PCS_DW12_GRP_A => 16#16_2c30# / Register_Width,
1191 BXT_PORT_PCS_DW10_01_B => 16#06_c428# / Register_Width,
1192 BXT_PORT_PCS_DW12_01_B => 16#06_c430# / Register_Width,
1193 BXT_PORT_PCS_DW10_01_C => 16#06_c828# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1194 BXT_PORT_PCS_DW12_01_C => 16#06_c830# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1195 BXT_PORT_PCS_DW10_GRP_B => 16#06_cc28# / Register_Width,
1196 BXT_PORT_PCS_DW12_GRP_B => 16#06_cc30# / Register_Width,
1197 BXT_PORT_PCS_DW10_GRP_C => 16#06_ce28# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1198 BXT_PORT_PCS_DW12_GRP_C => 16#06_ce30# / Register_Width,
1199
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]1200 -- Broxton DDI PHY registers
1201 BXT_P_CR_GT_DISP_PWRON => 16#13_8090# / Register_Width,
1202 BXT_PHY_CTL_A => 16#06_4c00# / Register_Width,
1203 BXT_PHY_CTL_B => 16#06_4c10# / Register_Width,
1204 BXT_PHY_CTL_C => 16#06_4c20# / Register_Width,
1205 BXT_PHY_CTL_FAM_EDP => 16#06_4c80# / Register_Width,
1206 BXT_PHY_CTL_FAM_DDI => 16#06_4c90# / Register_Width,
1207
1208 -- Broxton DDI PHY common lane registers
1209 BXT_PORT_CL1CM_DW0_A => 16#16_2000# / Register_Width,
1210 BXT_PORT_CL1CM_DW0_BC => 16#06_c000# / Register_Width,
1211 BXT_PORT_CL1CM_DW9_A => 16#16_2024# / Register_Width,
1212 BXT_PORT_CL1CM_DW9_BC => 16#06_c024# / Register_Width,
1213 BXT_PORT_CL1CM_DW10_A => 16#16_2028# / Register_Width,
1214 BXT_PORT_CL1CM_DW10_BC => 16#06_c028# / Register_Width,
1215 BXT_PORT_CL1CM_DW28_A => 16#16_2070# / Register_Width,
1216 BXT_PORT_CL1CM_DW28_BC => 16#06_c070# / Register_Width,
1217 BXT_PORT_CL1CM_DW30_A => 16#16_2078# / Register_Width,
1218 BXT_PORT_CL1CM_DW30_BC => 16#06_c078# / Register_Width,
1219 BXT_PORT_CL2CM_DW6_BC => 16#06_c358# / Register_Width,
1220
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1221 -- Broxton DDI PHY TX lane registers
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1222 BXT_PORT_TX_DW2_LN0_A => 16#16_2508# / Register_Width,
1223 BXT_PORT_TX_DW3_LN0_A => 16#16_250c# / Register_Width,
1224 BXT_PORT_TX_DW4_LN0_A => 16#16_2510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1225 BXT_PORT_TX_DW14_LN0_A => 16#16_2538# / Register_Width,
1226 BXT_PORT_TX_DW14_LN1_A => 16#16_25b8# / Register_Width,
1227 BXT_PORT_TX_DW14_LN2_A => 16#16_2738# / Register_Width,
1228 BXT_PORT_TX_DW14_LN3_A => 16#16_27b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1229 BXT_PORT_TX_DW2_GRP_A => 16#16_2d08# / Register_Width,
1230 BXT_PORT_TX_DW3_GRP_A => 16#16_2d0c# / Register_Width,
1231 BXT_PORT_TX_DW4_GRP_A => 16#16_2d10# / Register_Width,
1232 BXT_PORT_TX_DW2_LN0_B => 16#06_c508# / Register_Width,
1233 BXT_PORT_TX_DW3_LN0_B => 16#06_c50c# / Register_Width,
1234 BXT_PORT_TX_DW4_LN0_B => 16#06_c510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1235 BXT_PORT_TX_DW14_LN0_B => 16#06_c538# / Register_Width,
1236 BXT_PORT_TX_DW14_LN1_B => 16#06_c5b8# / Register_Width,
1237 BXT_PORT_TX_DW14_LN2_B => 16#06_c738# / Register_Width,
1238 BXT_PORT_TX_DW14_LN3_B => 16#06_c7b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1239 BXT_PORT_TX_DW2_GRP_B => 16#06_cd08# / Register_Width,
1240 BXT_PORT_TX_DW3_GRP_B => 16#06_cd0c# / Register_Width,
1241 BXT_PORT_TX_DW4_GRP_B => 16#06_cd10# / Register_Width,
1242 BXT_PORT_TX_DW2_LN0_C => 16#06_c908# / Register_Width,
1243 BXT_PORT_TX_DW3_LN0_C => 16#06_c90c# / Register_Width,
1244 BXT_PORT_TX_DW4_LN0_C => 16#06_c910# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1245 BXT_PORT_TX_DW14_LN0_C => 16#06_c938# / Register_Width,
1246 BXT_PORT_TX_DW14_LN1_C => 16#06_c9b8# / Register_Width,
1247 BXT_PORT_TX_DW14_LN2_C => 16#06_cb38# / Register_Width,
1248 BXT_PORT_TX_DW14_LN3_C => 16#06_cbb8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1249 BXT_PORT_TX_DW2_GRP_C => 16#06_cf08# / Register_Width,
1250 BXT_PORT_TX_DW3_GRP_C => 16#06_cf0c# / Register_Width,
1251 BXT_PORT_TX_DW4_GRP_C => 16#06_cf10# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1252
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]1253 -- Broxton DDI PHY ref registers
1254 BXT_PORT_REF_DW3_A => 16#16_218c# / Register_Width,
1255 BXT_PORT_REF_DW3_BC => 16#06_c18c# / Register_Width,
1256 BXT_PORT_REF_DW6_A => 16#16_2198# / Register_Width,
1257 BXT_PORT_REF_DW6_BC => 16#06_c198# / Register_Width,
1258 BXT_PORT_REF_DW8_A => 16#16_21a0# / Register_Width,
1259 BXT_PORT_REF_DW8_BC => 16#06_c1a0# / Register_Width,
1260
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1261 -- Power Down Well registers
1262 PWR_WELL_CTL_BIOS => 16#04_5400# / Register_Width,
1263 PWR_WELL_CTL_DRIVER => 16#04_5404# / Register_Width,
1264 PWR_WELL_CTL_KVMR => 16#04_5408# / Register_Width,
1265 PWR_WELL_CTL_DEBUG => 16#04_540c# / Register_Width,
1266 PWR_WELL_CTL5 => 16#04_5410# / Register_Width,
1267 PWR_WELL_CTL6 => 16#04_5414# / Register_Width,
1268
1269 -- class Panel registers
1270 PCH_PP_STATUS => 16#0c_7200# / Register_Width,
1271 PCH_PP_CONTROL => 16#0c_7204# / Register_Width,
1272 PCH_PP_ON_DELAYS => 16#0c_7208# / Register_Width,
1273 PCH_PP_OFF_DELAYS => 16#0c_720c# / Register_Width,
1274 PCH_PP_DIVISOR => 16#0c_7210# / Register_Width,
1275 BLC_PWM_CPU_CTL => 16#04_8254# / Register_Width,
1276 BLC_PWM_PCH_CTL2 => 16#0c_8254# / Register_Width,
1277
1278 -- PCH LVDS Connector Registers
1279 PCH_LVDS => 16#0e_1180# / Register_Width,
1280
1281 -- PCH ADPA Connector Registers
1282 PCH_ADPA => 16#0e_1100# / Register_Width,
1283
1284 -- PCH HDMIB Connector Registers
1285 PCH_HDMIB => 16#0e_1140# / Register_Width,
1286
1287 -- PCH HDMIC Connector Registers
1288 PCH_HDMIC => 16#0e_1150# / Register_Width,
1289
1290 -- PCH HDMID Connector Registers
1291 PCH_HDMID => 16#0e_1160# / Register_Width,
1292
1293 -- Intel Registers
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]1294 CPU_VGACNTRL => 16#04_1000# / Register_Width,
1295 GMCH_VGACNTRL => 16#07_1400# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1296 FUSE_STATUS => 16#04_2000# / Register_Width,
1297 FBA_CFB_BASE => 16#04_3200# / Register_Width,
1298 IPS_CTL => 16#04_3408# / Register_Width,
1299 ARB_CTL => 16#04_5000# / Register_Width,
1300 DBUF_CTL => 16#04_5008# / Register_Width,
1301 NDE_RSTWRN_OPT => 16#04_6408# / Register_Width,
1302 PCH_DREF_CONTROL => 16#0c_6200# / Register_Width,
1303 BLC_PWM_PCH_CTL1 => 16#0c_8250# / Register_Width,
1304 BLC_PWM_CPU_CTL2 => 16#04_8250# / Register_Width,
1305 PCH_DPLL_SEL => 16#0c_7000# / Register_Width,
1306 GT_MAILBOX => 16#13_8124# / Register_Width,
1307 GT_MAILBOX_DATA => 16#13_8128# / Register_Width,
1308 GT_MAILBOX_DATA_1 => 16#13_812c# / Register_Width,
1309
1310 PCH_DP_B => 16#0e_4100# / Register_Width,
1311 PCH_DP_AUX_CTL_B => 16#0e_4110# / Register_Width,
1312 PCH_DP_AUX_DATA_B_1 => 16#0e_4114# / Register_Width,
1313 PCH_DP_AUX_DATA_B_2 => 16#0e_4118# / Register_Width,
1314 PCH_DP_AUX_DATA_B_3 => 16#0e_411c# / Register_Width,
1315 PCH_DP_AUX_DATA_B_4 => 16#0e_4120# / Register_Width,
1316 PCH_DP_AUX_DATA_B_5 => 16#0e_4124# / Register_Width,
1317 PCH_DP_C => 16#0e_4200# / Register_Width,
1318 PCH_DP_AUX_CTL_C => 16#0e_4210# / Register_Width,
1319 PCH_DP_AUX_DATA_C_1 => 16#0e_4214# / Register_Width,
1320 PCH_DP_AUX_DATA_C_2 => 16#0e_4218# / Register_Width,
1321 PCH_DP_AUX_DATA_C_3 => 16#0e_421c# / Register_Width,
1322 PCH_DP_AUX_DATA_C_4 => 16#0e_4220# / Register_Width,
1323 PCH_DP_AUX_DATA_C_5 => 16#0e_4224# / Register_Width,
1324 PCH_DP_D => 16#0e_4300# / Register_Width,
1325 PCH_DP_AUX_CTL_D => 16#0e_4310# / Register_Width,
1326 PCH_DP_AUX_DATA_D_1 => 16#0e_4314# / Register_Width,
1327 PCH_DP_AUX_DATA_D_2 => 16#0e_4318# / Register_Width,
1328 PCH_DP_AUX_DATA_D_3 => 16#0e_431c# / Register_Width,
1329 PCH_DP_AUX_DATA_D_4 => 16#0e_4320# / Register_Width,
1330 PCH_DP_AUX_DATA_D_5 => 16#0e_4324# / Register_Width,
1331
1332 -- watermark registers
1333 WM1_LP_ILK => 16#04_5108# / Register_Width,
1334 WM2_LP_ILK => 16#04_510c# / Register_Width,
1335 WM3_LP_ILK => 16#04_5110# / Register_Width,
1336
1337 -- audio VID/DID
1338 AUD_VID_DID => 16#06_5020# / Register_Width,
1339 PCH_AUD_VID_DID => 16#0e_5020# / Register_Width,
1340
1341 -- interrupt registers
1342 DEISR => 16#04_4000# / Register_Width,
1343 DEIMR => 16#04_4004# / Register_Width,
1344 DEIIR => 16#04_4008# / Register_Width,
1345 DEIER => 16#04_400c# / Register_Width,
1346 GTISR => 16#04_4010# / Register_Width,
1347 GTIMR => 16#04_4014# / Register_Width,
1348 GTIIR => 16#04_4018# / Register_Width,
1349 GTIER => 16#04_401c# / Register_Width,
1350 SDEISR => 16#0c_4000# / Register_Width,
1351 SDEIMR => 16#0c_4004# / Register_Width,
1352 SDEIIR => 16#0c_4008# / Register_Width,
1353 SDEIER => 16#0c_400c# / Register_Width,
1354
1355 -- I2C stuff
Arthur Heymans229ed1c2018-03-28 16:45:43 +0200[diff] [blame^]1356 GMCH_GMBUS0 => 16#00_5100# / Register_Width,
1357 GMCH_GMBUS1 => 16#00_5104# / Register_Width,
1358 GMCH_GMBUS2 => 16#00_5108# / Register_Width,
1359 GMCH_GMBUS3 => 16#00_510c# / Register_Width,
1360 GMCH_GMBUS4 => 16#00_5110# / Register_Width,
1361 GMCH_GMBUS5 => 16#00_5120# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1362 PCH_GMBUS0 => 16#0c_5100# / Register_Width,
1363 PCH_GMBUS1 => 16#0c_5104# / Register_Width,
1364 PCH_GMBUS2 => 16#0c_5108# / Register_Width,
1365 PCH_GMBUS3 => 16#0c_510c# / Register_Width,
1366 PCH_GMBUS4 => 16#0c_5110# / Register_Width,
1367 PCH_GMBUS5 => 16#0c_5120# / Register_Width,
1368
1369 -- clock gating -- maybe have to touch this
1370 DSPCLK_GATE_D => 16#04_2020# / Register_Width,
1371 PCH_FDI_CHICKEN_B_C => 16#0c_2000# / Register_Width,
1372 PCH_DSPCLK_GATE_D => 16#0c_2020# / Register_Width,
1373
1374 -- hotplug and initial detection
1375 HOTPLUG_CTL => 16#04_4030# / Register_Width,
1376 SHOTPLUG_CTL => 16#0c_4030# / Register_Width,
1377 SFUSE_STRAP => 16#0c_2014# / Register_Width,
1378
1379 -- Render Engine Command Streamer
1380 ARB_MODE => 16#00_4030# / Register_Width,
1381 HWS_PGA => 16#00_4080# / Register_Width,
1382 RCS_RING_BUFFER_TAIL => 16#00_2030# / Register_Width,
1383 VCS_RING_BUFFER_TAIL => 16#01_2030# / Register_Width,
1384 BCS_RING_BUFFER_TAIL => 16#02_2030# / Register_Width,
1385 RCS_RING_BUFFER_HEAD => 16#00_2034# / Register_Width,
1386 VCS_RING_BUFFER_HEAD => 16#01_2034# / Register_Width,
1387 BCS_RING_BUFFER_HEAD => 16#02_2034# / Register_Width,
1388 RCS_RING_BUFFER_STRT => 16#00_2038# / Register_Width,
1389 VCS_RING_BUFFER_STRT => 16#01_2038# / Register_Width,
1390 BCS_RING_BUFFER_STRT => 16#02_2038# / Register_Width,
1391 RCS_RING_BUFFER_CTL => 16#00_203c# / Register_Width,
1392 VCS_RING_BUFFER_CTL => 16#01_203c# / Register_Width,
1393 BCS_RING_BUFFER_CTL => 16#02_203c# / Register_Width,
1394 MI_MODE => 16#00_209c# / Register_Width,
1395 INSTPM => 16#00_20c0# / Register_Width,
1396 GAB_CTL_REG => 16#02_4000# / Register_Width,
1397 PP_DCLV_HIGH => 16#00_2220# / Register_Width,
1398 PP_DCLV_LOW => 16#00_2228# / Register_Width,
1399 VCS_PP_DCLV_HIGH => 16#01_2220# / Register_Width,
1400 VCS_PP_DCLV_LOW => 16#01_2228# / Register_Width,
1401 BCS_PP_DCLV_HIGH => 16#02_2220# / Register_Width,
1402 BCS_PP_DCLV_LOW => 16#02_2228# / Register_Width,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1403 ILK_DISPLAY_CHICKEN2 => 16#04_2004# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1404 UCGCTL1 => 16#00_9400# / Register_Width,
1405 UCGCTL2 => 16#00_9404# / Register_Width,
1406 MBCTL => 16#00_907c# / Register_Width,
1407 HWSTAM => 16#00_2098# / Register_Width,
1408 VCS_HWSTAM => 16#01_2098# / Register_Width,
1409 BCS_HWSTAM => 16#02_2098# / Register_Width,
1410 IIR => 16#04_4028# / Register_Width,
1411 PIPE_FRMCNT_A => 16#07_0040# / Register_Width,
1412 PIPE_FRMCNT_B => 16#07_1040# / Register_Width,
1413 PIPE_FRMCNT_C => 16#07_2040# / Register_Width,
1414 FBC_CTL => 16#04_3208# / Register_Width,
1415 PIPE_VSYNCSHIFT_A => 16#06_0028# / Register_Width,
1416 PIPE_VSYNCSHIFT_B => 16#06_1028# / Register_Width,
1417 PIPE_VSYNCSHIFT_C => 16#06_2028# / Register_Width,
1418 WM_PIPE_A => 16#04_5100# / Register_Width,
1419 WM_PIPE_B => 16#04_5104# / Register_Width,
1420 WM_PIPE_C => 16#04_5200# / Register_Width,
1421 PIPE_SCANLINE_A => 16#07_0000# / Register_Width,
1422 PIPE_SCANLINE_B => 16#07_1000# / Register_Width,
1423 PIPE_SCANLINE_C => 16#07_2000# / Register_Width,
1424 GFX_MODE => 16#00_2520# / Register_Width,
1425 CACHE_MODE_0 => 16#00_2120# / Register_Width,
1426 SLEEP_PSMI_CONTROL => 16#01_2050# / Register_Width,
1427 CTX_SIZE => 16#00_21a0# / Register_Width,
1428 GAC_ECO_BITS => 16#01_4090# / Register_Width,
1429 GAM_ECOCHK => 16#00_4090# / Register_Width,
1430 QUIRK_02084 => 16#00_2084# / Register_Width,
1431 QUIRK_02090 => 16#00_2090# / Register_Width,
1432 GT_MODE => 16#00_20d0# / Register_Width,
1433 QUIRK_F0060 => 16#0f_0060# / Register_Width,
1434 QUIRK_F1060 => 16#0f_1060# / Register_Width,
1435 QUIRK_F2060 => 16#0f_2060# / Register_Width,
1436 AUD_CNTRL_ST2 => 16#0e_50c0# / Register_Width,
1437 AUD_CNTL_ST_A => 16#0e_50b4# / Register_Width,
1438 AUD_CNTL_ST_B => 16#0e_51b4# / Register_Width,
1439 AUD_CNTL_ST_C => 16#0e_52b4# / Register_Width,
1440 AUD_HDMIW_HDMIEDID_A => 16#0e_5050# / Register_Width,
1441 AUD_HDMIW_HDMIEDID_B => 16#0e_5150# / Register_Width,
1442 AUD_HDMIW_HDMIEDID_C => 16#0e_5250# / Register_Width,
1443 AUD_CONFIG_A => 16#0e_5000# / Register_Width,
1444 AUD_CONFIG_B => 16#0e_5100# / Register_Width,
1445 AUD_CONFIG_C => 16#0e_5200# / Register_Width,
1446 TRANS_DP_CTL_A => 16#0e_0300# / Register_Width,
1447 TRANS_DP_CTL_B => 16#0e_1300# / Register_Width,
1448 TRANS_DP_CTL_C => 16#0e_2300# / Register_Width,
1449 TRANS_VSYNCSHIFT_A => 16#0e_0028# / Register_Width,
1450 TRANS_VSYNCSHIFT_B => 16#0e_1028# / Register_Width,
1451 TRANS_VSYNCSHIFT_C => 16#0e_2028# / Register_Width,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]1452 PCH_RAWCLK_FREQ => 16#0c_6204# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1453 QUIRK_C2004 => 16#0c_2004# / Register_Width);
1454
1455 subtype Registers_Index is Registers_Invalid_Index range
1456 Registers_Invalid_Index'Succ (Invalid_Register) ..
1457 Registers_Invalid_Index'Last;
1458
1459 -- aliased registers
1460 DP_CTL_A : constant Registers_Index := DDI_BUF_CTL_A;
1461 DP_AUX_CTL_A : constant Registers_Index := DDI_AUX_CTL_A;
1462 DP_AUX_DATA_A_1 : constant Registers_Index := DDI_AUX_DATA_A_1;
1463 DP_AUX_DATA_A_2 : constant Registers_Index := DDI_AUX_DATA_A_2;
1464 DP_AUX_DATA_A_3 : constant Registers_Index := DDI_AUX_DATA_A_3;
1465 DP_AUX_DATA_A_4 : constant Registers_Index := DDI_AUX_DATA_A_4;
1466 DP_AUX_DATA_A_5 : constant Registers_Index := DDI_AUX_DATA_A_5;
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1467 ILK_DISPLAY_CHICKEN1 : constant Registers_Index := FUSE_STATUS;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1468
1469 ---------------------------------------------------------------------------
1470
1471 Default_Timeout_MS : constant := 10;
1472
1473 ---------------------------------------------------------------------------
1474
1475 procedure Posting_Read
1476 (Register : in Registers_Index)
1477 with
1478 Global => (In_Out => Register_State),
1479 Depends => (Register_State =>+ (Register)),
1480 Pre => True,
1481 Post => True;
1482
1483 pragma Warnings (GNATprove, Off, "unused variable ""Verbose""",
1484 Reason => "Only used on debugging path");
1485 procedure Read
1486 (Register : in Registers_Index;
1487 Value : out Word32;
1488 Verbose : in Boolean := True)
1489 with
1490 Global => (In_Out => Register_State),
1491 Depends => ((Value, Register_State) => (Register, Register_State),
1492 null => Verbose),
1493 Pre => True,
1494 Post => True;
1495 pragma Warnings (GNATprove, On, "unused variable ""Verbose""");
1496
1497 procedure Write
1498 (Register : Registers_Index;
1499 Value : Word32)
1500 with
1501 Global => (In_Out => Register_State),
1502 Depends => (Register_State => (Register, Register_State, Value)),
1503 Pre => True,
1504 Post => True;
1505
1506 procedure Is_Set_Mask
1507 (Register : in Registers_Index;
1508 Mask : in Word32;
1509 Result : out Boolean);
1510
1511 pragma Warnings (GNATprove, Off, "unused initial value of ""Verbose""",
1512 Reason => "Only used on debugging path");
Nico Huberbcb2c472017-02-02 16:39:26 +0100[diff] [blame]1513 procedure Wait
1514 (Register : Registers_Index;
1515 Mask : Word32;
1516 Value : Word32;
1517 TOut_MS : Natural := Default_Timeout_MS;
1518 Verbose : Boolean := False);
1519
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1520 procedure Wait_Set_Mask
1521 (Register : Registers_Index;
1522 Mask : Word32;
1523 TOut_MS : Natural := Default_Timeout_MS;
1524 Verbose : Boolean := False);
1525
1526 procedure Wait_Unset_Mask
1527 (Register : Registers_Index;
1528 Mask : Word32;
1529 TOut_MS : Natural := Default_Timeout_MS;
1530 Verbose : Boolean := False);
1531 pragma Warnings (GNATprove, On, "unused initial value of ""Verbose""");
1532
1533 procedure Set_Mask
1534 (Register : Registers_Index;
1535 Mask : Word32);
1536
1537 procedure Unset_Mask
1538 (Register : Registers_Index;
1539 Mask : Word32);
1540
1541 procedure Unset_And_Set_Mask
1542 (Register : Registers_Index;
1543 Mask_Unset : Word32;
1544 Mask_Set : Word32);
1545
Nico Huber17d64b62017-07-15 20:51:25 +0200[diff] [blame]1546 procedure Clear_Fences;
1547
Nico Huberb03c8f12017-08-25 13:29:08 +0200[diff] [blame]1548 procedure Add_Fence
1549 (First_Page : in GTT_Range;
1550 Last_Page : in GTT_Range;
1551 Tiling : in XY_Tiling;
1552 Pitch : in Natural;
1553 Success : out Boolean);
1554
1555 procedure Remove_Fence (First_Page, Last_Page : GTT_Range);
1556
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1557 pragma Warnings (Off, "declaration of ""Write_GTT"" hides one at *");
1558 procedure Write_GTT
1559 (GTT_Page : GTT_Range;
1560 Device_Address : GTT_Address_Type;
1561 Valid : Boolean)
1562 with
1563 Global => (In_Out => GTT_State),
1564 Depends => (GTT_State =>+ (GTT_Page, Device_Address, Valid)),
1565 Pre => True,
1566 Post => True;
1567 pragma Warnings (On, "declaration of ""Write_GTT"" hides one at *");
1568
Nico Huber2b6f6992017-07-09 18:11:34 +0200[diff] [blame]1569 procedure Set_Register_Base (Base : Word64; GTT_Base : Word64 := 0)
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1570 with
1571 Global => (Output => Address_State),
Nico Huber2b6f6992017-07-09 18:11:34 +0200[diff] [blame]1572 Depends => (Address_State => (Base, GTT_Base)),
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1573 Pre => True,
1574 Post => True;
1575
1576end HW.GFX.GMA.Registers;