commit d0f84b9acd65e047876c36b4571f1e4da17c4b23
author Nico Huber <nico.h@gmx.de> Sun Sep 22 21:31:52 2019 +0200
committer Nico Huber <nico.h@gmx.de> Fri Oct 18 12:27:46 2019 +0000
tree 2a318a99cb2e0c7ba2b5021ac9f045c38347adb8
parent 1eb5faa2eeca93b911af51bdbea854d286bfab81

gma hsw: Implement CDClk switching

For Haswell, we only read out the current CDClk setting and work with
that (CDClk is supposed to be set only once per boot, so we leave that
to the firmware). Broadwell supports actual frequency switching, with
the following limits:

  o a fuse may restrict us to 450MHz,
  o ULX supports at most 450MHz w/o additional cooling,
  o ULT supports at most 540MHz w/o additional cooling,
  o others support up to 675MHz.

We assume there is no `additional cooling`. With the CDClk now being
switchable, we have to update `DP_Aux_Request` to assume the current
CDClk frequency instead of the default.

Dot clocks, on these platforms, may run with full CDClk speed.

Change-Id: I8fb23a49b334f9f0045884c3af4087764397b941
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/35717
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

common/hw-gfx-gma-registers.ads

diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads
index 1d38ffd..4eb2c04 100644
--- a/common/hw-gfx-gma-registers.ads
+++ b/common/hw-gfx-gma-registers.ads
@@ -92,6 +92,7 @@
       CPU_VGACNTRL,
       FUSE_STATUS,
       ILK_DISPLAY_CHICKEN2,
+      FUSE_STRAP,
       DSPCLK_GATE_D,
       FBA_CFB_BASE,
       FBC_CTL,
@@ -141,6 +142,7 @@
       TRANSA_CLK_SEL,
       TRANSB_CLK_SEL,
       TRANSC_CLK_SEL,
+      CDCLK_FREQ,
       NDE_RSTWRN_OPT,
       BLC_PWM_CPU_CTL2,
       BLC_PWM_CPU_CTL,
@@ -710,6 +712,7 @@
       FDI_RXC_TUSIZE1,
       QUIRK_F2060,
       TRANSC_CHICKEN2,
+      LCPLL_CTL,
       BXT_P_CR_GT_DISP_PWRON,
       GT_MAILBOX,
       GT_MAILBOX_DATA,
@@ -1263,6 +1266,9 @@
       PORT_CLK_SEL_DDID     => 16#04_610c# / Register_Width,
       PORT_CLK_SEL_DDIE     => 16#04_6110# / Register_Width,
 
+      -- Haswell LCPLL registers
+      LCPLL_CTL             => 16#13_0040# / Register_Width,
+
       -- Skylake I_boost configuration
       DISPIO_CR_TX_BMU_CR0  => 16#06_c00c# / Register_Width,
 
@@ -1279,6 +1285,7 @@
 
       -- CD CLK register
       CDCLK_CTL             => 16#04_6000# / Register_Width,
+      CDCLK_FREQ            => 16#04_6200# / Register_Width,
 
       -- Skylake LCPLL registers
       LCPLL1_CTL            => 16#04_6010# / Register_Width,
@@ -1456,6 +1463,7 @@
       CPU_VGACNTRL          => 16#04_1000# / Register_Width,
       GMCH_VGACNTRL         => 16#07_1400# / Register_Width,
       FUSE_STATUS           => 16#04_2000# / Register_Width,
+      FUSE_STRAP            => 16#04_2014# / Register_Width,
       FBA_CFB_BASE          => 16#04_3200# / Register_Width,
       IPS_CTL               => 16#04_3408# / Register_Width,
       ARB_CTL               => 16#04_5000# / Register_Width,