gma g45: Read CDClk and calculate dot-clock limits
Numbers are taken from `intel_cdclk.c` of Linux' i915 driver.
We introduce three new procedures to the `Power_And_Clocks` interface:
o Limit_Dotclocks() limits the dot clocks of all pipe configs
according to the maximum supported CDClk. It also reports if
CDClk has to be switched for these configs.
o Update_CDClk() performs the CDClk switch if necessary. It may
further limit the dot clocks if the switch didn't succeed.
o Enable_CDClk() ensures that the CDClk is running. This may be
necessary to probe for DP displays when no pipes are active.
The latter two are no-ops for G45, as the CDClk runs at a fixed rate.
Dot clocks are limited to 90% of CDClk.
Change-Id: Ie50c0f8f51b3a0a6ed58c6461069c556cc92f51e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/35715
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads
index 81fb219..1d38ffd 100644
--- a/common/hw-gfx-gma-registers.ads
+++ b/common/hw-gfx-gma-registers.ads
@@ -70,6 +70,8 @@
UCGCTL1,
UCGCTL2,
GMCH_CLKCFG,
+ GMCH_HPLLVCO_MOBILE,
+ GMCH_HPLLVCO,
VCS_RING_BUFFER_TAIL,
VCS_RING_BUFFER_HEAD,
VCS_RING_BUFFER_STRT,
@@ -1617,7 +1619,9 @@
-- MCHBAR Mirror
- GMCH_CLKCFG => 16#01_0c00# / Register_Width);
+ GMCH_CLKCFG => 16#01_0c00# / Register_Width,
+ GMCH_HPLLVCO_MOBILE => 16#01_0c0f# / Register_Width,
+ GMCH_HPLLVCO => 16#01_0c38# / Register_Width);
subtype Registers_Index is Registers_Invalid_Index range
Registers_Invalid_Index'Succ (Invalid_Register) ..