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review.sourcearcade.org / libgfxinit / 636390ca01e7ecd6c53c1db60a6b97685bb5483e / . / common / hw-gfx-gma-registers.ads
blob: 40d3437ea4089a8a171986e5ce5c67286c9d7e3d [file] [log] [blame]
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1--
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]2-- Copyright (C) 2015-2017 secunet Security Networks AG
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
Nico Huber125a29e2016-10-18 00:23:54 +0200[diff] [blame]6-- the Free Software Foundation; either version 2 of the License, or
7-- (at your option) any later version.
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]8--
9-- This program is distributed in the hope that it will be useful,
10-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12-- GNU General Public License for more details.
13--
14
15with System;
16with HW.GFX.GMA;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]17
18private package HW.GFX.GMA.Registers
19with
20 Abstract_State =>
21 ((Address_State with Part_Of => GMA.State),
22 (Register_State with External, Part_Of => GMA.Device_State),
23 (GTT_State with External, Part_Of => GMA.Device_State)),
24 Initializes => Address_State
25is
26 type Registers_Invalid_Index is
27 (Invalid_Register, -- Allow a placeholder when access is not acceptable
28
29 RCS_RING_BUFFER_TAIL,
30 RCS_RING_BUFFER_HEAD,
31 RCS_RING_BUFFER_STRT,
32 RCS_RING_BUFFER_CTL,
33 QUIRK_02084,
34 QUIRK_02090,
35 HWSTAM,
36 MI_MODE,
37 INSTPM,
38 GT_MODE,
39 CACHE_MODE_0,
40 CTX_SIZE,
41 PP_DCLV_HIGH,
42 PP_DCLV_LOW,
43 GFX_MODE,
44 ARB_MODE,
45 HWS_PGA,
46 GAM_ECOCHK,
Arthur Heymans229ed1c2018-03-28 16:45:43 +0200[diff] [blame]47 GMCH_GMBUS0,
48 GMCH_GMBUS1,
49 GMCH_GMBUS2,
50 GMCH_GMBUS3,
51 GMCH_GMBUS4,
52 GMCH_GMBUS5,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]53 MBCTL,
54 UCGCTL1,
55 UCGCTL2,
56 VCS_RING_BUFFER_TAIL,
57 VCS_RING_BUFFER_HEAD,
58 VCS_RING_BUFFER_STRT,
59 VCS_RING_BUFFER_CTL,
60 SLEEP_PSMI_CONTROL,
61 VCS_HWSTAM,
62 VCS_PP_DCLV_HIGH,
63 VCS_PP_DCLV_LOW,
64 GAC_ECO_BITS,
65 BCS_RING_BUFFER_TAIL,
66 BCS_RING_BUFFER_HEAD,
67 BCS_RING_BUFFER_STRT,
68 BCS_RING_BUFFER_CTL,
69 BCS_HWSTAM,
70 BCS_PP_DCLV_HIGH,
71 BCS_PP_DCLV_LOW,
72 GAB_CTL_REG,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]73 CPU_VGACNTRL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]74 FUSE_STATUS,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]75 ILK_DISPLAY_CHICKEN2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]76 DSPCLK_GATE_D,
77 FBA_CFB_BASE,
78 FBC_CTL,
79 IPS_CTL,
80 DEISR,
81 DEIMR,
82 DEIIR,
83 DEIER,
84 GTISR,
85 GTIMR,
86 GTIIR,
87 GTIER,
88 IIR,
89 HOTPLUG_CTL,
90 ARB_CTL,
91 DBUF_CTL,
92 WM_PIPE_A,
93 WM_PIPE_B,
94 WM1_LP_ILK,
95 WM2_LP_ILK,
96 WM3_LP_ILK,
97 WM_PIPE_C,
98 WM_LINETIME_A,
99 WM_LINETIME_B,
100 WM_LINETIME_C,
101 PWR_WELL_CTL_BIOS,
102 PWR_WELL_CTL_DRIVER,
103 PWR_WELL_CTL_KVMR,
104 PWR_WELL_CTL_DEBUG,
105 PWR_WELL_CTL5,
106 PWR_WELL_CTL6,
107 CDCLK_CTL,
108 LCPLL1_CTL,
109 LCPLL2_CTL,
110 SPLL_CTL,
111 WRPLL_CTL_1,
112 WRPLL_CTL_2,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]113 BXT_DE_PLL_ENABLE,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]114 BXT_PORT_PLL_ENABLE_A,
115 BXT_PORT_PLL_ENABLE_B,
116 BXT_PORT_PLL_ENABLE_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]117 PORT_CLK_SEL_DDIA,
118 PORT_CLK_SEL_DDIB,
119 PORT_CLK_SEL_DDIC,
120 PORT_CLK_SEL_DDID,
121 PORT_CLK_SEL_DDIE,
122 TRANSA_CLK_SEL,
123 TRANSB_CLK_SEL,
124 TRANSC_CLK_SEL,
125 NDE_RSTWRN_OPT,
126 BLC_PWM_CPU_CTL2,
127 BLC_PWM_CPU_CTL,
128 HTOTAL_A,
129 HBLANK_A,
130 HSYNC_A,
131 VTOTAL_A,
132 VBLANK_A,
133 VSYNC_A,
134 PIPEASRC,
135 PIPE_VSYNCSHIFT_A,
136 PIPEA_DATA_M1,
137 PIPEA_DATA_N1,
138 PIPEA_LINK_M1,
139 PIPEA_LINK_N1,
140 FDI_TX_CTL_A,
141 PIPEA_DDI_FUNC_CTL,
142 PIPEA_MSA_MISC,
143 SRD_CTL_A,
144 SRD_STATUS_A,
145 HTOTAL_B,
146 HBLANK_B,
147 HSYNC_B,
148 VTOTAL_B,
149 VBLANK_B,
150 VSYNC_B,
151 PIPEBSRC,
152 PIPE_VSYNCSHIFT_B,
153 PIPEB_DATA_M1,
154 PIPEB_DATA_N1,
155 PIPEB_LINK_M1,
156 PIPEB_LINK_N1,
157 FDI_TX_CTL_B,
158 PIPEB_DDI_FUNC_CTL,
159 PIPEB_MSA_MISC,
160 SRD_CTL_B,
161 SRD_STATUS_B,
162 HTOTAL_C,
163 HBLANK_C,
164 HSYNC_C,
165 VTOTAL_C,
166 VBLANK_C,
167 VSYNC_C,
168 PIPECSRC,
169 PIPE_VSYNCSHIFT_C,
170 PIPEC_DATA_M1,
171 PIPEC_DATA_N1,
172 PIPEC_LINK_M1,
173 PIPEC_LINK_N1,
174 FDI_TX_CTL_C,
175 PIPEC_DDI_FUNC_CTL,
176 PIPEC_MSA_MISC,
177 SRD_CTL_C,
178 SRD_STATUS_C,
179 DDI_BUF_CTL_A,
180 DDI_AUX_CTL_A,
181 DDI_AUX_DATA_A_1,
182 DDI_AUX_DATA_A_2,
183 DDI_AUX_DATA_A_3,
184 DDI_AUX_DATA_A_4,
185 DDI_AUX_DATA_A_5,
186 DDI_AUX_MUTEX_A,
187 DP_TP_CTL_A,
188 DDI_BUF_CTL_B,
189 DDI_AUX_CTL_B,
190 DDI_AUX_DATA_B_1,
191 DDI_AUX_DATA_B_2,
192 DDI_AUX_DATA_B_3,
193 DDI_AUX_DATA_B_4,
194 DDI_AUX_DATA_B_5,
195 DDI_AUX_MUTEX_B,
196 DP_TP_CTL_B,
197 DP_TP_STATUS_B,
198 DDI_BUF_CTL_C,
199 DDI_AUX_CTL_C,
200 DDI_AUX_DATA_C_1,
201 DDI_AUX_DATA_C_2,
202 DDI_AUX_DATA_C_3,
203 DDI_AUX_DATA_C_4,
204 DDI_AUX_DATA_C_5,
205 DDI_AUX_MUTEX_C,
206 DP_TP_CTL_C,
207 DP_TP_STATUS_C,
208 DDI_BUF_CTL_D,
209 DDI_AUX_CTL_D,
210 DDI_AUX_DATA_D_1,
211 DDI_AUX_DATA_D_2,
212 DDI_AUX_DATA_D_3,
213 DDI_AUX_DATA_D_4,
214 DDI_AUX_DATA_D_5,
215 DDI_AUX_MUTEX_D,
216 DP_TP_CTL_D,
217 DP_TP_STATUS_D,
218 DDI_BUF_CTL_E,
219 DP_TP_CTL_E,
220 DP_TP_STATUS_E,
221 SRD_CTL,
222 SRD_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]223 BXT_PHY_CTL_A,
224 BXT_PHY_CTL_B,
225 BXT_PHY_CTL_C,
226 BXT_PHY_CTL_FAM_EDP,
227 BXT_PHY_CTL_FAM_DDI,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]228 DDI_BUF_TRANS_A_S0T1,
229 DDI_BUF_TRANS_A_S0T2,
230 DDI_BUF_TRANS_A_S1T1,
231 DDI_BUF_TRANS_A_S1T2,
232 DDI_BUF_TRANS_A_S2T1,
233 DDI_BUF_TRANS_A_S2T2,
234 DDI_BUF_TRANS_A_S3T1,
235 DDI_BUF_TRANS_A_S3T2,
236 DDI_BUF_TRANS_A_S4T1,
237 DDI_BUF_TRANS_A_S4T2,
238 DDI_BUF_TRANS_A_S5T1,
239 DDI_BUF_TRANS_A_S5T2,
240 DDI_BUF_TRANS_A_S6T1,
241 DDI_BUF_TRANS_A_S6T2,
242 DDI_BUF_TRANS_A_S7T1,
243 DDI_BUF_TRANS_A_S7T2,
244 DDI_BUF_TRANS_A_S8T1,
245 DDI_BUF_TRANS_A_S8T2,
246 DDI_BUF_TRANS_A_S9T1,
247 DDI_BUF_TRANS_A_S9T2,
248 DDI_BUF_TRANS_B_S0T1,
249 DDI_BUF_TRANS_B_S0T2,
250 DDI_BUF_TRANS_B_S1T1,
251 DDI_BUF_TRANS_B_S1T2,
252 DDI_BUF_TRANS_B_S2T1,
253 DDI_BUF_TRANS_B_S2T2,
254 DDI_BUF_TRANS_B_S3T1,
255 DDI_BUF_TRANS_B_S3T2,
256 DDI_BUF_TRANS_B_S4T1,
257 DDI_BUF_TRANS_B_S4T2,
258 DDI_BUF_TRANS_B_S5T1,
259 DDI_BUF_TRANS_B_S5T2,
260 DDI_BUF_TRANS_B_S6T1,
261 DDI_BUF_TRANS_B_S6T2,
262 DDI_BUF_TRANS_B_S7T1,
263 DDI_BUF_TRANS_B_S7T2,
264 DDI_BUF_TRANS_B_S8T1,
265 DDI_BUF_TRANS_B_S8T2,
266 DDI_BUF_TRANS_B_S9T1,
267 DDI_BUF_TRANS_B_S9T2,
268 DDI_BUF_TRANS_C_S0T1,
269 DDI_BUF_TRANS_C_S0T2,
270 DDI_BUF_TRANS_C_S1T1,
271 DDI_BUF_TRANS_C_S1T2,
272 DDI_BUF_TRANS_C_S2T1,
273 DDI_BUF_TRANS_C_S2T2,
274 DDI_BUF_TRANS_C_S3T1,
275 DDI_BUF_TRANS_C_S3T2,
276 DDI_BUF_TRANS_C_S4T1,
277 DDI_BUF_TRANS_C_S4T2,
278 DDI_BUF_TRANS_C_S5T1,
279 DDI_BUF_TRANS_C_S5T2,
280 DDI_BUF_TRANS_C_S6T1,
281 DDI_BUF_TRANS_C_S6T2,
282 DDI_BUF_TRANS_C_S7T1,
283 DDI_BUF_TRANS_C_S7T2,
284 DDI_BUF_TRANS_C_S8T1,
285 DDI_BUF_TRANS_C_S8T2,
286 DDI_BUF_TRANS_C_S9T1,
287 DDI_BUF_TRANS_C_S9T2,
288 DDI_BUF_TRANS_D_S0T1,
289 DDI_BUF_TRANS_D_S0T2,
290 DDI_BUF_TRANS_D_S1T1,
291 DDI_BUF_TRANS_D_S1T2,
292 DDI_BUF_TRANS_D_S2T1,
293 DDI_BUF_TRANS_D_S2T2,
294 DDI_BUF_TRANS_D_S3T1,
295 DDI_BUF_TRANS_D_S3T2,
296 DDI_BUF_TRANS_D_S4T1,
297 DDI_BUF_TRANS_D_S4T2,
298 DDI_BUF_TRANS_D_S5T1,
299 DDI_BUF_TRANS_D_S5T2,
300 DDI_BUF_TRANS_D_S6T1,
301 DDI_BUF_TRANS_D_S6T2,
302 DDI_BUF_TRANS_D_S7T1,
303 DDI_BUF_TRANS_D_S7T2,
304 DDI_BUF_TRANS_D_S8T1,
305 DDI_BUF_TRANS_D_S8T2,
306 DDI_BUF_TRANS_D_S9T1,
307 DDI_BUF_TRANS_D_S9T2,
308 DDI_BUF_TRANS_E_S0T1,
309 DDI_BUF_TRANS_E_S0T2,
310 DDI_BUF_TRANS_E_S1T1,
311 DDI_BUF_TRANS_E_S1T2,
312 DDI_BUF_TRANS_E_S2T1,
313 DDI_BUF_TRANS_E_S2T2,
314 DDI_BUF_TRANS_E_S3T1,
315 DDI_BUF_TRANS_E_S3T2,
316 DDI_BUF_TRANS_E_S4T1,
317 DDI_BUF_TRANS_E_S4T2,
318 DDI_BUF_TRANS_E_S5T1,
319 DDI_BUF_TRANS_E_S5T2,
320 DDI_BUF_TRANS_E_S6T1,
321 DDI_BUF_TRANS_E_S6T2,
322 DDI_BUF_TRANS_E_S7T1,
323 DDI_BUF_TRANS_E_S7T2,
324 DDI_BUF_TRANS_E_S8T1,
325 DDI_BUF_TRANS_E_S8T2,
326 DDI_BUF_TRANS_E_S9T1,
327 DDI_BUF_TRANS_E_S9T2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]328 AUD_VID_DID,
329 PFA_WIN_POS,
330 PFA_WIN_SZ,
331 PFA_CTL_1,
332 PS_WIN_POS_1_A,
333 PS_WIN_SZ_1_A,
334 PS_CTRL_1_A,
335 PS_WIN_POS_2_A,
336 PS_WIN_SZ_2_A,
337 PS_CTRL_2_A,
338 PFB_WIN_POS,
339 PFB_WIN_SZ,
340 PFB_CTL_1,
341 PS_WIN_POS_1_B,
342 PS_WIN_SZ_1_B,
343 PS_CTRL_1_B,
344 PS_WIN_POS_2_B,
345 PS_WIN_SZ_2_B,
346 PS_CTRL_2_B,
347 PFC_WIN_POS,
348 PFC_WIN_SZ,
349 PFC_CTL_1,
350 PS_WIN_POS_1_C,
351 PS_WIN_SZ_1_C,
352 PS_CTRL_1_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]353 BXT_PORT_CL1CM_DW0_BC,
Nico Huber58afc202017-06-12 21:34:55 +0200[diff] [blame]354 DISPIO_CR_TX_BMU_CR0,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]355 BXT_PORT_CL1CM_DW9_BC,
356 BXT_PORT_CL1CM_DW10_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]357 BXT_PORT_PLL_EBB_0_B,
358 BXT_PORT_PLL_EBB_4_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]359 DPLL1_CFGR1,
360 DPLL1_CFGR2,
361 DPLL2_CFGR1,
362 DPLL2_CFGR2,
363 DPLL3_CFGR1,
364 DPLL3_CFGR2,
365 DPLL_CTRL1,
366 DPLL_CTRL2,
367 DPLL_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]368 BXT_PORT_CL1CM_DW28_BC,
369 BXT_PORT_CL1CM_DW30_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]370 BXT_PORT_PLL_0_B,
371 BXT_PORT_PLL_1_B,
372 BXT_PORT_PLL_2_B,
373 BXT_PORT_PLL_3_B,
374 BXT_PORT_PLL_6_B,
375 BXT_PORT_PLL_8_B,
376 BXT_PORT_PLL_9_B,
377 BXT_PORT_PLL_10_B,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]378 BXT_PORT_REF_DW3_BC,
379 BXT_PORT_REF_DW6_BC,
380 BXT_PORT_REF_DW8_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]381 BXT_PORT_PLL_EBB_0_C,
382 BXT_PORT_PLL_EBB_4_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]383 BXT_PORT_CL2CM_DW6_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]384 BXT_PORT_PLL_0_C,
385 BXT_PORT_PLL_1_C,
386 BXT_PORT_PLL_2_C,
387 BXT_PORT_PLL_3_C,
388 BXT_PORT_PLL_6_C,
389 BXT_PORT_PLL_8_C,
390 BXT_PORT_PLL_9_C,
391 BXT_PORT_PLL_10_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]392 BXT_PORT_PCS_DW10_01_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]393 BXT_PORT_PCS_DW12_01_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]394 BXT_PORT_TX_DW2_LN0_B,
395 BXT_PORT_TX_DW3_LN0_B,
396 BXT_PORT_TX_DW4_LN0_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]397 BXT_PORT_TX_DW14_LN0_B,
398 BXT_PORT_TX_DW14_LN1_B,
399 BXT_PORT_TX_DW14_LN2_B,
400 BXT_PORT_TX_DW14_LN3_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]401 BXT_PORT_PCS_DW10_01_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]402 BXT_PORT_PCS_DW12_01_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]403 BXT_PORT_TX_DW2_LN0_C,
404 BXT_PORT_TX_DW3_LN0_C,
405 BXT_PORT_TX_DW4_LN0_C,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]406 BXT_PORT_TX_DW14_LN0_C,
407 BXT_PORT_TX_DW14_LN1_C,
408 BXT_PORT_TX_DW14_LN2_C,
409 BXT_PORT_TX_DW14_LN3_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]410 BXT_PORT_PCS_DW10_GRP_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]411 BXT_PORT_PCS_DW12_GRP_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]412 BXT_PORT_TX_DW2_GRP_B,
413 BXT_PORT_TX_DW3_GRP_B,
414 BXT_PORT_TX_DW4_GRP_B,
415 BXT_PORT_PCS_DW10_GRP_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]416 BXT_PORT_PCS_DW12_GRP_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]417 BXT_PORT_TX_DW2_GRP_C,
418 BXT_PORT_TX_DW3_GRP_C,
419 BXT_PORT_TX_DW4_GRP_C,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]420 BXT_DE_PLL_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]421 HTOTAL_EDP,
422 HBLANK_EDP,
423 HSYNC_EDP,
424 VTOTAL_EDP,
425 VBLANK_EDP,
426 VSYNC_EDP,
427 PIPE_EDP_DATA_M1,
428 PIPE_EDP_DATA_N1,
429 PIPE_EDP_LINK_M1,
430 PIPE_EDP_LINK_N1,
431 PIPE_EDP_DDI_FUNC_CTL,
432 PIPE_EDP_MSA_MISC,
433 SRD_CTL_EDP,
434 SRD_STATUS_EDP,
435 PIPE_SCANLINE_A,
436 PIPEACONF,
437 PIPEAMISC,
438 PIPE_FRMCNT_A,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame^]439 PIPEA_GMCH_DATA_M,
440 PIPEA_GMCH_DATA_N,
441 PIPEA_GMCH_LINK_M,
442 PIPEA_GMCH_LINK_N,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]443 DSPACNTR,
444 DSPALINOFF,
445 DSPASTRIDE,
446 PLANE_POS_1_A,
447 PLANE_SIZE_1_A,
448 DSPASURF,
449 DSPATILEOFF,
450 PLANE_WM_1_A_0,
451 PLANE_WM_1_A_1,
452 PLANE_WM_1_A_2,
453 PLANE_WM_1_A_3,
454 PLANE_WM_1_A_4,
455 PLANE_WM_1_A_5,
456 PLANE_WM_1_A_6,
457 PLANE_WM_1_A_7,
458 PLANE_BUF_CFG_1_A,
459 SPACNTR,
460 PIPE_SCANLINE_B,
461 PIPEBCONF,
462 PIPEBMISC,
463 PIPE_FRMCNT_B,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame^]464 PIPEB_GMCH_DATA_M,
465 PIPEB_GMCH_DATA_N,
466 PIPEB_GMCH_LINK_M,
467 PIPEB_GMCH_LINK_N,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]468 DSPBCNTR,
469 DSPBLINOFF,
470 DSPBSTRIDE,
471 PLANE_POS_1_B,
472 PLANE_SIZE_1_B,
473 DSPBSURF,
474 DSPBTILEOFF,
475 PLANE_WM_1_B_0,
476 PLANE_WM_1_B_1,
477 PLANE_WM_1_B_2,
478 PLANE_WM_1_B_3,
479 PLANE_WM_1_B_4,
480 PLANE_WM_1_B_5,
481 PLANE_WM_1_B_6,
482 PLANE_WM_1_B_7,
483 PLANE_BUF_CFG_1_B,
484 SPBCNTR,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]485 GMCH_VGACNTRL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]486 PIPE_SCANLINE_C,
487 PIPECCONF,
488 PIPECMISC,
489 PIPE_FRMCNT_C,
490 DSPCCNTR,
491 DSPCLINOFF,
492 DSPCSTRIDE,
493 PLANE_POS_1_C,
494 PLANE_SIZE_1_C,
495 DSPCSURF,
496 DSPCTILEOFF,
497 PLANE_WM_1_C_0,
498 PLANE_WM_1_C_1,
499 PLANE_WM_1_C_2,
500 PLANE_WM_1_C_3,
501 PLANE_WM_1_C_4,
502 PLANE_WM_1_C_5,
503 PLANE_WM_1_C_6,
504 PLANE_WM_1_C_7,
505 PLANE_BUF_CFG_1_C,
506 SPCCNTR,
507 PIPE_EDP_CONF,
508 PCH_FDI_CHICKEN_B_C,
509 QUIRK_C2004,
510 SFUSE_STRAP,
511 PCH_DSPCLK_GATE_D,
512 SDEISR,
513 SDEIMR,
514 SDEIIR,
515 SDEIER,
516 SHOTPLUG_CTL,
517 PCH_GMBUS0,
518 PCH_GMBUS1,
519 PCH_GMBUS2,
520 PCH_GMBUS3,
521 PCH_GMBUS4,
522 PCH_GMBUS5,
523 SBI_ADDR,
524 SBI_DATA,
525 SBI_CTL_STAT,
526 PCH_DPLL_A,
527 PCH_DPLL_B,
528 PCH_PIXCLK_GATE,
529 PCH_FPA0,
530 PCH_FPA1,
531 PCH_FPB0,
532 PCH_FPB1,
533 PCH_DREF_CONTROL,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]534 PCH_RAWCLK_FREQ,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]535 PCH_DPLL_SEL,
536 PCH_PP_STATUS,
537 PCH_PP_CONTROL,
538 PCH_PP_ON_DELAYS,
539 PCH_PP_OFF_DELAYS,
540 PCH_PP_DIVISOR,
541 BLC_PWM_PCH_CTL1,
542 BLC_PWM_PCH_CTL2,
543 TRANS_HTOTAL_A,
544 TRANS_HBLANK_A,
545 TRANS_HSYNC_A,
546 TRANS_VTOTAL_A,
547 TRANS_VBLANK_A,
548 TRANS_VSYNC_A,
549 TRANS_VSYNCSHIFT_A,
550 TRANSA_DATA_M1,
551 TRANSA_DATA_N1,
552 TRANSA_DP_LINK_M1,
553 TRANSA_DP_LINK_N1,
554 TRANS_DP_CTL_A,
555 TRANS_HTOTAL_B,
556 TRANS_HBLANK_B,
557 TRANS_HSYNC_B,
558 TRANS_VTOTAL_B,
559 TRANS_VBLANK_B,
560 TRANS_VSYNC_B,
561 TRANS_VSYNCSHIFT_B,
562 TRANSB_DATA_M1,
563 TRANSB_DATA_N1,
564 TRANSB_DP_LINK_M1,
565 TRANSB_DP_LINK_N1,
566 PCH_ADPA,
567 PCH_HDMIB,
568 PCH_HDMIC,
569 PCH_HDMID,
570 PCH_LVDS,
571 TRANS_DP_CTL_B,
572 TRANS_HTOTAL_C,
573 TRANS_HBLANK_C,
574 TRANS_HSYNC_C,
575 TRANS_VTOTAL_C,
576 TRANS_VBLANK_C,
577 TRANS_VSYNC_C,
578 TRANS_VSYNCSHIFT_C,
579 TRANSC_DATA_M1,
580 TRANSC_DATA_N1,
581 TRANSC_DP_LINK_M1,
582 TRANSC_DP_LINK_N1,
583 TRANS_DP_CTL_C,
584 PCH_DP_B,
585 PCH_DP_AUX_CTL_B,
586 PCH_DP_AUX_DATA_B_1,
587 PCH_DP_AUX_DATA_B_2,
588 PCH_DP_AUX_DATA_B_3,
589 PCH_DP_AUX_DATA_B_4,
590 PCH_DP_AUX_DATA_B_5,
591 PCH_DP_C,
592 PCH_DP_AUX_CTL_C,
593 PCH_DP_AUX_DATA_C_1,
594 PCH_DP_AUX_DATA_C_2,
595 PCH_DP_AUX_DATA_C_3,
596 PCH_DP_AUX_DATA_C_4,
597 PCH_DP_AUX_DATA_C_5,
598 PCH_DP_D,
599 PCH_DP_AUX_CTL_D,
600 PCH_DP_AUX_DATA_D_1,
601 PCH_DP_AUX_DATA_D_2,
602 PCH_DP_AUX_DATA_D_3,
603 PCH_DP_AUX_DATA_D_4,
604 PCH_DP_AUX_DATA_D_5,
605 AUD_CONFIG_A,
606 PCH_AUD_VID_DID,
607 AUD_HDMIW_HDMIEDID_A,
608 AUD_CNTL_ST_A,
609 AUD_CNTRL_ST2,
610 AUD_CONFIG_B,
611 AUD_HDMIW_HDMIEDID_B,
612 AUD_CNTL_ST_B,
613 AUD_CONFIG_C,
614 AUD_HDMIW_HDMIEDID_C,
615 AUD_CNTL_ST_C,
616 TRANSACONF,
617 FDI_RXA_CTL,
618 FDI_RX_MISC_A,
619 FDI_RXA_IIR,
620 FDI_RXA_IMR,
621 FDI_RXA_TUSIZE1,
622 QUIRK_F0060,
623 TRANSA_CHICKEN2,
624 TRANSBCONF,
625 FDI_RXB_CTL,
626 FDI_RX_MISC_B,
627 FDI_RXB_IIR,
628 FDI_RXB_IMR,
629 FDI_RXB_TUSIZE1,
630 QUIRK_F1060,
631 TRANSB_CHICKEN2,
632 TRANSCCONF,
633 FDI_RXC_CTL,
634 FDI_RX_MISC_C,
635 FDI_RXC_IIR,
636 FDI_RXC_IMR,
637 FDI_RXC_TUSIZE1,
638 QUIRK_F2060,
639 TRANSC_CHICKEN2,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]640 BXT_P_CR_GT_DISP_PWRON,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]641 GT_MAILBOX,
642 GT_MAILBOX_DATA,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]643 GT_MAILBOX_DATA_1,
644 BXT_PORT_CL1CM_DW0_A,
645 BXT_PORT_CL1CM_DW9_A,
646 BXT_PORT_CL1CM_DW10_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]647 BXT_PORT_PLL_EBB_0_A,
648 BXT_PORT_PLL_EBB_4_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]649 BXT_PORT_CL1CM_DW28_A,
650 BXT_PORT_CL1CM_DW30_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]651 BXT_PORT_PLL_0_A,
652 BXT_PORT_PLL_1_A,
653 BXT_PORT_PLL_2_A,
654 BXT_PORT_PLL_3_A,
655 BXT_PORT_PLL_6_A,
656 BXT_PORT_PLL_8_A,
657 BXT_PORT_PLL_9_A,
658 BXT_PORT_PLL_10_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]659 BXT_PORT_REF_DW3_A,
660 BXT_PORT_REF_DW6_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]661 BXT_PORT_REF_DW8_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]662 BXT_PORT_PCS_DW10_01_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]663 BXT_PORT_PCS_DW12_01_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]664 BXT_PORT_TX_DW2_LN0_A,
665 BXT_PORT_TX_DW3_LN0_A,
666 BXT_PORT_TX_DW4_LN0_A,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]667 BXT_PORT_TX_DW14_LN0_A,
668 BXT_PORT_TX_DW14_LN1_A,
669 BXT_PORT_TX_DW14_LN2_A,
670 BXT_PORT_TX_DW14_LN3_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]671 BXT_PORT_PCS_DW10_GRP_A,
672 BXT_PORT_PCS_DW12_GRP_A,
673 BXT_PORT_TX_DW2_GRP_A,
674 BXT_PORT_TX_DW3_GRP_A,
675 BXT_PORT_TX_DW4_GRP_A);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]676
677 pragma Warnings
678 (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)",
679 Reason => "TODO: Should it matter?");
680 pragma Keep_Names (Registers_Invalid_Index);
681 pragma Warnings
682 (GNATprove, On, "pragma ""KEEP_NAMES"" ignored *(not yet supported)");
683
684 Register_Width : constant := 4;
685
686 for Registers_Invalid_Index use
687 (Invalid_Register => 0,
688
689 ---------------------------------------------------------------------------
690 -- Pipe A registers
691 ---------------------------------------------------------------------------
692
693 -- pipe timing registers
694
695 HTOTAL_A => 16#06_0000# / Register_Width,
696 HBLANK_A => 16#06_0004# / Register_Width,
697 HSYNC_A => 16#06_0008# / Register_Width,
698 VTOTAL_A => 16#06_000c# / Register_Width,
699 VBLANK_A => 16#06_0010# / Register_Width,
700 VSYNC_A => 16#06_0014# / Register_Width,
701 PIPEASRC => 16#06_001c# / Register_Width,
702 PIPEACONF => 16#07_0008# / Register_Width,
703 PIPEAMISC => 16#07_0030# / Register_Width,
704 TRANS_HTOTAL_A => 16#0e_0000# / Register_Width,
705 TRANS_HBLANK_A => 16#0e_0004# / Register_Width,
706 TRANS_HSYNC_A => 16#0e_0008# / Register_Width,
707 TRANS_VTOTAL_A => 16#0e_000c# / Register_Width,
708 TRANS_VBLANK_A => 16#0e_0010# / Register_Width,
709 TRANS_VSYNC_A => 16#0e_0014# / Register_Width,
710 TRANSA_DATA_M1 => 16#0e_0030# / Register_Width,
711 TRANSA_DATA_N1 => 16#0e_0034# / Register_Width,
712 TRANSA_DP_LINK_M1 => 16#0e_0040# / Register_Width,
713 TRANSA_DP_LINK_N1 => 16#0e_0044# / Register_Width,
714 PIPEA_DATA_M1 => 16#06_0030# / Register_Width,
715 PIPEA_DATA_N1 => 16#06_0034# / Register_Width,
716 PIPEA_LINK_M1 => 16#06_0040# / Register_Width,
717 PIPEA_LINK_N1 => 16#06_0044# / Register_Width,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame^]718 PIPEA_GMCH_DATA_M => 16#07_0050# / Register_Width,
719 PIPEA_GMCH_DATA_N => 16#07_0054# / Register_Width,
720 PIPEA_GMCH_LINK_M => 16#07_0060# / Register_Width,
721 PIPEA_GMCH_LINK_N => 16#07_0064# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]722 PIPEA_DDI_FUNC_CTL => 16#06_0400# / Register_Width,
723 PIPEA_MSA_MISC => 16#06_0410# / Register_Width,
724
725 -- PCH sideband interface registers
726 SBI_ADDR => 16#0c_6000# / Register_Width,
727 SBI_DATA => 16#0c_6004# / Register_Width,
728 SBI_CTL_STAT => 16#0c_6008# / Register_Width,
729
730 -- clock registers
731 PCH_DPLL_A => 16#0c_6014# / Register_Width,
732 PCH_PIXCLK_GATE => 16#0c_6020# / Register_Width,
733 PCH_FPA0 => 16#0c_6040# / Register_Width,
734 PCH_FPA1 => 16#0c_6044# / Register_Width,
735
736 -- panel fitter
737 PFA_CTL_1 => 16#06_8080# / Register_Width,
738 PFA_WIN_POS => 16#06_8070# / Register_Width,
739 PFA_WIN_SZ => 16#06_8074# / Register_Width,
740 PS_WIN_POS_1_A => 16#06_8170# / Register_Width,
741 PS_WIN_SZ_1_A => 16#06_8174# / Register_Width,
742 PS_CTRL_1_A => 16#06_8180# / Register_Width,
743 PS_WIN_POS_2_A => 16#06_8270# / Register_Width,
744 PS_WIN_SZ_2_A => 16#06_8274# / Register_Width,
745 PS_CTRL_2_A => 16#06_8280# / Register_Width,
746
747 -- display control
748 DSPACNTR => 16#07_0180# / Register_Width,
749 DSPALINOFF => 16#07_0184# / Register_Width,
750 DSPASTRIDE => 16#07_0188# / Register_Width,
751 PLANE_POS_1_A => 16#07_018c# / Register_Width,
752 PLANE_SIZE_1_A => 16#07_0190# / Register_Width,
753 DSPASURF => 16#07_019c# / Register_Width,
754 DSPATILEOFF => 16#07_01a4# / Register_Width,
755
756 -- sprite control
757 SPACNTR => 16#07_0280# / Register_Width,
758
759 -- FDI and PCH transcoder control
760 FDI_TX_CTL_A => 16#06_0100# / Register_Width,
761 FDI_RXA_CTL => 16#0f_000c# / Register_Width,
762 FDI_RX_MISC_A => 16#0f_0010# / Register_Width,
763 FDI_RXA_IIR => 16#0f_0014# / Register_Width,
764 FDI_RXA_IMR => 16#0f_0018# / Register_Width,
765 FDI_RXA_TUSIZE1 => 16#0f_0030# / Register_Width,
766 TRANSACONF => 16#0f_0008# / Register_Width,
767 TRANSA_CHICKEN2 => 16#0f_0064# / Register_Width,
768
769 -- watermark registers
770 WM_LINETIME_A => 16#04_5270# / Register_Width,
771 PLANE_WM_1_A_0 => 16#07_0240# / Register_Width,
772 PLANE_WM_1_A_1 => 16#07_0244# / Register_Width,
773 PLANE_WM_1_A_2 => 16#07_0248# / Register_Width,
774 PLANE_WM_1_A_3 => 16#07_024c# / Register_Width,
775 PLANE_WM_1_A_4 => 16#07_0250# / Register_Width,
776 PLANE_WM_1_A_5 => 16#07_0254# / Register_Width,
777 PLANE_WM_1_A_6 => 16#07_0258# / Register_Width,
778 PLANE_WM_1_A_7 => 16#07_025c# / Register_Width,
779 PLANE_BUF_CFG_1_A => 16#07_027c# / Register_Width,
780
781 -- CPU transcoder clock select
782 TRANSA_CLK_SEL => 16#04_6140# / Register_Width,
783
784 ---------------------------------------------------------------------------
785 -- Pipe B registers
786 ---------------------------------------------------------------------------
787
788 -- pipe timing registers
789
790 HTOTAL_B => 16#06_1000# / Register_Width,
791 HBLANK_B => 16#06_1004# / Register_Width,
792 HSYNC_B => 16#06_1008# / Register_Width,
793 VTOTAL_B => 16#06_100c# / Register_Width,
794 VBLANK_B => 16#06_1010# / Register_Width,
795 VSYNC_B => 16#06_1014# / Register_Width,
796 PIPEBSRC => 16#06_101c# / Register_Width,
797 PIPEBCONF => 16#07_1008# / Register_Width,
798 PIPEBMISC => 16#07_1030# / Register_Width,
799 TRANS_HTOTAL_B => 16#0e_1000# / Register_Width,
800 TRANS_HBLANK_B => 16#0e_1004# / Register_Width,
801 TRANS_HSYNC_B => 16#0e_1008# / Register_Width,
802 TRANS_VTOTAL_B => 16#0e_100c# / Register_Width,
803 TRANS_VBLANK_B => 16#0e_1010# / Register_Width,
804 TRANS_VSYNC_B => 16#0e_1014# / Register_Width,
805 TRANSB_DATA_M1 => 16#0e_1030# / Register_Width,
806 TRANSB_DATA_N1 => 16#0e_1034# / Register_Width,
807 TRANSB_DP_LINK_M1 => 16#0e_1040# / Register_Width,
808 TRANSB_DP_LINK_N1 => 16#0e_1044# / Register_Width,
809 PIPEB_DATA_M1 => 16#06_1030# / Register_Width,
810 PIPEB_DATA_N1 => 16#06_1034# / Register_Width,
811 PIPEB_LINK_M1 => 16#06_1040# / Register_Width,
812 PIPEB_LINK_N1 => 16#06_1044# / Register_Width,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame^]813 PIPEB_GMCH_DATA_M => 16#07_1050# / Register_Width,
814 PIPEB_GMCH_DATA_N => 16#07_1054# / Register_Width,
815 PIPEB_GMCH_LINK_M => 16#07_1060# / Register_Width,
816 PIPEB_GMCH_LINK_N => 16#07_1064# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]817 PIPEB_DDI_FUNC_CTL => 16#06_1400# / Register_Width,
818 PIPEB_MSA_MISC => 16#06_1410# / Register_Width,
819
820 -- clock registers
821 PCH_DPLL_B => 16#0c_6018# / Register_Width,
822 PCH_FPB0 => 16#0c_6048# / Register_Width,
823 PCH_FPB1 => 16#0c_604c# / Register_Width,
824
825 -- panel fitter
826 PFB_CTL_1 => 16#06_8880# / Register_Width,
827 PFB_WIN_POS => 16#06_8870# / Register_Width,
828 PFB_WIN_SZ => 16#06_8874# / Register_Width,
829 PS_WIN_POS_1_B => 16#06_8970# / Register_Width,
830 PS_WIN_SZ_1_B => 16#06_8974# / Register_Width,
831 PS_CTRL_1_B => 16#06_8980# / Register_Width,
832 PS_WIN_POS_2_B => 16#06_8a70# / Register_Width,
833 PS_WIN_SZ_2_B => 16#06_8a74# / Register_Width,
834 PS_CTRL_2_B => 16#06_8a80# / Register_Width,
835
836 -- display control
837 DSPBCNTR => 16#07_1180# / Register_Width,
838 DSPBLINOFF => 16#07_1184# / Register_Width,
839 DSPBSTRIDE => 16#07_1188# / Register_Width,
840 PLANE_POS_1_B => 16#07_118c# / Register_Width,
841 PLANE_SIZE_1_B => 16#07_1190# / Register_Width,
842 DSPBSURF => 16#07_119c# / Register_Width,
843 DSPBTILEOFF => 16#07_11a4# / Register_Width,
844
845 -- sprite control
846 SPBCNTR => 16#07_1280# / Register_Width,
847
848 -- FDI and PCH transcoder control
849 FDI_TX_CTL_B => 16#06_1100# / Register_Width,
850 FDI_RXB_CTL => 16#0f_100c# / Register_Width,
851 FDI_RX_MISC_B => 16#0f_1010# / Register_Width,
852 FDI_RXB_IIR => 16#0f_1014# / Register_Width,
853 FDI_RXB_IMR => 16#0f_1018# / Register_Width,
854 FDI_RXB_TUSIZE1 => 16#0f_1030# / Register_Width,
855 TRANSBCONF => 16#0f_1008# / Register_Width,
856 TRANSB_CHICKEN2 => 16#0f_1064# / Register_Width,
857
858 -- watermark registers
859 WM_LINETIME_B => 16#04_5274# / Register_Width,
860 PLANE_WM_1_B_0 => 16#07_1240# / Register_Width,
861 PLANE_WM_1_B_1 => 16#07_1244# / Register_Width,
862 PLANE_WM_1_B_2 => 16#07_1248# / Register_Width,
863 PLANE_WM_1_B_3 => 16#07_124c# / Register_Width,
864 PLANE_WM_1_B_4 => 16#07_1250# / Register_Width,
865 PLANE_WM_1_B_5 => 16#07_1254# / Register_Width,
866 PLANE_WM_1_B_6 => 16#07_1258# / Register_Width,
867 PLANE_WM_1_B_7 => 16#07_125c# / Register_Width,
868 PLANE_BUF_CFG_1_B => 16#07_127c# / Register_Width,
869
870 -- CPU transcoder clock select
871 TRANSB_CLK_SEL => 16#04_6144# / Register_Width,
872
873 ---------------------------------------------------------------------------
874 -- Pipe C registers
875 ---------------------------------------------------------------------------
876
877 -- pipe timing registers
878
879 HTOTAL_C => 16#06_2000# / Register_Width,
880 HBLANK_C => 16#06_2004# / Register_Width,
881 HSYNC_C => 16#06_2008# / Register_Width,
882 VTOTAL_C => 16#06_200c# / Register_Width,
883 VBLANK_C => 16#06_2010# / Register_Width,
884 VSYNC_C => 16#06_2014# / Register_Width,
885 PIPECSRC => 16#06_201c# / Register_Width,
886 PIPECCONF => 16#07_2008# / Register_Width,
887 PIPECMISC => 16#07_2030# / Register_Width,
888 TRANS_HTOTAL_C => 16#0e_2000# / Register_Width,
889 TRANS_HBLANK_C => 16#0e_2004# / Register_Width,
890 TRANS_HSYNC_C => 16#0e_2008# / Register_Width,
891 TRANS_VTOTAL_C => 16#0e_200c# / Register_Width,
892 TRANS_VBLANK_C => 16#0e_2010# / Register_Width,
893 TRANS_VSYNC_C => 16#0e_2014# / Register_Width,
894 TRANSC_DATA_M1 => 16#0e_2030# / Register_Width,
895 TRANSC_DATA_N1 => 16#0e_2034# / Register_Width,
896 TRANSC_DP_LINK_M1 => 16#0e_2040# / Register_Width,
897 TRANSC_DP_LINK_N1 => 16#0e_2044# / Register_Width,
898 PIPEC_DATA_M1 => 16#06_2030# / Register_Width,
899 PIPEC_DATA_N1 => 16#06_2034# / Register_Width,
900 PIPEC_LINK_M1 => 16#06_2040# / Register_Width,
901 PIPEC_LINK_N1 => 16#06_2044# / Register_Width,
902 PIPEC_DDI_FUNC_CTL => 16#06_2400# / Register_Width,
903 PIPEC_MSA_MISC => 16#06_2410# / Register_Width,
904
905 -- panel fitter
906 PFC_CTL_1 => 16#06_9080# / Register_Width,
907 PFC_WIN_POS => 16#06_9070# / Register_Width,
908 PFC_WIN_SZ => 16#06_9074# / Register_Width,
909 PS_WIN_POS_1_C => 16#06_9170# / Register_Width,
910 PS_WIN_SZ_1_C => 16#06_9174# / Register_Width,
911 PS_CTRL_1_C => 16#06_9180# / Register_Width,
912
913 -- display control
914 DSPCCNTR => 16#07_2180# / Register_Width,
915 DSPCLINOFF => 16#07_2184# / Register_Width,
916 DSPCSTRIDE => 16#07_2188# / Register_Width,
917 PLANE_POS_1_C => 16#07_218c# / Register_Width,
918 PLANE_SIZE_1_C => 16#07_2190# / Register_Width,
919 DSPCSURF => 16#07_219c# / Register_Width,
920 DSPCTILEOFF => 16#07_21a4# / Register_Width,
921
922 -- sprite control
923 SPCCNTR => 16#07_2280# / Register_Width,
924
925 -- PCH transcoder control
926 FDI_TX_CTL_C => 16#06_2100# / Register_Width,
927 FDI_RXC_CTL => 16#0f_200c# / Register_Width,
928 FDI_RX_MISC_C => 16#0f_2010# / Register_Width,
929 FDI_RXC_IIR => 16#0f_2014# / Register_Width,
930 FDI_RXC_IMR => 16#0f_2018# / Register_Width,
931 FDI_RXC_TUSIZE1 => 16#0f_2030# / Register_Width,
932 TRANSCCONF => 16#0f_2008# / Register_Width,
933 TRANSC_CHICKEN2 => 16#0f_2064# / Register_Width,
934
935 -- watermark registers
936 WM_LINETIME_C => 16#04_5278# / Register_Width,
937 PLANE_WM_1_C_0 => 16#07_2240# / Register_Width,
938 PLANE_WM_1_C_1 => 16#07_2244# / Register_Width,
939 PLANE_WM_1_C_2 => 16#07_2248# / Register_Width,
940 PLANE_WM_1_C_3 => 16#07_224c# / Register_Width,
941 PLANE_WM_1_C_4 => 16#07_2250# / Register_Width,
942 PLANE_WM_1_C_5 => 16#07_2254# / Register_Width,
943 PLANE_WM_1_C_6 => 16#07_2258# / Register_Width,
944 PLANE_WM_1_C_7 => 16#07_225c# / Register_Width,
945 PLANE_BUF_CFG_1_C => 16#07_227c# / Register_Width,
946
947 -- CPU transcoder clock select
948 TRANSC_CLK_SEL => 16#04_6148# / Register_Width,
949
950 ---------------------------------------------------------------------------
951 -- Pipe EDP registers
952 ---------------------------------------------------------------------------
953
954 -- pipe timing registers
955
956 HTOTAL_EDP => 16#06_f000# / Register_Width,
957 HBLANK_EDP => 16#06_f004# / Register_Width,
958 HSYNC_EDP => 16#06_f008# / Register_Width,
959 VTOTAL_EDP => 16#06_f00c# / Register_Width,
960 VBLANK_EDP => 16#06_f010# / Register_Width,
961 VSYNC_EDP => 16#06_f014# / Register_Width,
962 PIPE_EDP_CONF => 16#07_f008# / Register_Width,
963 PIPE_EDP_DATA_M1 => 16#06_f030# / Register_Width,
964 PIPE_EDP_DATA_N1 => 16#06_f034# / Register_Width,
965 PIPE_EDP_LINK_M1 => 16#06_f040# / Register_Width,
966 PIPE_EDP_LINK_N1 => 16#06_f044# / Register_Width,
967 PIPE_EDP_DDI_FUNC_CTL => 16#06_f400# / Register_Width,
968 PIPE_EDP_MSA_MISC => 16#06_f410# / Register_Width,
969
970 -- PSR registers
971 SRD_CTL => 16#06_4800# / Register_Width,
972 SRD_CTL_A => 16#06_0800# / Register_Width,
973 SRD_CTL_B => 16#06_1800# / Register_Width,
974 SRD_CTL_C => 16#06_2800# / Register_Width,
975 SRD_CTL_EDP => 16#06_f800# / Register_Width,
976 SRD_STATUS => 16#06_4840# / Register_Width,
977 SRD_STATUS_A => 16#06_0840# / Register_Width,
978 SRD_STATUS_B => 16#06_1840# / Register_Width,
979 SRD_STATUS_C => 16#06_2840# / Register_Width,
980 SRD_STATUS_EDP => 16#06_f840# / Register_Width,
981
982 -- DDI registers
983 DDI_BUF_CTL_A => 16#06_4000# / Register_Width, -- aliased by DP_CTL_A
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]984 DDI_BUF_TRANS_A_S0T1 => 16#06_4e00# / Register_Width,
985 DDI_BUF_TRANS_A_S0T2 => 16#06_4e04# / Register_Width,
986 DDI_BUF_TRANS_A_S1T1 => 16#06_4e08# / Register_Width,
987 DDI_BUF_TRANS_A_S1T2 => 16#06_4e0c# / Register_Width,
988 DDI_BUF_TRANS_A_S2T1 => 16#06_4e10# / Register_Width,
989 DDI_BUF_TRANS_A_S2T2 => 16#06_4e14# / Register_Width,
990 DDI_BUF_TRANS_A_S3T1 => 16#06_4e18# / Register_Width,
991 DDI_BUF_TRANS_A_S3T2 => 16#06_4e1c# / Register_Width,
992 DDI_BUF_TRANS_A_S4T1 => 16#06_4e20# / Register_Width,
993 DDI_BUF_TRANS_A_S4T2 => 16#06_4e24# / Register_Width,
994 DDI_BUF_TRANS_A_S5T1 => 16#06_4e28# / Register_Width,
995 DDI_BUF_TRANS_A_S5T2 => 16#06_4e2c# / Register_Width,
996 DDI_BUF_TRANS_A_S6T1 => 16#06_4e30# / Register_Width,
997 DDI_BUF_TRANS_A_S6T2 => 16#06_4e34# / Register_Width,
998 DDI_BUF_TRANS_A_S7T1 => 16#06_4e38# / Register_Width,
999 DDI_BUF_TRANS_A_S7T2 => 16#06_4e3c# / Register_Width,
1000 DDI_BUF_TRANS_A_S8T1 => 16#06_4e40# / Register_Width,
1001 DDI_BUF_TRANS_A_S8T2 => 16#06_4e44# / Register_Width,
1002 DDI_BUF_TRANS_A_S9T1 => 16#06_4e48# / Register_Width,
1003 DDI_BUF_TRANS_A_S9T2 => 16#06_4e4c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1004 DDI_AUX_CTL_A => 16#06_4010# / Register_Width, -- aliased by DP_AUX_CTL_A
1005 DDI_AUX_DATA_A_1 => 16#06_4014# / Register_Width, -- aliased by DP_AUX_DATA_A_1
1006 DDI_AUX_DATA_A_2 => 16#06_4018# / Register_Width, -- aliased by DP_AUX_DATA_A_2
1007 DDI_AUX_DATA_A_3 => 16#06_401c# / Register_Width, -- aliased by DP_AUX_DATA_A_3
1008 DDI_AUX_DATA_A_4 => 16#06_4020# / Register_Width, -- aliased by DP_AUX_DATA_A_4
1009 DDI_AUX_DATA_A_5 => 16#06_4024# / Register_Width, -- aliased by DP_AUX_DATA_A_5
1010 DDI_AUX_MUTEX_A => 16#06_402c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1011
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1012 DDI_BUF_CTL_B => 16#06_4100# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1013 DDI_BUF_TRANS_B_S0T1 => 16#06_4e60# / Register_Width,
1014 DDI_BUF_TRANS_B_S0T2 => 16#06_4e64# / Register_Width,
1015 DDI_BUF_TRANS_B_S1T1 => 16#06_4e68# / Register_Width,
1016 DDI_BUF_TRANS_B_S1T2 => 16#06_4e6c# / Register_Width,
1017 DDI_BUF_TRANS_B_S2T1 => 16#06_4e70# / Register_Width,
1018 DDI_BUF_TRANS_B_S2T2 => 16#06_4e74# / Register_Width,
1019 DDI_BUF_TRANS_B_S3T1 => 16#06_4e78# / Register_Width,
1020 DDI_BUF_TRANS_B_S3T2 => 16#06_4e7c# / Register_Width,
1021 DDI_BUF_TRANS_B_S4T1 => 16#06_4e80# / Register_Width,
1022 DDI_BUF_TRANS_B_S4T2 => 16#06_4e84# / Register_Width,
1023 DDI_BUF_TRANS_B_S5T1 => 16#06_4e88# / Register_Width,
1024 DDI_BUF_TRANS_B_S5T2 => 16#06_4e8c# / Register_Width,
1025 DDI_BUF_TRANS_B_S6T1 => 16#06_4e90# / Register_Width,
1026 DDI_BUF_TRANS_B_S6T2 => 16#06_4e94# / Register_Width,
1027 DDI_BUF_TRANS_B_S7T1 => 16#06_4e98# / Register_Width,
1028 DDI_BUF_TRANS_B_S7T2 => 16#06_4e9c# / Register_Width,
1029 DDI_BUF_TRANS_B_S8T1 => 16#06_4ea0# / Register_Width,
1030 DDI_BUF_TRANS_B_S8T2 => 16#06_4ea4# / Register_Width,
1031 DDI_BUF_TRANS_B_S9T1 => 16#06_4ea8# / Register_Width,
1032 DDI_BUF_TRANS_B_S9T2 => 16#06_4eac# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1033 DDI_AUX_CTL_B => 16#06_4110# / Register_Width,
1034 DDI_AUX_DATA_B_1 => 16#06_4114# / Register_Width,
1035 DDI_AUX_DATA_B_2 => 16#06_4118# / Register_Width,
1036 DDI_AUX_DATA_B_3 => 16#06_411c# / Register_Width,
1037 DDI_AUX_DATA_B_4 => 16#06_4120# / Register_Width,
1038 DDI_AUX_DATA_B_5 => 16#06_4124# / Register_Width,
1039 DDI_AUX_MUTEX_B => 16#06_412c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1040
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1041 DDI_BUF_CTL_C => 16#06_4200# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1042 DDI_BUF_TRANS_C_S0T1 => 16#06_4ec0# / Register_Width,
1043 DDI_BUF_TRANS_C_S0T2 => 16#06_4ec4# / Register_Width,
1044 DDI_BUF_TRANS_C_S1T1 => 16#06_4ec8# / Register_Width,
1045 DDI_BUF_TRANS_C_S1T2 => 16#06_4ecc# / Register_Width,
1046 DDI_BUF_TRANS_C_S2T1 => 16#06_4ed0# / Register_Width,
1047 DDI_BUF_TRANS_C_S2T2 => 16#06_4ed4# / Register_Width,
1048 DDI_BUF_TRANS_C_S3T1 => 16#06_4ed8# / Register_Width,
1049 DDI_BUF_TRANS_C_S3T2 => 16#06_4edc# / Register_Width,
1050 DDI_BUF_TRANS_C_S4T1 => 16#06_4ee0# / Register_Width,
1051 DDI_BUF_TRANS_C_S4T2 => 16#06_4ee4# / Register_Width,
1052 DDI_BUF_TRANS_C_S5T1 => 16#06_4ee8# / Register_Width,
1053 DDI_BUF_TRANS_C_S5T2 => 16#06_4eec# / Register_Width,
1054 DDI_BUF_TRANS_C_S6T1 => 16#06_4ef0# / Register_Width,
1055 DDI_BUF_TRANS_C_S6T2 => 16#06_4ef4# / Register_Width,
1056 DDI_BUF_TRANS_C_S7T1 => 16#06_4ef8# / Register_Width,
1057 DDI_BUF_TRANS_C_S7T2 => 16#06_4efc# / Register_Width,
1058 DDI_BUF_TRANS_C_S8T1 => 16#06_4f00# / Register_Width,
1059 DDI_BUF_TRANS_C_S8T2 => 16#06_4f04# / Register_Width,
1060 DDI_BUF_TRANS_C_S9T1 => 16#06_4f08# / Register_Width,
1061 DDI_BUF_TRANS_C_S9T2 => 16#06_4f0c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1062 DDI_AUX_CTL_C => 16#06_4210# / Register_Width,
1063 DDI_AUX_DATA_C_1 => 16#06_4214# / Register_Width,
1064 DDI_AUX_DATA_C_2 => 16#06_4218# / Register_Width,
1065 DDI_AUX_DATA_C_3 => 16#06_421c# / Register_Width,
1066 DDI_AUX_DATA_C_4 => 16#06_4220# / Register_Width,
1067 DDI_AUX_DATA_C_5 => 16#06_4224# / Register_Width,
1068 DDI_AUX_MUTEX_C => 16#06_422c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1069
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1070 DDI_BUF_CTL_D => 16#06_4300# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1071 DDI_BUF_TRANS_D_S0T1 => 16#06_4f20# / Register_Width,
1072 DDI_BUF_TRANS_D_S0T2 => 16#06_4f24# / Register_Width,
1073 DDI_BUF_TRANS_D_S1T1 => 16#06_4f28# / Register_Width,
1074 DDI_BUF_TRANS_D_S1T2 => 16#06_4f2c# / Register_Width,
1075 DDI_BUF_TRANS_D_S2T1 => 16#06_4f30# / Register_Width,
1076 DDI_BUF_TRANS_D_S2T2 => 16#06_4f34# / Register_Width,
1077 DDI_BUF_TRANS_D_S3T1 => 16#06_4f38# / Register_Width,
1078 DDI_BUF_TRANS_D_S3T2 => 16#06_4f3c# / Register_Width,
1079 DDI_BUF_TRANS_D_S4T1 => 16#06_4f40# / Register_Width,
1080 DDI_BUF_TRANS_D_S4T2 => 16#06_4f44# / Register_Width,
1081 DDI_BUF_TRANS_D_S5T1 => 16#06_4f48# / Register_Width,
1082 DDI_BUF_TRANS_D_S5T2 => 16#06_4f4c# / Register_Width,
1083 DDI_BUF_TRANS_D_S6T1 => 16#06_4f50# / Register_Width,
1084 DDI_BUF_TRANS_D_S6T2 => 16#06_4f54# / Register_Width,
1085 DDI_BUF_TRANS_D_S7T1 => 16#06_4f58# / Register_Width,
1086 DDI_BUF_TRANS_D_S7T2 => 16#06_4f5c# / Register_Width,
1087 DDI_BUF_TRANS_D_S8T1 => 16#06_4f60# / Register_Width,
1088 DDI_BUF_TRANS_D_S8T2 => 16#06_4f64# / Register_Width,
1089 DDI_BUF_TRANS_D_S9T1 => 16#06_4f68# / Register_Width,
1090 DDI_BUF_TRANS_D_S9T2 => 16#06_4f6c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1091 DDI_AUX_CTL_D => 16#06_4310# / Register_Width,
1092 DDI_AUX_DATA_D_1 => 16#06_4314# / Register_Width,
1093 DDI_AUX_DATA_D_2 => 16#06_4318# / Register_Width,
1094 DDI_AUX_DATA_D_3 => 16#06_431c# / Register_Width,
1095 DDI_AUX_DATA_D_4 => 16#06_4320# / Register_Width,
1096 DDI_AUX_DATA_D_5 => 16#06_4324# / Register_Width,
1097 DDI_AUX_MUTEX_D => 16#06_432c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1098
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1099 DDI_BUF_CTL_E => 16#06_4400# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1100 DDI_BUF_TRANS_E_S0T1 => 16#06_4f80# / Register_Width,
1101 DDI_BUF_TRANS_E_S0T2 => 16#06_4f84# / Register_Width,
1102 DDI_BUF_TRANS_E_S1T1 => 16#06_4f88# / Register_Width,
1103 DDI_BUF_TRANS_E_S1T2 => 16#06_4f8c# / Register_Width,
1104 DDI_BUF_TRANS_E_S2T1 => 16#06_4f90# / Register_Width,
1105 DDI_BUF_TRANS_E_S2T2 => 16#06_4f94# / Register_Width,
1106 DDI_BUF_TRANS_E_S3T1 => 16#06_4f98# / Register_Width,
1107 DDI_BUF_TRANS_E_S3T2 => 16#06_4f9c# / Register_Width,
1108 DDI_BUF_TRANS_E_S4T1 => 16#06_4fa0# / Register_Width,
1109 DDI_BUF_TRANS_E_S4T2 => 16#06_4fa4# / Register_Width,
1110 DDI_BUF_TRANS_E_S5T1 => 16#06_4fa8# / Register_Width,
1111 DDI_BUF_TRANS_E_S5T2 => 16#06_4fac# / Register_Width,
1112 DDI_BUF_TRANS_E_S6T1 => 16#06_4fb0# / Register_Width,
1113 DDI_BUF_TRANS_E_S6T2 => 16#06_4fb4# / Register_Width,
1114 DDI_BUF_TRANS_E_S7T1 => 16#06_4fb8# / Register_Width,
1115 DDI_BUF_TRANS_E_S7T2 => 16#06_4fbc# / Register_Width,
1116 DDI_BUF_TRANS_E_S8T1 => 16#06_4fc0# / Register_Width,
1117 DDI_BUF_TRANS_E_S8T2 => 16#06_4fc4# / Register_Width,
1118 DDI_BUF_TRANS_E_S9T1 => 16#06_4fc8# / Register_Width,
1119 DDI_BUF_TRANS_E_S9T2 => 16#06_4fcc# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1120 DP_TP_CTL_A => 16#06_4040# / Register_Width,
1121 DP_TP_CTL_B => 16#06_4140# / Register_Width,
1122 DP_TP_CTL_C => 16#06_4240# / Register_Width,
1123 DP_TP_CTL_D => 16#06_4340# / Register_Width,
1124 DP_TP_CTL_E => 16#06_4440# / Register_Width,
1125 DP_TP_STATUS_B => 16#06_4144# / Register_Width,
1126 DP_TP_STATUS_C => 16#06_4244# / Register_Width,
1127 DP_TP_STATUS_D => 16#06_4344# / Register_Width,
1128 DP_TP_STATUS_E => 16#06_4444# / Register_Width,
1129 PORT_CLK_SEL_DDIA => 16#04_6100# / Register_Width,
1130 PORT_CLK_SEL_DDIB => 16#04_6104# / Register_Width,
1131 PORT_CLK_SEL_DDIC => 16#04_6108# / Register_Width,
1132 PORT_CLK_SEL_DDID => 16#04_610c# / Register_Width,
1133 PORT_CLK_SEL_DDIE => 16#04_6110# / Register_Width,
1134
Nico Huber58afc202017-06-12 21:34:55 +0200[diff] [blame]1135 -- Skylake I_boost configuration
1136 DISPIO_CR_TX_BMU_CR0 => 16#06_c00c# / Register_Width,
1137
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1138 -- Skylake DPLL registers
1139 DPLL1_CFGR1 => 16#06_c040# / Register_Width,
1140 DPLL1_CFGR2 => 16#06_c044# / Register_Width,
1141 DPLL2_CFGR1 => 16#06_c048# / Register_Width,
1142 DPLL2_CFGR2 => 16#06_c04c# / Register_Width,
1143 DPLL3_CFGR1 => 16#06_c050# / Register_Width,
1144 DPLL3_CFGR2 => 16#06_c054# / Register_Width,
1145 DPLL_CTRL1 => 16#06_c058# / Register_Width,
1146 DPLL_CTRL2 => 16#06_c05c# / Register_Width,
1147 DPLL_STATUS => 16#06_c060# / Register_Width,
1148
1149 -- CD CLK register
1150 CDCLK_CTL => 16#04_6000# / Register_Width,
1151
1152 -- Skylake LCPLL registers
1153 LCPLL1_CTL => 16#04_6010# / Register_Width,
1154 LCPLL2_CTL => 16#04_6014# / Register_Width,
1155
1156 -- SPLL register
1157 SPLL_CTL => 16#04_6020# / Register_Width,
1158
1159 -- WRPLL registers
1160 WRPLL_CTL_1 => 16#04_6040# / Register_Width,
1161 WRPLL_CTL_2 => 16#04_6060# / Register_Width,
1162
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]1163 -- Broxton Display Engine PLL registers
1164 BXT_DE_PLL_CTL => 16#06_d000# / Register_Width,
1165 BXT_DE_PLL_ENABLE => 16#04_6070# / Register_Width,
1166
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1167 -- Broxton DDI PHY PLL registers
1168 BXT_PORT_PLL_ENABLE_A => 16#04_6074# / Register_Width,
1169 BXT_PORT_PLL_ENABLE_B => 16#04_6078# / Register_Width,
1170 BXT_PORT_PLL_ENABLE_C => 16#04_607c# / Register_Width,
1171 BXT_PORT_PLL_EBB_0_A => 16#16_2034# / Register_Width,
1172 BXT_PORT_PLL_EBB_4_A => 16#16_2038# / Register_Width,
1173 BXT_PORT_PLL_0_A => 16#16_2100# / Register_Width,
1174 BXT_PORT_PLL_1_A => 16#16_2104# / Register_Width,
1175 BXT_PORT_PLL_2_A => 16#16_2108# / Register_Width,
1176 BXT_PORT_PLL_3_A => 16#16_210c# / Register_Width,
1177 BXT_PORT_PLL_6_A => 16#16_2118# / Register_Width,
1178 BXT_PORT_PLL_8_A => 16#16_2120# / Register_Width,
1179 BXT_PORT_PLL_9_A => 16#16_2124# / Register_Width,
1180 BXT_PORT_PLL_10_A => 16#16_2128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1181 BXT_PORT_PLL_EBB_0_B => 16#06_c034# / Register_Width,
1182 BXT_PORT_PLL_EBB_4_B => 16#06_c038# / Register_Width,
1183 BXT_PORT_PLL_0_B => 16#06_c100# / Register_Width,
1184 BXT_PORT_PLL_1_B => 16#06_c104# / Register_Width,
1185 BXT_PORT_PLL_2_B => 16#06_c108# / Register_Width,
1186 BXT_PORT_PLL_3_B => 16#06_c10c# / Register_Width,
1187 BXT_PORT_PLL_6_B => 16#06_c118# / Register_Width,
1188 BXT_PORT_PLL_8_B => 16#06_c120# / Register_Width,
1189 BXT_PORT_PLL_9_B => 16#06_c124# / Register_Width,
1190 BXT_PORT_PLL_10_B => 16#06_c128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1191 BXT_PORT_PLL_EBB_0_C => 16#06_c340# / Register_Width,
1192 BXT_PORT_PLL_EBB_4_C => 16#06_c344# / Register_Width,
1193 BXT_PORT_PLL_0_C => 16#06_c380# / Register_Width,
1194 BXT_PORT_PLL_1_C => 16#06_c384# / Register_Width,
1195 BXT_PORT_PLL_2_C => 16#06_c388# / Register_Width,
1196 BXT_PORT_PLL_3_C => 16#06_c38c# / Register_Width,
1197 BXT_PORT_PLL_6_C => 16#06_c398# / Register_Width,
1198 BXT_PORT_PLL_8_C => 16#06_c3a0# / Register_Width,
1199 BXT_PORT_PLL_9_C => 16#06_c3a4# / Register_Width,
1200 BXT_PORT_PLL_10_C => 16#06_c3a8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1201
1202 -- Broxton DDI PHY PCS? registers
1203 BXT_PORT_PCS_DW10_01_A => 16#16_2428# / Register_Width,
1204 BXT_PORT_PCS_DW12_01_A => 16#16_2430# / Register_Width,
1205 BXT_PORT_PCS_DW10_GRP_A => 16#16_2c28# / Register_Width,
1206 BXT_PORT_PCS_DW12_GRP_A => 16#16_2c30# / Register_Width,
1207 BXT_PORT_PCS_DW10_01_B => 16#06_c428# / Register_Width,
1208 BXT_PORT_PCS_DW12_01_B => 16#06_c430# / Register_Width,
1209 BXT_PORT_PCS_DW10_01_C => 16#06_c828# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1210 BXT_PORT_PCS_DW12_01_C => 16#06_c830# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1211 BXT_PORT_PCS_DW10_GRP_B => 16#06_cc28# / Register_Width,
1212 BXT_PORT_PCS_DW12_GRP_B => 16#06_cc30# / Register_Width,
1213 BXT_PORT_PCS_DW10_GRP_C => 16#06_ce28# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1214 BXT_PORT_PCS_DW12_GRP_C => 16#06_ce30# / Register_Width,
1215
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]1216 -- Broxton DDI PHY registers
1217 BXT_P_CR_GT_DISP_PWRON => 16#13_8090# / Register_Width,
1218 BXT_PHY_CTL_A => 16#06_4c00# / Register_Width,
1219 BXT_PHY_CTL_B => 16#06_4c10# / Register_Width,
1220 BXT_PHY_CTL_C => 16#06_4c20# / Register_Width,
1221 BXT_PHY_CTL_FAM_EDP => 16#06_4c80# / Register_Width,
1222 BXT_PHY_CTL_FAM_DDI => 16#06_4c90# / Register_Width,
1223
1224 -- Broxton DDI PHY common lane registers
1225 BXT_PORT_CL1CM_DW0_A => 16#16_2000# / Register_Width,
1226 BXT_PORT_CL1CM_DW0_BC => 16#06_c000# / Register_Width,
1227 BXT_PORT_CL1CM_DW9_A => 16#16_2024# / Register_Width,
1228 BXT_PORT_CL1CM_DW9_BC => 16#06_c024# / Register_Width,
1229 BXT_PORT_CL1CM_DW10_A => 16#16_2028# / Register_Width,
1230 BXT_PORT_CL1CM_DW10_BC => 16#06_c028# / Register_Width,
1231 BXT_PORT_CL1CM_DW28_A => 16#16_2070# / Register_Width,
1232 BXT_PORT_CL1CM_DW28_BC => 16#06_c070# / Register_Width,
1233 BXT_PORT_CL1CM_DW30_A => 16#16_2078# / Register_Width,
1234 BXT_PORT_CL1CM_DW30_BC => 16#06_c078# / Register_Width,
1235 BXT_PORT_CL2CM_DW6_BC => 16#06_c358# / Register_Width,
1236
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1237 -- Broxton DDI PHY TX lane registers
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1238 BXT_PORT_TX_DW2_LN0_A => 16#16_2508# / Register_Width,
1239 BXT_PORT_TX_DW3_LN0_A => 16#16_250c# / Register_Width,
1240 BXT_PORT_TX_DW4_LN0_A => 16#16_2510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1241 BXT_PORT_TX_DW14_LN0_A => 16#16_2538# / Register_Width,
1242 BXT_PORT_TX_DW14_LN1_A => 16#16_25b8# / Register_Width,
1243 BXT_PORT_TX_DW14_LN2_A => 16#16_2738# / Register_Width,
1244 BXT_PORT_TX_DW14_LN3_A => 16#16_27b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1245 BXT_PORT_TX_DW2_GRP_A => 16#16_2d08# / Register_Width,
1246 BXT_PORT_TX_DW3_GRP_A => 16#16_2d0c# / Register_Width,
1247 BXT_PORT_TX_DW4_GRP_A => 16#16_2d10# / Register_Width,
1248 BXT_PORT_TX_DW2_LN0_B => 16#06_c508# / Register_Width,
1249 BXT_PORT_TX_DW3_LN0_B => 16#06_c50c# / Register_Width,
1250 BXT_PORT_TX_DW4_LN0_B => 16#06_c510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1251 BXT_PORT_TX_DW14_LN0_B => 16#06_c538# / Register_Width,
1252 BXT_PORT_TX_DW14_LN1_B => 16#06_c5b8# / Register_Width,
1253 BXT_PORT_TX_DW14_LN2_B => 16#06_c738# / Register_Width,
1254 BXT_PORT_TX_DW14_LN3_B => 16#06_c7b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1255 BXT_PORT_TX_DW2_GRP_B => 16#06_cd08# / Register_Width,
1256 BXT_PORT_TX_DW3_GRP_B => 16#06_cd0c# / Register_Width,
1257 BXT_PORT_TX_DW4_GRP_B => 16#06_cd10# / Register_Width,
1258 BXT_PORT_TX_DW2_LN0_C => 16#06_c908# / Register_Width,
1259 BXT_PORT_TX_DW3_LN0_C => 16#06_c90c# / Register_Width,
1260 BXT_PORT_TX_DW4_LN0_C => 16#06_c910# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1261 BXT_PORT_TX_DW14_LN0_C => 16#06_c938# / Register_Width,
1262 BXT_PORT_TX_DW14_LN1_C => 16#06_c9b8# / Register_Width,
1263 BXT_PORT_TX_DW14_LN2_C => 16#06_cb38# / Register_Width,
1264 BXT_PORT_TX_DW14_LN3_C => 16#06_cbb8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1265 BXT_PORT_TX_DW2_GRP_C => 16#06_cf08# / Register_Width,
1266 BXT_PORT_TX_DW3_GRP_C => 16#06_cf0c# / Register_Width,
1267 BXT_PORT_TX_DW4_GRP_C => 16#06_cf10# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1268
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]1269 -- Broxton DDI PHY ref registers
1270 BXT_PORT_REF_DW3_A => 16#16_218c# / Register_Width,
1271 BXT_PORT_REF_DW3_BC => 16#06_c18c# / Register_Width,
1272 BXT_PORT_REF_DW6_A => 16#16_2198# / Register_Width,
1273 BXT_PORT_REF_DW6_BC => 16#06_c198# / Register_Width,
1274 BXT_PORT_REF_DW8_A => 16#16_21a0# / Register_Width,
1275 BXT_PORT_REF_DW8_BC => 16#06_c1a0# / Register_Width,
1276
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1277 -- Power Down Well registers
1278 PWR_WELL_CTL_BIOS => 16#04_5400# / Register_Width,
1279 PWR_WELL_CTL_DRIVER => 16#04_5404# / Register_Width,
1280 PWR_WELL_CTL_KVMR => 16#04_5408# / Register_Width,
1281 PWR_WELL_CTL_DEBUG => 16#04_540c# / Register_Width,
1282 PWR_WELL_CTL5 => 16#04_5410# / Register_Width,
1283 PWR_WELL_CTL6 => 16#04_5414# / Register_Width,
1284
1285 -- class Panel registers
1286 PCH_PP_STATUS => 16#0c_7200# / Register_Width,
1287 PCH_PP_CONTROL => 16#0c_7204# / Register_Width,
1288 PCH_PP_ON_DELAYS => 16#0c_7208# / Register_Width,
1289 PCH_PP_OFF_DELAYS => 16#0c_720c# / Register_Width,
1290 PCH_PP_DIVISOR => 16#0c_7210# / Register_Width,
1291 BLC_PWM_CPU_CTL => 16#04_8254# / Register_Width,
1292 BLC_PWM_PCH_CTL2 => 16#0c_8254# / Register_Width,
1293
1294 -- PCH LVDS Connector Registers
1295 PCH_LVDS => 16#0e_1180# / Register_Width,
1296
1297 -- PCH ADPA Connector Registers
1298 PCH_ADPA => 16#0e_1100# / Register_Width,
1299
1300 -- PCH HDMIB Connector Registers
1301 PCH_HDMIB => 16#0e_1140# / Register_Width,
1302
1303 -- PCH HDMIC Connector Registers
1304 PCH_HDMIC => 16#0e_1150# / Register_Width,
1305
1306 -- PCH HDMID Connector Registers
1307 PCH_HDMID => 16#0e_1160# / Register_Width,
1308
1309 -- Intel Registers
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]1310 CPU_VGACNTRL => 16#04_1000# / Register_Width,
1311 GMCH_VGACNTRL => 16#07_1400# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1312 FUSE_STATUS => 16#04_2000# / Register_Width,
1313 FBA_CFB_BASE => 16#04_3200# / Register_Width,
1314 IPS_CTL => 16#04_3408# / Register_Width,
1315 ARB_CTL => 16#04_5000# / Register_Width,
1316 DBUF_CTL => 16#04_5008# / Register_Width,
1317 NDE_RSTWRN_OPT => 16#04_6408# / Register_Width,
1318 PCH_DREF_CONTROL => 16#0c_6200# / Register_Width,
1319 BLC_PWM_PCH_CTL1 => 16#0c_8250# / Register_Width,
1320 BLC_PWM_CPU_CTL2 => 16#04_8250# / Register_Width,
1321 PCH_DPLL_SEL => 16#0c_7000# / Register_Width,
1322 GT_MAILBOX => 16#13_8124# / Register_Width,
1323 GT_MAILBOX_DATA => 16#13_8128# / Register_Width,
1324 GT_MAILBOX_DATA_1 => 16#13_812c# / Register_Width,
1325
1326 PCH_DP_B => 16#0e_4100# / Register_Width,
1327 PCH_DP_AUX_CTL_B => 16#0e_4110# / Register_Width,
1328 PCH_DP_AUX_DATA_B_1 => 16#0e_4114# / Register_Width,
1329 PCH_DP_AUX_DATA_B_2 => 16#0e_4118# / Register_Width,
1330 PCH_DP_AUX_DATA_B_3 => 16#0e_411c# / Register_Width,
1331 PCH_DP_AUX_DATA_B_4 => 16#0e_4120# / Register_Width,
1332 PCH_DP_AUX_DATA_B_5 => 16#0e_4124# / Register_Width,
1333 PCH_DP_C => 16#0e_4200# / Register_Width,
1334 PCH_DP_AUX_CTL_C => 16#0e_4210# / Register_Width,
1335 PCH_DP_AUX_DATA_C_1 => 16#0e_4214# / Register_Width,
1336 PCH_DP_AUX_DATA_C_2 => 16#0e_4218# / Register_Width,
1337 PCH_DP_AUX_DATA_C_3 => 16#0e_421c# / Register_Width,
1338 PCH_DP_AUX_DATA_C_4 => 16#0e_4220# / Register_Width,
1339 PCH_DP_AUX_DATA_C_5 => 16#0e_4224# / Register_Width,
1340 PCH_DP_D => 16#0e_4300# / Register_Width,
1341 PCH_DP_AUX_CTL_D => 16#0e_4310# / Register_Width,
1342 PCH_DP_AUX_DATA_D_1 => 16#0e_4314# / Register_Width,
1343 PCH_DP_AUX_DATA_D_2 => 16#0e_4318# / Register_Width,
1344 PCH_DP_AUX_DATA_D_3 => 16#0e_431c# / Register_Width,
1345 PCH_DP_AUX_DATA_D_4 => 16#0e_4320# / Register_Width,
1346 PCH_DP_AUX_DATA_D_5 => 16#0e_4324# / Register_Width,
1347
1348 -- watermark registers
1349 WM1_LP_ILK => 16#04_5108# / Register_Width,
1350 WM2_LP_ILK => 16#04_510c# / Register_Width,
1351 WM3_LP_ILK => 16#04_5110# / Register_Width,
1352
1353 -- audio VID/DID
1354 AUD_VID_DID => 16#06_5020# / Register_Width,
1355 PCH_AUD_VID_DID => 16#0e_5020# / Register_Width,
1356
1357 -- interrupt registers
1358 DEISR => 16#04_4000# / Register_Width,
1359 DEIMR => 16#04_4004# / Register_Width,
1360 DEIIR => 16#04_4008# / Register_Width,
1361 DEIER => 16#04_400c# / Register_Width,
1362 GTISR => 16#04_4010# / Register_Width,
1363 GTIMR => 16#04_4014# / Register_Width,
1364 GTIIR => 16#04_4018# / Register_Width,
1365 GTIER => 16#04_401c# / Register_Width,
1366 SDEISR => 16#0c_4000# / Register_Width,
1367 SDEIMR => 16#0c_4004# / Register_Width,
1368 SDEIIR => 16#0c_4008# / Register_Width,
1369 SDEIER => 16#0c_400c# / Register_Width,
1370
1371 -- I2C stuff
Arthur Heymans229ed1c2018-03-28 16:45:43 +0200[diff] [blame]1372 GMCH_GMBUS0 => 16#00_5100# / Register_Width,
1373 GMCH_GMBUS1 => 16#00_5104# / Register_Width,
1374 GMCH_GMBUS2 => 16#00_5108# / Register_Width,
1375 GMCH_GMBUS3 => 16#00_510c# / Register_Width,
1376 GMCH_GMBUS4 => 16#00_5110# / Register_Width,
1377 GMCH_GMBUS5 => 16#00_5120# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1378 PCH_GMBUS0 => 16#0c_5100# / Register_Width,
1379 PCH_GMBUS1 => 16#0c_5104# / Register_Width,
1380 PCH_GMBUS2 => 16#0c_5108# / Register_Width,
1381 PCH_GMBUS3 => 16#0c_510c# / Register_Width,
1382 PCH_GMBUS4 => 16#0c_5110# / Register_Width,
1383 PCH_GMBUS5 => 16#0c_5120# / Register_Width,
1384
1385 -- clock gating -- maybe have to touch this
1386 DSPCLK_GATE_D => 16#04_2020# / Register_Width,
1387 PCH_FDI_CHICKEN_B_C => 16#0c_2000# / Register_Width,
1388 PCH_DSPCLK_GATE_D => 16#0c_2020# / Register_Width,
1389
1390 -- hotplug and initial detection
1391 HOTPLUG_CTL => 16#04_4030# / Register_Width,
1392 SHOTPLUG_CTL => 16#0c_4030# / Register_Width,
1393 SFUSE_STRAP => 16#0c_2014# / Register_Width,
1394
1395 -- Render Engine Command Streamer
1396 ARB_MODE => 16#00_4030# / Register_Width,
1397 HWS_PGA => 16#00_4080# / Register_Width,
1398 RCS_RING_BUFFER_TAIL => 16#00_2030# / Register_Width,
1399 VCS_RING_BUFFER_TAIL => 16#01_2030# / Register_Width,
1400 BCS_RING_BUFFER_TAIL => 16#02_2030# / Register_Width,
1401 RCS_RING_BUFFER_HEAD => 16#00_2034# / Register_Width,
1402 VCS_RING_BUFFER_HEAD => 16#01_2034# / Register_Width,
1403 BCS_RING_BUFFER_HEAD => 16#02_2034# / Register_Width,
1404 RCS_RING_BUFFER_STRT => 16#00_2038# / Register_Width,
1405 VCS_RING_BUFFER_STRT => 16#01_2038# / Register_Width,
1406 BCS_RING_BUFFER_STRT => 16#02_2038# / Register_Width,
1407 RCS_RING_BUFFER_CTL => 16#00_203c# / Register_Width,
1408 VCS_RING_BUFFER_CTL => 16#01_203c# / Register_Width,
1409 BCS_RING_BUFFER_CTL => 16#02_203c# / Register_Width,
1410 MI_MODE => 16#00_209c# / Register_Width,
1411 INSTPM => 16#00_20c0# / Register_Width,
1412 GAB_CTL_REG => 16#02_4000# / Register_Width,
1413 PP_DCLV_HIGH => 16#00_2220# / Register_Width,
1414 PP_DCLV_LOW => 16#00_2228# / Register_Width,
1415 VCS_PP_DCLV_HIGH => 16#01_2220# / Register_Width,
1416 VCS_PP_DCLV_LOW => 16#01_2228# / Register_Width,
1417 BCS_PP_DCLV_HIGH => 16#02_2220# / Register_Width,
1418 BCS_PP_DCLV_LOW => 16#02_2228# / Register_Width,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1419 ILK_DISPLAY_CHICKEN2 => 16#04_2004# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1420 UCGCTL1 => 16#00_9400# / Register_Width,
1421 UCGCTL2 => 16#00_9404# / Register_Width,
1422 MBCTL => 16#00_907c# / Register_Width,
1423 HWSTAM => 16#00_2098# / Register_Width,
1424 VCS_HWSTAM => 16#01_2098# / Register_Width,
1425 BCS_HWSTAM => 16#02_2098# / Register_Width,
1426 IIR => 16#04_4028# / Register_Width,
1427 PIPE_FRMCNT_A => 16#07_0040# / Register_Width,
1428 PIPE_FRMCNT_B => 16#07_1040# / Register_Width,
1429 PIPE_FRMCNT_C => 16#07_2040# / Register_Width,
1430 FBC_CTL => 16#04_3208# / Register_Width,
1431 PIPE_VSYNCSHIFT_A => 16#06_0028# / Register_Width,
1432 PIPE_VSYNCSHIFT_B => 16#06_1028# / Register_Width,
1433 PIPE_VSYNCSHIFT_C => 16#06_2028# / Register_Width,
1434 WM_PIPE_A => 16#04_5100# / Register_Width,
1435 WM_PIPE_B => 16#04_5104# / Register_Width,
1436 WM_PIPE_C => 16#04_5200# / Register_Width,
1437 PIPE_SCANLINE_A => 16#07_0000# / Register_Width,
1438 PIPE_SCANLINE_B => 16#07_1000# / Register_Width,
1439 PIPE_SCANLINE_C => 16#07_2000# / Register_Width,
1440 GFX_MODE => 16#00_2520# / Register_Width,
1441 CACHE_MODE_0 => 16#00_2120# / Register_Width,
1442 SLEEP_PSMI_CONTROL => 16#01_2050# / Register_Width,
1443 CTX_SIZE => 16#00_21a0# / Register_Width,
1444 GAC_ECO_BITS => 16#01_4090# / Register_Width,
1445 GAM_ECOCHK => 16#00_4090# / Register_Width,
1446 QUIRK_02084 => 16#00_2084# / Register_Width,
1447 QUIRK_02090 => 16#00_2090# / Register_Width,
1448 GT_MODE => 16#00_20d0# / Register_Width,
1449 QUIRK_F0060 => 16#0f_0060# / Register_Width,
1450 QUIRK_F1060 => 16#0f_1060# / Register_Width,
1451 QUIRK_F2060 => 16#0f_2060# / Register_Width,
1452 AUD_CNTRL_ST2 => 16#0e_50c0# / Register_Width,
1453 AUD_CNTL_ST_A => 16#0e_50b4# / Register_Width,
1454 AUD_CNTL_ST_B => 16#0e_51b4# / Register_Width,
1455 AUD_CNTL_ST_C => 16#0e_52b4# / Register_Width,
1456 AUD_HDMIW_HDMIEDID_A => 16#0e_5050# / Register_Width,
1457 AUD_HDMIW_HDMIEDID_B => 16#0e_5150# / Register_Width,
1458 AUD_HDMIW_HDMIEDID_C => 16#0e_5250# / Register_Width,
1459 AUD_CONFIG_A => 16#0e_5000# / Register_Width,
1460 AUD_CONFIG_B => 16#0e_5100# / Register_Width,
1461 AUD_CONFIG_C => 16#0e_5200# / Register_Width,
1462 TRANS_DP_CTL_A => 16#0e_0300# / Register_Width,
1463 TRANS_DP_CTL_B => 16#0e_1300# / Register_Width,
1464 TRANS_DP_CTL_C => 16#0e_2300# / Register_Width,
1465 TRANS_VSYNCSHIFT_A => 16#0e_0028# / Register_Width,
1466 TRANS_VSYNCSHIFT_B => 16#0e_1028# / Register_Width,
1467 TRANS_VSYNCSHIFT_C => 16#0e_2028# / Register_Width,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]1468 PCH_RAWCLK_FREQ => 16#0c_6204# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1469 QUIRK_C2004 => 16#0c_2004# / Register_Width);
1470
1471 subtype Registers_Index is Registers_Invalid_Index range
1472 Registers_Invalid_Index'Succ (Invalid_Register) ..
1473 Registers_Invalid_Index'Last;
1474
1475 -- aliased registers
1476 DP_CTL_A : constant Registers_Index := DDI_BUF_CTL_A;
1477 DP_AUX_CTL_A : constant Registers_Index := DDI_AUX_CTL_A;
1478 DP_AUX_DATA_A_1 : constant Registers_Index := DDI_AUX_DATA_A_1;
1479 DP_AUX_DATA_A_2 : constant Registers_Index := DDI_AUX_DATA_A_2;
1480 DP_AUX_DATA_A_3 : constant Registers_Index := DDI_AUX_DATA_A_3;
1481 DP_AUX_DATA_A_4 : constant Registers_Index := DDI_AUX_DATA_A_4;
1482 DP_AUX_DATA_A_5 : constant Registers_Index := DDI_AUX_DATA_A_5;
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1483 ILK_DISPLAY_CHICKEN1 : constant Registers_Index := FUSE_STATUS;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1484
1485 ---------------------------------------------------------------------------
1486
1487 Default_Timeout_MS : constant := 10;
1488
1489 ---------------------------------------------------------------------------
1490
1491 procedure Posting_Read
1492 (Register : in Registers_Index)
1493 with
1494 Global => (In_Out => Register_State),
1495 Depends => (Register_State =>+ (Register)),
1496 Pre => True,
1497 Post => True;
1498
1499 pragma Warnings (GNATprove, Off, "unused variable ""Verbose""",
1500 Reason => "Only used on debugging path");
1501 procedure Read
1502 (Register : in Registers_Index;
1503 Value : out Word32;
1504 Verbose : in Boolean := True)
1505 with
1506 Global => (In_Out => Register_State),
1507 Depends => ((Value, Register_State) => (Register, Register_State),
1508 null => Verbose),
1509 Pre => True,
1510 Post => True;
1511 pragma Warnings (GNATprove, On, "unused variable ""Verbose""");
1512
1513 procedure Write
1514 (Register : Registers_Index;
1515 Value : Word32)
1516 with
1517 Global => (In_Out => Register_State),
1518 Depends => (Register_State => (Register, Register_State, Value)),
1519 Pre => True,
1520 Post => True;
1521
1522 procedure Is_Set_Mask
1523 (Register : in Registers_Index;
1524 Mask : in Word32;
1525 Result : out Boolean);
1526
1527 pragma Warnings (GNATprove, Off, "unused initial value of ""Verbose""",
1528 Reason => "Only used on debugging path");
Nico Huberbcb2c472017-02-02 16:39:26 +0100[diff] [blame]1529 procedure Wait
1530 (Register : Registers_Index;
1531 Mask : Word32;
1532 Value : Word32;
1533 TOut_MS : Natural := Default_Timeout_MS;
1534 Verbose : Boolean := False);
1535
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1536 procedure Wait_Set_Mask
1537 (Register : Registers_Index;
1538 Mask : Word32;
1539 TOut_MS : Natural := Default_Timeout_MS;
1540 Verbose : Boolean := False);
1541
1542 procedure Wait_Unset_Mask
1543 (Register : Registers_Index;
1544 Mask : Word32;
1545 TOut_MS : Natural := Default_Timeout_MS;
1546 Verbose : Boolean := False);
1547 pragma Warnings (GNATprove, On, "unused initial value of ""Verbose""");
1548
1549 procedure Set_Mask
1550 (Register : Registers_Index;
1551 Mask : Word32);
1552
1553 procedure Unset_Mask
1554 (Register : Registers_Index;
1555 Mask : Word32);
1556
1557 procedure Unset_And_Set_Mask
1558 (Register : Registers_Index;
1559 Mask_Unset : Word32;
1560 Mask_Set : Word32);
1561
Nico Huber17d64b62017-07-15 20:51:25 +0200[diff] [blame]1562 procedure Clear_Fences;
1563
Nico Huberb03c8f12017-08-25 13:29:08 +0200[diff] [blame]1564 procedure Add_Fence
1565 (First_Page : in GTT_Range;
1566 Last_Page : in GTT_Range;
1567 Tiling : in XY_Tiling;
1568 Pitch : in Natural;
1569 Success : out Boolean);
1570
1571 procedure Remove_Fence (First_Page, Last_Page : GTT_Range);
1572
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1573 pragma Warnings (Off, "declaration of ""Write_GTT"" hides one at *");
1574 procedure Write_GTT
1575 (GTT_Page : GTT_Range;
1576 Device_Address : GTT_Address_Type;
1577 Valid : Boolean)
1578 with
1579 Global => (In_Out => GTT_State),
1580 Depends => (GTT_State =>+ (GTT_Page, Device_Address, Valid)),
1581 Pre => True,
1582 Post => True;
1583 pragma Warnings (On, "declaration of ""Write_GTT"" hides one at *");
1584
Nico Huber2b6f6992017-07-09 18:11:34 +0200[diff] [blame]1585 procedure Set_Register_Base (Base : Word64; GTT_Base : Word64 := 0)
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1586 with
1587 Global => (Output => Address_State),
Nico Huber2b6f6992017-07-09 18:11:34 +0200[diff] [blame]1588 Depends => (Address_State => (Base, GTT_Base)),
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1589 Pre => True,
1590 Post => True;
1591
1592end HW.GFX.GMA.Registers;