gma broxton: Fill in port PLL configuration
PLL parameter selection is a much simplified version of what's done in
i915 on Linux. We just assume the error in the resulting clock of a
valid parameter tuple is always small enough. Trying to speak mathe-
matically, since the only calculated parameter M2 is given as a frac-
tion of 2^22, the error should stay below 2^-22.
As the PLLs are tied to specific DDI ports, they won't ever be shared
among ports and the allocation boils down to just configuring the PLL.
Change-Id: I206675506f1dbbb57d65bfdc308de1891ccbf61a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18423
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads
index cb558d7..84caefc 100644
--- a/common/hw-gfx-gma-registers.ads
+++ b/common/hw-gfx-gma-registers.ads
@@ -106,6 +106,9 @@
WRPLL_CTL_1,
WRPLL_CTL_2,
BXT_DE_PLL_ENABLE,
+ BXT_PORT_PLL_ENABLE_A,
+ BXT_PORT_PLL_ENABLE_B,
+ BXT_PORT_PLL_ENABLE_C,
PORT_CLK_SEL_DDIA,
PORT_CLK_SEL_DDIB,
PORT_CLK_SEL_DDIC,
@@ -245,6 +248,8 @@
BXT_PORT_CL1CM_DW0_BC,
BXT_PORT_CL1CM_DW9_BC,
BXT_PORT_CL1CM_DW10_BC,
+ BXT_PORT_PLL_EBB_0_B,
+ BXT_PORT_PLL_EBB_4_B,
DPLL1_CFGR1,
DPLL1_CFGR2,
DPLL2_CFGR1,
@@ -256,10 +261,32 @@
DPLL_STATUS,
BXT_PORT_CL1CM_DW28_BC,
BXT_PORT_CL1CM_DW30_BC,
+ BXT_PORT_PLL_0_B,
+ BXT_PORT_PLL_1_B,
+ BXT_PORT_PLL_2_B,
+ BXT_PORT_PLL_3_B,
+ BXT_PORT_PLL_6_B,
+ BXT_PORT_PLL_8_B,
+ BXT_PORT_PLL_9_B,
+ BXT_PORT_PLL_10_B,
BXT_PORT_REF_DW3_BC,
BXT_PORT_REF_DW6_BC,
BXT_PORT_REF_DW8_BC,
+ BXT_PORT_PLL_EBB_0_C,
+ BXT_PORT_PLL_EBB_4_C,
BXT_PORT_CL2CM_DW6_BC,
+ BXT_PORT_PLL_0_C,
+ BXT_PORT_PLL_1_C,
+ BXT_PORT_PLL_2_C,
+ BXT_PORT_PLL_3_C,
+ BXT_PORT_PLL_6_C,
+ BXT_PORT_PLL_8_C,
+ BXT_PORT_PLL_9_C,
+ BXT_PORT_PLL_10_C,
+ BXT_PORT_PCS_DW12_01_B,
+ BXT_PORT_PCS_DW12_01_C,
+ BXT_PORT_PCS_DW12_GRP_B,
+ BXT_PORT_PCS_DW12_GRP_C,
BXT_DE_PLL_CTL,
HTOTAL_EDP,
HBLANK_EDP,
@@ -478,11 +505,23 @@
BXT_PORT_CL1CM_DW0_A,
BXT_PORT_CL1CM_DW9_A,
BXT_PORT_CL1CM_DW10_A,
+ BXT_PORT_PLL_EBB_0_A,
+ BXT_PORT_PLL_EBB_4_A,
BXT_PORT_CL1CM_DW28_A,
BXT_PORT_CL1CM_DW30_A,
+ BXT_PORT_PLL_0_A,
+ BXT_PORT_PLL_1_A,
+ BXT_PORT_PLL_2_A,
+ BXT_PORT_PLL_3_A,
+ BXT_PORT_PLL_6_A,
+ BXT_PORT_PLL_8_A,
+ BXT_PORT_PLL_9_A,
+ BXT_PORT_PLL_10_A,
BXT_PORT_REF_DW3_A,
BXT_PORT_REF_DW6_A,
- BXT_PORT_REF_DW8_A);
+ BXT_PORT_REF_DW8_A,
+ BXT_PORT_PCS_DW12_01_A,
+ BXT_PORT_PCS_DW12_GRP_A);
pragma Warnings
(GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)",
@@ -859,6 +898,47 @@
BXT_DE_PLL_CTL => 16#06_d000# / Register_Width,
BXT_DE_PLL_ENABLE => 16#04_6070# / Register_Width,
+ -- Broxton DDI PHY PLL registers
+ BXT_PORT_PLL_ENABLE_A => 16#04_6074# / Register_Width,
+ BXT_PORT_PLL_ENABLE_B => 16#04_6078# / Register_Width,
+ BXT_PORT_PLL_ENABLE_C => 16#04_607c# / Register_Width,
+ BXT_PORT_PLL_EBB_0_A => 16#16_2034# / Register_Width,
+ BXT_PORT_PLL_EBB_4_A => 16#16_2038# / Register_Width,
+ BXT_PORT_PLL_0_A => 16#16_2100# / Register_Width,
+ BXT_PORT_PLL_1_A => 16#16_2104# / Register_Width,
+ BXT_PORT_PLL_2_A => 16#16_2108# / Register_Width,
+ BXT_PORT_PLL_3_A => 16#16_210c# / Register_Width,
+ BXT_PORT_PLL_6_A => 16#16_2118# / Register_Width,
+ BXT_PORT_PLL_8_A => 16#16_2120# / Register_Width,
+ BXT_PORT_PLL_9_A => 16#16_2124# / Register_Width,
+ BXT_PORT_PLL_10_A => 16#16_2128# / Register_Width,
+ BXT_PORT_PCS_DW12_01_A => 16#16_2430# / Register_Width,
+ BXT_PORT_PCS_DW12_GRP_A => 16#16_2c30# / Register_Width,
+ BXT_PORT_PLL_EBB_0_B => 16#06_c034# / Register_Width,
+ BXT_PORT_PLL_EBB_4_B => 16#06_c038# / Register_Width,
+ BXT_PORT_PLL_0_B => 16#06_c100# / Register_Width,
+ BXT_PORT_PLL_1_B => 16#06_c104# / Register_Width,
+ BXT_PORT_PLL_2_B => 16#06_c108# / Register_Width,
+ BXT_PORT_PLL_3_B => 16#06_c10c# / Register_Width,
+ BXT_PORT_PLL_6_B => 16#06_c118# / Register_Width,
+ BXT_PORT_PLL_8_B => 16#06_c120# / Register_Width,
+ BXT_PORT_PLL_9_B => 16#06_c124# / Register_Width,
+ BXT_PORT_PLL_10_B => 16#06_c128# / Register_Width,
+ BXT_PORT_PCS_DW12_01_B => 16#06_c430# / Register_Width,
+ BXT_PORT_PCS_DW12_GRP_B => 16#06_cc30# / Register_Width,
+ BXT_PORT_PLL_EBB_0_C => 16#06_c340# / Register_Width,
+ BXT_PORT_PLL_EBB_4_C => 16#06_c344# / Register_Width,
+ BXT_PORT_PLL_0_C => 16#06_c380# / Register_Width,
+ BXT_PORT_PLL_1_C => 16#06_c384# / Register_Width,
+ BXT_PORT_PLL_2_C => 16#06_c388# / Register_Width,
+ BXT_PORT_PLL_3_C => 16#06_c38c# / Register_Width,
+ BXT_PORT_PLL_6_C => 16#06_c398# / Register_Width,
+ BXT_PORT_PLL_8_C => 16#06_c3a0# / Register_Width,
+ BXT_PORT_PLL_9_C => 16#06_c3a4# / Register_Width,
+ BXT_PORT_PLL_10_C => 16#06_c3a8# / Register_Width,
+ BXT_PORT_PCS_DW12_01_C => 16#06_c830# / Register_Width,
+ BXT_PORT_PCS_DW12_GRP_C => 16#06_ce30# / Register_Width,
+
-- Broxton DDI PHY registers
BXT_P_CR_GT_DISP_PWRON => 16#13_8090# / Register_Width,
BXT_PHY_CTL_A => 16#06_4c00# / Register_Width,