commit 58afc202b1b29898f68f239ec7e50ac532b5d46c
author Nico Huber <nico.huber@secunet.com> Mon Jun 12 21:34:55 2017 +0200
committer Nico Huber <nico.h@gmx.de> Tue Jul 25 20:23:59 2017 +0000
tree bce198ed9feb3b08fdb1412531e0867c139976ad
parent 18ff0c13b740f4153f39dfeb5b9af474bfa13e0a

gma skl: Add I_boost configuration

Hardcoded to 1 since we don't support Skylake-Y (ULX).

Change-Id: I22fa056531cac18828c867f9c9f5745ec424d38c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20168
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

common/hw-gfx-gma-registers.ads

diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads
index ef25770..f3825ea 100644
--- a/common/hw-gfx-gma-registers.ads
+++ b/common/hw-gfx-gma-registers.ads
@@ -346,6 +346,7 @@
       PS_WIN_SZ_1_C,
       PS_CTRL_1_C,
       BXT_PORT_CL1CM_DW0_BC,
+      DISPIO_CR_TX_BMU_CR0,
       BXT_PORT_CL1CM_DW9_BC,
       BXT_PORT_CL1CM_DW10_BC,
       BXT_PORT_PLL_EBB_0_B,
@@ -1109,6 +1110,9 @@
       PORT_CLK_SEL_DDID     => 16#04_610c# / Register_Width,
       PORT_CLK_SEL_DDIE     => 16#04_6110# / Register_Width,
 
+      -- Skylake I_boost configuration
+      DISPIO_CR_TX_BMU_CR0  => 16#06_c00c# / Register_Width,
+
       -- Skylake DPLL registers
       DPLL1_CFGR1           => 16#06_c040# / Register_Width,
       DPLL1_CFGR2           => 16#06_c044# / Register_Width,