gma: Configure cursor plane
Programming the cursor plane registers is straight forward.
On newer hardware, we also have to account for the cursor in GPU
internal buffer allocation. Fortunately, we have enough resources
for a static configuration that always accounts for a cursor.
Cursors with a location that is off limits are placed off-screen
in the top-left corner, hence, are invisible.
Change-Id: I08ffd81d524e14e464af6e6f6fb5effbd4890d8a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/23204
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads
index da100ce..1220d1a 100644
--- a/common/hw-gfx-gma-registers.ads
+++ b/common/hw-gfx-gma-registers.ads
@@ -459,6 +459,19 @@
PIPEA_GMCH_DATA_N,
PIPEA_GMCH_LINK_M,
PIPEA_GMCH_LINK_N,
+ CUR_CTL_A,
+ CUR_BASE_A,
+ CUR_POS_A,
+ CUR_FBC_CTL_A,
+ CUR_WM_A_0,
+ CUR_WM_A_1,
+ CUR_WM_A_2,
+ CUR_WM_A_3,
+ CUR_WM_A_4,
+ CUR_WM_A_5,
+ CUR_WM_A_6,
+ CUR_WM_A_7,
+ CUR_BUF_CFG_A,
DSPACNTR,
DSPALINOFF,
DSPASTRIDE,
@@ -484,6 +497,19 @@
PIPEB_GMCH_DATA_N,
PIPEB_GMCH_LINK_M,
PIPEB_GMCH_LINK_N,
+ CUR_CTL_B,
+ CUR_BASE_B,
+ CUR_POS_B,
+ CUR_FBC_CTL_B,
+ CUR_WM_B_0,
+ CUR_WM_B_1,
+ CUR_WM_B_2,
+ CUR_WM_B_3,
+ CUR_WM_B_4,
+ CUR_WM_B_5,
+ CUR_WM_B_6,
+ CUR_WM_B_7,
+ CUR_BUF_CFG_B,
DSPBCNTR,
DSPBLINOFF,
DSPBSTRIDE,
@@ -506,6 +532,19 @@
PIPECCONF,
PIPECMISC,
PIPE_FRMCNT_C,
+ CUR_CTL_C,
+ CUR_BASE_C,
+ CUR_POS_C,
+ CUR_FBC_CTL_C,
+ CUR_WM_C_0,
+ CUR_WM_C_1,
+ CUR_WM_C_2,
+ CUR_WM_C_3,
+ CUR_WM_C_4,
+ CUR_WM_C_5,
+ CUR_WM_C_6,
+ CUR_WM_C_7,
+ CUR_BUF_CFG_C,
DSPCCNTR,
DSPCLINOFF,
DSPCSTRIDE,
@@ -768,6 +807,12 @@
PS_WIN_SZ_2_A => 16#06_8274# / Register_Width,
PS_CTRL_2_A => 16#06_8280# / Register_Width,
+ -- cursor control
+ CUR_CTL_A => 16#07_0080# / Register_Width,
+ CUR_BASE_A => 16#07_0084# / Register_Width,
+ CUR_POS_A => 16#07_0088# / Register_Width,
+ CUR_FBC_CTL_A => 16#07_00a0# / Register_Width,
+
-- display control
DSPACNTR => 16#07_0180# / Register_Width,
DSPALINOFF => 16#07_0184# / Register_Width,
@@ -801,6 +846,15 @@
PLANE_WM_1_A_6 => 16#07_0258# / Register_Width,
PLANE_WM_1_A_7 => 16#07_025c# / Register_Width,
PLANE_BUF_CFG_1_A => 16#07_027c# / Register_Width,
+ CUR_WM_A_0 => 16#07_0140# / Register_Width,
+ CUR_WM_A_1 => 16#07_0144# / Register_Width,
+ CUR_WM_A_2 => 16#07_0148# / Register_Width,
+ CUR_WM_A_3 => 16#07_014c# / Register_Width,
+ CUR_WM_A_4 => 16#07_0150# / Register_Width,
+ CUR_WM_A_5 => 16#07_0154# / Register_Width,
+ CUR_WM_A_6 => 16#07_0158# / Register_Width,
+ CUR_WM_A_7 => 16#07_015c# / Register_Width,
+ CUR_BUF_CFG_A => 16#07_017c# / Register_Width,
-- CPU transcoder clock select
TRANSA_CLK_SEL => 16#04_6140# / Register_Width,
@@ -862,6 +916,12 @@
PS_WIN_SZ_2_B => 16#06_8a74# / Register_Width,
PS_CTRL_2_B => 16#06_8a80# / Register_Width,
+ -- cursor control
+ CUR_CTL_B => 16#07_1080# / Register_Width,
+ CUR_BASE_B => 16#07_1084# / Register_Width,
+ CUR_POS_B => 16#07_1088# / Register_Width,
+ CUR_FBC_CTL_B => 16#07_10a0# / Register_Width,
+
-- display control
DSPBCNTR => 16#07_1180# / Register_Width,
DSPBLINOFF => 16#07_1184# / Register_Width,
@@ -895,6 +955,15 @@
PLANE_WM_1_B_6 => 16#07_1258# / Register_Width,
PLANE_WM_1_B_7 => 16#07_125c# / Register_Width,
PLANE_BUF_CFG_1_B => 16#07_127c# / Register_Width,
+ CUR_WM_B_0 => 16#07_1140# / Register_Width,
+ CUR_WM_B_1 => 16#07_1144# / Register_Width,
+ CUR_WM_B_2 => 16#07_1148# / Register_Width,
+ CUR_WM_B_3 => 16#07_114c# / Register_Width,
+ CUR_WM_B_4 => 16#07_1150# / Register_Width,
+ CUR_WM_B_5 => 16#07_1154# / Register_Width,
+ CUR_WM_B_6 => 16#07_1158# / Register_Width,
+ CUR_WM_B_7 => 16#07_115c# / Register_Width,
+ CUR_BUF_CFG_B => 16#07_117c# / Register_Width,
-- CPU transcoder clock select
TRANSB_CLK_SEL => 16#04_6144# / Register_Width,
@@ -939,6 +1008,12 @@
PS_WIN_SZ_1_C => 16#06_9174# / Register_Width,
PS_CTRL_1_C => 16#06_9180# / Register_Width,
+ -- cursor control
+ CUR_CTL_C => 16#07_2080# / Register_Width,
+ CUR_BASE_C => 16#07_2084# / Register_Width,
+ CUR_POS_C => 16#07_2088# / Register_Width,
+ CUR_FBC_CTL_C => 16#07_20a0# / Register_Width,
+
-- display control
DSPCCNTR => 16#07_2180# / Register_Width,
DSPCLINOFF => 16#07_2184# / Register_Width,
@@ -972,6 +1047,15 @@
PLANE_WM_1_C_6 => 16#07_2258# / Register_Width,
PLANE_WM_1_C_7 => 16#07_225c# / Register_Width,
PLANE_BUF_CFG_1_C => 16#07_227c# / Register_Width,
+ CUR_WM_C_0 => 16#07_2140# / Register_Width,
+ CUR_WM_C_1 => 16#07_2144# / Register_Width,
+ CUR_WM_C_2 => 16#07_2148# / Register_Width,
+ CUR_WM_C_3 => 16#07_214c# / Register_Width,
+ CUR_WM_C_4 => 16#07_2150# / Register_Width,
+ CUR_WM_C_5 => 16#07_2154# / Register_Width,
+ CUR_WM_C_6 => 16#07_2158# / Register_Width,
+ CUR_WM_C_7 => 16#07_215c# / Register_Width,
+ CUR_BUF_CFG_C => 16#07_217c# / Register_Width,
-- CPU transcoder clock select
TRANSC_CLK_SEL => 16#04_6148# / Register_Width,