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Ollie Lho184a4042005-11-26 21:55:36 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ollie Lho184a4042005-11-26 21:55:36 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
Stefan Reinauer8fa64812009-08-12 09:27:45 +00005 * Copyright (C) 2005-2009 coresystems GmbH
Uwe Hermannd1107642007-08-29 17:52:32 +00006 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00007 * Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger
Adam Jurkowskie4984102009-12-21 15:30:46 +00008 * Copyright (C) 2009 Kontron Modular Computers GmbH
Helge Wagnerdd73d832012-08-24 23:03:46 +00009 * Copyright (C) 2011, 2012 Stefan Tauner
Nico Huber93c30692017-03-20 14:25:09 +010010 * Copyright (C) 2017 secunet Security Networks AG
11 * (Written by Nico Huber <nico.huber@secunet.com> for secunet)
Ollie Lho184a4042005-11-26 21:55:36 +000012 *
Uwe Hermannd1107642007-08-29 17:52:32 +000013 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
Ollie Lho184a4042005-11-26 21:55:36 +000016 *
Uwe Hermannd1107642007-08-29 17:52:32 +000017 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
Uwe Hermannd1107642007-08-29 17:52:32 +000021 */
22
23/*
24 * Contains the chipset specific flash enables.
Ollie Lho184a4042005-11-26 21:55:36 +000025 */
26
Lane Brooksd54958a2007-11-13 16:45:22 +000027#define _LARGEFILE64_SOURCE
28
Felix Singer980d6b82022-08-19 02:48:15 +020029#include <stdbool.h>
Ollie Lhocbbf1252004-03-17 22:22:08 +000030#include <stdlib.h>
Uwe Hermanne8ba5382009-05-22 11:37:27 +000031#include <string.h>
Carl-Daniel Hailfingerdcef67e2010-06-21 23:20:15 +000032#include <unistd.h>
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +000033#include <inttypes.h>
34#include <errno.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000035#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000036#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000037#include "hwaccess.h"
Stefan Reinauer86de2832006-03-31 11:26:55 +000038
Michael Karcher89bed6d2010-06-13 10:16:12 +000039#define NOT_DONE_YET 1
40
Carl-Daniel Hailfinger1d3a2fe2010-07-27 22:03:46 +000041#if defined(__i386__) || defined(__x86_64__)
42
Uwe Hermann372eeb52007-12-04 21:49:06 +000043static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
Luc Verhaegen6b141752007-05-20 16:16:13 +000044{
45 uint8_t tmp;
46
Uwe Hermann372eeb52007-12-04 21:49:06 +000047 /*
48 * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
49 * 0xFFFE0000-0xFFFFFFFF ROM select enable.
50 */
Luc Verhaegen6b141752007-05-20 16:16:13 +000051 tmp = pci_read_byte(dev, 0x47);
52 tmp |= 0x46;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +000053 rpci_write_byte(dev, 0x47, tmp);
Luc Verhaegen6b141752007-05-20 16:16:13 +000054
55 return 0;
56}
57
Rudolf Marek23907d82012-02-07 21:29:48 +000058static int enable_flash_rdc_r8610(struct pci_dev *dev, const char *name)
59{
60 uint8_t tmp;
61
62 /* enable ROMCS for writes */
63 tmp = pci_read_byte(dev, 0x43);
64 tmp |= 0x80;
65 pci_write_byte(dev, 0x43, tmp);
66
67 /* read the bootstrapping register */
68 tmp = pci_read_byte(dev, 0x40) & 0x3;
69 switch (tmp) {
70 case 3:
Nico Huber2e50cdc2018-09-23 20:20:26 +020071 internal_buses_supported &= BUS_FWH;
Rudolf Marek23907d82012-02-07 21:29:48 +000072 break;
73 case 2:
Nico Huber2e50cdc2018-09-23 20:20:26 +020074 internal_buses_supported &= BUS_LPC;
Rudolf Marek23907d82012-02-07 21:29:48 +000075 break;
76 default:
Nico Huber2e50cdc2018-09-23 20:20:26 +020077 internal_buses_supported &= BUS_PARALLEL;
Rudolf Marek23907d82012-02-07 21:29:48 +000078 break;
79 }
80
81 return 0;
82}
83
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000084static int enable_flash_sis85c496(struct pci_dev *dev, const char *name)
85{
86 uint8_t tmp;
87
88 tmp = pci_read_byte(dev, 0xd0);
89 tmp |= 0xf8;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +000090 rpci_write_byte(dev, 0xd0, tmp);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000091
92 return 0;
93}
94
95static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name)
96{
Stefan Taunere34e3e82013-01-01 00:06:51 +000097 #define SIS_MAPREG 0x40
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000098 uint8_t new, newer;
99
100 /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */
101 /* This is 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
Stefan Taunere34e3e82013-01-01 00:06:51 +0000102 new = pci_read_byte(dev, SIS_MAPREG);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000103 new &= (~0x04); /* No idea why we clear bit 2. */
104 new |= 0xb; /* 0x3 for some chipsets, bit 7 seems to be don't care. */
Stefan Taunere34e3e82013-01-01 00:06:51 +0000105 rpci_write_byte(dev, SIS_MAPREG, new);
106 newer = pci_read_byte(dev, SIS_MAPREG);
107 if (newer != new) { /* FIXME: share this with other code? */
108 msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n",
109 SIS_MAPREG, new, name);
110 msg_pinfo("Stuck at 0x%02x.\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000111 return -1;
112 }
113 return 0;
114}
115
116static struct pci_dev *find_southbridge(uint16_t vendor, const char *name)
117{
118 struct pci_dev *sbdev;
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000119
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000120 sbdev = pci_dev_find_vendorclass(vendor, 0x0601);
121 if (!sbdev)
122 sbdev = pci_dev_find_vendorclass(vendor, 0x0680);
123 if (!sbdev)
124 sbdev = pci_dev_find_vendorclass(vendor, 0x0000);
125 if (!sbdev)
Sean Nelson316a29f2010-05-07 20:09:04 +0000126 msg_perr("No southbridge found for %s!\n", name);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000127 if (sbdev)
Sean Nelson316a29f2010-05-07 20:09:04 +0000128 msg_pdbg("Found southbridge %04x:%04x at %02x:%02x:%01x\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000129 sbdev->vendor_id, sbdev->device_id,
130 sbdev->bus, sbdev->dev, sbdev->func);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000131 return sbdev;
132}
133
134static int enable_flash_sis501(struct pci_dev *dev, const char *name)
135{
136 uint8_t tmp;
137 int ret = 0;
138 struct pci_dev *sbdev;
139
140 sbdev = find_southbridge(dev->vendor_id, name);
141 if (!sbdev)
142 return -1;
143
144 ret = enable_flash_sis_mapping(sbdev, name);
145
146 tmp = sio_read(0x22, 0x80);
147 tmp &= (~0x20);
148 tmp |= 0x4;
149 sio_write(0x22, 0x80, tmp);
150
151 tmp = sio_read(0x22, 0x70);
152 tmp &= (~0x20);
153 tmp |= 0x4;
154 sio_write(0x22, 0x70, tmp);
Elyes HAOUAS2f1d0072018-10-04 10:42:42 +0200155
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000156 return ret;
157}
158
159static int enable_flash_sis5511(struct pci_dev *dev, const char *name)
160{
161 uint8_t tmp;
162 int ret = 0;
163 struct pci_dev *sbdev;
164
165 sbdev = find_southbridge(dev->vendor_id, name);
166 if (!sbdev)
167 return -1;
168
169 ret = enable_flash_sis_mapping(sbdev, name);
170
171 tmp = sio_read(0x22, 0x50);
172 tmp &= (~0x20);
173 tmp |= 0x4;
174 sio_write(0x22, 0x50, tmp);
175
176 return ret;
177}
178
Stefan Taunere34e3e82013-01-01 00:06:51 +0000179static int enable_flash_sis5x0(struct pci_dev *dev, const char *name, uint8_t dis_mask, uint8_t en_mask)
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000180{
Stefan Taunere34e3e82013-01-01 00:06:51 +0000181 #define SIS_REG 0x45
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000182 uint8_t new, newer;
183 int ret = 0;
184 struct pci_dev *sbdev;
185
186 sbdev = find_southbridge(dev->vendor_id, name);
187 if (!sbdev)
188 return -1;
189
190 ret = enable_flash_sis_mapping(sbdev, name);
191
Stefan Taunere34e3e82013-01-01 00:06:51 +0000192 new = pci_read_byte(sbdev, SIS_REG);
193 new &= (~dis_mask);
194 new |= en_mask;
195 rpci_write_byte(sbdev, SIS_REG, new);
196 newer = pci_read_byte(sbdev, SIS_REG);
197 if (newer != new) { /* FIXME: share this with other code? */
198 msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", SIS_REG, new, name);
199 msg_pinfo("Stuck at 0x%02x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000200 ret = -1;
201 }
202
203 return ret;
204}
205
Stefan Taunere34e3e82013-01-01 00:06:51 +0000206static int enable_flash_sis530(struct pci_dev *dev, const char *name)
207{
208 return enable_flash_sis5x0(dev, name, 0x20, 0x04);
209}
210
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000211static int enable_flash_sis540(struct pci_dev *dev, const char *name)
212{
Stefan Taunere34e3e82013-01-01 00:06:51 +0000213 return enable_flash_sis5x0(dev, name, 0x80, 0x40);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000214}
215
Uwe Hermann987942d2006-11-07 11:16:21 +0000216/* Datasheet:
217 * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
218 * - URL: http://www.intel.com/design/intarch/datashts/290562.htm
219 * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
220 * - Order Number: 290562-001
221 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000222static int enable_flash_piix4(struct pci_dev *dev, const char *name)
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000223{
224 uint16_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000225 uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000226
Nico Huber2e50cdc2018-09-23 20:20:26 +0200227 internal_buses_supported &= BUS_PARALLEL;
Maciej Pijankaa661e152009-12-08 17:26:24 +0000228
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000229 old = pci_read_word(dev, xbcs);
230
231 /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
Uwe Hermanna7e05482007-05-09 10:17:44 +0000232 * FFF00000-FFF7FFFF are forwarded to ISA).
Uwe Hermannc556d322008-10-28 11:50:05 +0000233 * Note: This bit is reserved on PIIX/PIIX3/MPIIX.
Uwe Hermanna7e05482007-05-09 10:17:44 +0000234 * Set bit 7: Extended BIOS Enable (PCI master accesses to
235 * FFF80000-FFFDFFFF are forwarded to ISA).
236 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
237 * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
238 * of 1 Mbyte, or the aliases at the top of 4 Gbyte
239 * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
240 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
241 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
242 */
Uwe Hermannc556d322008-10-28 11:50:05 +0000243 if (dev->device_id == 0x122e || dev->device_id == 0x7000
244 || dev->device_id == 0x1234)
245 new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */
Uwe Hermann87203452008-10-26 18:40:42 +0000246 else
247 new = old | 0x02c4;
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000248
249 if (new == old)
250 return 0;
251
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000252 rpci_write_word(dev, xbcs, new);
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000253
Stefan Taunere34e3e82013-01-01 00:06:51 +0000254 if (pci_read_word(dev, xbcs) != new) { /* FIXME: share this with other code? */
255 msg_pinfo("Setting register 0x%04x to 0x%04x on %s failed (WARNING ONLY).\n", xbcs, new, name);
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000256 return -1;
257 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000258
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000259 return 0;
260}
261
Duncan Laurie4095ed72014-08-20 15:39:32 +0000262/* Handle BIOS_CNTL (aka. BCR). Disable locks and enable writes. The register can either be in PCI config space
263 * at the offset given by 'bios_cntl' or at the memory-mapped address 'addr'.
264 *
265 * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, in Poulsbo, Tunnel Creek and other Atom
Stefan Tauner92d6a862013-10-25 00:33:37 +0000266 * chipsets/SoCs it is even 32b, but just treating it as 8 bit wide seems to work fine in practice. */
Duncan Laurie4095ed72014-08-20 15:39:32 +0000267static int enable_flash_ich_bios_cntl_common(enum ich_chipset ich_generation, void *addr,
268 struct pci_dev *dev, uint8_t bios_cntl)
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000269{
Stefan Taunerd5c4ab42011-09-09 12:46:32 +0000270 uint8_t old, new, wanted;
Stefan Reinauereb366472006-09-06 15:48:48 +0000271
Stefan Tauner92d6a862013-10-25 00:33:37 +0000272 switch (ich_generation) {
273 case CHIPSET_ICH_UNKNOWN:
274 return ERROR_FATAL;
275 /* Non-SPI-capable */
276 case CHIPSET_ICH:
277 case CHIPSET_ICH2345:
278 break;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000279 /* Some Atom chipsets are special: The second byte of BIOS_CNTL (D9h) contains a prefetch bit similar to
280 * what other SPI-capable chipsets have at DCh. Others like Bay Trail use a memmapped register.
Stefan Tauner92d6a862013-10-25 00:33:37 +0000281 * The Tunnel Creek datasheet contains a lot of details about the SPI controller, among other things it
282 * mentions that the prefetching and caching does only happen for direct memory reads.
283 * Therefore - at least for Tunnel Creek - it should not matter to flashrom because we use the
284 * programmed access only and not memory mapping. */
285 case CHIPSET_TUNNEL_CREEK:
286 case CHIPSET_POULSBO:
287 case CHIPSET_CENTERTON:
288 old = pci_read_byte(dev, bios_cntl + 1);
289 msg_pdbg("BIOS Prefetch Enable: %sabled, ", (old & 1) ? "en" : "dis");
290 break;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000291 case CHIPSET_BAYTRAIL:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000292 case CHIPSET_ICH7:
293 default: /* Future version might behave the same */
Duncan Laurie4095ed72014-08-20 15:39:32 +0000294 if (ich_generation == CHIPSET_BAYTRAIL)
295 old = (mmio_readl(addr) >> 2) & 0x3;
296 else
297 old = (pci_read_byte(dev, bios_cntl) >> 2) & 0x3;
Stefan Tauner92d6a862013-10-25 00:33:37 +0000298 msg_pdbg("SPI Read Configuration: ");
299 if (old == 3)
300 msg_pdbg("invalid prefetching/caching settings, ");
301 else
302 msg_pdbg("prefetching %sabled, caching %sabled, ",
303 (old & 0x2) ? "en" : "dis",
304 (old & 0x1) ? "dis" : "en");
305 }
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000306
Duncan Laurie4095ed72014-08-20 15:39:32 +0000307 if (ich_generation == CHIPSET_BAYTRAIL)
308 wanted = old = mmio_readl(addr);
309 else
310 wanted = old = pci_read_byte(dev, bios_cntl);
311
Stefan Taunerf9a8da52011-06-11 18:16:50 +0000312 /*
313 * Quote from the 6 Series datasheet (Document Number: 324645-004):
314 * "Bit 5: SMM BIOS Write Protect Disable (SMM_BWP)
315 * 1 = BIOS region SMM protection is enabled.
316 * The BIOS Region is not writable unless all processors are in SMM."
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000317 * In earlier chipsets this bit is reserved.
Stefan Reinauer62218c32012-08-26 02:35:13 +0000318 *
319 * Try to unset it in any case.
320 * It won't hurt and makes sense in some cases according to Stefan Reinauer.
Stefan Tauner92d6a862013-10-25 00:33:37 +0000321 *
322 * At least in Centerton aforementioned bit is located at bit 7. It is unspecified in all other Atom
323 * and Desktop chipsets before Ibex Peak/5 Series, but we reset bit 5 anyway.
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000324 */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000325 int smm_bwp_bit;
326 if (ich_generation == CHIPSET_CENTERTON)
327 smm_bwp_bit = 7;
328 else
329 smm_bwp_bit = 5;
330 wanted &= ~(1 << smm_bwp_bit);
Stefan Reinauer62218c32012-08-26 02:35:13 +0000331
Stefan Tauner92d6a862013-10-25 00:33:37 +0000332 /* Tunnel Creek has a cache disable at bit 2 of the lowest BIOS_CNTL byte. */
333 if (ich_generation == CHIPSET_TUNNEL_CREEK)
334 wanted |= (1 << 2);
335
336 wanted |= (1 << 0); /* Set BIOS Write Enable */
337 wanted &= ~(1 << 1); /* Disable lock (futile) */
Stefan Reinauer62218c32012-08-26 02:35:13 +0000338
339 /* Only write the register if it's necessary */
340 if (wanted != old) {
Duncan Laurie4095ed72014-08-20 15:39:32 +0000341 if (ich_generation == CHIPSET_BAYTRAIL) {
342 rmmio_writel(wanted, addr);
343 new = mmio_readl(addr);
344 } else {
345 rpci_write_byte(dev, bios_cntl, wanted);
346 new = pci_read_byte(dev, bios_cntl);
347 }
Stefan Reinauer62218c32012-08-26 02:35:13 +0000348 } else
349 new = old;
350
351 msg_pdbg("\nBIOS_CNTL = 0x%02x: ", new);
352 msg_pdbg("BIOS Lock Enable: %sabled, ", (new & (1 << 1)) ? "en" : "dis");
353 msg_pdbg("BIOS Write Enable: %sabled\n", (new & (1 << 0)) ? "en" : "dis");
Stefan Tauner92d6a862013-10-25 00:33:37 +0000354 if (new & (1 << smm_bwp_bit))
Stefan Taunerc6fa32d2013-01-04 22:54:07 +0000355 msg_pwarn("Warning: BIOS region SMM protection is enabled!\n");
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000356
Stefan Reinauer62218c32012-08-26 02:35:13 +0000357 if (new != wanted)
Angel Ponsabefc462020-04-29 15:23:59 +0200358 msg_pwarn("Warning: Setting BIOS Control at 0x%x from 0x%02x to 0x%02x failed.\n"
Stefan Tauner92d6a862013-10-25 00:33:37 +0000359 "New value is 0x%02x.\n", bios_cntl, old, wanted, new);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000360
Stefan Tauner92d6a862013-10-25 00:33:37 +0000361 /* Return an error if we could not set the write enable only. */
Stefan Reinauer62218c32012-08-26 02:35:13 +0000362 if (!(new & (1 << 0)))
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000363 return -1;
Uwe Hermannffec5f32007-08-23 16:08:21 +0000364
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000365 return 0;
366}
367
Duncan Laurie4095ed72014-08-20 15:39:32 +0000368static int enable_flash_ich_bios_cntl_config_space(struct pci_dev *dev, enum ich_chipset ich_generation,
369 uint8_t bios_cntl)
370{
371 return enable_flash_ich_bios_cntl_common(ich_generation, NULL, dev, bios_cntl);
372}
373
374static int enable_flash_ich_bios_cntl_memmapped(enum ich_chipset ich_generation, void *addr)
375{
376 return enable_flash_ich_bios_cntl_common(ich_generation, addr, NULL, 0);
377}
378
Stefan Tauner92d6a862013-10-25 00:33:37 +0000379static int enable_flash_ich_fwh_decode(struct pci_dev *dev, enum ich_chipset ich_generation)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000380{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000381 uint8_t fwh_sel1 = 0, fwh_sel2 = 0, fwh_dec_en_lo = 0, fwh_dec_en_hi = 0; /* silence compilers */
382 bool implemented = 0;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000383 void *ilb = NULL; /* Only for Baytrail */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000384 switch (ich_generation) {
385 case CHIPSET_ICH:
386 /* FIXME: Unlike later chipsets, ICH and ICH-0 do only support mapping of the top-most 4MB
387 * and therefore do only feature FWH_DEC_EN (E3h, different default too) and FWH_SEL (E8h). */
388 break;
389 case CHIPSET_ICH2345:
Kyösti Mälkki88ee0402013-09-14 23:37:01 +0000390 fwh_sel1 = 0xe8;
391 fwh_sel2 = 0xee;
392 fwh_dec_en_lo = 0xf0;
393 fwh_dec_en_hi = 0xe3;
Stefan Tauner92d6a862013-10-25 00:33:37 +0000394 implemented = 1;
395 break;
396 case CHIPSET_POULSBO:
397 case CHIPSET_TUNNEL_CREEK:
398 /* FIXME: Similar to ICH and ICH-0, Tunnel Creek and Poulsbo do only feature one register each,
399 * FWH_DEC_EN (D7h) and FWH_SEL (D0h). */
400 break;
401 case CHIPSET_CENTERTON:
402 /* FIXME: Similar to above FWH_DEC_EN (D4h) and FWH_SEL (D0h). */
403 break;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000404 case CHIPSET_BAYTRAIL: {
405 uint32_t ilb_base = pci_read_long(dev, 0x50) & 0xfffffe00; /* bits 31:9 */
406 if (ilb_base == 0) {
407 msg_perr("Error: Invalid ILB_BASE_ADDRESS\n");
408 return ERROR_FATAL;
409 }
410 ilb = rphysmap("BYT IBASE", ilb_base, 512);
411 fwh_sel1 = 0x18;
412 fwh_dec_en_lo = 0xd8;
413 fwh_dec_en_hi = 0xd9;
414 implemented = 1;
415 break;
416 }
Stefan Tauner92d6a862013-10-25 00:33:37 +0000417 case CHIPSET_ICH6:
418 case CHIPSET_ICH7:
419 default: /* Future version might behave the same */
420 fwh_sel1 = 0xd0;
421 fwh_sel2 = 0xd4;
422 fwh_dec_en_lo = 0xd8;
423 fwh_dec_en_hi = 0xd9;
424 implemented = 1;
425 break;
Kyösti Mälkki88ee0402013-09-14 23:37:01 +0000426 }
Kyösti Mälkki743babc2013-09-14 23:36:53 +0000427
Stefan Tauner92d6a862013-10-25 00:33:37 +0000428 char *idsel = extract_programmer_param("fwh_idsel");
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000429 if (idsel && strlen(idsel)) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000430 if (!implemented) {
431 msg_perr("Error: fwh_idsel= specified, but (yet) unsupported on this chipset.\n");
432 goto idsel_garbage_out;
433 }
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000434 errno = 0;
435 /* Base 16, nothing else makes sense. */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000436 uint64_t fwh_idsel = (uint64_t)strtoull(idsel, NULL, 16);
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000437 if (errno) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000438 msg_perr("Error: fwh_idsel= specified, but value could not be converted.\n");
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000439 goto idsel_garbage_out;
440 }
Duncan Laurie4095ed72014-08-20 15:39:32 +0000441 uint64_t fwh_mask = 0xffffffff;
442 if (fwh_sel2 > 0)
443 fwh_mask |= (0xffffULL << 32);
444 if (fwh_idsel & ~fwh_mask) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000445 msg_perr("Error: fwh_idsel= specified, but value had unused bits set.\n");
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000446 goto idsel_garbage_out;
447 }
Duncan Laurie4095ed72014-08-20 15:39:32 +0000448 uint64_t fwh_idsel_old;
449 if (ich_generation == CHIPSET_BAYTRAIL) {
450 fwh_idsel_old = mmio_readl(ilb + fwh_sel1);
451 rmmio_writel(fwh_idsel, ilb + fwh_sel1);
452 } else {
Stefan Tauner5c316f92015-02-08 21:57:52 +0000453 fwh_idsel_old = (uint64_t)pci_read_long(dev, fwh_sel1) << 16;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000454 rpci_write_long(dev, fwh_sel1, (fwh_idsel >> 16) & 0xffffffff);
455 if (fwh_sel2 > 0) {
456 fwh_idsel_old |= pci_read_word(dev, fwh_sel2);
457 rpci_write_word(dev, fwh_sel2, fwh_idsel & 0xffff);
458 }
459 }
Stefan Taunereff156e2014-07-13 17:06:11 +0000460 msg_pdbg("Setting IDSEL from 0x%012" PRIx64 " to 0x%012" PRIx64 " for top 16 MB.\n",
Stefan Tauner92d6a862013-10-25 00:33:37 +0000461 fwh_idsel_old, fwh_idsel);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000462 /* FIXME: Decode settings are not changed. */
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000463 } else if (idsel) {
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000464 msg_perr("Error: fwh_idsel= specified, but no value given.\n");
Sylvain "ythier" Hitier3093f8f2011-09-03 11:22:27 +0000465idsel_garbage_out:
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000466 free(idsel);
Tadas Slotkus0e3f1cf2011-09-06 18:49:31 +0000467 return ERROR_FATAL;
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000468 }
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000469 free(idsel);
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000470
Stefan Tauner92d6a862013-10-25 00:33:37 +0000471 if (!implemented) {
Stefan Taunereff156e2014-07-13 17:06:11 +0000472 msg_pdbg2("FWH IDSEL handling is not implemented on this chipset.\n");
Stefan Tauner92d6a862013-10-25 00:33:37 +0000473 return 0;
474 }
475
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000476 /* Ignore all legacy ranges below 1 MB.
477 * We currently only support flashing the chip which responds to
478 * IDSEL=0. To support IDSEL!=0, flashbase and decode size calculations
479 * have to be adjusted.
480 */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000481 int max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0;
482 bool contiguous = 1;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000483 uint32_t fwh_conf;
484 if (ich_generation == CHIPSET_BAYTRAIL)
485 fwh_conf = mmio_readl(ilb + fwh_sel1);
486 else
487 fwh_conf = pci_read_long(dev, fwh_sel1);
488
Stefan Tauner92d6a862013-10-25 00:33:37 +0000489 int i;
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000490 /* FWH_SEL1 */
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000491 for (i = 7; i >= 0; i--) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000492 int tmp = (fwh_conf >> (i * 4)) & 0xf;
Stefan Taunereff156e2014-07-13 17:06:11 +0000493 msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000494 (0x1ff8 + i) * 0x80000,
495 (0x1ff0 + i) * 0x80000,
496 tmp);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000497 if ((tmp == 0) && contiguous) {
498 max_decode_fwh_idsel = (8 - i) * 0x80000;
499 } else {
500 contiguous = 0;
501 }
502 }
Duncan Laurie4095ed72014-08-20 15:39:32 +0000503 if (fwh_sel2 > 0) {
504 /* FWH_SEL2 */
505 fwh_conf = pci_read_word(dev, fwh_sel2);
506 for (i = 3; i >= 0; i--) {
507 int tmp = (fwh_conf >> (i * 4)) & 0xf;
508 msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n",
509 (0xff4 + i) * 0x100000,
510 (0xff0 + i) * 0x100000,
511 tmp);
512 if ((tmp == 0) && contiguous) {
513 max_decode_fwh_idsel = (8 - i) * 0x100000;
514 } else {
515 contiguous = 0;
516 }
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000517 }
518 }
519 contiguous = 1;
520 /* FWH_DEC_EN1 */
Kyösti Mälkki743babc2013-09-14 23:36:53 +0000521 fwh_conf = pci_read_byte(dev, fwh_dec_en_hi);
522 fwh_conf <<= 8;
523 fwh_conf |= pci_read_byte(dev, fwh_dec_en_lo);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000524 for (i = 7; i >= 0; i--) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000525 int tmp = (fwh_conf >> (i + 0x8)) & 0x1;
Stefan Taunereff156e2014-07-13 17:06:11 +0000526 msg_pdbg("0x%08x/0x%08x FWH decode %sabled\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000527 (0x1ff8 + i) * 0x80000,
528 (0x1ff0 + i) * 0x80000,
529 tmp ? "en" : "dis");
Michael Karcher96785392010-01-03 15:09:17 +0000530 if ((tmp == 1) && contiguous) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000531 max_decode_fwh_decode = (8 - i) * 0x80000;
532 } else {
533 contiguous = 0;
534 }
535 }
536 for (i = 3; i >= 0; i--) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000537 int tmp = (fwh_conf >> i) & 0x1;
Stefan Taunereff156e2014-07-13 17:06:11 +0000538 msg_pdbg("0x%08x/0x%08x FWH decode %sabled\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000539 (0xff4 + i) * 0x100000,
540 (0xff0 + i) * 0x100000,
541 tmp ? "en" : "dis");
Michael Karcher96785392010-01-03 15:09:17 +0000542 if ((tmp == 1) && contiguous) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000543 max_decode_fwh_decode = (8 - i) * 0x100000;
544 } else {
545 contiguous = 0;
546 }
547 }
548 max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode);
Stefan Taunereff156e2014-07-13 17:06:11 +0000549 msg_pdbg("Maximum FWH chip size: 0x%x bytes\n", max_rom_decode.fwh);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000550
Kyösti Mälkki743babc2013-09-14 23:36:53 +0000551 return 0;
552}
553
Stefan Tauner92d6a862013-10-25 00:33:37 +0000554static int enable_flash_ich_fwh(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl)
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000555{
Kyösti Mälkki88ee0402013-09-14 23:37:01 +0000556 int err;
557
558 /* Configure FWH IDSEL decoder maps. */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000559 if ((err = enable_flash_ich_fwh_decode(dev, ich_generation)) != 0)
Kyösti Mälkki88ee0402013-09-14 23:37:01 +0000560 return err;
561
Nico Huber2e50cdc2018-09-23 20:20:26 +0200562 internal_buses_supported &= BUS_FWH;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000563 return enable_flash_ich_bios_cntl_config_space(dev, ich_generation, bios_cntl);
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000564}
565
Stefan Tauner92d6a862013-10-25 00:33:37 +0000566static int enable_flash_ich0(struct pci_dev *dev, const char *name)
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000567{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000568 return enable_flash_ich_fwh(dev, CHIPSET_ICH, 0x4e);
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000569}
570
Stefan Tauner92d6a862013-10-25 00:33:37 +0000571static int enable_flash_ich2345(struct pci_dev *dev, const char *name)
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000572{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000573 return enable_flash_ich_fwh(dev, CHIPSET_ICH2345, 0x4e);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000574}
575
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000576static int enable_flash_ich6(struct pci_dev *dev, const char *name)
577{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000578 return enable_flash_ich_fwh(dev, CHIPSET_ICH6, 0xdc);
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000579}
580
Adam Jurkowskie4984102009-12-21 15:30:46 +0000581static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
582{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000583 return enable_flash_ich_fwh(dev, CHIPSET_POULSBO, 0xd8);
Adam Jurkowskie4984102009-12-21 15:30:46 +0000584}
585
Nico Huber2e50cdc2018-09-23 20:20:26 +0200586static enum chipbustype enable_flash_ich_report_gcs(
587 struct pci_dev *const dev, const enum ich_chipset ich_generation, const uint8_t *const rcrb)
Ingo Feldschmiddadc0a62011-09-07 19:18:25 +0000588{
Nico Huber0ea99f52017-03-17 17:22:53 +0100589 uint32_t gcs;
Nico Huber93c30692017-03-20 14:25:09 +0100590 const char *reg_name;
591 bool bild, top_swap;
Nico Huber0ea99f52017-03-17 17:22:53 +0100592
593 switch (ich_generation) {
594 case CHIPSET_BAYTRAIL:
Nico Huber93c30692017-03-20 14:25:09 +0100595 reg_name = "GCS";
Nico Huber0ea99f52017-03-17 17:22:53 +0100596 gcs = mmio_readl(rcrb + 0);
Nico Huber93c30692017-03-20 14:25:09 +0100597 bild = gcs & 1;
Nico Huber0ea99f52017-03-17 17:22:53 +0100598 top_swap = (gcs & 2) >> 1;
599 break;
Nico Huber93c30692017-03-20 14:25:09 +0100600 case CHIPSET_100_SERIES_SUNRISE_POINT:
David Hendricksa5216362017-08-08 20:02:22 -0700601 case CHIPSET_C620_SERIES_LEWISBURG:
Thomas Heijligen5ec84b32019-03-19 17:00:03 +0100602 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +0200603 case CHIPSET_500_SERIES_TIGER_POINT:
Werner Zehe57d4e42022-01-03 09:44:29 +0100604 case CHIPSET_ELKHART_LAKE:
Nico Huber37509862019-01-18 14:23:02 +0100605 case CHIPSET_APOLLO_LAKE:
Angel Pons4db0fdf2020-07-10 17:04:10 +0200606 case CHIPSET_GEMINI_LAKE:
Nico Huber93c30692017-03-20 14:25:09 +0100607 reg_name = "BIOS_SPI_BC";
608 gcs = pci_read_long(dev, 0xdc);
609 bild = (gcs >> 7) & 1;
610 top_swap = (gcs >> 4) & 1;
611 break;
Nico Huber0ea99f52017-03-17 17:22:53 +0100612 default:
Nico Huber93c30692017-03-20 14:25:09 +0100613 reg_name = "GCS";
Nico Huber0ea99f52017-03-17 17:22:53 +0100614 gcs = mmio_readl(rcrb + 0x3410);
Nico Huber93c30692017-03-20 14:25:09 +0100615 bild = gcs & 1;
Nico Huber0ea99f52017-03-17 17:22:53 +0100616 top_swap = mmio_readb(rcrb + 0x3414) & 1;
617 break;
618 }
619
Nico Huber93c30692017-03-20 14:25:09 +0100620 msg_pdbg("%s = 0x%x: ", reg_name, gcs);
621 msg_pdbg("BIOS Interface Lock-Down: %sabled, ", bild ? "en" : "dis");
Duncan Laurie4095ed72014-08-20 15:39:32 +0000622
Nico Huber2e50cdc2018-09-23 20:20:26 +0200623 struct boot_straps {
624 const char *name;
625 enum chipbustype bus;
626 };
627 static const struct boot_straps boot_straps_EP80579[] =
628 { { "SPI", BUS_SPI },
Nico Hubera508ca02019-07-24 19:34:43 +0200629 { "reserved", BUS_NONE },
630 { "reserved", BUS_NONE },
Nico Huber2e50cdc2018-09-23 20:20:26 +0200631 { "LPC", BUS_LPC | BUS_FWH } };
632 static const struct boot_straps boot_straps_ich7_nm10[] =
Nico Hubera508ca02019-07-24 19:34:43 +0200633 { { "reserved", BUS_NONE },
Nico Huber2e50cdc2018-09-23 20:20:26 +0200634 { "SPI", BUS_SPI },
Nico Hubera508ca02019-07-24 19:34:43 +0200635 { "PCI", BUS_NONE },
Nico Huber2e50cdc2018-09-23 20:20:26 +0200636 { "LPC", BUS_LPC | BUS_FWH } };
637 static const struct boot_straps boot_straps_tunnel_creek[] =
638 { { "SPI", BUS_SPI },
639 { "LPC", BUS_LPC | BUS_FWH } };
640 static const struct boot_straps boot_straps_ich8910[] =
641 { { "SPI", BUS_SPI },
642 { "SPI", BUS_SPI },
Nico Hubera508ca02019-07-24 19:34:43 +0200643 { "PCI", BUS_NONE },
Nico Huber2e50cdc2018-09-23 20:20:26 +0200644 { "LPC", BUS_LPC | BUS_FWH } };
645 static const struct boot_straps boot_straps_pch567[] =
646 { { "LPC", BUS_LPC | BUS_FWH },
Nico Hubera508ca02019-07-24 19:34:43 +0200647 { "reserved", BUS_NONE },
648 { "PCI", BUS_NONE },
Nico Huber2e50cdc2018-09-23 20:20:26 +0200649 { "SPI", BUS_SPI } };
650 static const struct boot_straps boot_straps_pch89_baytrail[] =
651 { { "LPC", BUS_LPC | BUS_FWH },
Nico Hubera508ca02019-07-24 19:34:43 +0200652 { "reserved", BUS_NONE },
653 { "reserved", BUS_NONE },
Nico Huber2e50cdc2018-09-23 20:20:26 +0200654 { "SPI", BUS_SPI } };
655 static const struct boot_straps boot_straps_pch8_lp[] =
656 { { "SPI", BUS_SPI },
657 { "LPC", BUS_LPC | BUS_FWH } };
Michał Żygowski5c9f5422021-06-16 15:13:54 +0200658 static const struct boot_straps boot_straps_pch500[] =
659 { { "SPI", BUS_SPI },
660 { "eSPI", BUS_NONE } };
Nico Huber37509862019-01-18 14:23:02 +0100661 static const struct boot_straps boot_straps_apl[] =
662 { { "SPI", BUS_SPI },
Nico Hubera508ca02019-07-24 19:34:43 +0200663 { "reserved", BUS_NONE } };
Nico Huber2e50cdc2018-09-23 20:20:26 +0200664 static const struct boot_straps boot_straps_unknown[] =
Nico Hubera508ca02019-07-24 19:34:43 +0200665 { { "unknown", BUS_NONE },
666 { "unknown", BUS_NONE },
667 { "unknown", BUS_NONE },
668 { "unknown", BUS_NONE } };
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000669
Nico Huber2e50cdc2018-09-23 20:20:26 +0200670 const struct boot_straps *boot_straps;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000671 switch (ich_generation) {
Stefan Taunera8d838d2011-11-06 23:51:09 +0000672 case CHIPSET_ICH7:
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000673 /* EP80579 may need further changes, but this is the least
674 * intrusive way to get correct BOOT Strap printing without
675 * changing the rest of its code path). */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000676 if (dev->device_id == 0x5031)
Nico Huber2e50cdc2018-09-23 20:20:26 +0200677 boot_straps = boot_straps_EP80579;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000678 else
Nico Huber2e50cdc2018-09-23 20:20:26 +0200679 boot_straps = boot_straps_ich7_nm10;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000680 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000681 case CHIPSET_ICH8:
682 case CHIPSET_ICH9:
683 case CHIPSET_ICH10:
Nico Huber2e50cdc2018-09-23 20:20:26 +0200684 boot_straps = boot_straps_ich8910;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000685 break;
Stefan Tauner92d6a862013-10-25 00:33:37 +0000686 case CHIPSET_TUNNEL_CREEK:
Nico Huber2e50cdc2018-09-23 20:20:26 +0200687 boot_straps = boot_straps_tunnel_creek;
Stefan Tauner92d6a862013-10-25 00:33:37 +0000688 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000689 case CHIPSET_5_SERIES_IBEX_PEAK:
690 case CHIPSET_6_SERIES_COUGAR_POINT:
Helge Wagnera0fce5f2012-07-24 16:33:55 +0000691 case CHIPSET_7_SERIES_PANTHER_POINT:
Nico Huber2e50cdc2018-09-23 20:20:26 +0200692 boot_straps = boot_straps_pch567;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000693 break;
Duncan Laurie90eb2262013-03-15 03:12:29 +0000694 case CHIPSET_8_SERIES_LYNX_POINT:
Duncan Laurie823096e2014-08-20 15:39:38 +0000695 case CHIPSET_9_SERIES_WILDCAT_POINT:
Duncan Laurie4095ed72014-08-20 15:39:32 +0000696 case CHIPSET_BAYTRAIL:
Nico Huber2e50cdc2018-09-23 20:20:26 +0200697 boot_straps = boot_straps_pch89_baytrail;
Duncan Laurie90eb2262013-03-15 03:12:29 +0000698 break;
699 case CHIPSET_8_SERIES_LYNX_POINT_LP:
Nico Huber51205912017-03-17 17:59:54 +0100700 case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
Nico Huber93c30692017-03-20 14:25:09 +0100701 case CHIPSET_100_SERIES_SUNRISE_POINT:
David Hendricksa5216362017-08-08 20:02:22 -0700702 case CHIPSET_C620_SERIES_LEWISBURG:
Thomas Heijligen5ec84b32019-03-19 17:00:03 +0100703 case CHIPSET_300_SERIES_CANNON_POINT:
Nico Huber2e50cdc2018-09-23 20:20:26 +0200704 boot_straps = boot_straps_pch8_lp;
Duncan Laurie90eb2262013-03-15 03:12:29 +0000705 break;
Michał Żygowski5c9f5422021-06-16 15:13:54 +0200706 case CHIPSET_500_SERIES_TIGER_POINT:
707 boot_straps = boot_straps_pch500;
708 break;
Nico Huber37509862019-01-18 14:23:02 +0100709 case CHIPSET_APOLLO_LAKE:
Angel Pons4db0fdf2020-07-10 17:04:10 +0200710 case CHIPSET_GEMINI_LAKE:
Werner Zehe57d4e42022-01-03 09:44:29 +0100711 case CHIPSET_ELKHART_LAKE:
Nico Huber37509862019-01-18 14:23:02 +0100712 boot_straps = boot_straps_apl;
713 break;
Duncan Laurie90eb2262013-03-15 03:12:29 +0000714 case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet
Stefan Tauner92d6a862013-10-25 00:33:37 +0000715 case CHIPSET_CENTERTON: // FIXME: Datasheet does not mention GCS at all
Nico Huber2e50cdc2018-09-23 20:20:26 +0200716 boot_straps = boot_straps_unknown;
Duncan Laurie90eb2262013-03-15 03:12:29 +0000717 break;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000718 default:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000719 msg_gerr("%s: unknown ICH generation. Please report!\n", __func__);
Nico Huber2e50cdc2018-09-23 20:20:26 +0200720 boot_straps = boot_straps_unknown;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000721 break;
722 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000723
Duncan Laurie4095ed72014-08-20 15:39:32 +0000724 uint8_t bbs;
725 switch (ich_generation) {
726 case CHIPSET_TUNNEL_CREEK:
727 bbs = (gcs >> 1) & 0x1;
728 break;
729 case CHIPSET_8_SERIES_LYNX_POINT_LP:
Nico Huber51205912017-03-17 17:59:54 +0100730 case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
731 /* LP PCHs use a single bit for BBS */
Duncan Laurie4095ed72014-08-20 15:39:32 +0000732 bbs = (gcs >> 10) & 0x1;
733 break;
Nico Huber93c30692017-03-20 14:25:09 +0100734 case CHIPSET_100_SERIES_SUNRISE_POINT:
David Hendricksa5216362017-08-08 20:02:22 -0700735 case CHIPSET_C620_SERIES_LEWISBURG:
Thomas Heijligen5ec84b32019-03-19 17:00:03 +0100736 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +0200737 case CHIPSET_500_SERIES_TIGER_POINT:
Nico Huber37509862019-01-18 14:23:02 +0100738 case CHIPSET_APOLLO_LAKE:
Angel Pons4db0fdf2020-07-10 17:04:10 +0200739 case CHIPSET_GEMINI_LAKE:
Werner Zehe57d4e42022-01-03 09:44:29 +0100740 case CHIPSET_ELKHART_LAKE:
Nico Huber93c30692017-03-20 14:25:09 +0100741 bbs = (gcs >> 6) & 0x1;
742 break;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000743 default:
744 /* Other chipsets use two bits for BBS */
745 bbs = (gcs >> 10) & 0x3;
746 break;
747 }
Nico Huber2e50cdc2018-09-23 20:20:26 +0200748 msg_pdbg("Boot BIOS Straps: 0x%x (%s)\n", bbs, boot_straps[bbs].name);
Duncan Laurie4095ed72014-08-20 15:39:32 +0000749
750 /* Centerton has its TS bit in [GPE0BLK] + 0x30 while the exact location for Tunnel Creek is unknown. */
751 if (ich_generation != CHIPSET_TUNNEL_CREEK && ich_generation != CHIPSET_CENTERTON)
752 msg_pdbg("Top Swap: %s\n", (top_swap) ? "enabled (A16(+) inverted)" : "not enabled");
Nico Huber2e50cdc2018-09-23 20:20:26 +0200753
754 return boot_straps[bbs].bus;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000755}
756
757static int enable_flash_ich_spi(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl)
758{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000759 /* Get physical address of Root Complex Register Block */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000760 uint32_t rcra = pci_read_long(dev, 0xf0) & 0xffffc000;
761 msg_pdbg("Root Complex Register Block address = 0x%x\n", rcra);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000762
763 /* Map RCBA to virtual memory */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000764 void *rcrb = rphysmap("ICH RCRB", rcra, 0x4000);
Stefan Tauner7fb5aa02013-08-14 15:48:44 +0000765 if (rcrb == ERROR_PTR)
Niklas Söderlund5d307202013-09-14 09:02:27 +0000766 return ERROR_FATAL;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000767
Nico Huber2e50cdc2018-09-23 20:20:26 +0200768 const enum chipbustype boot_buses = enable_flash_ich_report_gcs(dev, ich_generation, rcrb);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000769
Stefan Tauner92d6a862013-10-25 00:33:37 +0000770 /* Handle FWH-related parameters and initialization */
771 int ret_fwh = enable_flash_ich_fwh(dev, ich_generation, bios_cntl);
772 if (ret_fwh == ERROR_FATAL)
773 return ret_fwh;
774
Angel Pons399a4dd2020-04-15 12:59:42 +0200775 /*
776 * It seems that the ICH7 does not support SPI and LPC chips at the same time. When booted
777 * from LPC, the SCIP bit will never clear, which causes long delays and many error messages.
778 * To avoid this, we will not enable SPI on ICH7 when the southbridge is strapped to LPC.
779 */
780 if (ich_generation == CHIPSET_ICH7 && (boot_buses & BUS_LPC))
781 return 0;
782
Stefan Tauner92d6a862013-10-25 00:33:37 +0000783 /* SPIBAR is at RCRB+0x3020 for ICH[78], Tunnel Creek and Centerton, and RCRB+0x3800 for ICH9. */
784 uint16_t spibar_offset;
785 switch (ich_generation) {
Duncan Laurie4095ed72014-08-20 15:39:32 +0000786 case CHIPSET_BAYTRAIL:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000787 case CHIPSET_ICH_UNKNOWN:
788 return ERROR_FATAL;
789 case CHIPSET_ICH7:
790 case CHIPSET_ICH8:
791 case CHIPSET_TUNNEL_CREEK:
792 case CHIPSET_CENTERTON:
793 spibar_offset = 0x3020;
794 break;
795 case CHIPSET_ICH9:
796 default: /* Future version might behave the same */
797 spibar_offset = 0x3800;
798 break;
799 }
800 msg_pdbg("SPIBAR = 0x%0*" PRIxPTR " + 0x%04x\n", PRIxPTR_WIDTH, (uintptr_t)rcrb, spibar_offset);
801 void *spibar = rcrb + spibar_offset;
802
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000803 /* This adds BUS_SPI */
Nico Huber560111e2017-04-26 12:27:17 +0200804 int ret_spi = ich_init_spi(spibar, ich_generation);
Stefan Tauner50e7c602011-11-08 10:55:54 +0000805 if (ret_spi == ERROR_FATAL)
806 return ret_spi;
Elyes HAOUAS0cacb112019-02-04 12:16:38 +0100807
Nico Huber2e50cdc2018-09-23 20:20:26 +0200808 if (((boot_buses & BUS_FWH) && ret_fwh) || ((boot_buses & BUS_SPI) && ret_spi))
Stefan Tauner92d6a862013-10-25 00:33:37 +0000809 return ERROR_NONFATAL;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000810
Nico Huber2e50cdc2018-09-23 20:20:26 +0200811 /* Suppress unknown laptop warning if we booted from SPI. */
812 if (boot_buses & BUS_SPI)
Felix Singerd1ab7d22022-08-19 03:03:47 +0200813 laptop_ok = true;
Nico Huber2e50cdc2018-09-23 20:20:26 +0200814
Stefan Tauner92d6a862013-10-25 00:33:37 +0000815 return 0;
816}
817
818static int enable_flash_tunnelcreek(struct pci_dev *dev, const char *name)
819{
820 return enable_flash_ich_spi(dev, CHIPSET_TUNNEL_CREEK, 0xd8);
821}
822
823static int enable_flash_s12x0(struct pci_dev *dev, const char *name)
824{
825 return enable_flash_ich_spi(dev, CHIPSET_CENTERTON, 0xd8);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000826}
Stefan Reinauera9424d52008-06-27 16:28:34 +0000827
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000828static int enable_flash_ich7(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000829{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000830 return enable_flash_ich_spi(dev, CHIPSET_ICH7, 0xdc);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000831}
832
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000833static int enable_flash_ich8(struct pci_dev *dev, const char *name)
834{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000835 return enable_flash_ich_spi(dev, CHIPSET_ICH8, 0xdc);
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000836}
837
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000838static int enable_flash_ich9(struct pci_dev *dev, const char *name)
839{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000840 return enable_flash_ich_spi(dev, CHIPSET_ICH9, 0xdc);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000841}
842
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000843static int enable_flash_ich10(struct pci_dev *dev, const char *name)
844{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000845 return enable_flash_ich_spi(dev, CHIPSET_ICH10, 0xdc);
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000846}
847
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000848/* Ibex Peak aka. 5 series & 3400 series */
849static int enable_flash_pch5(struct pci_dev *dev, const char *name)
850{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000851 return enable_flash_ich_spi(dev, CHIPSET_5_SERIES_IBEX_PEAK, 0xdc);
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000852}
853
854/* Cougar Point aka. 6 series & c200 series */
855static int enable_flash_pch6(struct pci_dev *dev, const char *name)
856{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000857 return enable_flash_ich_spi(dev, CHIPSET_6_SERIES_COUGAR_POINT, 0xdc);
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000858}
859
Stefan Tauner2abab942012-04-27 20:41:23 +0000860/* Panther Point aka. 7 series */
861static int enable_flash_pch7(struct pci_dev *dev, const char *name)
862{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000863 return enable_flash_ich_spi(dev, CHIPSET_7_SERIES_PANTHER_POINT, 0xdc);
Stefan Tauner2abab942012-04-27 20:41:23 +0000864}
865
866/* Lynx Point aka. 8 series */
867static int enable_flash_pch8(struct pci_dev *dev, const char *name)
868{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000869 return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_LYNX_POINT, 0xdc);
Stefan Tauner2abab942012-04-27 20:41:23 +0000870}
871
Stefan Tauner92d6a862013-10-25 00:33:37 +0000872/* Lynx Point LP aka. 8 series low-power */
Duncan Laurie90eb2262013-03-15 03:12:29 +0000873static int enable_flash_pch8_lp(struct pci_dev *dev, const char *name)
874{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000875 return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_LYNX_POINT_LP, 0xdc);
Duncan Laurie90eb2262013-03-15 03:12:29 +0000876}
877
878/* Wellsburg (for Haswell-EP Xeons) */
879static int enable_flash_pch8_wb(struct pci_dev *dev, const char *name)
880{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000881 return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_WELLSBURG, 0xdc);
Duncan Laurie90eb2262013-03-15 03:12:29 +0000882}
883
Duncan Laurie823096e2014-08-20 15:39:38 +0000884/* Wildcat Point */
885static int enable_flash_pch9(struct pci_dev *dev, const char *name)
886{
887 return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT, 0xdc);
888}
889
Nico Huber51205912017-03-17 17:59:54 +0100890/* Wildcat Point LP */
891static int enable_flash_pch9_lp(struct pci_dev *dev, const char *name)
892{
893 return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT_LP, 0xdc);
894}
895
Nico Huber93c30692017-03-20 14:25:09 +0100896/* Sunrise Point */
897static int enable_flash_pch100_shutdown(void *const pci_acc)
898{
899 pci_cleanup(pci_acc);
900 return 0;
901}
902
Nico Huber37509862019-01-18 14:23:02 +0100903static int enable_flash_pch100_or_c620(
904 struct pci_dev *const dev, const char *const name,
905 const int slot, const int func, const enum ich_chipset pch_generation)
Nico Huber93c30692017-03-20 14:25:09 +0100906{
Nico Huber93c30692017-03-20 14:25:09 +0100907 int ret = ERROR_FATAL;
908
909 /*
910 * The SPI PCI device is usually hidden (by hiding PCI vendor
911 * and device IDs). So we need a PCI access method that works
912 * even when the OS doesn't know the PCI device. We can't use
913 * this method globally since it would bring along other con-
914 * straints (e.g. on PCI domains, extended PCIe config space).
915 */
916 struct pci_access *const pci_acc = pci_alloc();
Youness Alaouia54ceb12017-07-26 18:03:36 -0400917 struct pci_access *const saved_pacc = pacc;
Nico Huber93c30692017-03-20 14:25:09 +0100918 if (!pci_acc) {
919 msg_perr("Can't allocate PCI accessor.\n");
920 return ret;
921 }
922 pci_acc->method = PCI_ACCESS_I386_TYPE1;
923 pci_init(pci_acc);
924 register_shutdown(enable_flash_pch100_shutdown, pci_acc);
925
Nico Huber37509862019-01-18 14:23:02 +0100926 struct pci_dev *const spi_dev = pci_get_dev(pci_acc, dev->domain, dev->bus, slot, func);
Nico Huber93c30692017-03-20 14:25:09 +0100927 if (!spi_dev) {
928 msg_perr("Can't allocate PCI device.\n");
929 return ret;
930 }
931
Youness Alaouia54ceb12017-07-26 18:03:36 -0400932 /* Modify pacc so the rpci_write can register the undo callback with a
933 * device using the correct pci_access */
934 pacc = pci_acc;
Nico Huber2e50cdc2018-09-23 20:20:26 +0200935 const enum chipbustype boot_buses = enable_flash_ich_report_gcs(spi_dev, pch_generation, NULL);
Nico Huber93c30692017-03-20 14:25:09 +0100936
937 const int ret_bc = enable_flash_ich_bios_cntl_config_space(spi_dev, pch_generation, 0xdc);
938 if (ret_bc == ERROR_FATAL)
939 goto _freepci_ret;
940
941 const uint32_t phys_spibar = pci_read_long(spi_dev, PCI_BASE_ADDRESS_0) & 0xfffff000;
942 void *const spibar = rphysmap("SPIBAR", phys_spibar, 0x1000);
943 if (spibar == ERROR_PTR)
944 goto _freepci_ret;
945 msg_pdbg("SPIBAR = 0x%0*" PRIxPTR " (phys = 0x%08x)\n", PRIxPTR_WIDTH, (uintptr_t)spibar, phys_spibar);
946
947 /* This adds BUS_SPI */
948 const int ret_spi = ich_init_spi(spibar, pch_generation);
949 if (ret_spi != ERROR_FATAL) {
950 if (ret_bc || ret_spi)
951 ret = ERROR_NONFATAL;
952 else
953 ret = 0;
954 }
955
Nico Huber2e50cdc2018-09-23 20:20:26 +0200956 /* Suppress unknown laptop warning if we booted from SPI. */
957 if (!ret && (boot_buses & BUS_SPI))
Felix Singerd1ab7d22022-08-19 03:03:47 +0200958 laptop_ok = true;
Nico Huber2e50cdc2018-09-23 20:20:26 +0200959
Nico Huber93c30692017-03-20 14:25:09 +0100960_freepci_ret:
961 pci_free_dev(spi_dev);
Youness Alaouia54ceb12017-07-26 18:03:36 -0400962 pacc = saved_pacc;
Nico Huber93c30692017-03-20 14:25:09 +0100963 return ret;
964}
965
David Hendricksa5216362017-08-08 20:02:22 -0700966static int enable_flash_pch100(struct pci_dev *const dev, const char *const name)
967{
Nico Huber37509862019-01-18 14:23:02 +0100968 return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_100_SERIES_SUNRISE_POINT);
David Hendricksa5216362017-08-08 20:02:22 -0700969}
970
971static int enable_flash_c620(struct pci_dev *const dev, const char *const name)
972{
Nico Huber37509862019-01-18 14:23:02 +0100973 return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_C620_SERIES_LEWISBURG);
974}
975
Thomas Heijligen5ec84b32019-03-19 17:00:03 +0100976static int enable_flash_pch300(struct pci_dev *const dev, const char *const name)
977{
978 return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_300_SERIES_CANNON_POINT);
979}
980
Michał Żygowski5c9f5422021-06-16 15:13:54 +0200981static int enable_flash_pch500(struct pci_dev *const dev, const char *const name)
982{
983 return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_500_SERIES_TIGER_POINT);
984}
985
Werner Zehe57d4e42022-01-03 09:44:29 +0100986static int enable_flash_mcc(struct pci_dev *const dev, const char *const name)
987{
988 return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_ELKHART_LAKE);
989}
990
Nico Huber37509862019-01-18 14:23:02 +0100991static int enable_flash_apl(struct pci_dev *const dev, const char *const name)
992{
993 return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE);
David Hendricksa5216362017-08-08 20:02:22 -0700994}
995
Angel Pons4db0fdf2020-07-10 17:04:10 +0200996static int enable_flash_glk(struct pci_dev *const dev, const char *const name)
997{
998 return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_GEMINI_LAKE);
999}
1000
Duncan Laurie4095ed72014-08-20 15:39:32 +00001001/* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley.
1002 * These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately.
1003 *
1004 * Differences include:
1005 * - RCBA at LPC config 0xF0 too but mapped range is only 4 B long instead of 16 kB.
1006 * - GCS at [RCRB] + 0 (instead of [RCRB] + 0x3410).
1007 * - TS (Top Swap) in GCS (instead of [RCRB] + 0x3414).
1008 * - SPIBAR (coined SBASE) at LPC config 0x54 (instead of [RCRB] + 0x3800).
1009 * - BIOS_CNTL (coined BCR) at [SPIBAR] + 0xFC (instead of LPC config 0xDC).
1010 */
1011static int enable_flash_silvermont(struct pci_dev *dev, const char *name)
1012{
1013 enum ich_chipset ich_generation = CHIPSET_BAYTRAIL;
1014
1015 /* Get physical address of Root Complex Register Block */
1016 uint32_t rcba = pci_read_long(dev, 0xf0) & 0xfffffc00;
1017 msg_pdbg("Root Complex Register Block address = 0x%x\n", rcba);
1018
1019 /* Handle GCS (in RCRB) */
1020 void *rcrb = physmap("BYT RCRB", rcba, 4);
Edward O'Callaghan2e3e1062020-12-02 13:17:46 +11001021 if (rcrb == ERROR_PTR)
1022 return ERROR_FATAL;
Nico Huber2e50cdc2018-09-23 20:20:26 +02001023 const enum chipbustype boot_buses = enable_flash_ich_report_gcs(dev, ich_generation, rcrb);
Duncan Laurie4095ed72014-08-20 15:39:32 +00001024 physunmap(rcrb, 4);
1025
1026 /* Handle fwh_idsel parameter */
1027 int ret_fwh = enable_flash_ich_fwh_decode(dev, ich_generation);
1028 if (ret_fwh == ERROR_FATAL)
1029 return ret_fwh;
1030
Nico Huber2e50cdc2018-09-23 20:20:26 +02001031 internal_buses_supported &= BUS_FWH;
Duncan Laurie4095ed72014-08-20 15:39:32 +00001032
1033 /* Get physical address of SPI Base Address and map it */
1034 uint32_t sbase = pci_read_long(dev, 0x54) & 0xfffffe00;
1035 msg_pdbg("SPI_BASE_ADDRESS = 0x%x\n", sbase);
1036 void *spibar = rphysmap("BYT SBASE", sbase, 512); /* Last defined address on Bay Trail is 0x100 */
Edward O'Callaghaneaf701d2020-10-15 19:19:05 +11001037 if (spibar == ERROR_PTR)
1038 return ERROR_FATAL;
Duncan Laurie4095ed72014-08-20 15:39:32 +00001039
1040 /* Enable Flash Writes.
1041 * Silvermont-based: BCR at SBASE + 0xFC (some bits of BCR are also accessible via BC at IBASE + 0x1C).
1042 */
1043 enable_flash_ich_bios_cntl_memmapped(ich_generation, spibar + 0xFC);
1044
Nico Huber560111e2017-04-26 12:27:17 +02001045 int ret_spi = ich_init_spi(spibar, ich_generation);
Duncan Laurie4095ed72014-08-20 15:39:32 +00001046 if (ret_spi == ERROR_FATAL)
1047 return ret_spi;
1048
Nico Huber2e50cdc2018-09-23 20:20:26 +02001049 if (((boot_buses & BUS_FWH) && ret_fwh) || ((boot_buses & BUS_SPI) && ret_spi))
Duncan Laurie4095ed72014-08-20 15:39:32 +00001050 return ERROR_NONFATAL;
1051
Nico Huber2e50cdc2018-09-23 20:20:26 +02001052 /* Suppress unknown laptop warning if we booted from SPI. */
1053 if (boot_buses & BUS_SPI)
Felix Singerd1ab7d22022-08-19 03:03:47 +02001054 laptop_ok = true;
Nico Huber2e50cdc2018-09-23 20:20:26 +02001055
Duncan Laurie4095ed72014-08-20 15:39:32 +00001056 return 0;
1057}
1058
Michael Karcher89bed6d2010-06-13 10:16:12 +00001059static int via_no_byte_merge(struct pci_dev *dev, const char *name)
1060{
1061 uint8_t val;
1062
1063 val = pci_read_byte(dev, 0x71);
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001064 if (val & 0x40) {
Michael Karcher89bed6d2010-06-13 10:16:12 +00001065 msg_pdbg("Disabling byte merging\n");
1066 val &= ~0x40;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001067 rpci_write_byte(dev, 0x71, val);
Michael Karcher89bed6d2010-06-13 10:16:12 +00001068 }
1069 return NOT_DONE_YET; /* need to find south bridge, too */
1070}
1071
Uwe Hermann372eeb52007-12-04 21:49:06 +00001072static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001073{
Ollie Lho184a4042005-11-26 21:55:36 +00001074 uint8_t val;
Ollie Lho761bf1b2004-03-20 16:46:10 +00001075
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001076 /* Enable ROM decode range (1MB) FFC00000 - FFFFFFFF. */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001077 rpci_write_byte(dev, 0x41, 0x7f);
Bari Ari9477c4e2008-04-29 13:46:38 +00001078
Uwe Hermannffec5f32007-08-23 16:08:21 +00001079 /* ROM write enable */
Ollie Lhocbbf1252004-03-17 22:22:08 +00001080 val = pci_read_byte(dev, 0x40);
1081 val |= 0x10;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001082 rpci_write_byte(dev, 0x40, val);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001083
1084 if (pci_read_byte(dev, 0x40) != val) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00001085 msg_pwarn("\nWarning: Failed to enable flash write on \"%s\"\n", name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001086 return -1;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001087 }
Luc Verhaegen6382b442007-03-02 22:16:38 +00001088
Helge Wagnerdd73d832012-08-24 23:03:46 +00001089 if (dev->device_id == 0x3227) { /* VT8237/VT8237R */
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001090 /* All memory cycles, not just ROM ones, go to LPC. */
1091 val = pci_read_byte(dev, 0x59);
1092 val &= ~0x80;
1093 rpci_write_byte(dev, 0x59, val);
Luc Verhaegen73d21192009-12-23 00:54:26 +00001094 }
1095
Uwe Hermanna7e05482007-05-09 10:17:44 +00001096 return 0;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001097}
1098
Helge Wagnerdd73d832012-08-24 23:03:46 +00001099static int enable_flash_vt_vx(struct pci_dev *dev, const char *name)
1100{
1101 struct pci_dev *south_north = pci_dev_find(0x1106, 0xa353);
1102 if (south_north == NULL) {
1103 msg_perr("Could not find South-North Module Interface Control device!\n");
1104 return ERROR_FATAL;
1105 }
1106
1107 msg_pdbg("Strapped to ");
1108 if ((pci_read_byte(south_north, 0x56) & 0x01) == 0) {
1109 msg_pdbg("LPC.\n");
1110 return enable_flash_vt823x(dev, name);
1111 }
1112 msg_pdbg("SPI.\n");
1113
1114 uint32_t mmio_base;
1115 void *mmio_base_physmapped;
1116 uint32_t spi_cntl;
1117 #define SPI_CNTL_LEN 0x08
1118 uint32_t spi0_mm_base = 0;
1119 switch(dev->device_id) {
1120 case 0x8353: /* VX800/VX820 */
1121 spi0_mm_base = pci_read_long(dev, 0xbc) << 8;
Lubomir Rinteld0803c82017-10-30 07:57:53 +01001122 if (spi0_mm_base == 0x0) {
1123 msg_pdbg ("MMIO not enabled!\n");
1124 return ERROR_FATAL;
1125 }
Helge Wagnerdd73d832012-08-24 23:03:46 +00001126 break;
1127 case 0x8409: /* VX855/VX875 */
1128 case 0x8410: /* VX900 */
1129 mmio_base = pci_read_long(dev, 0xbc) << 8;
Lubomir Rinteld0803c82017-10-30 07:57:53 +01001130 if (mmio_base == 0x0) {
1131 msg_pdbg ("MMIO not enabled!\n");
1132 return ERROR_FATAL;
1133 }
Helge Wagnerdd73d832012-08-24 23:03:46 +00001134 mmio_base_physmapped = physmap("VIA VX MMIO register", mmio_base, SPI_CNTL_LEN);
Stefan Tauner7fb5aa02013-08-14 15:48:44 +00001135 if (mmio_base_physmapped == ERROR_PTR)
Helge Wagnerdd73d832012-08-24 23:03:46 +00001136 return ERROR_FATAL;
Helge Wagnerdd73d832012-08-24 23:03:46 +00001137
1138 /* Offset 0 - Bit 0 holds SPI Bus0 Enable Bit. */
1139 spi_cntl = mmio_readl(mmio_base_physmapped) + 0x00;
1140 if ((spi_cntl & 0x01) == 0) {
1141 msg_pdbg ("SPI Bus0 disabled!\n");
1142 physunmap(mmio_base_physmapped, SPI_CNTL_LEN);
1143 return ERROR_FATAL;
1144 }
1145 /* Offset 1-3 has SPI Bus Memory Map Base Address: */
1146 spi0_mm_base = spi_cntl & 0xFFFFFF00;
1147
1148 /* Offset 4 - Bit 0 holds SPI Bus1 Enable Bit. */
1149 spi_cntl = mmio_readl(mmio_base_physmapped) + 0x04;
1150 if ((spi_cntl & 0x01) == 1)
1151 msg_pdbg2("SPI Bus1 is enabled too.\n");
1152
1153 physunmap(mmio_base_physmapped, SPI_CNTL_LEN);
1154 break;
1155 default:
1156 msg_perr("%s: Unsupported chipset %x:%x!\n", __func__, dev->vendor_id, dev->device_id);
1157 return ERROR_FATAL;
1158 }
1159
Nico Huber560111e2017-04-26 12:27:17 +02001160 return via_init_spi(spi0_mm_base);
Helge Wagnerdd73d832012-08-24 23:03:46 +00001161}
1162
1163static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
1164{
Nico Huber560111e2017-04-26 12:27:17 +02001165 return via_init_spi(pci_read_long(dev, 0xbc) << 8);
Helge Wagnerdd73d832012-08-24 23:03:46 +00001166}
1167
Uwe Hermann372eeb52007-12-04 21:49:06 +00001168static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001169{
Uwe Hermannf4a673b2007-06-06 21:35:45 +00001170 uint8_t reg8;
Ollie Lho761bf1b2004-03-20 16:46:10 +00001171
Uwe Hermann394131e2008-10-18 21:14:13 +00001172#define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
1173#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00001174#define CS5530_RESET_CONTROL_REG 0x44 /* F0 index 0x44 */
1175#define CS5530_USB_SHADOW_REG 0x43 /* F0 index 0x43 */
Ollie Lhocbbf1252004-03-17 22:22:08 +00001176
Uwe Hermann394131e2008-10-18 21:14:13 +00001177#define LOWER_ROM_ADDRESS_RANGE (1 << 0)
1178#define ROM_WRITE_ENABLE (1 << 1)
1179#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
1180#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00001181#define CS5530_ISA_MASTER (1 << 7)
1182#define CS5530_ENABLE_SA2320 (1 << 2)
1183#define CS5530_ENABLE_SA20 (1 << 6)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001184
Nico Huber2e50cdc2018-09-23 20:20:26 +02001185 internal_buses_supported &= BUS_PARALLEL;
Stefan Taunerc0aaf952011-05-19 02:58:17 +00001186 /* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and
1187 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB.
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00001188 * FIXME: Should we really touch the low mapping below 1 MB? Flashrom
1189 * ignores that region completely.
Uwe Hermannf4a673b2007-06-06 21:35:45 +00001190 * Make the configured ROM areas writable.
1191 */
1192 reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
1193 reg8 |= LOWER_ROM_ADDRESS_RANGE;
1194 reg8 |= UPPER_ROM_ADDRESS_RANGE;
1195 reg8 |= ROM_WRITE_ENABLE;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001196 rpci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001197
Uwe Hermannf4a673b2007-06-06 21:35:45 +00001198 /* Set positive decode on ROM. */
1199 reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
1200 reg8 |= BIOS_ROM_POSITIVE_DECODE;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001201 rpci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001202
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00001203 reg8 = pci_read_byte(dev, CS5530_RESET_CONTROL_REG);
1204 if (reg8 & CS5530_ISA_MASTER) {
1205 /* We have A0-A23 available. */
1206 max_rom_decode.parallel = 16 * 1024 * 1024;
1207 } else {
1208 reg8 = pci_read_byte(dev, CS5530_USB_SHADOW_REG);
1209 if (reg8 & CS5530_ENABLE_SA2320) {
1210 /* We have A0-19, A20-A23 available. */
1211 max_rom_decode.parallel = 16 * 1024 * 1024;
1212 } else if (reg8 & CS5530_ENABLE_SA20) {
1213 /* We have A0-19, A20 available. */
1214 max_rom_decode.parallel = 2 * 1024 * 1024;
1215 } else {
1216 /* A20 and above are not active. */
1217 max_rom_decode.parallel = 1024 * 1024;
1218 }
1219 }
1220
Ollie Lhocbbf1252004-03-17 22:22:08 +00001221 return 0;
1222}
1223
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001224/*
Mart Raudseppe1344da2008-02-08 10:10:57 +00001225 * Geode systems write protect the BIOS via RCONFs (cache settings similar
Elyes HAOUAS124ef382018-03-27 12:15:09 +02001226 * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22.
Mart Raudseppe1344da2008-02-08 10:10:57 +00001227 *
1228 * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
1229 * To enable write to NOR Boot flash for the benefit of systems that have such
1230 * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
Mart Raudseppe1344da2008-02-08 10:10:57 +00001231 */
Uwe Hermann372eeb52007-12-04 21:49:06 +00001232static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
Lane Brooksd54958a2007-11-13 16:45:22 +00001233{
Uwe Hermann394131e2008-10-18 21:14:13 +00001234#define MSR_RCONF_DEFAULT 0x1808
1235#define MSR_NORF_CTL 0x51400018
Mart Raudsepp0514a5f2008-02-08 09:59:58 +00001236
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001237 msr_t msr;
Lane Brooksd54958a2007-11-13 16:45:22 +00001238
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001239 /* Geode only has a single core */
1240 if (setup_cpu_msr(0))
Lane Brooksd54958a2007-11-13 16:45:22 +00001241 return -1;
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001242
1243 msr = rdmsr(MSR_RCONF_DEFAULT);
1244 if ((msr.hi >> 24) != 0x22) {
1245 msr.hi &= 0xfbffffff;
1246 wrmsr(MSR_RCONF_DEFAULT, msr);
Lane Brooksd54958a2007-11-13 16:45:22 +00001247 }
Mart Raudseppe1344da2008-02-08 10:10:57 +00001248
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001249 msr = rdmsr(MSR_NORF_CTL);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +00001250 /* Raise WE_CS3 bit. */
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001251 msr.lo |= 0x08;
1252 wrmsr(MSR_NORF_CTL, msr);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +00001253
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001254 cleanup_cpu_msr();
Mart Raudsepp0514a5f2008-02-08 09:59:58 +00001255
Uwe Hermann394131e2008-10-18 21:14:13 +00001256#undef MSR_RCONF_DEFAULT
1257#undef MSR_NORF_CTL
Lane Brooksd54958a2007-11-13 16:45:22 +00001258 return 0;
1259}
1260
Uwe Hermann372eeb52007-12-04 21:49:06 +00001261static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001262{
Stefan Taunere34e3e82013-01-01 00:06:51 +00001263 #define SC_REG 0x52
Ollie Lho184a4042005-11-26 21:55:36 +00001264 uint8_t new;
Ollie Lho761bf1b2004-03-20 16:46:10 +00001265
Stefan Taunere34e3e82013-01-01 00:06:51 +00001266 rpci_write_byte(dev, SC_REG, 0xee);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001267
Stefan Taunere34e3e82013-01-01 00:06:51 +00001268 new = pci_read_byte(dev, SC_REG);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001269
Stefan Taunere34e3e82013-01-01 00:06:51 +00001270 if (new != 0xee) { /* FIXME: share this with other code? */
1271 msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", SC_REG, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001272 return -1;
1273 }
Uwe Hermannffec5f32007-08-23 16:08:21 +00001274
Ollie Lhocbbf1252004-03-17 22:22:08 +00001275 return 0;
1276}
1277
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001278/* Works for AMD-768, AMD-8111, VIA VT82C586A/B, VIA VT82C596, VIA VT82C686A/B.
1279 *
1280 * ROM decode control register matrix
Elyes HAOUASac01baa2018-05-28 16:52:21 +02001281 * AMD-768 AMD-8111 VT82C586A/B VT82C596 VT82C686A/B
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001282 * 7 FFC0_0000h–FFFF_FFFFh <- FFFE0000h-FFFEFFFFh <- <-
1283 * 6 FFB0_0000h–FFBF_FFFFh <- FFF80000h-FFFDFFFFh <- <-
1284 * 5 00E8... <- <- FFF00000h-FFF7FFFFh <-
1285 */
1286static int enable_flash_amd_via(struct pci_dev *dev, const char *name, uint8_t decode_val)
Ollie Lho761bf1b2004-03-20 16:46:10 +00001287{
Stefan Taunere34e3e82013-01-01 00:06:51 +00001288 #define AMD_MAPREG 0x43
1289 #define AMD_ENREG 0x40
Ollie Lho184a4042005-11-26 21:55:36 +00001290 uint8_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +00001291
Stefan Taunere34e3e82013-01-01 00:06:51 +00001292 old = pci_read_byte(dev, AMD_MAPREG);
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001293 new = old | decode_val;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001294 if (new != old) {
Stefan Taunere34e3e82013-01-01 00:06:51 +00001295 rpci_write_byte(dev, AMD_MAPREG, new);
1296 if (pci_read_byte(dev, AMD_MAPREG) != new) {
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001297 msg_pwarn("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n",
Stefan Taunere34e3e82013-01-01 00:06:51 +00001298 AMD_MAPREG, new, name);
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001299 } else
1300 msg_pdbg("Changed ROM decode range to 0x%02x successfully.\n", new);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001301 }
1302
Uwe Hermann190f8492008-10-25 18:03:50 +00001303 /* Enable 'ROM write' bit. */
Stefan Taunere34e3e82013-01-01 00:06:51 +00001304 old = pci_read_byte(dev, AMD_ENREG);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001305 new = old | 0x01;
1306 if (new == old)
1307 return 0;
Stefan Taunere34e3e82013-01-01 00:06:51 +00001308 rpci_write_byte(dev, AMD_ENREG, new);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001309
Stefan Taunere34e3e82013-01-01 00:06:51 +00001310 if (pci_read_byte(dev, AMD_ENREG) != new) {
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001311 msg_pwarn("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n",
Stefan Taunere34e3e82013-01-01 00:06:51 +00001312 AMD_ENREG, new, name);
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001313 return ERROR_NONFATAL;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001314 }
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001315 msg_pdbg2("Set ROM enable bit successfully.\n");
Uwe Hermannffec5f32007-08-23 16:08:21 +00001316
Ollie Lhocbbf1252004-03-17 22:22:08 +00001317 return 0;
1318}
1319
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001320static int enable_flash_amd_768_8111(struct pci_dev *dev, const char *name)
1321{
1322 /* Enable decoding of 0xFFB00000 to 0xFFFFFFFF (5 MB). */
1323 max_rom_decode.lpc = 5 * 1024 * 1024;
1324 return enable_flash_amd_via(dev, name, 0xC0);
1325}
1326
1327static int enable_flash_vt82c586(struct pci_dev *dev, const char *name)
1328{
1329 /* Enable decoding of 0xFFF80000 to 0xFFFFFFFF. (512 kB) */
1330 max_rom_decode.parallel = 512 * 1024;
1331 return enable_flash_amd_via(dev, name, 0xC0);
1332}
1333
1334/* Works for VT82C686A/B too. */
1335static int enable_flash_vt82c596(struct pci_dev *dev, const char *name)
1336{
Stefan Taunerc2eec2c2014-05-03 21:33:01 +00001337 /* Enable decoding of 0xFFF00000 to 0xFFFFFFFF. (1 MB) */
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001338 max_rom_decode.parallel = 1024 * 1024;
1339 return enable_flash_amd_via(dev, name, 0xE0);
1340}
1341
Marc Jones3af487d2008-10-15 17:50:29 +00001342static int enable_flash_sb600(struct pci_dev *dev, const char *name)
1343{
Michael Karcherb05b9e12010-07-22 18:04:19 +00001344 uint32_t prot;
Marc Jones3af487d2008-10-15 17:50:29 +00001345 uint8_t reg;
Michael Karcherb05b9e12010-07-22 18:04:19 +00001346 int ret;
Marc Jones3af487d2008-10-15 17:50:29 +00001347
Jason Wanga3f04be2008-11-28 21:36:51 +00001348 /* Clear ROM protect 0-3. */
1349 for (reg = 0x50; reg < 0x60; reg += 4) {
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001350 prot = pci_read_long(dev, reg);
1351 /* No protection flags for this region?*/
1352 if ((prot & 0x3) == 0)
1353 continue;
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001354 msg_pdbg("Chipset %s%sprotected flash from 0x%08x to 0x%08x, unlocking...",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001355 (prot & 0x2) ? "read " : "",
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001356 (prot & 0x1) ? "write " : "",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001357 (prot & 0xfffff800),
1358 (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001359 prot &= 0xfffffffc;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001360 rpci_write_byte(dev, reg, prot);
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001361 prot = pci_read_long(dev, reg);
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001362 if ((prot & 0x3) != 0) {
1363 msg_perr("Disabling %s%sprotection of flash addresses from 0x%08x to 0x%08x failed.\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001364 (prot & 0x2) ? "read " : "",
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001365 (prot & 0x1) ? "write " : "",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001366 (prot & 0xfffff800),
1367 (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001368 continue;
1369 }
1370 msg_pdbg("done.\n");
Jason Wanga3f04be2008-11-28 21:36:51 +00001371 }
1372
Nico Huber2e50cdc2018-09-23 20:20:26 +02001373 internal_buses_supported &= BUS_LPC | BUS_FWH;
Michael Karcherb05b9e12010-07-22 18:04:19 +00001374
1375 ret = sb600_probe_spi(dev);
Jason Wanga3f04be2008-11-28 21:36:51 +00001376
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001377 /* Read ROM strap override register. */
1378 OUTB(0x8f, 0xcd6);
1379 reg = INB(0xcd7);
1380 reg &= 0x0e;
Sean Nelson316a29f2010-05-07 20:09:04 +00001381 msg_pdbg("ROM strap override is %sactive", (reg & 0x02) ? "" : "not ");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001382 if (reg & 0x02) {
1383 switch ((reg & 0x0c) >> 2) {
1384 case 0x00:
Sean Nelson316a29f2010-05-07 20:09:04 +00001385 msg_pdbg(": LPC");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001386 break;
1387 case 0x01:
Sean Nelson316a29f2010-05-07 20:09:04 +00001388 msg_pdbg(": PCI");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001389 break;
1390 case 0x02:
Sean Nelson316a29f2010-05-07 20:09:04 +00001391 msg_pdbg(": FWH");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001392 break;
1393 case 0x03:
Sean Nelson316a29f2010-05-07 20:09:04 +00001394 msg_pdbg(": SPI");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001395 break;
1396 }
1397 }
Sean Nelson316a29f2010-05-07 20:09:04 +00001398 msg_pdbg("\n");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001399
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001400 /* Force enable SPI ROM in SB600 PM register.
1401 * If we enable SPI ROM here, we have to disable it after we leave.
Zheng Bao284a6002009-05-04 22:33:50 +00001402 * But how can we know which ROM we are going to handle? So we have
1403 * to trade off. We only access LPC ROM if we boot via LPC ROM. And
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001404 * only SPI ROM if we boot via SPI ROM. If you want to access SPI on
1405 * boards with LPC straps, you have to use the code below.
Zheng Bao284a6002009-05-04 22:33:50 +00001406 */
1407 /*
Jason Wanga3f04be2008-11-28 21:36:51 +00001408 OUTB(0x8f, 0xcd6);
1409 OUTB(0x0e, 0xcd7);
Zheng Bao284a6002009-05-04 22:33:50 +00001410 */
Marc Jones3af487d2008-10-15 17:50:29 +00001411
Michael Karcherb05b9e12010-07-22 18:04:19 +00001412 return ret;
Marc Jones3af487d2008-10-15 17:50:29 +00001413}
1414
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001415/* sets bit 0 in 0x6d */
1416static int enable_flash_nvidia_common(struct pci_dev *dev, const char *name)
1417{
1418 uint8_t old, new;
1419
1420 old = pci_read_byte(dev, 0x6d);
1421 new = old | 0x01;
1422 if (new == old)
1423 return 0;
1424
1425 rpci_write_byte(dev, 0x6d, new);
1426 if (pci_read_byte(dev, 0x6d) != new) {
1427 msg_pinfo("Setting register 0x6d to 0x%02x on %s failed.\n", new, name);
1428 return 1;
1429 }
1430 return 0;
1431}
1432
Luc Verhaegen90e8e612009-05-26 09:48:28 +00001433static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name)
1434{
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001435 rpci_write_byte(dev, 0x92, 0);
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001436 if (enable_flash_nvidia_common(dev, name))
1437 return ERROR_NONFATAL;
1438 else
1439 return 0;
Luc Verhaegen90e8e612009-05-26 09:48:28 +00001440}
1441
Uwe Hermann372eeb52007-12-04 21:49:06 +00001442static int enable_flash_ck804(struct pci_dev *dev, const char *name)
Yinghai Lu952dfce2005-07-06 17:13:46 +00001443{
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001444 uint32_t segctrl;
1445 uint8_t reg, old, new;
1446 unsigned int err = 0;
Yinghai Lu952dfce2005-07-06 17:13:46 +00001447
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001448 /* 0x8A is special: it is a single byte and only one nibble is touched. */
1449 reg = 0x8A;
1450 segctrl = pci_read_byte(dev, reg);
1451 if ((segctrl & 0x3) != 0x0) {
1452 if ((segctrl & 0xC) != 0x0) {
1453 msg_pinfo("Can not unlock existing protection in register 0x%02x.\n", reg);
1454 err++;
1455 } else {
1456 msg_pdbg("Unlocking protection in register 0x%02x... ", reg);
1457 rpci_write_byte(dev, reg, segctrl & 0xF0);
1458
1459 segctrl = pci_read_byte(dev, reg);
1460 if ((segctrl & 0x3) != 0x0) {
1461 msg_pinfo("Could not unlock protection in register 0x%02x (new value: 0x%x).\n",
1462 reg, segctrl);
1463 err++;
1464 } else
1465 msg_pdbg("OK\n");
1466 }
Jonathan Kollasch9ce498e2011-08-06 12:45:21 +00001467 }
1468
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001469 for (reg = 0x8C; reg <= 0x94; reg += 4) {
1470 segctrl = pci_read_long(dev, reg);
1471 if ((segctrl & 0x33333333) == 0x00000000) {
1472 /* reads and writes are unlocked */
1473 continue;
1474 }
1475 if ((segctrl & 0xCCCCCCCC) != 0x00000000) {
1476 msg_pinfo("Can not unlock existing protection in register 0x%02x.\n", reg);
1477 err++;
1478 continue;
1479 }
1480 msg_pdbg("Unlocking protection in register 0x%02x... ", reg);
1481 rpci_write_long(dev, reg, 0x00000000);
1482
1483 segctrl = pci_read_long(dev, reg);
1484 if ((segctrl & 0x33333333) != 0x00000000) {
1485 msg_pinfo("Could not unlock protection in register 0x%02x (new value: 0x%08x).\n",
1486 reg, segctrl);
1487 err++;
1488 } else
1489 msg_pdbg("OK\n");
1490 }
1491
1492 if (err > 0) {
1493 msg_pinfo("%d locks could not be disabled, disabling writes (reads may also fail).\n", err);
Felix Singer980d6b82022-08-19 02:48:15 +02001494 programmer_may_write = false;
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001495 }
1496
1497 reg = 0x88;
1498 old = pci_read_byte(dev, reg);
1499 new = old | 0xC0;
Uwe Hermanna7e05482007-05-09 10:17:44 +00001500 if (new != old) {
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001501 rpci_write_byte(dev, reg, new);
Stefan Taunere34e3e82013-01-01 00:06:51 +00001502 if (pci_read_byte(dev, reg) != new) { /* FIXME: share this with other code? */
1503 msg_pinfo("Setting register 0x%02x to 0x%02x on %s failed.\n", reg, new, name);
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001504 err++;
Uwe Hermanna7e05482007-05-09 10:17:44 +00001505 }
1506 }
Yinghai Lu952dfce2005-07-06 17:13:46 +00001507
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001508 if (enable_flash_nvidia_common(dev, name))
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001509 err++;
1510
1511 if (err > 0)
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001512 return ERROR_NONFATAL;
1513 else
Uwe Hermanna7e05482007-05-09 10:17:44 +00001514 return 0;
Yinghai Lu952dfce2005-07-06 17:13:46 +00001515}
1516
Joshua Roys85835d82010-09-15 14:47:56 +00001517static int enable_flash_osb4(struct pci_dev *dev, const char *name)
1518{
1519 uint8_t tmp;
1520
Nico Huber2e50cdc2018-09-23 20:20:26 +02001521 internal_buses_supported &= BUS_PARALLEL;
Joshua Roys85835d82010-09-15 14:47:56 +00001522
1523 tmp = INB(0xc06);
1524 tmp |= 0x1;
1525 OUTB(tmp, 0xc06);
1526
1527 tmp = INB(0xc6f);
1528 tmp |= 0x40;
1529 OUTB(tmp, 0xc6f);
1530
1531 return 0;
1532}
1533
Uwe Hermann372eeb52007-12-04 21:49:06 +00001534/* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
1535static int enable_flash_sb400(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +00001536{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001537 uint8_t tmp;
Stefan Reinauer86de2832006-03-31 11:26:55 +00001538 struct pci_dev *smbusdev;
1539
Uwe Hermann372eeb52007-12-04 21:49:06 +00001540 /* Look for the SMBus device. */
Carl-Daniel Hailfingerf6e3efb2009-05-06 00:35:31 +00001541 smbusdev = pci_dev_find(0x1002, 0x4372);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001542
Uwe Hermanna7e05482007-05-09 10:17:44 +00001543 if (!smbusdev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001544 msg_perr("ERROR: SMBus device not found. Aborting.\n");
Tadas Slotkus0e3f1cf2011-09-06 18:49:31 +00001545 return ERROR_FATAL;
Stefan Reinauer86de2832006-03-31 11:26:55 +00001546 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001547
Uwe Hermann372eeb52007-12-04 21:49:06 +00001548 /* Enable some SMBus stuff. */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001549 tmp = pci_read_byte(smbusdev, 0x79);
1550 tmp |= 0x01;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001551 rpci_write_byte(smbusdev, 0x79, tmp);
Stefan Reinauer86de2832006-03-31 11:26:55 +00001552
Uwe Hermann372eeb52007-12-04 21:49:06 +00001553 /* Change southbridge. */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001554 tmp = pci_read_byte(dev, 0x48);
1555 tmp |= 0x21;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001556 rpci_write_byte(dev, 0x48, tmp);
Stefan Reinauer86de2832006-03-31 11:26:55 +00001557
Uwe Hermann372eeb52007-12-04 21:49:06 +00001558 /* Now become a bit silly. */
Andriy Gapon65c1b862008-05-22 13:22:45 +00001559 tmp = INB(0xc6f);
1560 OUTB(tmp, 0xeb);
1561 OUTB(tmp, 0xeb);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001562 tmp |= 0x40;
Andriy Gapon65c1b862008-05-22 13:22:45 +00001563 OUTB(tmp, 0xc6f);
1564 OUTB(tmp, 0xeb);
1565 OUTB(tmp, 0xeb);
Stefan Reinauer86de2832006-03-31 11:26:55 +00001566
1567 return 0;
1568}
1569
Uwe Hermann372eeb52007-12-04 21:49:06 +00001570static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
Yinghai Luca782972007-01-22 20:21:17 +00001571{
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001572 uint8_t val;
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001573 uint16_t wordval;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001574
Uwe Hermann372eeb52007-12-04 21:49:06 +00001575 /* Set the 0-16 MB enable bits. */
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001576 val = pci_read_byte(dev, 0x88);
1577 val |= 0xff; /* 256K */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001578 rpci_write_byte(dev, 0x88, val);
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001579 val = pci_read_byte(dev, 0x8c);
1580 val |= 0xff; /* 1M */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001581 rpci_write_byte(dev, 0x8c, val);
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001582 wordval = pci_read_word(dev, 0x90);
1583 wordval |= 0x7fff; /* 16M */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001584 rpci_write_word(dev, 0x90, wordval);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001585
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001586 if (enable_flash_nvidia_common(dev, name))
1587 return ERROR_NONFATAL;
1588 else
Uwe Hermanna7e05482007-05-09 10:17:44 +00001589 return 0;
Yinghai Luca782972007-01-22 20:21:17 +00001590}
1591
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001592/*
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001593 * The MCP6x/MCP7x code is based on cleanroom reverse engineering.
1594 * It is assumed that LPC chips need the MCP55 code and SPI chips need the
1595 * code provided in enable_flash_mcp6x_7x_common.
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001596 */
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001597static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001598{
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001599 int ret = 0, want_spi = 0;
Michael Karchercfa674f2010-02-25 11:38:23 +00001600 uint8_t val;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001601
1602 /* dev is the ISA bridge. No idea what the stuff below does. */
Michael Karchercfa674f2010-02-25 11:38:23 +00001603 val = pci_read_byte(dev, 0x8a);
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001604 msg_pdbg("ISA/LPC bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5 "
Michael Karchercfa674f2010-02-25 11:38:23 +00001605 "is %i\n", val, (val >> 6) & 0x1, (val >> 5) & 0x1);
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001606
Michael Karchercfa674f2010-02-25 11:38:23 +00001607 switch ((val >> 5) & 0x3) {
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001608 case 0x0:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001609 ret = enable_flash_mcp55(dev, name);
Nico Huber2e50cdc2018-09-23 20:20:26 +02001610 internal_buses_supported &= BUS_LPC;
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001611 msg_pdbg("Flash bus type is LPC\n");
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001612 break;
1613 case 0x2:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001614 want_spi = 1;
1615 /* SPI is added in mcp6x_spi_init if it works.
1616 * Do we really want to disable LPC in this case?
1617 */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +00001618 internal_buses_supported = BUS_NONE;
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001619 msg_pdbg("Flash bus type is SPI\n");
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001620 break;
1621 default:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001622 /* Should not happen. */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +00001623 internal_buses_supported = BUS_NONE;
Stefan Tauner7ba3d6c2014-06-12 21:07:03 +00001624 msg_pwarn("Flash bus type is unknown (none)\n");
Elyes HAOUASac01baa2018-05-28 16:52:21 +02001625 msg_pinfo("Please send the log files created by \"flashrom -p internal -o logfile\" to\n"
Stefan Tauner7ba3d6c2014-06-12 21:07:03 +00001626 "flashrom@flashrom.org with \"your board name: flashrom -V\" as the subject to\n"
1627 "help us finish support for your chipset. Thanks.\n");
1628 return ERROR_NONFATAL;
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001629 }
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001630
1631 /* Force enable SPI and disable LPC? Not a good idea. */
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001632#if 0
Michael Karchercfa674f2010-02-25 11:38:23 +00001633 val |= (1 << 6);
1634 val &= ~(1 << 5);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001635 rpci_write_byte(dev, 0x8a, val);
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001636#endif
1637
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001638 if (mcp6x_spi_init(want_spi))
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001639 ret = 1;
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001640
Nico Huber2e50cdc2018-09-23 20:20:26 +02001641 /* Suppress unknown laptop warning if we booted from SPI. */
1642 if (!ret && want_spi)
Felix Singerd1ab7d22022-08-19 03:03:47 +02001643 laptop_ok = true;
Nico Huber2e50cdc2018-09-23 20:20:26 +02001644
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001645 return ret;
1646}
1647
Uwe Hermann372eeb52007-12-04 21:49:06 +00001648static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001649{
Michael Karchercfa674f2010-02-25 11:38:23 +00001650 uint8_t val;
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001651
Uwe Hermanne823ee02007-06-05 15:02:18 +00001652 /* Set the 4MB enable bit. */
Michael Karchercfa674f2010-02-25 11:38:23 +00001653 val = pci_read_byte(dev, 0x41);
1654 val |= 0x0e;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001655 rpci_write_byte(dev, 0x41, val);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001656
Michael Karchercfa674f2010-02-25 11:38:23 +00001657 val = pci_read_byte(dev, 0x43);
1658 val |= (1 << 4);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001659 rpci_write_byte(dev, 0x43, val);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001660
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001661 return 0;
1662}
1663
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001664/*
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001665 * Usually on the x86 architectures (and on other PC-like platforms like some
1666 * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD
1667 * Elan SC520 only a small piece of the system flash is mapped there, but the
1668 * complete flash is mapped somewhere below 1G. The position can be determined
1669 * by the BOOTCS PAR register.
1670 */
1671static int get_flashbase_sc520(struct pci_dev *dev, const char *name)
1672{
1673 int i, bootcs_found = 0;
1674 uint32_t parx = 0;
1675 void *mmcr;
1676
1677 /* 1. Map MMCR */
Stefan Reinauer0593f212009-01-26 01:10:48 +00001678 mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize());
Niklas Söderlund5d307202013-09-14 09:02:27 +00001679 if (mmcr == ERROR_PTR)
1680 return ERROR_FATAL;
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001681
1682 /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for
1683 * BOOTCS region (PARx[31:29] = 100b)e
1684 */
1685 for (i = 0x88; i <= 0xc4; i += 4) {
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +00001686 parx = mmio_readl(mmcr + i);
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001687 if ((parx >> 29) == 4) {
1688 bootcs_found = 1;
1689 break; /* BOOTCS found */
1690 }
1691 }
1692
1693 /* 3. PARx[25] = 1b --> flashbase[29:16] = PARx[13:0]
1694 * PARx[25] = 0b --> flashbase[29:12] = PARx[17:0]
1695 */
1696 if (bootcs_found) {
1697 if (parx & (1 << 25)) {
1698 parx &= (1 << 14) - 1; /* Mask [13:0] */
1699 flashbase = parx << 16;
1700 } else {
1701 parx &= (1 << 18) - 1; /* Mask [17:0] */
1702 flashbase = parx << 12;
1703 }
1704 } else {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001705 msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. "
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001706 "Assuming flash at 4G.\n");
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001707 }
1708
1709 /* 4. Clean up */
Carl-Daniel Hailfingerbe726812009-08-09 12:44:08 +00001710 physunmap(mmcr, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001711 return 0;
1712}
1713
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001714#endif
1715
Nico Huber2e50cdc2018-09-23 20:20:26 +02001716#define B_P (BUS_PARALLEL)
1717#define B_PFL (BUS_NONSPI)
1718#define B_PFLS (BUS_NONSPI | BUS_SPI)
1719#define B_FL (BUS_FWH | BUS_LPC)
1720#define B_FLS (BUS_FWH | BUS_LPC | BUS_SPI)
1721#define B_FS (BUS_FWH | BUS_SPI)
1722#define B_L (BUS_LPC)
1723#define B_LS (BUS_LPC | BUS_SPI)
1724#define B_S (BUS_SPI)
1725
Idwer Vollering326a0602011-06-18 18:45:41 +00001726/* Please keep this list numerically sorted by vendor/device ID. */
Uwe Hermann05fab752009-05-16 23:42:17 +00001727const struct penable chipset_enables[] = {
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001728#if defined(__i386__) || defined(__x86_64__)
Nico Huber2e50cdc2018-09-23 20:20:26 +02001729 {0x1002, 0x4377, B_PFL, OK, "ATI", "SB400", enable_flash_sb400},
1730 {0x1002, 0x438d, B_FLS, OK, "AMD", "SB600", enable_flash_sb600},
1731 {0x1002, 0x439d, B_FLS, OK, "AMD", "SB7x0/SB8x0/SB9x0", enable_flash_sb600},
1732 {0x100b, 0x0510, B_PFL, NT, "AMD", "SC1100", enable_flash_sc1100},
1733 {0x1022, 0x2080, B_PFL, OK, "AMD", "CS5536", enable_flash_cs5536},
1734 {0x1022, 0x2090, B_PFL, OK, "AMD", "CS5536", enable_flash_cs5536},
1735 {0x1022, 0x3000, B_PFL, OK, "AMD", "Elan SC520", get_flashbase_sc520},
1736 {0x1022, 0x7440, B_PFL, OK, "AMD", "AMD-768", enable_flash_amd_768_8111},
1737 {0x1022, 0x7468, B_PFL, OK, "AMD", "AMD-8111", enable_flash_amd_768_8111},
1738 {0x1022, 0x780e, B_FLS, OK, "AMD", "FCH", enable_flash_sb600},
1739 {0x1022, 0x790e, B_FLS, OK, "AMD", "FP4", enable_flash_sb600},
1740 {0x1039, 0x0406, B_PFL, NT, "SiS", "501/5101/5501", enable_flash_sis501},
1741 {0x1039, 0x0496, B_PFL, NT, "SiS", "85C496+497", enable_flash_sis85c496},
1742 {0x1039, 0x0530, B_PFL, OK, "SiS", "530", enable_flash_sis530},
1743 {0x1039, 0x0540, B_PFL, NT, "SiS", "540", enable_flash_sis540},
1744 {0x1039, 0x0620, B_PFL, NT, "SiS", "620", enable_flash_sis530},
1745 {0x1039, 0x0630, B_PFL, OK, "SiS", "630", enable_flash_sis540},
1746 {0x1039, 0x0635, B_PFL, NT, "SiS", "635", enable_flash_sis540},
1747 {0x1039, 0x0640, B_PFL, NT, "SiS", "640", enable_flash_sis540},
1748 {0x1039, 0x0645, B_PFL, NT, "SiS", "645", enable_flash_sis540},
1749 {0x1039, 0x0646, B_PFL, OK, "SiS", "645DX", enable_flash_sis540},
1750 {0x1039, 0x0648, B_PFL, OK, "SiS", "648", enable_flash_sis540},
1751 {0x1039, 0x0650, B_PFL, OK, "SiS", "650", enable_flash_sis540},
1752 {0x1039, 0x0651, B_PFL, OK, "SiS", "651", enable_flash_sis540},
1753 {0x1039, 0x0655, B_PFL, NT, "SiS", "655", enable_flash_sis540},
1754 {0x1039, 0x0661, B_PFL, OK, "SiS", "661", enable_flash_sis540},
1755 {0x1039, 0x0730, B_PFL, OK, "SiS", "730", enable_flash_sis540},
1756 {0x1039, 0x0733, B_PFL, NT, "SiS", "733", enable_flash_sis540},
1757 {0x1039, 0x0735, B_PFL, OK, "SiS", "735", enable_flash_sis540},
1758 {0x1039, 0x0740, B_PFL, NT, "SiS", "740", enable_flash_sis540},
1759 {0x1039, 0x0741, B_PFL, OK, "SiS", "741", enable_flash_sis540},
1760 {0x1039, 0x0745, B_PFL, OK, "SiS", "745", enable_flash_sis540},
1761 {0x1039, 0x0746, B_PFL, NT, "SiS", "746", enable_flash_sis540},
1762 {0x1039, 0x0748, B_PFL, NT, "SiS", "748", enable_flash_sis540},
1763 {0x1039, 0x0755, B_PFL, OK, "SiS", "755", enable_flash_sis540},
1764 {0x1039, 0x5511, B_PFL, NT, "SiS", "5511", enable_flash_sis5511},
1765 {0x1039, 0x5571, B_PFL, NT, "SiS", "5571", enable_flash_sis530},
1766 {0x1039, 0x5591, B_PFL, NT, "SiS", "5591/5592", enable_flash_sis530},
1767 {0x1039, 0x5596, B_PFL, NT, "SiS", "5596", enable_flash_sis5511},
1768 {0x1039, 0x5597, B_PFL, NT, "SiS", "5597/5598/5581/5120", enable_flash_sis530},
1769 {0x1039, 0x5600, B_PFL, NT, "SiS", "600", enable_flash_sis530},
1770 {0x1078, 0x0100, B_P, OK, "AMD", "CS5530(A)", enable_flash_cs5530},
1771 {0x10b9, 0x1533, B_PFL, OK, "ALi", "M1533", enable_flash_ali_m1533},
1772 {0x10de, 0x0030, B_PFL, OK, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2},
1773 {0x10de, 0x0050, B_PFL, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */
1774 {0x10de, 0x0051, B_PFL, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */
1775 {0x10de, 0x0060, B_PFL, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2},
1776 {0x10de, 0x00e0, B_PFL, OK, "NVIDIA", "NForce3", enable_flash_nvidia_nforce2},
Uwe Hermanneac10162008-03-13 18:52:51 +00001777 /* Slave, should not be here, to fix known bug for A01. */
Nico Huber2e50cdc2018-09-23 20:20:26 +02001778 {0x10de, 0x00d3, B_PFL, OK, "NVIDIA", "CK804", enable_flash_ck804},
1779 {0x10de, 0x0260, B_PFL, OK, "NVIDIA", "MCP51", enable_flash_ck804},
1780 {0x10de, 0x0261, B_PFL, OK, "NVIDIA", "MCP51", enable_flash_ck804},
1781 {0x10de, 0x0262, B_PFL, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1782 {0x10de, 0x0263, B_PFL, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1783 {0x10de, 0x0360, B_L, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* M57SLI*/
Carl-Daniel Hailfinger33d7b6a2010-05-22 07:27:16 +00001784 /* 10de:0361 is present in Tyan S2915 OEM systems, but not connected to
1785 * the flash chip. Instead, 10de:0364 is connected to the flash chip.
1786 * Until we have PCI device class matching or some fallback mechanism,
1787 * this is needed to get flashrom working on Tyan S2915 and maybe other
1788 * dual-MCP55 boards.
1789 */
1790#if 0
Nico Huber2e50cdc2018-09-23 20:20:26 +02001791 {0x10de, 0x0361, B_L, NT, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
Carl-Daniel Hailfinger33d7b6a2010-05-22 07:27:16 +00001792#endif
Nico Huber2e50cdc2018-09-23 20:20:26 +02001793 {0x10de, 0x0362, B_L, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1794 {0x10de, 0x0363, B_L, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1795 {0x10de, 0x0364, B_L, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1796 {0x10de, 0x0365, B_L, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1797 {0x10de, 0x0366, B_L, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1798 {0x10de, 0x0367, B_L, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */
1799 {0x10de, 0x03e0, B_LS, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1800 {0x10de, 0x03e1, B_LS, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1801 {0x10de, 0x03e3, B_LS, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1802 {0x10de, 0x0440, B_LS, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1803 {0x10de, 0x0441, B_LS, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1804 {0x10de, 0x0442, B_LS, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1805 {0x10de, 0x0443, B_LS, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1806 {0x10de, 0x0548, B_LS, OK, "NVIDIA", "MCP67", enable_flash_mcp6x_7x},
1807 {0x10de, 0x075c, B_LS, OK, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x},
1808 {0x10de, 0x075d, B_LS, OK, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x},
1809 {0x10de, 0x07d7, B_LS, OK, "NVIDIA", "MCP73", enable_flash_mcp6x_7x},
1810 {0x10de, 0x0aac, B_LS, OK, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1811 {0x10de, 0x0aad, B_LS, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1812 {0x10de, 0x0aae, B_LS, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1813 {0x10de, 0x0aaf, B_LS, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1814 {0x10de, 0x0d80, B_LS, NT, "NVIDIA", "MCP89", enable_flash_mcp6x_7x},
Michael Karcher89bed6d2010-06-13 10:16:12 +00001815 /* VIA northbridges */
Nico Huber2e50cdc2018-09-23 20:20:26 +02001816 {0x1106, 0x0585, B_PFLS, NT, "VIA", "VT82C585VPX", via_no_byte_merge},
1817 {0x1106, 0x0595, B_PFLS, NT, "VIA", "VT82C595", via_no_byte_merge},
1818 {0x1106, 0x0597, B_PFLS, NT, "VIA", "VT82C597", via_no_byte_merge},
1819 {0x1106, 0x0601, B_PFLS, NT, "VIA", "VT8601/VT8601A", via_no_byte_merge},
1820 {0x1106, 0x0691, B_PFLS, OK, "VIA", "VT82C69x", via_no_byte_merge},
1821 {0x1106, 0x8601, B_PFLS, NT, "VIA", "VT8601T", via_no_byte_merge},
Michael Karcher89bed6d2010-06-13 10:16:12 +00001822 /* VIA southbridges */
Nico Huber2e50cdc2018-09-23 20:20:26 +02001823 {0x1106, 0x0586, B_PFL, OK, "VIA", "VT82C586A/B", enable_flash_vt82c586},
1824 {0x1106, 0x0596, B_PFL, OK, "VIA", "VT82C596", enable_flash_vt82c596},
1825 {0x1106, 0x0686, B_PFL, OK, "VIA", "VT82C686A/B", enable_flash_vt82c596},
1826 {0x1106, 0x3074, B_FL, OK, "VIA", "VT8233", enable_flash_vt823x},
1827 {0x1106, 0x3147, B_FL, OK, "VIA", "VT8233A", enable_flash_vt823x},
1828 {0x1106, 0x3177, B_FL, OK, "VIA", "VT8235", enable_flash_vt823x},
1829 {0x1106, 0x3227, B_FL, OK, "VIA", "VT8237(R)", enable_flash_vt823x},
1830 {0x1106, 0x3287, B_FL, OK, "VIA", "VT8251", enable_flash_vt823x},
1831 {0x1106, 0x3337, B_FL, OK, "VIA", "VT8237A", enable_flash_vt823x},
1832 {0x1106, 0x3372, B_LS, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi},
1833 {0x1106, 0x8231, B_FL, NT, "VIA", "VT8231", enable_flash_vt823x},
1834 {0x1106, 0x8324, B_FL, OK, "VIA", "CX700", enable_flash_vt823x},
1835 {0x1106, 0x8353, B_FLS, NT, "VIA", "VX800/VX820", enable_flash_vt_vx},
1836 {0x1106, 0x8409, B_FLS, OK, "VIA", "VX855/VX875", enable_flash_vt_vx},
1837 {0x1106, 0x8410, B_FLS, OK, "VIA", "VX900", enable_flash_vt_vx},
1838 {0x1166, 0x0200, B_P, OK, "Broadcom", "OSB4", enable_flash_osb4},
1839 {0x1166, 0x0205, B_PFL, OK, "Broadcom", "HT-1000", enable_flash_ht1000},
1840 {0x17f3, 0x6030, B_PFL, OK, "RDC", "R8610/R3210", enable_flash_rdc_r8610},
1841 {0x8086, 0x0c60, B_FS, NT, "Intel", "S12x0", enable_flash_s12x0},
1842 {0x8086, 0x0f1c, B_FS, OK, "Intel", "Bay Trail", enable_flash_silvermont},
1843 {0x8086, 0x0f1d, B_FS, NT, "Intel", "Bay Trail", enable_flash_silvermont},
1844 {0x8086, 0x0f1e, B_FS, NT, "Intel", "Bay Trail", enable_flash_silvermont},
1845 {0x8086, 0x0f1f, B_FS, NT, "Intel", "Bay Trail", enable_flash_silvermont},
1846 {0x8086, 0x122e, B_P, OK, "Intel", "PIIX", enable_flash_piix4},
1847 {0x8086, 0x1234, B_P, NT, "Intel", "MPIIX", enable_flash_piix4},
1848 {0x8086, 0x1c44, B_FS, DEP, "Intel", "Z68", enable_flash_pch6},
1849 {0x8086, 0x1c46, B_FS, DEP, "Intel", "P67", enable_flash_pch6},
1850 {0x8086, 0x1c47, B_FS, NT, "Intel", "UM67", enable_flash_pch6},
1851 {0x8086, 0x1c49, B_FS, DEP, "Intel", "HM65", enable_flash_pch6},
1852 {0x8086, 0x1c4a, B_FS, DEP, "Intel", "H67", enable_flash_pch6},
1853 {0x8086, 0x1c4b, B_FS, NT, "Intel", "HM67", enable_flash_pch6},
1854 {0x8086, 0x1c4c, B_FS, NT, "Intel", "Q65", enable_flash_pch6},
Evgeny Zinovievd493baa2021-03-06 21:14:39 +03001855 {0x8086, 0x1c4d, B_FS, DEP, "Intel", "QS67", enable_flash_pch6},
Angel Pons3b3fc932020-11-20 10:05:29 +01001856 {0x8086, 0x1c4e, B_FS, DEP, "Intel", "Q67", enable_flash_pch6},
Nico Huber2e50cdc2018-09-23 20:20:26 +02001857 {0x8086, 0x1c4f, B_FS, DEP, "Intel", "QM67", enable_flash_pch6},
1858 {0x8086, 0x1c50, B_FS, NT, "Intel", "B65", enable_flash_pch6},
1859 {0x8086, 0x1c52, B_FS, NT, "Intel", "C202", enable_flash_pch6},
1860 {0x8086, 0x1c54, B_FS, DEP, "Intel", "C204", enable_flash_pch6},
1861 {0x8086, 0x1c56, B_FS, NT, "Intel", "C206", enable_flash_pch6},
1862 {0x8086, 0x1c5c, B_FS, DEP, "Intel", "H61", enable_flash_pch6},
1863 {0x8086, 0x1d40, B_FS, DEP, "Intel", "C60x/X79", enable_flash_pch6},
1864 {0x8086, 0x1d41, B_FS, DEP, "Intel", "C60x/X79", enable_flash_pch6},
Edward O'Callaghan55f65642020-11-02 14:43:10 +11001865 {0x8086, 0x1e41, B_FS, DEP, "Intel", "Desktop Sample", enable_flash_pch7},
1866 {0x8086, 0x1e42, B_FS, DEP, "Intel", "Mobile Sample", enable_flash_pch7},
1867 {0x8086, 0x1e43, B_FS, DEP, "Intel", "SFF Sample", enable_flash_pch7},
Nico Huber2e50cdc2018-09-23 20:20:26 +02001868 {0x8086, 0x1e44, B_FS, DEP, "Intel", "Z77", enable_flash_pch7},
1869 {0x8086, 0x1e46, B_FS, NT, "Intel", "Z75", enable_flash_pch7},
Jacob Garber1592fe52020-08-28 12:48:32 -06001870 {0x8086, 0x1e47, B_FS, DEP, "Intel", "Q77", enable_flash_pch7},
Angel Ponsd58128e2019-10-06 21:07:44 +02001871 {0x8086, 0x1e48, B_FS, DEP, "Intel", "Q75", enable_flash_pch7},
Nico Huber2e50cdc2018-09-23 20:20:26 +02001872 {0x8086, 0x1e49, B_FS, DEP, "Intel", "B75", enable_flash_pch7},
1873 {0x8086, 0x1e4a, B_FS, DEP, "Intel", "H77", enable_flash_pch7},
Jacob Garber198bef32021-02-20 10:51:56 -07001874 {0x8086, 0x1e53, B_FS, DEP, "Intel", "C216", enable_flash_pch7},
Nico Huber2e50cdc2018-09-23 20:20:26 +02001875 {0x8086, 0x1e55, B_FS, DEP, "Intel", "QM77", enable_flash_pch7},
1876 {0x8086, 0x1e56, B_FS, DEP, "Intel", "QS77", enable_flash_pch7},
1877 {0x8086, 0x1e57, B_FS, DEP, "Intel", "HM77", enable_flash_pch7},
1878 {0x8086, 0x1e58, B_FS, NT, "Intel", "UM77", enable_flash_pch7},
Angel Pons728062f2019-12-18 00:26:15 +01001879 {0x8086, 0x1e59, B_FS, DEP, "Intel", "HM76", enable_flash_pch7},
Evgeny Zinovieva9335cc2020-03-09 03:05:42 +03001880 {0x8086, 0x1e5d, B_FS, DEP, "Intel", "HM75", enable_flash_pch7},
Nico Huber2e50cdc2018-09-23 20:20:26 +02001881 {0x8086, 0x1e5e, B_FS, NT, "Intel", "HM70", enable_flash_pch7},
1882 {0x8086, 0x1e5f, B_FS, DEP, "Intel", "NM70", enable_flash_pch7},
1883 {0x8086, 0x1f38, B_FS, DEP, "Intel", "Avoton/Rangeley", enable_flash_silvermont},
1884 {0x8086, 0x1f39, B_FS, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont},
1885 {0x8086, 0x1f3a, B_FS, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont},
1886 {0x8086, 0x1f3b, B_FS, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont},
1887 {0x8086, 0x229c, B_FS, OK, "Intel", "Braswell", enable_flash_silvermont},
1888 {0x8086, 0x2310, B_FS, NT, "Intel", "DH89xxCC (Cave Creek)", enable_flash_pch7},
1889 {0x8086, 0x2390, B_FS, NT, "Intel", "Coleto Creek", enable_flash_pch7},
1890 {0x8086, 0x2410, B_FL, OK, "Intel", "ICH", enable_flash_ich0},
1891 {0x8086, 0x2420, B_FL, OK, "Intel", "ICH0", enable_flash_ich0},
1892 {0x8086, 0x2440, B_FL, OK, "Intel", "ICH2", enable_flash_ich2345},
1893 {0x8086, 0x244c, B_FL, OK, "Intel", "ICH2-M", enable_flash_ich2345},
1894 {0x8086, 0x2450, B_FL, NT, "Intel", "C-ICH", enable_flash_ich2345},
1895 {0x8086, 0x2480, B_FL, OK, "Intel", "ICH3-S", enable_flash_ich2345},
1896 {0x8086, 0x248c, B_FL, OK, "Intel", "ICH3-M", enable_flash_ich2345},
1897 {0x8086, 0x24c0, B_FL, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich2345},
1898 {0x8086, 0x24cc, B_FL, OK, "Intel", "ICH4-M", enable_flash_ich2345},
1899 {0x8086, 0x24d0, B_FL, OK, "Intel", "ICH5/ICH5R", enable_flash_ich2345},
1900 {0x8086, 0x25a1, B_FL, OK, "Intel", "6300ESB", enable_flash_ich2345},
1901 {0x8086, 0x2640, B_FL, OK, "Intel", "ICH6/ICH6R", enable_flash_ich6},
1902 {0x8086, 0x2641, B_FL, OK, "Intel", "ICH6-M", enable_flash_ich6},
1903 {0x8086, 0x2642, B_FL, NT, "Intel", "ICH6W/ICH6RW", enable_flash_ich6},
1904 {0x8086, 0x2670, B_FL, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich6},
1905 {0x8086, 0x27b0, B_FS, OK, "Intel", "ICH7DH", enable_flash_ich7},
1906 {0x8086, 0x27b8, B_FS, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7},
1907 {0x8086, 0x27b9, B_FS, OK, "Intel", "ICH7M", enable_flash_ich7},
1908 {0x8086, 0x27bc, B_FS, OK, "Intel", "NM10", enable_flash_ich7},
1909 {0x8086, 0x27bd, B_FS, OK, "Intel", "ICH7MDH", enable_flash_ich7},
1910 {0x8086, 0x2810, B_FS, DEP, "Intel", "ICH8/ICH8R", enable_flash_ich8},
1911 {0x8086, 0x2811, B_FS, DEP, "Intel", "ICH8M-E", enable_flash_ich8},
1912 {0x8086, 0x2812, B_FS, DEP, "Intel", "ICH8DH", enable_flash_ich8},
1913 {0x8086, 0x2814, B_FS, DEP, "Intel", "ICH8DO", enable_flash_ich8},
1914 {0x8086, 0x2815, B_FS, DEP, "Intel", "ICH8M", enable_flash_ich8},
1915 {0x8086, 0x2910, B_FS, DEP, "Intel", "ICH9 Eng. Sample", enable_flash_ich9},
1916 {0x8086, 0x2912, B_FS, DEP, "Intel", "ICH9DH", enable_flash_ich9},
1917 {0x8086, 0x2914, B_FS, DEP, "Intel", "ICH9DO", enable_flash_ich9},
1918 {0x8086, 0x2916, B_FS, DEP, "Intel", "ICH9R", enable_flash_ich9},
1919 {0x8086, 0x2917, B_FS, DEP, "Intel", "ICH9M-E", enable_flash_ich9},
1920 {0x8086, 0x2918, B_FS, DEP, "Intel", "ICH9", enable_flash_ich9},
1921 {0x8086, 0x2919, B_FS, DEP, "Intel", "ICH9M", enable_flash_ich9},
1922 {0x8086, 0x3a10, B_FS, NT, "Intel", "ICH10R Eng. Sample", enable_flash_ich10},
1923 {0x8086, 0x3a14, B_FS, DEP, "Intel", "ICH10DO", enable_flash_ich10},
1924 {0x8086, 0x3a16, B_FS, DEP, "Intel", "ICH10R", enable_flash_ich10},
1925 {0x8086, 0x3a18, B_FS, DEP, "Intel", "ICH10", enable_flash_ich10},
1926 {0x8086, 0x3a1a, B_FS, DEP, "Intel", "ICH10D", enable_flash_ich10},
1927 {0x8086, 0x3a1e, B_FS, NT, "Intel", "ICH10 Eng. Sample", enable_flash_ich10},
1928 {0x8086, 0x3b00, B_FS, NT, "Intel", "3400 Desktop", enable_flash_pch5},
1929 {0x8086, 0x3b01, B_FS, NT, "Intel", "3400 Mobile", enable_flash_pch5},
1930 {0x8086, 0x3b02, B_FS, NT, "Intel", "P55", enable_flash_pch5},
1931 {0x8086, 0x3b03, B_FS, DEP, "Intel", "PM55", enable_flash_pch5},
1932 {0x8086, 0x3b06, B_FS, DEP, "Intel", "H55", enable_flash_pch5},
1933 {0x8086, 0x3b07, B_FS, DEP, "Intel", "QM57", enable_flash_pch5},
1934 {0x8086, 0x3b08, B_FS, NT, "Intel", "H57", enable_flash_pch5},
1935 {0x8086, 0x3b09, B_FS, DEP, "Intel", "HM55", enable_flash_pch5},
1936 {0x8086, 0x3b0a, B_FS, NT, "Intel", "Q57", enable_flash_pch5},
1937 {0x8086, 0x3b0b, B_FS, NT, "Intel", "HM57", enable_flash_pch5},
1938 {0x8086, 0x3b0d, B_FS, NT, "Intel", "3400 Mobile SFF", enable_flash_pch5},
1939 {0x8086, 0x3b0e, B_FS, NT, "Intel", "B55", enable_flash_pch5},
1940 {0x8086, 0x3b0f, B_FS, DEP, "Intel", "QS57", enable_flash_pch5},
1941 {0x8086, 0x3b12, B_FS, NT, "Intel", "3400", enable_flash_pch5},
1942 {0x8086, 0x3b14, B_FS, DEP, "Intel", "3420", enable_flash_pch5},
1943 {0x8086, 0x3b16, B_FS, NT, "Intel", "3450", enable_flash_pch5},
1944 {0x8086, 0x3b1e, B_FS, NT, "Intel", "B55", enable_flash_pch5},
1945 {0x8086, 0x5031, B_FS, OK, "Intel", "EP80579", enable_flash_ich7},
1946 {0x8086, 0x7000, B_P, OK, "Intel", "PIIX3", enable_flash_piix4},
1947 {0x8086, 0x7110, B_P, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4},
1948 {0x8086, 0x7198, B_P, OK, "Intel", "440MX", enable_flash_piix4},
1949 {0x8086, 0x8119, B_FL, OK, "Intel", "SCH Poulsbo", enable_flash_poulsbo},
1950 {0x8086, 0x8186, B_FS, OK, "Intel", "Atom E6xx(T) (Tunnel Creek)", enable_flash_tunnelcreek},
1951 {0x8086, 0x8c40, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1952 {0x8086, 0x8c41, B_FS, NT, "Intel", "Lynx Point Mobile Eng. Sample", enable_flash_pch8},
1953 {0x8086, 0x8c42, B_FS, NT, "Intel", "Lynx Point Desktop Eng. Sample",enable_flash_pch8},
1954 {0x8086, 0x8c43, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1955 {0x8086, 0x8c44, B_FS, DEP, "Intel", "Z87", enable_flash_pch8},
1956 {0x8086, 0x8c45, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1957 {0x8086, 0x8c46, B_FS, NT, "Intel", "Z85", enable_flash_pch8},
1958 {0x8086, 0x8c47, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1959 {0x8086, 0x8c48, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1960 {0x8086, 0x8c49, B_FS, NT, "Intel", "HM86", enable_flash_pch8},
1961 {0x8086, 0x8c4a, B_FS, DEP, "Intel", "H87", enable_flash_pch8},
1962 {0x8086, 0x8c4b, B_FS, DEP, "Intel", "HM87", enable_flash_pch8},
1963 {0x8086, 0x8c4c, B_FS, NT, "Intel", "Q85", enable_flash_pch8},
1964 {0x8086, 0x8c4d, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1965 {0x8086, 0x8c4e, B_FS, NT, "Intel", "Q87", enable_flash_pch8},
1966 {0x8086, 0x8c4f, B_FS, NT, "Intel", "QM87", enable_flash_pch8},
1967 {0x8086, 0x8c50, B_FS, DEP, "Intel", "B85", enable_flash_pch8},
1968 {0x8086, 0x8c51, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1969 {0x8086, 0x8c52, B_FS, NT, "Intel", "C222", enable_flash_pch8},
1970 {0x8086, 0x8c53, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1971 {0x8086, 0x8c54, B_FS, DEP, "Intel", "C224", enable_flash_pch8},
1972 {0x8086, 0x8c55, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1973 {0x8086, 0x8c56, B_FS, NT, "Intel", "C226", enable_flash_pch8},
1974 {0x8086, 0x8c57, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1975 {0x8086, 0x8c58, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1976 {0x8086, 0x8c59, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1977 {0x8086, 0x8c5a, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1978 {0x8086, 0x8c5b, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1979 {0x8086, 0x8c5c, B_FS, DEP, "Intel", "H81", enable_flash_pch8},
1980 {0x8086, 0x8c5d, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1981 {0x8086, 0x8c5e, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1982 {0x8086, 0x8c5f, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1983 {0x8086, 0x8cc1, B_FS, NT, "Intel", "9 Series", enable_flash_pch9},
1984 {0x8086, 0x8cc2, B_FS, NT, "Intel", "9 Series Engineering Sample", enable_flash_pch9},
1985 {0x8086, 0x8cc3, B_FS, NT, "Intel", "9 Series", enable_flash_pch9},
Sophie van Soesteec477f2021-07-04 13:54:26 +02001986 {0x8086, 0x8cc4, B_FS, DEP, "Intel", "Z97", enable_flash_pch9},
Nico Huber2e50cdc2018-09-23 20:20:26 +02001987 {0x8086, 0x8cc6, B_FS, NT, "Intel", "H97", enable_flash_pch9},
1988 {0x8086, 0x8d40, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1989 {0x8086, 0x8d41, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1990 {0x8086, 0x8d42, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1991 {0x8086, 0x8d43, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1992 {0x8086, 0x8d44, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1993 {0x8086, 0x8d45, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1994 {0x8086, 0x8d46, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1995 {0x8086, 0x8d47, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1996 {0x8086, 0x8d48, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1997 {0x8086, 0x8d49, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1998 {0x8086, 0x8d4a, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1999 {0x8086, 0x8d4b, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2000 {0x8086, 0x8d4c, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2001 {0x8086, 0x8d4d, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2002 {0x8086, 0x8d4e, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2003 {0x8086, 0x8d4f, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2004 {0x8086, 0x8d50, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2005 {0x8086, 0x8d51, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2006 {0x8086, 0x8d52, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2007 {0x8086, 0x8d53, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2008 {0x8086, 0x8d54, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2009 {0x8086, 0x8d55, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2010 {0x8086, 0x8d56, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2011 {0x8086, 0x8d57, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2012 {0x8086, 0x8d58, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2013 {0x8086, 0x8d59, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2014 {0x8086, 0x8d5a, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2015 {0x8086, 0x8d5b, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2016 {0x8086, 0x8d5c, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2017 {0x8086, 0x8d5d, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2018 {0x8086, 0x8d5e, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2019 {0x8086, 0x8d5f, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2020 {0x8086, 0x9c41, B_FS, NT, "Intel", "Lynx Point LP Eng. Sample", enable_flash_pch8_lp},
2021 {0x8086, 0x9c43, B_FS, NT, "Intel", "Lynx Point LP Premium", enable_flash_pch8_lp},
2022 {0x8086, 0x9c45, B_FS, NT, "Intel", "Lynx Point LP Mainstream", enable_flash_pch8_lp},
2023 {0x8086, 0x9c47, B_FS, NT, "Intel", "Lynx Point LP Value", enable_flash_pch8_lp},
2024 {0x8086, 0x9cc1, B_FS, NT, "Intel", "Haswell U Sample", enable_flash_pch9_lp},
2025 {0x8086, 0x9cc2, B_FS, NT, "Intel", "Broadwell U Sample", enable_flash_pch9_lp},
2026 {0x8086, 0x9cc3, B_FS, DEP, "Intel", "Broadwell U Premium", enable_flash_pch9_lp},
Nikolai Artemiev2bb67922020-11-03 17:19:52 +11002027 {0x8086, 0x9cc5, B_FS, DEP, "Intel", "Broadwell U Base", enable_flash_pch9_lp},
Nico Huber2e50cdc2018-09-23 20:20:26 +02002028 {0x8086, 0x9cc6, B_FS, NT, "Intel", "Broadwell Y Sample", enable_flash_pch9_lp},
2029 {0x8086, 0x9cc7, B_FS, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9_lp},
2030 {0x8086, 0x9cc9, B_FS, NT, "Intel", "Broadwell Y Base", enable_flash_pch9_lp},
2031 {0x8086, 0x9ccb, B_FS, NT, "Intel", "Broadwell H", enable_flash_pch9},
2032 {0x8086, 0x9d41, B_S, NT, "Intel", "Skylake / Kaby Lake Sample", enable_flash_pch100},
2033 {0x8086, 0x9d43, B_S, NT, "Intel", "Skylake U Base", enable_flash_pch100},
2034 {0x8086, 0x9d46, B_S, NT, "Intel", "Skylake Y Premium", enable_flash_pch100},
Angel Pons7113d172020-02-29 23:13:43 +01002035 {0x8086, 0x9d48, B_S, DEP, "Intel", "Skylake U Premium", enable_flash_pch100},
Nico Huber2e50cdc2018-09-23 20:20:26 +02002036 {0x8086, 0x9d4b, B_S, NT, "Intel", "Kaby Lake Y w/ iHDCP2.2 Prem.", enable_flash_pch100},
Wim Vervoorn3799a1c2020-01-20 15:01:54 +01002037 {0x8086, 0x9d4e, B_S, DEP, "Intel", "Kaby Lake U w/ iHDCP2.2 Prem.", enable_flash_pch100},
Nico Huber2e50cdc2018-09-23 20:20:26 +02002038 {0x8086, 0x9d50, B_S, NT, "Intel", "Kaby Lake U w/ iHDCP2.2 Base", enable_flash_pch100},
2039 {0x8086, 0x9d51, B_S, NT, "Intel", "Kabe Lake w/ iHDCP2.2 Sample", enable_flash_pch100},
2040 {0x8086, 0x9d53, B_S, NT, "Intel", "Kaby Lake U Base", enable_flash_pch100},
2041 {0x8086, 0x9d56, B_S, NT, "Intel", "Kaby Lake Y Premium", enable_flash_pch100},
2042 {0x8086, 0x9d58, B_S, NT, "Intel", "Kaby Lake U Premium", enable_flash_pch100},
Matt DeVillierbde44a12019-07-04 17:52:40 -05002043 {0x8086, 0x9d84, B_S, DEP, "Intel", "Cannon Lake U Premium", enable_flash_pch300},
Matt DeVillier4f29bb72020-08-12 12:48:06 -05002044 {0x8086, 0x0284, B_S, DEP, "Intel", "Comet Lake U Premium", enable_flash_pch300},
Sam McNally76303902021-03-11 11:41:46 +11002045 {0x8086, 0x0285, B_S, DEP, "Intel", "Comet Lake U Base", enable_flash_pch300},
Michał Żygowski5c9f5422021-06-16 15:13:54 +02002046 {0x8086, 0xa082, B_S, DEP, "Intel", "Tiger Lake U Premium", enable_flash_pch500},
Nico Huber2e50cdc2018-09-23 20:20:26 +02002047 {0x8086, 0xa141, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100},
2048 {0x8086, 0xa142, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100},
Angel Ponsabb34fe2020-12-06 23:09:13 +01002049 {0x8086, 0xa143, B_S, DEP, "Intel", "H110", enable_flash_pch100},
Nico Huber2e50cdc2018-09-23 20:20:26 +02002050 {0x8086, 0xa144, B_S, NT, "Intel", "H170", enable_flash_pch100},
2051 {0x8086, 0xa145, B_S, NT, "Intel", "Z170", enable_flash_pch100},
2052 {0x8086, 0xa146, B_S, NT, "Intel", "Q170", enable_flash_pch100},
2053 {0x8086, 0xa147, B_S, NT, "Intel", "Q150", enable_flash_pch100},
2054 {0x8086, 0xa148, B_S, NT, "Intel", "B150", enable_flash_pch100},
2055 {0x8086, 0xa149, B_S, NT, "Intel", "C236", enable_flash_pch100},
2056 {0x8086, 0xa14a, B_S, NT, "Intel", "C232", enable_flash_pch100},
2057 {0x8086, 0xa14b, B_S, NT, "Intel", "Sunrise Point Server Sample", enable_flash_pch100},
2058 {0x8086, 0xa14d, B_S, NT, "Intel", "QM170", enable_flash_pch100},
2059 {0x8086, 0xa14e, B_S, NT, "Intel", "HM170", enable_flash_pch100},
Nico Huberea0c0932019-07-04 17:34:16 +02002060 {0x8086, 0xa150, B_S, DEP, "Intel", "CM236", enable_flash_pch100},
Nico Huber2e50cdc2018-09-23 20:20:26 +02002061 {0x8086, 0xa151, B_S, NT, "Intel", "QMS180", enable_flash_pch100},
2062 {0x8086, 0xa152, B_S, NT, "Intel", "HM175", enable_flash_pch100},
2063 {0x8086, 0xa153, B_S, NT, "Intel", "QM175", enable_flash_pch100},
2064 {0x8086, 0xa154, B_S, NT, "Intel", "CM238", enable_flash_pch100},
2065 {0x8086, 0xa155, B_S, NT, "Intel", "QMU185", enable_flash_pch100},
Luka Kovacic9f064192020-07-30 13:31:15 +02002066 {0x8086, 0xa1a4, B_S, DEP, "Intel", "C620 Series Chipset (QS/PRQ)", enable_flash_c620},
Angel Pons77a2a6e2020-03-23 16:05:07 +01002067 {0x8086, 0xa1c0, B_S, NT, "Intel", "C620 Series Chipset (QS/PRQ)", enable_flash_c620},
Nico Huber2e50cdc2018-09-23 20:20:26 +02002068 {0x8086, 0xa1c1, B_S, NT, "Intel", "C621 Series Chipset (QS/PRQ)", enable_flash_c620},
2069 {0x8086, 0xa1c2, B_S, NT, "Intel", "C622 Series Chipset (QS/PRQ)", enable_flash_c620},
2070 {0x8086, 0xa1c3, B_S, NT, "Intel", "C624 Series Chipset (QS/PRQ)", enable_flash_c620},
2071 {0x8086, 0xa1c4, B_S, NT, "Intel", "C625 Series Chipset (QS/PRQ)", enable_flash_c620},
2072 {0x8086, 0xa1c5, B_S, NT, "Intel", "C626 Series Chipset (QS/PRQ)", enable_flash_c620},
2073 {0x8086, 0xa1c6, B_S, NT, "Intel", "C627 Series Chipset (QS/PRQ)", enable_flash_c620},
2074 {0x8086, 0xa1c7, B_S, NT, "Intel", "C628 Series Chipset (QS/PRQ)", enable_flash_c620},
Angel Pons77a2a6e2020-03-23 16:05:07 +01002075 {0x8086, 0xa1c8, B_S, NT, "Intel", "C620 Series Chipset (QS/PRQ)", enable_flash_c620},
2076 {0x8086, 0xa1c9, B_S, NT, "Intel", "C620 Series Chipset (QS/PRQ)", enable_flash_c620},
2077 {0x8086, 0xa1ca, B_S, NT, "Intel", "C629 Series Chipset (QS/PRQ)", enable_flash_c620},
Jonathan Zhangc218a052020-08-19 12:16:40 -07002078 {0x8086, 0xa1cb, B_S, NT, "Intel", "C621A Series Chipset (QS/PRQ)", enable_flash_c620},
2079 {0x8086, 0xa1cc, B_S, NT, "Intel", "C627A Series Chipset (QS/PRQ)", enable_flash_c620},
2080 {0x8086, 0xa1cd, B_S, NT, "Intel", "C629A Series Chipset (QS/PRQ)", enable_flash_c620},
Angel Pons77a2a6e2020-03-23 16:05:07 +01002081 {0x8086, 0xa240, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620},
2082 {0x8086, 0xa241, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620},
Nico Huber2e50cdc2018-09-23 20:20:26 +02002083 {0x8086, 0xa242, B_S, NT, "Intel", "C624 Series Chipset Supersku", enable_flash_c620},
2084 {0x8086, 0xa243, B_S, NT, "Intel", "C627 Series Chipset Supersku", enable_flash_c620},
2085 {0x8086, 0xa244, B_S, NT, "Intel", "C621 Series Chipset Supersku", enable_flash_c620},
2086 {0x8086, 0xa245, B_S, NT, "Intel", "C627 Series Chipset Supersku", enable_flash_c620},
2087 {0x8086, 0xa246, B_S, NT, "Intel", "C628 Series Chipset Supersku", enable_flash_c620},
2088 {0x8086, 0xa247, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620},
Angel Pons77a2a6e2020-03-23 16:05:07 +01002089 {0x8086, 0xa248, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620},
2090 {0x8086, 0xa249, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620},
Jonathan Zhang3bf7cfb2021-08-30 23:25:06 -07002091 {0x8086, 0x1bca, B_S, NT, "Intel", "Emmitsburg Chipset SKU", enable_flash_c620},
Nico Huber2e50cdc2018-09-23 20:20:26 +02002092 {0x8086, 0xa2c4, B_S, NT, "Intel", "H270", enable_flash_pch100},
2093 {0x8086, 0xa2c5, B_S, NT, "Intel", "Z270", enable_flash_pch100},
2094 {0x8086, 0xa2c6, B_S, NT, "Intel", "Q270", enable_flash_pch100},
2095 {0x8086, 0xa2c7, B_S, NT, "Intel", "Q250", enable_flash_pch100},
2096 {0x8086, 0xa2c8, B_S, NT, "Intel", "B250", enable_flash_pch100},
2097 {0x8086, 0xa2c9, B_S, NT, "Intel", "Z370", enable_flash_pch100},
Angel Ponsb499b672021-04-22 17:08:00 +02002098 {0x8086, 0xa2ca, B_S, DEP, "Intel", "H310C", enable_flash_pch100},
2099 {0x8086, 0xa2cc, B_S, DEP, "Intel", "B365", enable_flash_pch100},
Nico Huber2e50cdc2018-09-23 20:20:26 +02002100 {0x8086, 0xa2d2, B_S, NT, "Intel", "X299", enable_flash_pch100},
Nico Huberd2d39932019-01-18 16:49:37 +01002101 {0x8086, 0x5ae8, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl},
Jan Samek1f967c82020-01-08 12:35:14 +01002102 {0x8086, 0x5af0, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl},
Angel Pons1c7297f2021-05-17 10:50:40 +02002103 {0x8086, 0x3197, B_S, NT, "Intel", "Gemini Lake", enable_flash_glk},
Angel Pons4db0fdf2020-07-10 17:04:10 +02002104 {0x8086, 0x31e8, B_S, DEP, "Intel", "Gemini Lake", enable_flash_glk},
Werner Zehe57d4e42022-01-03 09:44:29 +01002105 {0x8086, 0x4b24, B_S, DEP, "Intel", "Elkhart Lake", enable_flash_mcc},
Nico Huber2a5dfaf2019-07-04 16:01:51 +02002106 {0x8086, 0xa303, B_S, NT, "Intel", "H310", enable_flash_pch300},
2107 {0x8086, 0xa304, B_S, NT, "Intel", "H370", enable_flash_pch300},
melvyn269c324a2021-10-30 16:02:22 -07002108 {0x8086, 0xa305, B_S, DEP, "Intel", "Z390", enable_flash_pch300},
Nico Huber2a5dfaf2019-07-04 16:01:51 +02002109 {0x8086, 0xa306, B_S, NT, "Intel", "Q370", enable_flash_pch300},
2110 {0x8086, 0xa308, B_S, NT, "Intel", "B360", enable_flash_pch300},
Angel Pons0c8221b2022-10-20 21:23:33 +02002111 {0x8086, 0xa309, B_S, DEP, "Intel", "C246", enable_flash_pch300},
Nico Huber2a5dfaf2019-07-04 16:01:51 +02002112 {0x8086, 0xa30a, B_S, NT, "Intel", "C242", enable_flash_pch300},
2113 {0x8086, 0xa30c, B_S, NT, "Intel", "QM370", enable_flash_pch300},
2114 {0x8086, 0xa30d, B_S, NT, "Intel", "HM370", enable_flash_pch300},
Nico Huberea0c0932019-07-04 17:34:16 +02002115 {0x8086, 0xa30e, B_S, DEP, "Intel", "CM246", enable_flash_pch300},
Johanna Schanderb5433b72019-12-29 15:16:14 +01002116 {0x8086, 0x3482, B_S, DEP, "Intel", "Ice Lake U Premium", enable_flash_pch300},
Gaggery Tsaibc0285c2019-12-12 11:52:03 -08002117 {0x8086, 0x0684, B_S, NT, "Intel", "H470", enable_flash_pch300},
2118 {0x8086, 0x0685, B_S, NT, "Intel", "Z490", enable_flash_pch300},
2119 {0x8086, 0x0687, B_S, NT, "Intel", "Q470", enable_flash_pch300},
2120 {0x8086, 0x068c, B_S, NT, "Intel", "QM480", enable_flash_pch300},
2121 {0x8086, 0x068d, B_S, NT, "Intel", "HM470", enable_flash_pch300},
2122 {0x8086, 0x068e, B_S, NT, "Intel", "WM490", enable_flash_pch300},
2123 {0x8086, 0x0697, B_S, NT, "Intel", "W480", enable_flash_pch300},
Nico Huber756b6b32022-12-21 17:15:13 +00002124 {0x8086, 0x4da4, B_S, NT, "Intel", "Jasper Lake", enable_flash_pch300},
Tim Crawfordfafc3d82021-11-17 06:23:25 -07002125 {0x8086, 0x4384, B_S, NT, "Intel", "Q570", enable_flash_pch500},
2126 {0x8086, 0x4385, B_S, NT, "Intel", "Z590", enable_flash_pch500},
2127 {0x8086, 0x4386, B_S, NT, "Intel", "H570", enable_flash_pch500},
2128 {0x8086, 0x4387, B_S, NT, "Intel", "B560", enable_flash_pch500},
2129 {0x8086, 0x4388, B_S, NT, "Intel", "H510", enable_flash_pch500},
2130 {0x8086, 0x438f, B_S, NT, "Intel", "W580", enable_flash_pch500},
2131 {0x8086, 0x4389, B_S, NT, "Intel", "WM590", enable_flash_pch500},
2132 {0x8086, 0x438a, B_S, NT, "Intel", "QM580", enable_flash_pch500},
2133 {0x8086, 0x438b, B_S, DEP, "Intel", "HM570", enable_flash_pch500},
Nico Huber29c23dd2022-12-21 15:25:09 +00002134 {0x8086, 0x51a4, B_S, DEP, "Intel", "Alder Lake-P", enable_flash_pch500},
2135 {0x8086, 0x54a4, B_S, DEP, "Intel", "Alder Lake-N", enable_flash_pch500},
2136 {0x8086, 0x7aa4, B_S, NT, "Intel", "Alder Lake-S", enable_flash_pch500},
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00002137#endif
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +00002138 {0},
Ollie Lhocbbf1252004-03-17 22:22:08 +00002139};
Ollie Lho761bf1b2004-03-20 16:46:10 +00002140
Uwe Hermanna7e05482007-05-09 10:17:44 +00002141int chipset_flash_enable(void)
Ollie Lhocbbf1252004-03-17 22:22:08 +00002142{
Peter Huewe73f8ec82011-01-24 19:15:51 +00002143 struct pci_dev *dev = NULL;
Uwe Hermann372eeb52007-12-04 21:49:06 +00002144 int ret = -2; /* Nothing! */
Uwe Hermanna7e05482007-05-09 10:17:44 +00002145 int i;
Ollie Lhocbbf1252004-03-17 22:22:08 +00002146
Uwe Hermann372eeb52007-12-04 21:49:06 +00002147 /* Now let's try to find the chipset we have... */
Uwe Hermann05fab752009-05-16 23:42:17 +00002148 for (i = 0; chipset_enables[i].vendor_name != NULL; i++) {
2149 dev = pci_dev_find(chipset_enables[i].vendor_id,
2150 chipset_enables[i].device_id);
Michael Karcher89bed6d2010-06-13 10:16:12 +00002151 if (!dev)
2152 continue;
2153 if (ret != -2) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00002154 msg_pwarn("Warning: unexpected second chipset match: "
Paul Menzelab6328f2010-10-08 11:03:02 +00002155 "\"%s %s\"\n"
2156 "ignoring, please report lspci and board URL "
2157 "to flashrom@flashrom.org\n"
Stefan Reinauerbf282b12011-03-29 21:41:41 +00002158 "with \'CHIPSET: your board name\' in the "
Paul Menzelab6328f2010-10-08 11:03:02 +00002159 "subject line.\n",
Michael Karcher89bed6d2010-06-13 10:16:12 +00002160 chipset_enables[i].vendor_name,
2161 chipset_enables[i].device_name);
2162 continue;
2163 }
Stefan Taunerec8c2482011-07-21 19:59:34 +00002164 msg_pinfo("Found chipset \"%s %s\"",
2165 chipset_enables[i].vendor_name,
2166 chipset_enables[i].device_name);
Stefan Tauner716e0982011-07-25 20:38:52 +00002167 msg_pdbg(" with PCI ID %04x:%04x",
Carl-Daniel Hailfingerf469c272010-05-22 07:31:50 +00002168 chipset_enables[i].vendor_id,
2169 chipset_enables[i].device_id);
Stefan Tauner5c316f92015-02-08 21:57:52 +00002170 msg_pinfo(".\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +00002171
Stefan Tauner23e10b82016-01-23 16:16:49 +00002172 if (chipset_enables[i].status == BAD) {
2173 msg_perr("ERROR: This chipset is not supported yet.\n");
2174 return ERROR_FATAL;
2175 }
Stefan Taunerec8c2482011-07-21 19:59:34 +00002176 if (chipset_enables[i].status == NT) {
Stefan Tauner5c316f92015-02-08 21:57:52 +00002177 msg_pinfo("This chipset is marked as untested. If "
Stefan Taunerec8c2482011-07-21 19:59:34 +00002178 "you are using an up-to-date version\nof "
Stefan Tauner2abab942012-04-27 20:41:23 +00002179 "flashrom *and* were (not) able to "
2180 "successfully update your firmware with it,\n"
2181 "then please email a report to "
2182 "flashrom@flashrom.org including a verbose "
2183 "(-V) log.\nThank you!\n");
Stefan Taunerec8c2482011-07-21 19:59:34 +00002184 }
Nico Huber2e50cdc2018-09-23 20:20:26 +02002185 if (!(chipset_enables[i].buses & (internal_buses_supported | BUS_SPI))) {
2186 msg_pdbg("Skipping chipset enable: No supported buses enabled.\n");
2187 continue;
2188 }
Stefan Taunerec8c2482011-07-21 19:59:34 +00002189 msg_pinfo("Enabling flash write... ");
Stefan Tauner23e10b82016-01-23 16:16:49 +00002190 ret = chipset_enables[i].doit(dev, chipset_enables[i].device_name);
Michael Karcher89bed6d2010-06-13 10:16:12 +00002191 if (ret == NOT_DONE_YET) {
2192 ret = -2;
2193 msg_pinfo("OK - searching further chips.\n");
2194 } else if (ret < 0)
Sean Nelson316a29f2010-05-07 20:09:04 +00002195 msg_pinfo("FAILED!\n");
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002196 else if (ret == 0)
Sean Nelson316a29f2010-05-07 20:09:04 +00002197 msg_pinfo("OK.\n");
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002198 else if (ret == ERROR_NONFATAL)
Michael Karchera4448d92010-07-22 18:04:15 +00002199 msg_pinfo("PROBLEMS, continuing anyway\n");
Tadas Slotkusad470342011-09-03 17:15:00 +00002200 if (ret == ERROR_FATAL) {
2201 msg_perr("FATAL ERROR!\n");
2202 return ret;
2203 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00002204 }
Michael Karcher89bed6d2010-06-13 10:16:12 +00002205
Uwe Hermanna7e05482007-05-09 10:17:44 +00002206 return ret;
Ollie Lhocbbf1252004-03-17 22:22:08 +00002207}