commit | 55f6564524189f99097b3c6525b1b339a72cd063 | [log] [tgz] |
---|---|---|
author | Edward O'Callaghan <quasisec@google.com> | Mon Nov 02 14:43:10 2020 +1100 |
committer | Nico Huber <nico.h@gmx.de> | Thu Jan 05 16:07:04 2023 +0000 |
tree | 640e378ca1287a26f1a91ff4c0f088a84a7fa6bf | |
parent | 0ad11992be40c7e1e9b8a1f45a48a3e5362f6f7c [diff] |
chipset_enable.c: Add Intel pch7 did=0x1e4{1,2,3} support Modified to be pch7 over pch6 as per-coreboot and review comments. Change-Id: Ic69dc024e9af0c43d6b3a8213a5dc5d2f898c447 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/47090 Original-Reviewed-by: Sam McNally <sammc@google.com> Original-Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>