ichspi: add support for Intel Hardware Sequencing
Based on the new opaque programmer framework this patch adds support
for Intel Hardware Sequencing on ICH8 and its successors.
By default (or when setting the ich_spi_mode option to auto)
the module tries to use swseq and only activates hwseq if need be:
- if important opcodes are inaccessible due to lockdown
- if more than one flash chip is attached.
The other options (swseq, hwseq) select the respective mode (if possible).
A general description of Hardware Sequencing can be found in this blog entry:
http://blogs.coreboot.org/blog/2011/06/11/gsoc-2011-flashrom-part-1/
Besides adding hwseq this patch also introduces these unrelated changes:
- Fix enable_flash_ich_dc_spi to pass ERROR_FATAL from ich_init_spi.
The whole error handling looks a bit odd to me, so this patch does
change very little. Also, it does not touch the tunnelcreek method,
which should be refactored anyway.
- Add null-pointer guards to find_opcode and find_preop
to matches the other opcode methods better:
curopcodes == NULL has some meaning and is actively used/checked in
other functions.
TODO: adding real documentation when we have a directory for it
Corresponding to flashrom svn r1461.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
diff --git a/chipset_enable.c b/chipset_enable.c
index 15bd3eb..77e0862 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -491,7 +491,7 @@
static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
enum ich_chipset ich_generation)
{
- int ret;
+ int ret, ret_spi;
uint8_t bbs, buc;
uint32_t tmp, gcs;
void *rcrb;
@@ -569,10 +569,12 @@
}
/* This adds BUS_SPI */
- if (ich_init_spi(dev, tmp, rcrb, ich_generation) != 0) {
- if (!ret)
- ret = ERROR_NONFATAL;
- }
+ ret_spi = ich_init_spi(dev, tmp, rcrb, ich_generation);
+ if (ret_spi == ERROR_FATAL)
+ return ret_spi;
+
+ if (ret || ret_spi)
+ ret = ERROR_NONFATAL;
return ret;
}