Flashrom update from Stefan, resolve issue 21
Corresponding to flashrom svn r34 and coreboot v2 svn r2111.
diff --git a/flash_enable.c b/flash_enable.c
index 19fd9b0..582766f 100644
--- a/flash_enable.c
+++ b/flash_enable.c
@@ -1,7 +1,23 @@
+/*
+ * flash rom utility: enable flash writes
+ *
+ * Copyright (C) 2000-2004 ???
+ * Copyright (C) 2005 coresystems GmbH <stepan@openbios.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2
+ *
+ */
+
#include <sys/io.h>
#include <stdio.h>
#include <pci/pci.h>
#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+#include "lbtable.h"
+#include "debug.h"
static int enable_flash_sis630(struct pci_dev *dev, char *name)
{
@@ -60,7 +76,7 @@
static int enable_flash_e7500(struct pci_dev *dev, char *name)
{
/* register 4e.b gets or'ed with one */
- unsigned char old, new;
+ uint8_t old, new;
/* if it fails, it fails. There are so many variations of broken mobos
* that it is hard to argue that we should quit at this point.
*/
@@ -85,7 +101,7 @@
static int enable_flash_ich4(struct pci_dev *dev, char *name)
{
/* register 4e.b gets or'ed with one */
- unsigned char old, new;
+ uint8_t old, new;
/* if it fails, it fails. There are so many variations of broken mobos
* that it is hard to argue that we should quit at this point.
*/
@@ -109,7 +125,7 @@
static int enable_flash_vt8235(struct pci_dev *dev, char *name)
{
- unsigned char old, new, val;
+ uint8_t old, new, val;
unsigned int base;
int ok;
@@ -147,7 +163,7 @@
static int enable_flash_vt8231(struct pci_dev *dev, char *name)
{
- unsigned char val;
+ uint8_t val;
val = pci_read_byte(dev, 0x40);
val |= 0x10;
@@ -163,7 +179,7 @@
static int enable_flash_cs5530(struct pci_dev *dev, char *name)
{
- unsigned char new;
+ uint8_t new;
pci_write_byte(dev, 0x52, 0xee);
@@ -174,12 +190,17 @@
0x52, new, name);
return -1;
}
+
+ new = pci_read_byte(dev, 0x5b) | 0x20;
+ pci_write_byte(dev, 0x5b, new);
+
return 0;
}
+
static int enable_flash_sc1100(struct pci_dev *dev, char *name)
{
- unsigned char new;
+ uint8_t new;
pci_write_byte(dev, 0x52, 0xee);
@@ -195,7 +216,7 @@
static int enable_flash_sis5595(struct pci_dev *dev, char *name)
{
- unsigned char new, newer;
+ uint8_t new, newer;
new = pci_read_byte(dev, 0x45);
@@ -219,7 +240,7 @@
static int enable_flash_amd8111(struct pci_dev *dev, char *name)
{
/* register 4e.b gets or'ed with one */
- unsigned char old, new;
+ uint8_t old, new;
/* if it fails, it fails. There are so many variations of broken mobos
* that it is hard to argue that we should quit at this point.
*/
@@ -253,7 +274,7 @@
static int enable_flash_ck804(struct pci_dev *dev, char *name)
{
/* register 4e.b gets or'ed with one */
- unsigned char old, new;
+ uint8_t old, new;
/* if it fails, it fails. There are so many variations of broken mobos
* that it is hard to argue that we should quit at this point.
*/
@@ -305,6 +326,69 @@
{0x10de, 0x00d3, "NVIDIA CK804", enable_flash_ck804}, // Slave, should not be here, to fix known bug for A01.
};
+static int mbenable_island_aruma(void)
+{
+#define EFIR 0x2e // Exteneded function index register, either 0x2e or 0x4e
+#define EFDR EFIR + 1 // Extended function data register, one plus the index reg.
+ char b;
+// Disable the flash write protect. The flash write protect is
+// connected to the WinBond w83627hf GPIO 24.
+
+ /* get io privilege access winbond config space */
+ if (iopl(3) != 0) {
+ perror("Can not set io priviliage");
+ exit(1);
+ }
+
+ printf("Disabling mainboard flash write protection.\n");
+
+ outb(0x87, EFIR); // sequence to unlock extended functions
+ outb(0x87, EFIR);
+
+ outb(0x20, EFIR); // SIO device ID register
+ b = inb(EFDR);
+ printf_debug("W83627HF device ID = 0x%x\n",b);
+
+ if (b != 0x52) {
+ perror("Incorrect device ID, aborting write protect disable\n");
+ exit(1);
+ }
+
+ outb(0x2b, EFIR); // GPIO multiplexed pin reg.
+ b = inb(EFDR) | 0x10;
+ outb(0x2b, EFIR);
+ outb(b, EFDR); // select GPIO 24 instead of WDTO
+
+ outb(0x7, EFIR); // logical device select
+ outb(0x8, EFDR); // point to device 8, GPIO port 2
+
+ outb(0x30, EFIR); // logic device activation control
+ outb(0x1, EFDR); // activate
+
+ outb(0xf0, EFIR); // GPIO 20-27 I/O selection register
+ b = inb(EFDR) & ~0x10;
+ outb(0xf0, EFIR);
+ outb(b, EFDR); // set GPIO 24 as an output
+
+ outb(0xf1, EFIR); // GPIO 20-27 data register
+ b = inb(EFDR) | 0x10;
+ outb(0xf1, EFIR);
+ outb(b, EFDR); // set GPIO 24
+
+ outb(0xaa, EFIR); // command to exit extended functions
+
+ return 0;
+}
+
+typedef struct mbenable {
+ char *vendor, *part;
+ int (*doit)(void);
+} MAINBOARD_ENABLE;
+
+static MAINBOARD_ENABLE mbenables[] = {
+ { "ISLAND", "ARUMA", mbenable_island_aruma },
+};
+
int enable_flash_write()
{
int i;
@@ -317,6 +401,18 @@
pci_init(pacc); /* Initialize the PCI library */
pci_scan_bus(pacc); /* We want to get the list of devices */
+
+ /* First look whether we have to do something for this
+ * motherboard.
+ */
+ for (i = 0; i < sizeof(mbenables) / sizeof(mbenables[0]); i++) {
+ if(lb_vendor && !strcmp(mbenables[i].vendor, lb_vendor) &&
+ lb_part && !strcmp(mbenables[i].part, lb_part)) {
+ mbenables[i].doit();
+ break;
+ }
+ }
+
/* now let's try to find the chipset we have ... */
for (i = 0; i < sizeof(enables) / sizeof(enables[0]) && (!dev);
i++) {