commit | 3750986348cb99b8f0d828b73972b545a2f9c878 | [log] [tgz] |
---|---|---|
author | Nico Huber <nico.huber@secunet.com> | Fri Jan 18 14:23:02 2019 +0100 |
committer | Nico Huber <nico.h@gmx.de> | Sat Jul 06 17:15:58 2019 +0000 |
tree | 62b7c2d2a5b84561596fdbbeddc6111d27dfc315 | |
parent | 908adf4589d34eaf3bd8395afa52aed8c8887cfd [diff] |
chipset_enable: Add Apollo Lake It works the same as 100 series PCHs and on. The SPI device is at 0:0d.2, though. Mark as BAD until `ichspi` is revised. Change-Id: I7b1ad402ba562b7b977be111f8cf61f1be50843a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/30994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>