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Ollie Lho184a4042005-11-26 21:55:36 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ollie Lho184a4042005-11-26 21:55:36 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
6 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Ollie Lho184a4042005-11-26 21:55:36 +00007 *
Uwe Hermannd1107642007-08-29 17:52:32 +00008 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
Ollie Lho184a4042005-11-26 21:55:36 +000011 *
Uwe Hermannd1107642007-08-29 17:52:32 +000012 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22/*
23 * Contains the chipset specific flash enables.
Ollie Lho184a4042005-11-26 21:55:36 +000024 */
25
Lane Brooksd54958a2007-11-13 16:45:22 +000026#define _LARGEFILE64_SOURCE
27
Ollie Lhocbbf1252004-03-17 22:22:08 +000028#include <stdlib.h>
Uwe Hermanne8ba5382009-05-22 11:37:27 +000029#include <string.h>
Lane Brooksd54958a2007-11-13 16:45:22 +000030#include <sys/types.h>
31#include <sys/stat.h>
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +000032#include <sys/mman.h>
Lane Brooksd54958a2007-11-13 16:45:22 +000033#include <fcntl.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000034#include "flash.h"
Stefan Reinauer86de2832006-03-31 11:26:55 +000035
Stefan Reinauer9a6d1762008-12-03 21:24:40 +000036unsigned long flashbase = 0;
37
Stefan Reinauer2cb94e12008-06-30 23:45:22 +000038/**
39 * flashrom defaults to LPC flash devices. If a known SPI controller is found
40 * and the SPI strappings are set, this will be overwritten by the probing code.
41 *
42 * Eventually, this will become an array when multiple flash support works.
43 */
44
45flashbus_t flashbus = BUS_TYPE_LPC;
46void *spibar = NULL;
47
FENG yu ningc05a2952008-12-08 18:16:58 +000048extern int ichspi_lock;
49
Uwe Hermann372eeb52007-12-04 21:49:06 +000050static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
Luc Verhaegen6b141752007-05-20 16:16:13 +000051{
52 uint8_t tmp;
53
Uwe Hermann372eeb52007-12-04 21:49:06 +000054 /*
55 * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
56 * 0xFFFE0000-0xFFFFFFFF ROM select enable.
57 */
Luc Verhaegen6b141752007-05-20 16:16:13 +000058 tmp = pci_read_byte(dev, 0x47);
59 tmp |= 0x46;
60 pci_write_byte(dev, 0x47, tmp);
61
62 return 0;
63}
64
Uwe Hermann372eeb52007-12-04 21:49:06 +000065static int enable_flash_sis630(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +000066{
Uwe Hermann372eeb52007-12-04 21:49:06 +000067 uint8_t b;
Ollie Lhocbbf1252004-03-17 22:22:08 +000068
Uwe Hermann372eeb52007-12-04 21:49:06 +000069 /* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
Alex Beregszaszic9fb5d92007-09-11 15:58:18 +000070 b = pci_read_byte(dev, 0x40);
71 pci_write_byte(dev, 0x40, b | 0xb);
Uwe Hermann372eeb52007-12-04 21:49:06 +000072
73 /* Flash write enable on SiS 540/630. */
Alex Beregszaszic9fb5d92007-09-11 15:58:18 +000074 b = pci_read_byte(dev, 0x45);
75 pci_write_byte(dev, 0x45, b | 0x40);
Ollie Lhocbbf1252004-03-17 22:22:08 +000076
Uwe Hermann372eeb52007-12-04 21:49:06 +000077 /* The same thing on SiS 950 Super I/O side... */
78
79 /* First probe for Super I/O on config port 0x2e. */
Andriy Gapon65c1b862008-05-22 13:22:45 +000080 OUTB(0x87, 0x2e);
81 OUTB(0x01, 0x2e);
82 OUTB(0x55, 0x2e);
83 OUTB(0x55, 0x2e);
Ollie Lhocbbf1252004-03-17 22:22:08 +000084
Andriy Gapon65c1b862008-05-22 13:22:45 +000085 if (INB(0x2f) != 0x87) {
Uwe Hermann372eeb52007-12-04 21:49:06 +000086 /* If that failed, try config port 0x4e. */
Andriy Gapon65c1b862008-05-22 13:22:45 +000087 OUTB(0x87, 0x4e);
88 OUTB(0x01, 0x4e);
89 OUTB(0x55, 0x4e);
90 OUTB(0xaa, 0x4e);
91 if (INB(0x4f) != 0x87) {
Ollie Lhocbbf1252004-03-17 22:22:08 +000092 printf("Can not access SiS 950\n");
93 return -1;
94 }
Andriy Gapon65c1b862008-05-22 13:22:45 +000095 OUTB(0x24, 0x4e);
96 b = INB(0x4f) | 0xfc;
97 OUTB(0x24, 0x4e);
98 OUTB(b, 0x4f);
99 OUTB(0x02, 0x4e);
100 OUTB(0x02, 0x4f);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000101 }
102
Andriy Gapon65c1b862008-05-22 13:22:45 +0000103 OUTB(0x24, 0x2e);
104 printf("2f is %#x\n", INB(0x2f));
105 b = INB(0x2f) | 0xfc;
106 OUTB(0x24, 0x2e);
107 OUTB(b, 0x2f);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000108
Andriy Gapon65c1b862008-05-22 13:22:45 +0000109 OUTB(0x02, 0x2e);
110 OUTB(0x02, 0x2f);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000111
112 return 0;
113}
114
Uwe Hermann987942d2006-11-07 11:16:21 +0000115/* Datasheet:
116 * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
117 * - URL: http://www.intel.com/design/intarch/datashts/290562.htm
118 * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
119 * - Order Number: 290562-001
120 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000121static int enable_flash_piix4(struct pci_dev *dev, const char *name)
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000122{
123 uint16_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000124 uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000125
126 old = pci_read_word(dev, xbcs);
127
128 /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
Uwe Hermanna7e05482007-05-09 10:17:44 +0000129 * FFF00000-FFF7FFFF are forwarded to ISA).
Uwe Hermannc556d322008-10-28 11:50:05 +0000130 * Note: This bit is reserved on PIIX/PIIX3/MPIIX.
Uwe Hermanna7e05482007-05-09 10:17:44 +0000131 * Set bit 7: Extended BIOS Enable (PCI master accesses to
132 * FFF80000-FFFDFFFF are forwarded to ISA).
133 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
134 * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
135 * of 1 Mbyte, or the aliases at the top of 4 Gbyte
136 * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
137 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
138 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
139 */
Uwe Hermannc556d322008-10-28 11:50:05 +0000140 if (dev->device_id == 0x122e || dev->device_id == 0x7000
141 || dev->device_id == 0x1234)
142 new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */
Uwe Hermann87203452008-10-26 18:40:42 +0000143 else
144 new = old | 0x02c4;
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000145
146 if (new == old)
147 return 0;
148
149 pci_write_word(dev, xbcs, new);
150
151 if (pci_read_word(dev, xbcs) != new) {
152 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name);
153 return -1;
154 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000155
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000156 return 0;
157}
158
Uwe Hermann372eeb52007-12-04 21:49:06 +0000159/*
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000160 * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet"
161 * http://download.intel.com/design/chipsets/datashts/30701303.pdf
Uwe Hermann372eeb52007-12-04 21:49:06 +0000162 */
163static int enable_flash_ich(struct pci_dev *dev, const char *name,
164 int bios_cntl)
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000165{
Ollie Lho184a4042005-11-26 21:55:36 +0000166 uint8_t old, new;
Stefan Reinauereb366472006-09-06 15:48:48 +0000167
Uwe Hermann372eeb52007-12-04 21:49:06 +0000168 /*
169 * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but
Uwe Hermanna7e05482007-05-09 10:17:44 +0000170 * just treating it as 8 bit wide seems to work fine in practice.
Stefan Reinauereb366472006-09-06 15:48:48 +0000171 */
Stefan Reinauer86de2832006-03-31 11:26:55 +0000172 old = pci_read_byte(dev, bios_cntl);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000173
Uwe Hermann793bdcd2008-05-22 22:47:04 +0000174 printf_debug("\nBIOS Lock Enable: %sabled, ",
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000175 (old & (1 << 1)) ? "en" : "dis");
176 printf_debug("BIOS Write Enable: %sabled, ",
177 (old & (1 << 0)) ? "en" : "dis");
178 printf_debug("BIOS_CNTL is 0x%x\n", old);
179
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000180 new = old | 1;
181
182 if (new == old)
183 return 0;
184
Stefan Reinauer86de2832006-03-31 11:26:55 +0000185 pci_write_byte(dev, bios_cntl, new);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000186
Stefan Reinauer86de2832006-03-31 11:26:55 +0000187 if (pci_read_byte(dev, bios_cntl) != new) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000188 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000189 return -1;
190 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000191
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000192 return 0;
193}
194
Uwe Hermann372eeb52007-12-04 21:49:06 +0000195static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000196{
Stefan Reinauereb366472006-09-06 15:48:48 +0000197 return enable_flash_ich(dev, name, 0x4e);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000198}
199
Uwe Hermann372eeb52007-12-04 21:49:06 +0000200static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000201{
Stefan Reinauereb366472006-09-06 15:48:48 +0000202 return enable_flash_ich(dev, name, 0xdc);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000203}
204
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000205#define ICH_STRAP_RSVD 0x00
206#define ICH_STRAP_SPI 0x01
207#define ICH_STRAP_PCI 0x02
208#define ICH_STRAP_LPC 0x03
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000209
Uwe Hermann394131e2008-10-18 21:14:13 +0000210static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
211{
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000212 uint32_t mmio_base;
213
214 mmio_base = (pci_read_long(dev, 0xbc)) << 8;
215 printf_debug("MMIO base at = 0x%x\n", mmio_base);
Stefan Reinauer0593f212009-01-26 01:10:48 +0000216 spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70);
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000217
Uwe Hermann394131e2008-10-18 21:14:13 +0000218 printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000219 mmio_readw(spibar + 0x6c));
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000220
221 flashbus = BUS_TYPE_VIA_SPI;
Rudolf Marek0c2029f2009-02-01 18:40:50 +0000222 ich_init_opcodes();
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000223
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000224 return 0;
225}
226
Uwe Hermann394131e2008-10-18 21:14:13 +0000227static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
228 int ich_generation)
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000229{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000230 int ret, i;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000231 uint8_t old, new, bbs, buc;
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000232 uint16_t spibar_offset, tmp2;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000233 uint32_t tmp, gcs;
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000234 void *rcrb;
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000235 //TODO: These names are incorrect for EP80579. For that, the solution would look like the commented line
236 //static const char *straps_names[] = {"SPI", "reserved", "reserved", "LPC" };
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000237 static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" };
Uwe Hermann394131e2008-10-18 21:14:13 +0000238
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000239 /* Enable Flash Writes */
240 ret = enable_flash_ich_dc(dev, name);
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000241
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000242 /* Get physical address of Root Complex Register Block */
243 tmp = pci_read_long(dev, 0xf0) & 0xffffc000;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000244 printf_debug("\nRoot Complex Register Block address = 0x%x\n", tmp);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000245
246 /* Map RCBA to virtual memory */
Stefan Reinauer0593f212009-01-26 01:10:48 +0000247 rcrb = physmap("ICH RCRB", tmp, 0x4000);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000248
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000249 gcs = mmio_readl(rcrb + 0x3410);
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000250 printf_debug("GCS = 0x%x: ", gcs);
251 printf_debug("BIOS Interface Lock-Down: %sabled, ",
252 (gcs & 0x1) ? "en" : "dis");
253 bbs = (gcs >> 10) & 0x3;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000254 printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000255
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000256 buc = mmio_readb(rcrb + 0x3414);
Uwe Hermann394131e2008-10-18 21:14:13 +0000257 printf_debug("Top Swap : %s\n",
258 (buc & 1) ? "enabled (A16 inverted)" : "not enabled");
Stefan Reinauera9424d52008-06-27 16:28:34 +0000259
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000260 /* It seems the ICH7 does not support SPI and LPC chips at the same
261 * time. At least not with our current code. So we prevent searching
262 * on ICH7 when the southbridge is strapped to LPC
263 */
264
265 if (ich_generation == 7 && bbs == ICH_STRAP_LPC) {
266 /* No further SPI initialization required */
267 return ret;
268 }
269
270 switch (ich_generation) {
271 case 7:
272 flashbus = BUS_TYPE_ICH7_SPI;
273 spibar_offset = 0x3020;
274 break;
275 case 8:
276 flashbus = BUS_TYPE_ICH9_SPI;
277 spibar_offset = 0x3020;
278 break;
279 case 9:
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000280 case 10:
Uwe Hermann394131e2008-10-18 21:14:13 +0000281 default: /* Future version might behave the same */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000282 flashbus = BUS_TYPE_ICH9_SPI;
283 spibar_offset = 0x3800;
284 break;
285 }
286
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000287 /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000288 printf_debug("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000289
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000290 /* Assign Virtual Address */
Uwe Hermann394131e2008-10-18 21:14:13 +0000291 spibar = rcrb + spibar_offset;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000292
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000293 switch (flashbus) {
294 case BUS_TYPE_ICH7_SPI:
Uwe Hermann394131e2008-10-18 21:14:13 +0000295 printf_debug("0x00: 0x%04x (SPIS)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000296 mmio_readw(spibar + 0));
Uwe Hermann394131e2008-10-18 21:14:13 +0000297 printf_debug("0x02: 0x%04x (SPIC)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000298 mmio_readw(spibar + 2));
Uwe Hermann394131e2008-10-18 21:14:13 +0000299 printf_debug("0x04: 0x%08x (SPIA)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000300 mmio_readl(spibar + 4));
Uwe Hermann394131e2008-10-18 21:14:13 +0000301 for (i = 0; i < 8; i++) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000302 int offs;
303 offs = 8 + (i * 8);
Uwe Hermann394131e2008-10-18 21:14:13 +0000304 printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs,
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000305 mmio_readl(spibar + offs), i);
Uwe Hermann394131e2008-10-18 21:14:13 +0000306 printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000307 mmio_readl(spibar + offs + 4), i);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000308 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000309 printf_debug("0x50: 0x%08x (BBAR)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000310 mmio_readl(spibar + 0x50));
Uwe Hermann394131e2008-10-18 21:14:13 +0000311 printf_debug("0x54: 0x%04x (PREOP)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000312 mmio_readw(spibar + 0x54));
Uwe Hermann394131e2008-10-18 21:14:13 +0000313 printf_debug("0x56: 0x%04x (OPTYPE)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000314 mmio_readw(spibar + 0x56));
Uwe Hermann394131e2008-10-18 21:14:13 +0000315 printf_debug("0x58: 0x%08x (OPMENU)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000316 mmio_readl(spibar + 0x58));
Uwe Hermann394131e2008-10-18 21:14:13 +0000317 printf_debug("0x5c: 0x%08x (OPMENU+4)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000318 mmio_readl(spibar + 0x5c));
Uwe Hermann394131e2008-10-18 21:14:13 +0000319 for (i = 0; i < 4; i++) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000320 int offs;
321 offs = 0x60 + (i * 4);
Uwe Hermann394131e2008-10-18 21:14:13 +0000322 printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs,
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000323 mmio_readl(spibar + offs), i);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000324 }
325 printf_debug("\n");
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000326 if (mmio_readw(spibar) & (1 << 15)) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000327 printf("WARNING: SPI Configuration Lockdown activated.\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000328 ichspi_lock = 1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000329 }
FENG yu ningf041e9b2008-12-15 02:32:11 +0000330 ich_init_opcodes();
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000331 break;
332 case BUS_TYPE_ICH9_SPI:
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000333 tmp2 = mmio_readw(spibar + 4);
FENG yu ning37179b82009-01-18 06:39:32 +0000334 printf_debug("0x04: 0x%04x (HSFS)\n", tmp2);
335 printf_debug("FLOCKDN %i, ", (tmp2 >> 15 & 1));
336 printf_debug("FDV %i, ", (tmp2 >> 14) & 1);
337 printf_debug("FDOPSS %i, ", (tmp2 >> 13) & 1);
338 printf_debug("SCIP %i, ", (tmp2 >> 5) & 1);
339 printf_debug("BERASE %i, ", (tmp2 >> 3) & 3);
340 printf_debug("AEL %i, ", (tmp2 >> 2) & 1);
341 printf_debug("FCERR %i, ", (tmp2 >> 1) & 1);
342 printf_debug("FDONE %i\n", (tmp2 >> 0) & 1);
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000343
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000344 tmp = mmio_readl(spibar + 0x50);
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000345 printf_debug("0x50: 0x%08x (FRAP)\n", tmp);
346 printf_debug("BMWAG %i, ", (tmp >> 24) & 0xff);
347 printf_debug("BMRAG %i, ", (tmp >> 16) & 0xff);
348 printf_debug("BRWA %i, ", (tmp >> 8) & 0xff);
349 printf_debug("BRRA %i\n", (tmp >> 0) & 0xff);
350
351 printf_debug("0x54: 0x%08x (FREG0)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000352 mmio_readl(spibar + 0x54));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000353 printf_debug("0x58: 0x%08x (FREG1)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000354 mmio_readl(spibar + 0x58));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000355 printf_debug("0x5C: 0x%08x (FREG2)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000356 mmio_readl(spibar + 0x5C));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000357 printf_debug("0x60: 0x%08x (FREG3)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000358 mmio_readl(spibar + 0x60));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000359 printf_debug("0x64: 0x%08x (FREG4)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000360 mmio_readl(spibar + 0x64));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000361 printf_debug("0x74: 0x%08x (PR0)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000362 mmio_readl(spibar + 0x74));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000363 printf_debug("0x78: 0x%08x (PR1)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000364 mmio_readl(spibar + 0x78));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000365 printf_debug("0x7C: 0x%08x (PR2)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000366 mmio_readl(spibar + 0x7C));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000367 printf_debug("0x80: 0x%08x (PR3)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000368 mmio_readl(spibar + 0x80));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000369 printf_debug("0x84: 0x%08x (PR4)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000370 mmio_readl(spibar + 0x84));
FENG yu ning37179b82009-01-18 06:39:32 +0000371 printf_debug("0x90: 0x%08x (SSFS, SSFC)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000372 mmio_readl(spibar + 0x90));
FENG yu ning37179b82009-01-18 06:39:32 +0000373 printf_debug("0x94: 0x%04x (PREOP)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000374 mmio_readw(spibar + 0x94));
FENG yu ning37179b82009-01-18 06:39:32 +0000375 printf_debug("0x96: 0x%04x (OPTYPE)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000376 mmio_readw(spibar + 0x96));
FENG yu ning37179b82009-01-18 06:39:32 +0000377 printf_debug("0x98: 0x%08x (OPMENU)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000378 mmio_readl(spibar + 0x98));
FENG yu ning37179b82009-01-18 06:39:32 +0000379 printf_debug("0x9C: 0x%08x (OPMENU+4)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000380 mmio_readl(spibar + 0x9C));
FENG yu ning37179b82009-01-18 06:39:32 +0000381 printf_debug("0xA0: 0x%08x (BBAR)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000382 mmio_readl(spibar + 0xA0));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000383 printf_debug("0xB0: 0x%08x (FDOC)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000384 mmio_readl(spibar + 0xB0));
FENG yu ning37179b82009-01-18 06:39:32 +0000385 if (tmp2 & (1 << 15)) {
386 printf("WARNING: SPI Configuration Lockdown activated.\n");
387 ichspi_lock = 1;
388 }
Peter Stugee8a3e4c2008-12-22 14:12:08 +0000389 ich_init_opcodes();
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000390 break;
391 default:
392 /* Nothing */
393 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000394 }
395
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000396 old = pci_read_byte(dev, 0xdc);
397 printf_debug("SPI Read Configuration: ");
398 new = (old >> 2) & 0x3;
399 switch (new) {
400 case 0:
401 case 1:
402 case 2:
403 printf_debug("prefetching %sabled, caching %sabled, ",
Uwe Hermann394131e2008-10-18 21:14:13 +0000404 (new & 0x2) ? "en" : "dis",
405 (new & 0x1) ? "dis" : "en");
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000406 break;
407 default:
408 printf_debug("invalid prefetching/caching settings, ");
409 break;
410 }
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000411
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000412 return ret;
413}
Stefan Reinauera9424d52008-06-27 16:28:34 +0000414
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000415static int enable_flash_ich7(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000416{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000417 return enable_flash_ich_dc_spi(dev, name, 7);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000418}
419
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000420static int enable_flash_ich8(struct pci_dev *dev, const char *name)
421{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000422 return enable_flash_ich_dc_spi(dev, name, 8);
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000423}
424
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000425static int enable_flash_ich9(struct pci_dev *dev, const char *name)
426{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000427 return enable_flash_ich_dc_spi(dev, name, 9);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000428}
429
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000430static int enable_flash_ich10(struct pci_dev *dev, const char *name)
431{
432 return enable_flash_ich_dc_spi(dev, name, 10);
433}
434
Uwe Hermann372eeb52007-12-04 21:49:06 +0000435static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000436{
Ollie Lho184a4042005-11-26 21:55:36 +0000437 uint8_t val;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000438
Uwe Hermann394131e2008-10-18 21:14:13 +0000439 /* enable ROM decode range (1MB) FFC00000 - FFFFFFFF */
Bari Ari9477c4e2008-04-29 13:46:38 +0000440 pci_write_byte(dev, 0x41, 0x7f);
441
Uwe Hermannffec5f32007-08-23 16:08:21 +0000442 /* ROM write enable */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000443 val = pci_read_byte(dev, 0x40);
444 val |= 0x10;
445 pci_write_byte(dev, 0x40, val);
446
447 if (pci_read_byte(dev, 0x40) != val) {
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000448 printf("\nWARNING: Failed to enable ROM Write on \"%s\"\n",
Uwe Hermanna7e05482007-05-09 10:17:44 +0000449 name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000450 return -1;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000451 }
Luc Verhaegen6382b442007-03-02 22:16:38 +0000452
Uwe Hermanna7e05482007-05-09 10:17:44 +0000453 return 0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000454}
455
Uwe Hermann372eeb52007-12-04 21:49:06 +0000456static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000457{
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000458 uint8_t reg8;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000459
Uwe Hermann394131e2008-10-18 21:14:13 +0000460#define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
461#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000462
Uwe Hermann394131e2008-10-18 21:14:13 +0000463#define LOWER_ROM_ADDRESS_RANGE (1 << 0)
464#define ROM_WRITE_ENABLE (1 << 1)
465#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
466#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000467
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000468 /* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and
469 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB.
470 * Make the configured ROM areas writable.
471 */
472 reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
473 reg8 |= LOWER_ROM_ADDRESS_RANGE;
474 reg8 |= UPPER_ROM_ADDRESS_RANGE;
475 reg8 |= ROM_WRITE_ENABLE;
476 pci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000477
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000478 /* Set positive decode on ROM. */
479 reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
480 reg8 |= BIOS_ROM_POSITIVE_DECODE;
481 pci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000482
Ollie Lhocbbf1252004-03-17 22:22:08 +0000483 return 0;
484}
485
Mart Raudseppe1344da2008-02-08 10:10:57 +0000486/**
487 * Geode systems write protect the BIOS via RCONFs (cache settings similar
488 * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22. Reading and
489 * writing to MSRs, however requires instructions rdmsr/wrmsr, which are
490 * ring0 privileged instructions so only the kernel can do the read/write.
491 * This function, therefore, requires that the msr kernel module be loaded
492 * to access these instructions from user space using device /dev/cpu/0/msr.
493 *
494 * This hard-coded location could have potential problems on SMP machines
495 * since it assumes cpu0, but it is safe on the Geode which is not SMP.
496 *
497 * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
498 * To enable write to NOR Boot flash for the benefit of systems that have such
499 * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
500 *
501 * This is probably not portable beyond Linux.
502 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000503static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
Lane Brooksd54958a2007-11-13 16:45:22 +0000504{
Uwe Hermann394131e2008-10-18 21:14:13 +0000505#define MSR_RCONF_DEFAULT 0x1808
506#define MSR_NORF_CTL 0x51400018
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000507
Lane Brooksd54958a2007-11-13 16:45:22 +0000508 int fd_msr;
509 unsigned char buf[8];
Lane Brooksd54958a2007-11-13 16:45:22 +0000510
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000511 fd_msr = open("/dev/cpu/0/msr", O_RDWR);
Bertrand Jacquinb452a912009-05-05 21:08:36 +0000512 if (fd_msr == -1) {
Peter Stuge7725fa82009-05-06 13:38:55 +0000513 perror("open(/dev/cpu/0/msr)");
514 printf("Cannot operate on MSR. Did you run 'modprobe msr'?\n");
Lane Brooksd54958a2007-11-13 16:45:22 +0000515 return -1;
516 }
Mart Raudseppe1344da2008-02-08 10:10:57 +0000517
518 if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) {
519 perror("lseek64");
520 close(fd_msr);
521 return -1;
522 }
523
524 if (read(fd_msr, buf, 8) != 8) {
Mart Raudsepp3697ac72008-02-11 14:32:45 +0000525 perror("read msr");
Mart Raudseppe1344da2008-02-08 10:10:57 +0000526 close(fd_msr);
527 return -1;
528 }
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000529
Lane Brooksd54958a2007-11-13 16:45:22 +0000530 if (buf[7] != 0x22) {
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000531 buf[7] &= 0xfb;
Uwe Hermann394131e2008-10-18 21:14:13 +0000532 if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT,
533 SEEK_SET) == -1) {
Mart Raudseppe1344da2008-02-08 10:10:57 +0000534 perror("lseek64");
535 close(fd_msr);
536 return -1;
537 }
538
Lane Brooksd54958a2007-11-13 16:45:22 +0000539 if (write(fd_msr, buf, 8) < 0) {
540 perror("msr write");
Mart Raudseppe1344da2008-02-08 10:10:57 +0000541 close(fd_msr);
Lane Brooksd54958a2007-11-13 16:45:22 +0000542 return -1;
543 }
Lane Brooksd54958a2007-11-13 16:45:22 +0000544 }
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000545
Mart Raudseppe1344da2008-02-08 10:10:57 +0000546 if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) {
547 perror("lseek64");
548 close(fd_msr);
549 return -1;
550 }
551
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000552 if (read(fd_msr, buf, 8) != 8) {
553 perror("read msr");
Mart Raudseppe1344da2008-02-08 10:10:57 +0000554 close(fd_msr);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000555 return -1;
556 }
557
558 /* Raise WE_CS3 bit. */
559 buf[0] |= 0x08;
560
Mart Raudseppe1344da2008-02-08 10:10:57 +0000561 if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) {
562 perror("lseek64");
563 close(fd_msr);
564 return -1;
565 }
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000566 if (write(fd_msr, buf, 8) < 0) {
567 perror("msr write");
Mart Raudseppe1344da2008-02-08 10:10:57 +0000568 close(fd_msr);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000569 return -1;
570 }
571
572 close(fd_msr);
573
Uwe Hermann394131e2008-10-18 21:14:13 +0000574#undef MSR_RCONF_DEFAULT
575#undef MSR_NORF_CTL
Lane Brooksd54958a2007-11-13 16:45:22 +0000576 return 0;
577}
578
Uwe Hermann372eeb52007-12-04 21:49:06 +0000579static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000580{
Ollie Lho184a4042005-11-26 21:55:36 +0000581 uint8_t new;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000582
Ollie Lhocbbf1252004-03-17 22:22:08 +0000583 pci_write_byte(dev, 0x52, 0xee);
584
585 new = pci_read_byte(dev, 0x52);
586
587 if (new != 0xee) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000588 printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000589 return -1;
590 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000591
Ollie Lhocbbf1252004-03-17 22:22:08 +0000592 return 0;
593}
594
Uwe Hermann372eeb52007-12-04 21:49:06 +0000595static int enable_flash_sis5595(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000596{
Ollie Lho184a4042005-11-26 21:55:36 +0000597 uint8_t new, newer;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000598
Ollie Lhocbbf1252004-03-17 22:22:08 +0000599 new = pci_read_byte(dev, 0x45);
600
Uwe Hermann372eeb52007-12-04 21:49:06 +0000601 new &= (~0x20); /* Clear bit 5. */
602 new |= 0x4; /* Set bit 2. */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000603
604 pci_write_byte(dev, 0x45, new);
605
606 newer = pci_read_byte(dev, 0x45);
607 if (newer != new) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000608 printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000609 printf("Stuck at 0x%x\n", newer);
610 return -1;
611 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000612
Urja Rannikkoa88daa72008-10-18 13:54:30 +0000613 /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */
Uwe Hermann394131e2008-10-18 21:14:13 +0000614 new = pci_read_byte(dev, 0x40);
Urja Rannikkoa88daa72008-10-18 13:54:30 +0000615 new &= 0xFB;
616 new |= 0x3;
Uwe Hermann394131e2008-10-18 21:14:13 +0000617 pci_write_byte(dev, 0x40, new);
618 newer = pci_read_byte(dev, 0x40);
Urja Rannikkoa88daa72008-10-18 13:54:30 +0000619 if (newer != new) {
620 printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
621 printf("Stuck at 0x%x\n", newer);
622 return -1;
623 }
Ollie Lhocbbf1252004-03-17 22:22:08 +0000624 return 0;
625}
626
Uwe Hermann190f8492008-10-25 18:03:50 +0000627/* Works for AMD-8111, VIA VT82C586A/B, VIA VT82C686A/B. */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000628static int enable_flash_amd8111(struct pci_dev *dev, const char *name)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000629{
Ollie Lho184a4042005-11-26 21:55:36 +0000630 uint8_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000631
Uwe Hermann372eeb52007-12-04 21:49:06 +0000632 /* Enable decoding at 0xffb00000 to 0xffffffff. */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000633 old = pci_read_byte(dev, 0x43);
Ollie Lhod11f3612004-12-07 17:19:04 +0000634 new = old | 0xC0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000635 if (new != old) {
636 pci_write_byte(dev, 0x43, new);
637 if (pci_read_byte(dev, 0x43) != new) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000638 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000639 }
640 }
641
Uwe Hermann190f8492008-10-25 18:03:50 +0000642 /* Enable 'ROM write' bit. */
Ollie Lho761bf1b2004-03-20 16:46:10 +0000643 old = pci_read_byte(dev, 0x40);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000644 new = old | 0x01;
645 if (new == old)
646 return 0;
647 pci_write_byte(dev, 0x40, new);
648
649 if (pci_read_byte(dev, 0x40) != new) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000650 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000651 return -1;
652 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000653
Ollie Lhocbbf1252004-03-17 22:22:08 +0000654 return 0;
655}
656
Marc Jones3af487d2008-10-15 17:50:29 +0000657static int enable_flash_sb600(struct pci_dev *dev, const char *name)
658{
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000659 uint32_t tmp, prot;
Marc Jones3af487d2008-10-15 17:50:29 +0000660 uint8_t reg;
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000661 struct pci_dev *smbus_dev;
662 int has_spi = 1;
Marc Jones3af487d2008-10-15 17:50:29 +0000663
Jason Wanga3f04be2008-11-28 21:36:51 +0000664 /* Clear ROM protect 0-3. */
665 for (reg = 0x50; reg < 0x60; reg += 4) {
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000666 prot = pci_read_long(dev, reg);
667 /* No protection flags for this region?*/
668 if ((prot & 0x3) == 0)
669 continue;
670 printf_debug("SB600 %s%sprotected from %u to %u\n",
671 (prot & 0x1) ? "write " : "",
672 (prot & 0x2) ? "read " : "",
673 (prot & 0xfffffc00),
674 (prot & 0xfffffc00) + ((prot & 0x3ff) << 8));
675 prot &= 0xfffffffc;
676 pci_write_byte(dev, reg, prot);
677 prot = pci_read_long(dev, reg);
Carl-Daniel Hailfinger9bb88ac2009-05-06 13:51:44 +0000678 if (prot & 0x3)
Peter Stuge19997ae2009-05-06 15:05:39 +0000679 printf("SB600 %s%sunprotect failed from %u to %u\n",
Carl-Daniel Hailfinger9bb88ac2009-05-06 13:51:44 +0000680 (prot & 0x1) ? "write " : "",
681 (prot & 0x2) ? "read " : "",
682 (prot & 0xfffffc00),
683 (prot & 0xfffffc00) + ((prot & 0x3ff) << 8));
Jason Wanga3f04be2008-11-28 21:36:51 +0000684 }
685
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000686 /* Read SPI_BaseAddr */
687 tmp = pci_read_long(dev, 0xa0);
688 tmp &= 0xfffffff0; /* remove low 4 bits (reserved) */
689 printf_debug("SPI base address is at 0x%x\n", tmp);
690
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000691 /* If the BAR has address 0, it is unlikely SPI is used. */
692 if (!tmp)
693 has_spi = 0;
694
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000695 /* Physical memory can only be mapped at page (4k) boundaries */
696 sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000);
697 /* The low bits of the SPI base address are used as offset into the mapped page */
698 sb600_spibar += tmp & 0xfff;
699
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000700 /* Look for the SMBus device. */
701 smbus_dev = pci_dev_find(0x1002, 0x4385);
702
703 if (!smbus_dev) {
704 fprintf(stderr, "ERROR: SMBus device not found. Not enabling SPI.\n");
705 has_spi = 0;
706 } else {
707 /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */
708 /* GPIO11/SPI_DO and GPIO12/SPI_DI status */
709 reg = pci_read_byte(smbus_dev, 0xAB);
710 reg &= 0xC0;
711 printf_debug("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO");
712 printf_debug("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI");
713 if (reg != 0x00)
714 has_spi = 0;
715 /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */
716 reg = pci_read_byte(smbus_dev, 0x83);
717 reg &= 0xC0;
718 printf_debug("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD");
719 printf_debug("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000720 /* SPI_HOLD is not used on all boards, filter it out. */
721 if ((reg & 0x80) != 0x00)
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000722 has_spi = 0;
723 /* GPIO47/SPI_CLK status */
724 reg = pci_read_byte(smbus_dev, 0xA7);
725 reg &= 0x40;
726 printf_debug("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK");
727 if (reg != 0x00)
728 has_spi = 0;
729 }
730
731 if (has_spi)
732 flashbus = BUS_TYPE_SB600_SPI;
Jason Wanga3f04be2008-11-28 21:36:51 +0000733
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000734 /* Read ROM strap override register. */
735 OUTB(0x8f, 0xcd6);
736 reg = INB(0xcd7);
737 reg &= 0x0e;
738 printf_debug("ROM strap override is %sactive", (reg & 0x02) ? "" : "not ");
739 if (reg & 0x02) {
740 switch ((reg & 0x0c) >> 2) {
741 case 0x00:
742 printf_debug(": LPC");
743 break;
744 case 0x01:
745 printf_debug(": PCI");
746 break;
747 case 0x02:
748 printf_debug(": FWH");
749 break;
750 case 0x03:
751 printf_debug(": SPI");
752 break;
753 }
754 }
755 printf_debug("\n");
756
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000757 /* Force enable SPI ROM in SB600 PM register.
758 * If we enable SPI ROM here, we have to disable it after we leave.
Zheng Bao284a6002009-05-04 22:33:50 +0000759 * But how can we know which ROM we are going to handle? So we have
760 * to trade off. We only access LPC ROM if we boot via LPC ROM. And
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000761 * only SPI ROM if we boot via SPI ROM. If you want to access SPI on
762 * boards with LPC straps, you have to use the code below.
Zheng Bao284a6002009-05-04 22:33:50 +0000763 */
764 /*
Jason Wanga3f04be2008-11-28 21:36:51 +0000765 OUTB(0x8f, 0xcd6);
766 OUTB(0x0e, 0xcd7);
Zheng Bao284a6002009-05-04 22:33:50 +0000767 */
Marc Jones3af487d2008-10-15 17:50:29 +0000768
769 return 0;
770}
771
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000772static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name)
773{
774 uint8_t tmp;
775
776 pci_write_byte(dev, 0x92, 0);
777
778 tmp = pci_read_byte(dev, 0x6d);
779 tmp |= 0x01;
780 pci_write_byte(dev, 0x6d, tmp);
781
782 return 0;
783}
784
Uwe Hermann372eeb52007-12-04 21:49:06 +0000785static int enable_flash_ck804(struct pci_dev *dev, const char *name)
Yinghai Lu952dfce2005-07-06 17:13:46 +0000786{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000787 uint8_t old, new;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000788
Uwe Hermanna7e05482007-05-09 10:17:44 +0000789 old = pci_read_byte(dev, 0x88);
790 new = old | 0xc0;
791 if (new != old) {
792 pci_write_byte(dev, 0x88, new);
793 if (pci_read_byte(dev, 0x88) != new) {
794 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name);
795 }
796 }
Yinghai Lu952dfce2005-07-06 17:13:46 +0000797
Uwe Hermanna7e05482007-05-09 10:17:44 +0000798 old = pci_read_byte(dev, 0x6d);
799 new = old | 0x01;
800 if (new == old)
801 return 0;
802 pci_write_byte(dev, 0x6d, new);
803
804 if (pci_read_byte(dev, 0x6d) != new) {
805 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
806 return -1;
807 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000808
Uwe Hermanna7e05482007-05-09 10:17:44 +0000809 return 0;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000810}
811
Uwe Hermann372eeb52007-12-04 21:49:06 +0000812/* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
813static int enable_flash_sb400(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000814{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000815 uint8_t tmp;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000816 struct pci_dev *smbusdev;
817
Uwe Hermann372eeb52007-12-04 21:49:06 +0000818 /* Look for the SMBus device. */
Carl-Daniel Hailfingerf6e3efb2009-05-06 00:35:31 +0000819 smbusdev = pci_dev_find(0x1002, 0x4372);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000820
Uwe Hermanna7e05482007-05-09 10:17:44 +0000821 if (!smbusdev) {
Uwe Hermann372eeb52007-12-04 21:49:06 +0000822 fprintf(stderr, "ERROR: SMBus device not found. Aborting.\n");
Stefan Reinauer86de2832006-03-31 11:26:55 +0000823 exit(1);
824 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000825
Uwe Hermann372eeb52007-12-04 21:49:06 +0000826 /* Enable some SMBus stuff. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000827 tmp = pci_read_byte(smbusdev, 0x79);
828 tmp |= 0x01;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000829 pci_write_byte(smbusdev, 0x79, tmp);
830
Uwe Hermann372eeb52007-12-04 21:49:06 +0000831 /* Change southbridge. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000832 tmp = pci_read_byte(dev, 0x48);
833 tmp |= 0x21;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000834 pci_write_byte(dev, 0x48, tmp);
835
Uwe Hermann372eeb52007-12-04 21:49:06 +0000836 /* Now become a bit silly. */
Andriy Gapon65c1b862008-05-22 13:22:45 +0000837 tmp = INB(0xc6f);
838 OUTB(tmp, 0xeb);
839 OUTB(tmp, 0xeb);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000840 tmp |= 0x40;
Andriy Gapon65c1b862008-05-22 13:22:45 +0000841 OUTB(tmp, 0xc6f);
842 OUTB(tmp, 0xeb);
843 OUTB(tmp, 0xeb);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000844
845 return 0;
846}
847
Uwe Hermann372eeb52007-12-04 21:49:06 +0000848static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
Yinghai Luca782972007-01-22 20:21:17 +0000849{
Uwe Hermann372eeb52007-12-04 21:49:06 +0000850 uint8_t old, new, byte;
851 uint16_t word;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000852
Uwe Hermann372eeb52007-12-04 21:49:06 +0000853 /* Set the 0-16 MB enable bits. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000854 byte = pci_read_byte(dev, 0x88);
855 byte |= 0xff; /* 256K */
856 pci_write_byte(dev, 0x88, byte);
857 byte = pci_read_byte(dev, 0x8c);
858 byte |= 0xff; /* 1M */
859 pci_write_byte(dev, 0x8c, byte);
860 word = pci_read_word(dev, 0x90);
Carl-Daniel Hailfingerdca0ab12007-10-17 22:30:07 +0000861 word |= 0x7fff; /* 16M */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000862 pci_write_word(dev, 0x90, word);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000863
Uwe Hermanna7e05482007-05-09 10:17:44 +0000864 old = pci_read_byte(dev, 0x6d);
865 new = old | 0x01;
866 if (new == old)
867 return 0;
868 pci_write_byte(dev, 0x6d, new);
Yinghai Luca782972007-01-22 20:21:17 +0000869
Uwe Hermanna7e05482007-05-09 10:17:44 +0000870 if (pci_read_byte(dev, 0x6d) != new) {
Uwe Hermann394131e2008-10-18 21:14:13 +0000871 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000872 return -1;
873 }
Yinghai Luca782972007-01-22 20:21:17 +0000874
875 return 0;
Yinghai Luca782972007-01-22 20:21:17 +0000876}
877
Uwe Hermann372eeb52007-12-04 21:49:06 +0000878static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000879{
Uwe Hermanne823ee02007-06-05 15:02:18 +0000880 uint8_t byte;
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000881
Uwe Hermanne823ee02007-06-05 15:02:18 +0000882 /* Set the 4MB enable bit. */
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000883 byte = pci_read_byte(dev, 0x41);
884 byte |= 0x0e;
885 pci_write_byte(dev, 0x41, byte);
886
887 byte = pci_read_byte(dev, 0x43);
Uwe Hermannffec5f32007-08-23 16:08:21 +0000888 byte |= (1 << 4);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000889 pci_write_byte(dev, 0x43, byte);
890
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000891 return 0;
892}
893
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000894/**
895 * Usually on the x86 architectures (and on other PC-like platforms like some
896 * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD
897 * Elan SC520 only a small piece of the system flash is mapped there, but the
898 * complete flash is mapped somewhere below 1G. The position can be determined
899 * by the BOOTCS PAR register.
900 */
901static int get_flashbase_sc520(struct pci_dev *dev, const char *name)
902{
903 int i, bootcs_found = 0;
904 uint32_t parx = 0;
905 void *mmcr;
906
907 /* 1. Map MMCR */
Stefan Reinauer0593f212009-01-26 01:10:48 +0000908 mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000909
910 /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for
911 * BOOTCS region (PARx[31:29] = 100b)e
912 */
913 for (i = 0x88; i <= 0xc4; i += 4) {
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000914 parx = mmio_readl(mmcr + i);
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000915 if ((parx >> 29) == 4) {
916 bootcs_found = 1;
917 break; /* BOOTCS found */
918 }
919 }
920
921 /* 3. PARx[25] = 1b --> flashbase[29:16] = PARx[13:0]
922 * PARx[25] = 0b --> flashbase[29:12] = PARx[17:0]
923 */
924 if (bootcs_found) {
925 if (parx & (1 << 25)) {
926 parx &= (1 << 14) - 1; /* Mask [13:0] */
927 flashbase = parx << 16;
928 } else {
929 parx &= (1 << 18) - 1; /* Mask [17:0] */
930 flashbase = parx << 12;
931 }
932 } else {
933 printf("AMD Elan SC520 detected, but no BOOTCS. Assuming flash at 4G\n");
934 }
935
936 /* 4. Clean up */
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000937 munmap(mmcr, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000938 return 0;
939}
940
Uwe Hermannb0039912009-05-07 13:24:49 +0000941#define OK 0
942#define NT 1 /* Not tested */
943
Uwe Hermann4179d292009-05-08 17:50:51 +0000944/* Please keep this list alphabetically sorted by vendor/device. */
Uwe Hermann05fab752009-05-16 23:42:17 +0000945const struct penable chipset_enables[] = {
Uwe Hermann4179d292009-05-08 17:50:51 +0000946 {0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533},
947 {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111},
948 {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111},
949 {0x1078, 0x0100, OK, "AMD", "CS5530(A)", enable_flash_cs5530},
950 {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536},
951 {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520},
952 {0x1002, 0x438D, OK, "AMD", "SB600", enable_flash_sb600},
953 {0x1002, 0x439d, OK, "AMD", "SB700", enable_flash_sb600},
954 {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100},
955 {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400},
956 {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000},
Uwe Hermannb0039912009-05-07 13:24:49 +0000957 {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4},
Uwe Hermann4179d292009-05-08 17:50:51 +0000958 {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich_4e},
959 {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich_dc},
960 {0x8086, 0x5031, OK, "Intel", "EP80579", enable_flash_ich7},
Uwe Hermannb0039912009-05-07 13:24:49 +0000961 {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich_4e},
Uwe Hermann4179d292009-05-08 17:50:51 +0000962 {0x8086, 0x3a18, OK, "Intel", "ICH10", enable_flash_ich10},
963 {0x8086, 0x3a1a, OK, "Intel", "ICH10D", enable_flash_ich10},
964 {0x8086, 0x3a14, OK, "Intel", "ICH10DO", enable_flash_ich10},
965 {0x8086, 0x3a16, OK, "Intel", "ICH10R", enable_flash_ich10},
Uwe Hermannb0039912009-05-07 13:24:49 +0000966 {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich_4e},
967 {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +0000968 {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich_4e},
Uwe Hermann4179d292009-05-08 17:50:51 +0000969 {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +0000970 {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich_4e},
971 {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich_4e},
972 {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +0000973 {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich_dc},
974 {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich_dc},
Uwe Hermannb0039912009-05-07 13:24:49 +0000975 {0x8086, 0x27b0, OK, "Intel", "ICH7DH", enable_flash_ich7},
976 {0x8086, 0x27b8, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7},
977 {0x8086, 0x27b9, OK, "Intel", "ICH7M", enable_flash_ich7},
978 {0x8086, 0x27bd, OK, "Intel", "ICH7MDH", enable_flash_ich7},
Uwe Hermann4179d292009-05-08 17:50:51 +0000979 {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +0000980 {0x8086, 0x2812, OK, "Intel", "ICH8DH", enable_flash_ich8},
981 {0x8086, 0x2814, OK, "Intel", "ICH8DO", enable_flash_ich8},
Uwe Hermann4179d292009-05-08 17:50:51 +0000982 {0x8086, 0x2810, OK, "Intel", "ICH8/ICH8R", enable_flash_ich8},
Uwe Hermannb0039912009-05-07 13:24:49 +0000983 {0x8086, 0x2815, OK, "Intel", "ICH8M", enable_flash_ich8},
Uwe Hermann4179d292009-05-08 17:50:51 +0000984 {0x8086, 0x2811, OK, "Intel", "ICH8M-E", enable_flash_ich8},
985 {0x8086, 0x2918, OK, "Intel", "ICH9", enable_flash_ich9},
Uwe Hermannb0039912009-05-07 13:24:49 +0000986 {0x8086, 0x2912, OK, "Intel", "ICH9DH", enable_flash_ich9},
987 {0x8086, 0x2914, OK, "Intel", "ICH9DO", enable_flash_ich9},
Uwe Hermannb0039912009-05-07 13:24:49 +0000988 {0x8086, 0x2919, OK, "Intel", "ICH9M", enable_flash_ich9},
Uwe Hermann4179d292009-05-08 17:50:51 +0000989 {0x8086, 0x2917, OK, "Intel", "ICH9M-E", enable_flash_ich9},
990 {0x8086, 0x2916, OK, "Intel", "ICH9R", enable_flash_ich9},
991 {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4},
992 {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4},
993 {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4},
994 {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4},
Uwe Hermannb0039912009-05-07 13:24:49 +0000995 {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */
996 {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000997 {0x10de, 0x0060, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2},
Uwe Hermanneac10162008-03-13 18:52:51 +0000998 /* Slave, should not be here, to fix known bug for A01. */
Uwe Hermannb0039912009-05-07 13:24:49 +0000999 {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804},
1000 {0x10de, 0x0260, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1001 {0x10de, 0x0261, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1002 {0x10de, 0x0262, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1003 {0x10de, 0x0263, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1004 {0x10de, 0x0360, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* M57SLI*/
1005 {0x10de, 0x0361, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1006 {0x10de, 0x0362, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1007 {0x10de, 0x0363, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1008 {0x10de, 0x0364, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1009 {0x10de, 0x0365, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1010 {0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1011 {0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */
1012 {0x10de, 0x0548, OK, "NVIDIA", "MCP67", enable_flash_mcp55},
Uwe Hermann4179d292009-05-08 17:50:51 +00001013 {0x1039, 0x0008, OK, "SiS", "SiS5595", enable_flash_sis5595},
1014 {0x1039, 0x0630, NT, "SiS", "SiS630", enable_flash_sis630},
1015 {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x},
1016 {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x},
1017 {0x1106, 0x3177, OK, "VIA", "VT8235", enable_flash_vt823x},
1018 {0x1106, 0x3227, OK, "VIA", "VT8237", enable_flash_vt823x},
1019 {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x},
1020 {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi},
1021 {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111},
1022 {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111},
Uwe Hermann05fab752009-05-16 23:42:17 +00001023
1024 {},
Ollie Lhocbbf1252004-03-17 22:22:08 +00001025};
Ollie Lho761bf1b2004-03-20 16:46:10 +00001026
Uwe Hermanne5ac1642008-03-12 11:54:51 +00001027void print_supported_chipsets(void)
1028{
Uwe Hermanne8ba5382009-05-22 11:37:27 +00001029 int i, j;
1030 const struct penable *c = chipset_enables;
Uwe Hermanne5ac1642008-03-12 11:54:51 +00001031
Uwe Hermanne8ba5382009-05-22 11:37:27 +00001032 printf("\nSupported chipsets:\n\nVendor: Chipset:"
1033 " PCI IDs:\n\n");
Uwe Hermanne5ac1642008-03-12 11:54:51 +00001034
Uwe Hermanne8ba5382009-05-22 11:37:27 +00001035 for (i = 0; c[i].vendor_name != NULL; i++) {
1036 printf("%s", c[i].vendor_name);
1037 for (j = 0; j < 25 - strlen(c[i].vendor_name); j++)
1038 printf(" ");
1039 printf("%s", c[i].device_name);
1040 for (j = 0; j < 25 - strlen(c[i].device_name); j++)
1041 printf(" ");
1042 printf("%04x:%04x%s\n", c[i].vendor_id, c[i].device_id,
1043 (c[i].status == OK) ? "" : " (untested)");
Uwe Hermann05fab752009-05-16 23:42:17 +00001044 }
Uwe Hermanne5ac1642008-03-12 11:54:51 +00001045}
1046
Uwe Hermanna7e05482007-05-09 10:17:44 +00001047int chipset_flash_enable(void)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001048{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001049 struct pci_dev *dev = 0;
Uwe Hermann372eeb52007-12-04 21:49:06 +00001050 int ret = -2; /* Nothing! */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001051 int i;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001052
Uwe Hermann372eeb52007-12-04 21:49:06 +00001053 /* Now let's try to find the chipset we have... */
Uwe Hermann05fab752009-05-16 23:42:17 +00001054 for (i = 0; chipset_enables[i].vendor_name != NULL; i++) {
1055 dev = pci_dev_find(chipset_enables[i].vendor_id,
1056 chipset_enables[i].device_id);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001057 if (dev)
1058 break;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001059 }
1060
Uwe Hermanna7e05482007-05-09 10:17:44 +00001061 if (dev) {
Uwe Hermannb0039912009-05-07 13:24:49 +00001062 printf("Found chipset \"%s %s\", enabling flash write... ",
Uwe Hermann05fab752009-05-16 23:42:17 +00001063 chipset_enables[i].vendor_name,
1064 chipset_enables[i].device_name);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001065
Uwe Hermann05fab752009-05-16 23:42:17 +00001066 ret = chipset_enables[i].doit(dev,
1067 chipset_enables[i].device_name);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001068 if (ret)
Uwe Hermanna502dce2007-10-17 23:55:15 +00001069 printf("FAILED!\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +00001070 else
Uwe Hermannac309342007-10-10 17:42:20 +00001071 printf("OK.\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +00001072 }
1073
1074 return ret;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001075}