Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 1 | /* |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 2 | * This file is part of the flashrom project. |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 3 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 4 | * Copyright (C) 2000 Silicon Integrated System Corporation |
| 5 | * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de> |
| 6 | * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de> |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 7 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 11 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | /* |
| 23 | * Contains the chipset specific flash enables. |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 24 | */ |
| 25 | |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 26 | #define _LARGEFILE64_SOURCE |
| 27 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 28 | #include <stdio.h> |
| 29 | #include <pci/pci.h> |
| 30 | #include <stdlib.h> |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 31 | #include <sys/types.h> |
| 32 | #include <sys/stat.h> |
| 33 | #include <fcntl.h> |
| 34 | #include <unistd.h> |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 35 | #include "flash.h" |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 36 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 37 | static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 38 | { |
| 39 | uint8_t tmp; |
| 40 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 41 | /* |
| 42 | * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and |
| 43 | * 0xFFFE0000-0xFFFFFFFF ROM select enable. |
| 44 | */ |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 45 | tmp = pci_read_byte(dev, 0x47); |
| 46 | tmp |= 0x46; |
| 47 | pci_write_byte(dev, 0x47, tmp); |
| 48 | |
| 49 | return 0; |
| 50 | } |
| 51 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 52 | static int enable_flash_sis630(struct pci_dev *dev, const char *name) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 53 | { |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 54 | uint8_t b; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 55 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 56 | /* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */ |
Alex Beregszaszi | c9fb5d9 | 2007-09-11 15:58:18 +0000 | [diff] [blame] | 57 | b = pci_read_byte(dev, 0x40); |
| 58 | pci_write_byte(dev, 0x40, b | 0xb); |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 59 | |
| 60 | /* Flash write enable on SiS 540/630. */ |
Alex Beregszaszi | c9fb5d9 | 2007-09-11 15:58:18 +0000 | [diff] [blame] | 61 | b = pci_read_byte(dev, 0x45); |
| 62 | pci_write_byte(dev, 0x45, b | 0x40); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 63 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 64 | /* The same thing on SiS 950 Super I/O side... */ |
| 65 | |
| 66 | /* First probe for Super I/O on config port 0x2e. */ |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 67 | outb(0x87, 0x2e); |
| 68 | outb(0x01, 0x2e); |
| 69 | outb(0x55, 0x2e); |
| 70 | outb(0x55, 0x2e); |
| 71 | |
| 72 | if (inb(0x2f) != 0x87) { |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 73 | /* If that failed, try config port 0x4e. */ |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 74 | outb(0x87, 0x4e); |
| 75 | outb(0x01, 0x4e); |
| 76 | outb(0x55, 0x4e); |
| 77 | outb(0xaa, 0x4e); |
| 78 | if (inb(0x4f) != 0x87) { |
| 79 | printf("Can not access SiS 950\n"); |
| 80 | return -1; |
| 81 | } |
| 82 | outb(0x24, 0x4e); |
| 83 | b = inb(0x4f) | 0xfc; |
| 84 | outb(0x24, 0x4e); |
| 85 | outb(b, 0x4f); |
| 86 | outb(0x02, 0x4e); |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 87 | outb(0x02, 0x4f); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 88 | } |
| 89 | |
| 90 | outb(0x24, 0x2e); |
| 91 | printf("2f is %#x\n", inb(0x2f)); |
| 92 | b = inb(0x2f) | 0xfc; |
| 93 | outb(0x24, 0x2e); |
| 94 | outb(b, 0x2f); |
| 95 | |
| 96 | outb(0x02, 0x2e); |
| 97 | outb(0x02, 0x2f); |
| 98 | |
| 99 | return 0; |
| 100 | } |
| 101 | |
Uwe Hermann | 987942d | 2006-11-07 11:16:21 +0000 | [diff] [blame] | 102 | /* Datasheet: |
| 103 | * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4) |
| 104 | * - URL: http://www.intel.com/design/intarch/datashts/290562.htm |
| 105 | * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf |
| 106 | * - Order Number: 290562-001 |
| 107 | */ |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 108 | static int enable_flash_piix4(struct pci_dev *dev, const char *name) |
Uwe Hermann | ea2c66d | 2006-11-05 18:26:08 +0000 | [diff] [blame] | 109 | { |
| 110 | uint16_t old, new; |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 111 | uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */ |
Uwe Hermann | ea2c66d | 2006-11-05 18:26:08 +0000 | [diff] [blame] | 112 | |
| 113 | old = pci_read_word(dev, xbcs); |
| 114 | |
| 115 | /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 116 | * FFF00000-FFF7FFFF are forwarded to ISA). |
| 117 | * Set bit 7: Extended BIOS Enable (PCI master accesses to |
| 118 | * FFF80000-FFFDFFFF are forwarded to ISA). |
| 119 | * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to |
| 120 | * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top |
| 121 | * of 1 Mbyte, or the aliases at the top of 4 Gbyte |
| 122 | * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#. |
| 123 | * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA. |
| 124 | * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable). |
| 125 | */ |
Uwe Hermann | ea2c66d | 2006-11-05 18:26:08 +0000 | [diff] [blame] | 126 | new = old | 0x2c4; |
| 127 | |
| 128 | if (new == old) |
| 129 | return 0; |
| 130 | |
| 131 | pci_write_word(dev, xbcs, new); |
| 132 | |
| 133 | if (pci_read_word(dev, xbcs) != new) { |
| 134 | printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name); |
| 135 | return -1; |
| 136 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 137 | |
Uwe Hermann | ea2c66d | 2006-11-05 18:26:08 +0000 | [diff] [blame] | 138 | return 0; |
| 139 | } |
| 140 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 141 | /* |
| 142 | * See ie. page 375 of "Intel ICH7 External Design Specification" |
| 143 | * http://download.intel.com/design/chipsets/datashts/30701302.pdf |
| 144 | */ |
| 145 | static int enable_flash_ich(struct pci_dev *dev, const char *name, |
| 146 | int bios_cntl) |
Ronald G. Minnich | 6a96741 | 2004-09-28 20:09:06 +0000 | [diff] [blame] | 147 | { |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 148 | uint8_t old, new; |
Stefan Reinauer | eb36647 | 2006-09-06 15:48:48 +0000 | [diff] [blame] | 149 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 150 | /* |
| 151 | * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 152 | * just treating it as 8 bit wide seems to work fine in practice. |
Stefan Reinauer | eb36647 | 2006-09-06 15:48:48 +0000 | [diff] [blame] | 153 | */ |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 154 | old = pci_read_byte(dev, bios_cntl); |
Ronald G. Minnich | 6a96741 | 2004-09-28 20:09:06 +0000 | [diff] [blame] | 155 | |
| 156 | new = old | 1; |
| 157 | |
| 158 | if (new == old) |
| 159 | return 0; |
| 160 | |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 161 | pci_write_byte(dev, bios_cntl, new); |
Ronald G. Minnich | 6a96741 | 2004-09-28 20:09:06 +0000 | [diff] [blame] | 162 | |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 163 | if (pci_read_byte(dev, bios_cntl) != new) { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 164 | printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name); |
Ronald G. Minnich | 6a96741 | 2004-09-28 20:09:06 +0000 | [diff] [blame] | 165 | return -1; |
| 166 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 167 | |
Ronald G. Minnich | 6a96741 | 2004-09-28 20:09:06 +0000 | [diff] [blame] | 168 | return 0; |
| 169 | } |
| 170 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 171 | static int enable_flash_ich_4e(struct pci_dev *dev, const char *name) |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 172 | { |
Stefan Reinauer | eb36647 | 2006-09-06 15:48:48 +0000 | [diff] [blame] | 173 | return enable_flash_ich(dev, name, 0x4e); |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 174 | } |
| 175 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 176 | static int enable_flash_ich_dc(struct pci_dev *dev, const char *name) |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 177 | { |
Stefan Reinauer | eb36647 | 2006-09-06 15:48:48 +0000 | [diff] [blame] | 178 | return enable_flash_ich(dev, name, 0xdc); |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 179 | } |
| 180 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 181 | static int enable_flash_vt823x(struct pci_dev *dev, const char *name) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 182 | { |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 183 | uint8_t val; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 184 | |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 185 | /* ROM write enable */ |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 186 | val = pci_read_byte(dev, 0x40); |
| 187 | val |= 0x10; |
| 188 | pci_write_byte(dev, 0x40, val); |
| 189 | |
| 190 | if (pci_read_byte(dev, 0x40) != val) { |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 191 | printf("\nWARNING: Failed to enable ROM Write on \"%s\"\n", |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 192 | name); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 193 | return -1; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 194 | } |
Luc Verhaegen | 6382b44 | 2007-03-02 22:16:38 +0000 | [diff] [blame] | 195 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 196 | return 0; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 197 | } |
| 198 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 199 | static int enable_flash_cs5530(struct pci_dev *dev, const char *name) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 200 | { |
Uwe Hermann | f4a673b | 2007-06-06 21:35:45 +0000 | [diff] [blame] | 201 | uint8_t reg8; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 202 | |
Uwe Hermann | f4a673b | 2007-06-06 21:35:45 +0000 | [diff] [blame] | 203 | #define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */ |
| 204 | #define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */ |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 205 | |
Uwe Hermann | f4a673b | 2007-06-06 21:35:45 +0000 | [diff] [blame] | 206 | #define LOWER_ROM_ADDRESS_RANGE (1 << 0) |
| 207 | #define ROM_WRITE_ENABLE (1 << 1) |
| 208 | #define UPPER_ROM_ADDRESS_RANGE (1 << 2) |
| 209 | #define BIOS_ROM_POSITIVE_DECODE (1 << 5) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 210 | |
Uwe Hermann | f4a673b | 2007-06-06 21:35:45 +0000 | [diff] [blame] | 211 | /* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and |
| 212 | * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB. |
| 213 | * Make the configured ROM areas writable. |
| 214 | */ |
| 215 | reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG); |
| 216 | reg8 |= LOWER_ROM_ADDRESS_RANGE; |
| 217 | reg8 |= UPPER_ROM_ADDRESS_RANGE; |
| 218 | reg8 |= ROM_WRITE_ENABLE; |
| 219 | pci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 220 | |
Uwe Hermann | f4a673b | 2007-06-06 21:35:45 +0000 | [diff] [blame] | 221 | /* Set positive decode on ROM. */ |
| 222 | reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2); |
| 223 | reg8 |= BIOS_ROM_POSITIVE_DECODE; |
| 224 | pci_write_byte(dev, DECODE_CONTROL_REG2, reg8); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 225 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 226 | return 0; |
| 227 | } |
| 228 | |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame^] | 229 | /** |
| 230 | * Geode systems write protect the BIOS via RCONFs (cache settings similar |
| 231 | * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22. Reading and |
| 232 | * writing to MSRs, however requires instructions rdmsr/wrmsr, which are |
| 233 | * ring0 privileged instructions so only the kernel can do the read/write. |
| 234 | * This function, therefore, requires that the msr kernel module be loaded |
| 235 | * to access these instructions from user space using device /dev/cpu/0/msr. |
| 236 | * |
| 237 | * This hard-coded location could have potential problems on SMP machines |
| 238 | * since it assumes cpu0, but it is safe on the Geode which is not SMP. |
| 239 | * |
| 240 | * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL. |
| 241 | * To enable write to NOR Boot flash for the benefit of systems that have such |
| 242 | * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select). |
| 243 | * |
| 244 | * This is probably not portable beyond Linux. |
| 245 | */ |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 246 | static int enable_flash_cs5536(struct pci_dev *dev, const char *name) |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 247 | { |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame^] | 248 | #define MSR_RCONF_DEFAULT 0x1808 |
| 249 | #define MSR_NORF_CTL 0x51400018 |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 250 | |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 251 | int fd_msr; |
| 252 | unsigned char buf[8]; |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 253 | |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 254 | fd_msr = open("/dev/cpu/0/msr", O_RDWR); |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 255 | if (!fd_msr) { |
| 256 | perror("open msr"); |
| 257 | return -1; |
| 258 | } |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame^] | 259 | |
| 260 | if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) { |
| 261 | perror("lseek64"); |
| 262 | close(fd_msr); |
| 263 | return -1; |
| 264 | } |
| 265 | |
| 266 | if (read(fd_msr, buf, 8) != 8) { |
| 267 | perror("read"); |
| 268 | close(fd_msr); |
| 269 | return -1; |
| 270 | } |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 271 | |
| 272 | printf("Enabling Geode MSR to write to flash.\n"); |
| 273 | |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 274 | if (buf[7] != 0x22) { |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 275 | buf[7] &= 0xfb; |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame^] | 276 | if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) { |
| 277 | perror("lseek64"); |
| 278 | close(fd_msr); |
| 279 | return -1; |
| 280 | } |
| 281 | |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 282 | if (write(fd_msr, buf, 8) < 0) { |
| 283 | perror("msr write"); |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 284 | printf("Cannot write to MSR. Did you run 'modprobe msr'?\n"); |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame^] | 285 | close(fd_msr); |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 286 | return -1; |
| 287 | } |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 288 | } |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 289 | |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame^] | 290 | if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) { |
| 291 | perror("lseek64"); |
| 292 | close(fd_msr); |
| 293 | return -1; |
| 294 | } |
| 295 | |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 296 | if (read(fd_msr, buf, 8) != 8) { |
| 297 | perror("read msr"); |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame^] | 298 | close(fd_msr); |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 299 | return -1; |
| 300 | } |
| 301 | |
| 302 | /* Raise WE_CS3 bit. */ |
| 303 | buf[0] |= 0x08; |
| 304 | |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame^] | 305 | if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) { |
| 306 | perror("lseek64"); |
| 307 | close(fd_msr); |
| 308 | return -1; |
| 309 | } |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 310 | if (write(fd_msr, buf, 8) < 0) { |
| 311 | perror("msr write"); |
| 312 | printf("Cannot write to MSR. Did you run 'modprobe msr'?\n"); |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame^] | 313 | close(fd_msr); |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 314 | return -1; |
| 315 | } |
| 316 | |
| 317 | close(fd_msr); |
| 318 | |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame^] | 319 | #undef MSR_RCONF_DEFAULT |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 320 | #undef MSR_NORF_CTL |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 321 | return 0; |
| 322 | } |
| 323 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 324 | static int enable_flash_sc1100(struct pci_dev *dev, const char *name) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 325 | { |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 326 | uint8_t new; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 327 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 328 | pci_write_byte(dev, 0x52, 0xee); |
| 329 | |
| 330 | new = pci_read_byte(dev, 0x52); |
| 331 | |
| 332 | if (new != 0xee) { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 333 | printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 334 | return -1; |
| 335 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 336 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 337 | return 0; |
| 338 | } |
| 339 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 340 | static int enable_flash_sis5595(struct pci_dev *dev, const char *name) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 341 | { |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 342 | uint8_t new, newer; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 343 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 344 | new = pci_read_byte(dev, 0x45); |
| 345 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 346 | new &= (~0x20); /* Clear bit 5. */ |
| 347 | new |= 0x4; /* Set bit 2. */ |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 348 | |
| 349 | pci_write_byte(dev, 0x45, new); |
| 350 | |
| 351 | newer = pci_read_byte(dev, 0x45); |
| 352 | if (newer != new) { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 353 | printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 354 | printf("Stuck at 0x%x\n", newer); |
| 355 | return -1; |
| 356 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 357 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 358 | return 0; |
| 359 | } |
| 360 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 361 | static int enable_flash_amd8111(struct pci_dev *dev, const char *name) |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 362 | { |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 363 | uint8_t old, new; |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 364 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 365 | /* Enable decoding at 0xffb00000 to 0xffffffff. */ |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 366 | old = pci_read_byte(dev, 0x43); |
Ollie Lho | d11f361 | 2004-12-07 17:19:04 +0000 | [diff] [blame] | 367 | new = old | 0xC0; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 368 | if (new != old) { |
| 369 | pci_write_byte(dev, 0x43, new); |
| 370 | if (pci_read_byte(dev, 0x43) != new) { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 371 | printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 372 | } |
| 373 | } |
| 374 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 375 | old = pci_read_byte(dev, 0x40); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 376 | new = old | 0x01; |
| 377 | if (new == old) |
| 378 | return 0; |
| 379 | pci_write_byte(dev, 0x40, new); |
| 380 | |
| 381 | if (pci_read_byte(dev, 0x40) != new) { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 382 | printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 383 | return -1; |
| 384 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 385 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 386 | return 0; |
| 387 | } |
| 388 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 389 | static int enable_flash_ck804(struct pci_dev *dev, const char *name) |
Yinghai Lu | 952dfce | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 390 | { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 391 | uint8_t old, new; |
Yinghai Lu | 952dfce | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 392 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 393 | old = pci_read_byte(dev, 0x88); |
| 394 | new = old | 0xc0; |
| 395 | if (new != old) { |
| 396 | pci_write_byte(dev, 0x88, new); |
| 397 | if (pci_read_byte(dev, 0x88) != new) { |
| 398 | printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name); |
| 399 | } |
| 400 | } |
Yinghai Lu | 952dfce | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 401 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 402 | old = pci_read_byte(dev, 0x6d); |
| 403 | new = old | 0x01; |
| 404 | if (new == old) |
| 405 | return 0; |
| 406 | pci_write_byte(dev, 0x6d, new); |
| 407 | |
| 408 | if (pci_read_byte(dev, 0x6d) != new) { |
| 409 | printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name); |
| 410 | return -1; |
| 411 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 412 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 413 | return 0; |
Yinghai Lu | 952dfce | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 414 | } |
| 415 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 416 | /* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */ |
| 417 | static int enable_flash_sb400(struct pci_dev *dev, const char *name) |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 418 | { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 419 | uint8_t tmp; |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 420 | struct pci_filter f; |
| 421 | struct pci_dev *smbusdev; |
| 422 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 423 | /* Look for the SMBus device. */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 424 | pci_filter_init((struct pci_access *)0, &f); |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 425 | f.vendor = 0x1002; |
| 426 | f.device = 0x4372; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 427 | |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 428 | for (smbusdev = pacc->devices; smbusdev; smbusdev = smbusdev->next) { |
| 429 | if (pci_filter_match(&f, smbusdev)) { |
| 430 | break; |
| 431 | } |
| 432 | } |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 433 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 434 | if (!smbusdev) { |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 435 | fprintf(stderr, "ERROR: SMBus device not found. Aborting.\n"); |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 436 | exit(1); |
| 437 | } |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 438 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 439 | /* Enable some SMBus stuff. */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 440 | tmp = pci_read_byte(smbusdev, 0x79); |
| 441 | tmp |= 0x01; |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 442 | pci_write_byte(smbusdev, 0x79, tmp); |
| 443 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 444 | /* Change southbridge. */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 445 | tmp = pci_read_byte(dev, 0x48); |
| 446 | tmp |= 0x21; |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 447 | pci_write_byte(dev, 0x48, tmp); |
| 448 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 449 | /* Now become a bit silly. */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 450 | tmp = inb(0xc6f); |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 451 | outb(tmp, 0xeb); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 452 | outb(tmp, 0xeb); |
| 453 | tmp |= 0x40; |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 454 | outb(tmp, 0xc6f); |
| 455 | outb(tmp, 0xeb); |
| 456 | outb(tmp, 0xeb); |
| 457 | |
| 458 | return 0; |
| 459 | } |
| 460 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 461 | static int enable_flash_mcp55(struct pci_dev *dev, const char *name) |
Yinghai Lu | ca78297 | 2007-01-22 20:21:17 +0000 | [diff] [blame] | 462 | { |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 463 | uint8_t old, new, byte; |
| 464 | uint16_t word; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 465 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 466 | /* Set the 0-16 MB enable bits. */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 467 | byte = pci_read_byte(dev, 0x88); |
| 468 | byte |= 0xff; /* 256K */ |
| 469 | pci_write_byte(dev, 0x88, byte); |
| 470 | byte = pci_read_byte(dev, 0x8c); |
| 471 | byte |= 0xff; /* 1M */ |
| 472 | pci_write_byte(dev, 0x8c, byte); |
| 473 | word = pci_read_word(dev, 0x90); |
Carl-Daniel Hailfinger | dca0ab1 | 2007-10-17 22:30:07 +0000 | [diff] [blame] | 474 | word |= 0x7fff; /* 16M */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 475 | pci_write_word(dev, 0x90, word); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 476 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 477 | old = pci_read_byte(dev, 0x6d); |
| 478 | new = old | 0x01; |
| 479 | if (new == old) |
| 480 | return 0; |
| 481 | pci_write_byte(dev, 0x6d, new); |
Yinghai Lu | ca78297 | 2007-01-22 20:21:17 +0000 | [diff] [blame] | 482 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 483 | if (pci_read_byte(dev, 0x6d) != new) { |
| 484 | printf |
| 485 | ("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", |
| 486 | 0x6d, new, name); |
| 487 | return -1; |
| 488 | } |
Yinghai Lu | ca78297 | 2007-01-22 20:21:17 +0000 | [diff] [blame] | 489 | |
| 490 | return 0; |
Yinghai Lu | ca78297 | 2007-01-22 20:21:17 +0000 | [diff] [blame] | 491 | } |
| 492 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 493 | static int enable_flash_ht1000(struct pci_dev *dev, const char *name) |
Stefan Reinauer | c868b9e | 2007-06-05 10:28:39 +0000 | [diff] [blame] | 494 | { |
Uwe Hermann | e823ee0 | 2007-06-05 15:02:18 +0000 | [diff] [blame] | 495 | uint8_t byte; |
Stefan Reinauer | c868b9e | 2007-06-05 10:28:39 +0000 | [diff] [blame] | 496 | |
Uwe Hermann | e823ee0 | 2007-06-05 15:02:18 +0000 | [diff] [blame] | 497 | /* Set the 4MB enable bit. */ |
Stefan Reinauer | c868b9e | 2007-06-05 10:28:39 +0000 | [diff] [blame] | 498 | byte = pci_read_byte(dev, 0x41); |
| 499 | byte |= 0x0e; |
| 500 | pci_write_byte(dev, 0x41, byte); |
| 501 | |
| 502 | byte = pci_read_byte(dev, 0x43); |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 503 | byte |= (1 << 4); |
Stefan Reinauer | c868b9e | 2007-06-05 10:28:39 +0000 | [diff] [blame] | 504 | pci_write_byte(dev, 0x43, byte); |
| 505 | |
Stefan Reinauer | c868b9e | 2007-06-05 10:28:39 +0000 | [diff] [blame] | 506 | return 0; |
| 507 | } |
| 508 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 509 | typedef struct penable { |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 510 | uint16_t vendor, device; |
| 511 | const char *name; |
| 512 | int (*doit) (struct pci_dev *dev, const char *name); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 513 | } FLASH_ENABLE; |
| 514 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 515 | static const FLASH_ENABLE enables[] = { |
Stefan Reinauer | eb36647 | 2006-09-06 15:48:48 +0000 | [diff] [blame] | 516 | {0x1039, 0x0630, "SIS630", enable_flash_sis630}, |
Uwe Hermann | ea2c66d | 2006-11-05 18:26:08 +0000 | [diff] [blame] | 517 | {0x8086, 0x7110, "PIIX4/PIIX4E/PIIX4M", enable_flash_piix4}, |
Uwe Hermann | 97a6470 | 2007-10-30 00:56:50 +0000 | [diff] [blame] | 518 | {0x8086, 0x7198, "Intel 440MX", enable_flash_piix4}, |
Stefan Reinauer | eb36647 | 2006-09-06 15:48:48 +0000 | [diff] [blame] | 519 | {0x8086, 0x2410, "ICH", enable_flash_ich_4e}, |
| 520 | {0x8086, 0x2420, "ICH0", enable_flash_ich_4e}, |
| 521 | {0x8086, 0x2440, "ICH2", enable_flash_ich_4e}, |
| 522 | {0x8086, 0x244c, "ICH2-M", enable_flash_ich_4e}, |
| 523 | {0x8086, 0x2480, "ICH3-S", enable_flash_ich_4e}, |
| 524 | {0x8086, 0x248c, "ICH3-M", enable_flash_ich_4e}, |
| 525 | {0x8086, 0x24c0, "ICH4/ICH4-L", enable_flash_ich_4e}, |
| 526 | {0x8086, 0x24cc, "ICH4-M", enable_flash_ich_4e}, |
| 527 | {0x8086, 0x24d0, "ICH5/ICH5R", enable_flash_ich_4e}, |
| 528 | {0x8086, 0x2640, "ICH6/ICH6R", enable_flash_ich_dc}, |
| 529 | {0x8086, 0x2641, "ICH6-M", enable_flash_ich_dc}, |
Uwe Hermann | 3ad2518 | 2007-03-31 19:48:38 +0000 | [diff] [blame] | 530 | {0x8086, 0x27b0, "ICH7DH", enable_flash_ich_dc}, |
Stefan Reinauer | eb36647 | 2006-09-06 15:48:48 +0000 | [diff] [blame] | 531 | {0x8086, 0x27b8, "ICH7/ICH7R", enable_flash_ich_dc}, |
| 532 | {0x8086, 0x27b9, "ICH7M", enable_flash_ich_dc}, |
| 533 | {0x8086, 0x27bd, "ICH7MDH", enable_flash_ich_dc}, |
| 534 | {0x8086, 0x2810, "ICH8/ICH8R", enable_flash_ich_dc}, |
| 535 | {0x8086, 0x2812, "ICH8DH", enable_flash_ich_dc}, |
| 536 | {0x8086, 0x2814, "ICH8DO", enable_flash_ich_dc}, |
Luc Verhaegen | 6382b44 | 2007-03-02 22:16:38 +0000 | [diff] [blame] | 537 | {0x1106, 0x8231, "VT8231", enable_flash_vt823x}, |
| 538 | {0x1106, 0x3177, "VT8235", enable_flash_vt823x}, |
| 539 | {0x1106, 0x3227, "VT8237", enable_flash_vt823x}, |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 540 | {0x1106, 0x8324, "CX700", enable_flash_vt823x}, |
Stefan Reinauer | c6b5f49 | 2006-11-07 10:22:20 +0000 | [diff] [blame] | 541 | {0x1106, 0x0686, "VT82C686", enable_flash_amd8111}, |
Uwe Hermann | f4a673b | 2007-06-06 21:35:45 +0000 | [diff] [blame] | 542 | {0x1078, 0x0100, "CS5530/CS5530A", enable_flash_cs5530}, |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 543 | {0x100b, 0x0510, "SC1100", enable_flash_sc1100}, |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 544 | {0x1039, 0x0008, "SIS5595", enable_flash_sis5595}, |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 545 | {0x1022, 0x2080, "AMD GEODE CS5536", enable_flash_cs5536}, |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 546 | {0x1022, 0x7468, "AMD8111", enable_flash_amd8111}, |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 547 | {0x10B9, 0x1533, "ALi M1533", enable_flash_ali_m1533}, |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 548 | {0x10de, 0x0050, "NVIDIA CK804", enable_flash_ck804}, /* LPC */ |
| 549 | {0x10de, 0x0051, "NVIDIA CK804", enable_flash_ck804}, /* Pro */ |
| 550 | {0x10de, 0x00d3, "NVIDIA CK804", enable_flash_ck804}, /* Slave, should not be here, to fix known bug for A01. */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 551 | {0x10de, 0x0260, "NVidia MCP51", enable_flash_ck804}, |
| 552 | {0x10de, 0x0261, "NVidia MCP51", enable_flash_ck804}, |
| 553 | {0x10de, 0x0262, "NVidia MCP51", enable_flash_ck804}, |
| 554 | {0x10de, 0x0263, "NVidia MCP51", enable_flash_ck804}, |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 555 | {0x10de, 0x0360, "NVIDIA MCP55", enable_flash_mcp55}, /* M57SLI-S4 */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 556 | {0x10de, 0x0361, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ |
| 557 | {0x10de, 0x0362, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ |
| 558 | {0x10de, 0x0363, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ |
| 559 | {0x10de, 0x0364, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ |
| 560 | {0x10de, 0x0365, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ |
| 561 | {0x10de, 0x0366, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ |
| 562 | {0x10de, 0x0367, "NVIDIA MCP55", enable_flash_mcp55}, /* Pro */ |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 563 | {0x1002, 0x4377, "ATI SB400", enable_flash_sb400}, |
Uwe Hermann | e823ee0 | 2007-06-05 15:02:18 +0000 | [diff] [blame] | 564 | {0x1166, 0x0205, "Broadcom HT-1000", enable_flash_ht1000}, |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 565 | }; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 566 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 567 | int chipset_flash_enable(void) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 568 | { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 569 | struct pci_dev *dev = 0; |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 570 | int ret = -2; /* Nothing! */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 571 | int i; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 572 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 573 | /* Now let's try to find the chipset we have... */ |
| 574 | /* TODO: Use ARRAY_SIZE. */ |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 575 | for (i = 0; i < sizeof(enables) / sizeof(enables[0]); i++) { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 576 | dev = pci_dev_find(enables[i].vendor, enables[i].device); |
| 577 | if (dev) |
| 578 | break; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 579 | } |
| 580 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 581 | if (dev) { |
Uwe Hermann | a502dce | 2007-10-17 23:55:15 +0000 | [diff] [blame] | 582 | printf("Found chipset \"%s\", enabling flash write... ", |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 583 | enables[i].name); |
| 584 | |
| 585 | ret = enables[i].doit(dev, enables[i].name); |
| 586 | if (ret) |
Uwe Hermann | a502dce | 2007-10-17 23:55:15 +0000 | [diff] [blame] | 587 | printf("FAILED!\n"); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 588 | else |
Uwe Hermann | ac30934 | 2007-10-10 17:42:20 +0000 | [diff] [blame] | 589 | printf("OK.\n"); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 590 | } |
| 591 | |
| 592 | return ret; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 593 | } |