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Ollie Lho184a4042005-11-26 21:55:36 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ollie Lho184a4042005-11-26 21:55:36 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
Stefan Reinauer8fa64812009-08-12 09:27:45 +00005 * Copyright (C) 2005-2009 coresystems GmbH
Uwe Hermannd1107642007-08-29 17:52:32 +00006 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00007 * Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger
Adam Jurkowskie4984102009-12-21 15:30:46 +00008 * Copyright (C) 2009 Kontron Modular Computers GmbH
Helge Wagnerdd73d832012-08-24 23:03:46 +00009 * Copyright (C) 2011, 2012 Stefan Tauner
Ollie Lho184a4042005-11-26 21:55:36 +000010 *
Uwe Hermannd1107642007-08-29 17:52:32 +000011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
Ollie Lho184a4042005-11-26 21:55:36 +000014 *
Uwe Hermannd1107642007-08-29 17:52:32 +000015 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 */
24
25/*
26 * Contains the chipset specific flash enables.
Ollie Lho184a4042005-11-26 21:55:36 +000027 */
28
Lane Brooksd54958a2007-11-13 16:45:22 +000029#define _LARGEFILE64_SOURCE
30
Ollie Lhocbbf1252004-03-17 22:22:08 +000031#include <stdlib.h>
Uwe Hermanne8ba5382009-05-22 11:37:27 +000032#include <string.h>
Carl-Daniel Hailfingerdcef67e2010-06-21 23:20:15 +000033#include <unistd.h>
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +000034#include <inttypes.h>
35#include <errno.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000036#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000037#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000038#include "hwaccess.h"
Stefan Reinauer86de2832006-03-31 11:26:55 +000039
Michael Karcher89bed6d2010-06-13 10:16:12 +000040#define NOT_DONE_YET 1
41
Carl-Daniel Hailfinger1d3a2fe2010-07-27 22:03:46 +000042#if defined(__i386__) || defined(__x86_64__)
43
Uwe Hermann372eeb52007-12-04 21:49:06 +000044static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
Luc Verhaegen6b141752007-05-20 16:16:13 +000045{
46 uint8_t tmp;
47
Uwe Hermann372eeb52007-12-04 21:49:06 +000048 /*
49 * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
50 * 0xFFFE0000-0xFFFFFFFF ROM select enable.
51 */
Luc Verhaegen6b141752007-05-20 16:16:13 +000052 tmp = pci_read_byte(dev, 0x47);
53 tmp |= 0x46;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +000054 rpci_write_byte(dev, 0x47, tmp);
Luc Verhaegen6b141752007-05-20 16:16:13 +000055
56 return 0;
57}
58
Rudolf Marek23907d82012-02-07 21:29:48 +000059static int enable_flash_rdc_r8610(struct pci_dev *dev, const char *name)
60{
61 uint8_t tmp;
62
63 /* enable ROMCS for writes */
64 tmp = pci_read_byte(dev, 0x43);
65 tmp |= 0x80;
66 pci_write_byte(dev, 0x43, tmp);
67
68 /* read the bootstrapping register */
69 tmp = pci_read_byte(dev, 0x40) & 0x3;
70 switch (tmp) {
71 case 3:
72 internal_buses_supported = BUS_FWH;
73 break;
74 case 2:
75 internal_buses_supported = BUS_LPC;
76 break;
77 default:
78 internal_buses_supported = BUS_PARALLEL;
79 break;
80 }
81
82 return 0;
83}
84
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000085static int enable_flash_sis85c496(struct pci_dev *dev, const char *name)
86{
87 uint8_t tmp;
88
89 tmp = pci_read_byte(dev, 0xd0);
90 tmp |= 0xf8;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +000091 rpci_write_byte(dev, 0xd0, tmp);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000092
93 return 0;
94}
95
96static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name)
97{
Stefan Taunere34e3e82013-01-01 00:06:51 +000098 #define SIS_MAPREG 0x40
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000099 uint8_t new, newer;
100
101 /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */
102 /* This is 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
Stefan Taunere34e3e82013-01-01 00:06:51 +0000103 new = pci_read_byte(dev, SIS_MAPREG);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000104 new &= (~0x04); /* No idea why we clear bit 2. */
105 new |= 0xb; /* 0x3 for some chipsets, bit 7 seems to be don't care. */
Stefan Taunere34e3e82013-01-01 00:06:51 +0000106 rpci_write_byte(dev, SIS_MAPREG, new);
107 newer = pci_read_byte(dev, SIS_MAPREG);
108 if (newer != new) { /* FIXME: share this with other code? */
109 msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n",
110 SIS_MAPREG, new, name);
111 msg_pinfo("Stuck at 0x%02x.\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000112 return -1;
113 }
114 return 0;
115}
116
117static struct pci_dev *find_southbridge(uint16_t vendor, const char *name)
118{
119 struct pci_dev *sbdev;
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000120
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000121 sbdev = pci_dev_find_vendorclass(vendor, 0x0601);
122 if (!sbdev)
123 sbdev = pci_dev_find_vendorclass(vendor, 0x0680);
124 if (!sbdev)
125 sbdev = pci_dev_find_vendorclass(vendor, 0x0000);
126 if (!sbdev)
Sean Nelson316a29f2010-05-07 20:09:04 +0000127 msg_perr("No southbridge found for %s!\n", name);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000128 if (sbdev)
Sean Nelson316a29f2010-05-07 20:09:04 +0000129 msg_pdbg("Found southbridge %04x:%04x at %02x:%02x:%01x\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000130 sbdev->vendor_id, sbdev->device_id,
131 sbdev->bus, sbdev->dev, sbdev->func);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000132 return sbdev;
133}
134
135static int enable_flash_sis501(struct pci_dev *dev, const char *name)
136{
137 uint8_t tmp;
138 int ret = 0;
139 struct pci_dev *sbdev;
140
141 sbdev = find_southbridge(dev->vendor_id, name);
142 if (!sbdev)
143 return -1;
144
145 ret = enable_flash_sis_mapping(sbdev, name);
146
147 tmp = sio_read(0x22, 0x80);
148 tmp &= (~0x20);
149 tmp |= 0x4;
150 sio_write(0x22, 0x80, tmp);
151
152 tmp = sio_read(0x22, 0x70);
153 tmp &= (~0x20);
154 tmp |= 0x4;
155 sio_write(0x22, 0x70, tmp);
156
157 return ret;
158}
159
160static int enable_flash_sis5511(struct pci_dev *dev, const char *name)
161{
162 uint8_t tmp;
163 int ret = 0;
164 struct pci_dev *sbdev;
165
166 sbdev = find_southbridge(dev->vendor_id, name);
167 if (!sbdev)
168 return -1;
169
170 ret = enable_flash_sis_mapping(sbdev, name);
171
172 tmp = sio_read(0x22, 0x50);
173 tmp &= (~0x20);
174 tmp |= 0x4;
175 sio_write(0x22, 0x50, tmp);
176
177 return ret;
178}
179
Stefan Taunere34e3e82013-01-01 00:06:51 +0000180static int enable_flash_sis5x0(struct pci_dev *dev, const char *name, uint8_t dis_mask, uint8_t en_mask)
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000181{
Stefan Taunere34e3e82013-01-01 00:06:51 +0000182 #define SIS_REG 0x45
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000183 uint8_t new, newer;
184 int ret = 0;
185 struct pci_dev *sbdev;
186
187 sbdev = find_southbridge(dev->vendor_id, name);
188 if (!sbdev)
189 return -1;
190
191 ret = enable_flash_sis_mapping(sbdev, name);
192
Stefan Taunere34e3e82013-01-01 00:06:51 +0000193 new = pci_read_byte(sbdev, SIS_REG);
194 new &= (~dis_mask);
195 new |= en_mask;
196 rpci_write_byte(sbdev, SIS_REG, new);
197 newer = pci_read_byte(sbdev, SIS_REG);
198 if (newer != new) { /* FIXME: share this with other code? */
199 msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", SIS_REG, new, name);
200 msg_pinfo("Stuck at 0x%02x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000201 ret = -1;
202 }
203
204 return ret;
205}
206
Stefan Taunere34e3e82013-01-01 00:06:51 +0000207static int enable_flash_sis530(struct pci_dev *dev, const char *name)
208{
209 return enable_flash_sis5x0(dev, name, 0x20, 0x04);
210}
211
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000212static int enable_flash_sis540(struct pci_dev *dev, const char *name)
213{
Stefan Taunere34e3e82013-01-01 00:06:51 +0000214 return enable_flash_sis5x0(dev, name, 0x80, 0x40);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000215}
216
Uwe Hermann987942d2006-11-07 11:16:21 +0000217/* Datasheet:
218 * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
219 * - URL: http://www.intel.com/design/intarch/datashts/290562.htm
220 * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
221 * - Order Number: 290562-001
222 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000223static int enable_flash_piix4(struct pci_dev *dev, const char *name)
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000224{
225 uint16_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000226 uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000227
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000228 internal_buses_supported = BUS_PARALLEL;
Maciej Pijankaa661e152009-12-08 17:26:24 +0000229
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000230 old = pci_read_word(dev, xbcs);
231
232 /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
Uwe Hermanna7e05482007-05-09 10:17:44 +0000233 * FFF00000-FFF7FFFF are forwarded to ISA).
Uwe Hermannc556d322008-10-28 11:50:05 +0000234 * Note: This bit is reserved on PIIX/PIIX3/MPIIX.
Uwe Hermanna7e05482007-05-09 10:17:44 +0000235 * Set bit 7: Extended BIOS Enable (PCI master accesses to
236 * FFF80000-FFFDFFFF are forwarded to ISA).
237 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
238 * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
239 * of 1 Mbyte, or the aliases at the top of 4 Gbyte
240 * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
241 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
242 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
243 */
Uwe Hermannc556d322008-10-28 11:50:05 +0000244 if (dev->device_id == 0x122e || dev->device_id == 0x7000
245 || dev->device_id == 0x1234)
246 new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */
Uwe Hermann87203452008-10-26 18:40:42 +0000247 else
248 new = old | 0x02c4;
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000249
250 if (new == old)
251 return 0;
252
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000253 rpci_write_word(dev, xbcs, new);
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000254
Stefan Taunere34e3e82013-01-01 00:06:51 +0000255 if (pci_read_word(dev, xbcs) != new) { /* FIXME: share this with other code? */
256 msg_pinfo("Setting register 0x%04x to 0x%04x on %s failed (WARNING ONLY).\n", xbcs, new, name);
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000257 return -1;
258 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000259
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000260 return 0;
261}
262
Duncan Laurie4095ed72014-08-20 15:39:32 +0000263/* Handle BIOS_CNTL (aka. BCR). Disable locks and enable writes. The register can either be in PCI config space
264 * at the offset given by 'bios_cntl' or at the memory-mapped address 'addr'.
265 *
266 * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, in Poulsbo, Tunnel Creek and other Atom
Stefan Tauner92d6a862013-10-25 00:33:37 +0000267 * chipsets/SoCs it is even 32b, but just treating it as 8 bit wide seems to work fine in practice. */
Duncan Laurie4095ed72014-08-20 15:39:32 +0000268static int enable_flash_ich_bios_cntl_common(enum ich_chipset ich_generation, void *addr,
269 struct pci_dev *dev, uint8_t bios_cntl)
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000270{
Stefan Taunerd5c4ab42011-09-09 12:46:32 +0000271 uint8_t old, new, wanted;
Stefan Reinauereb366472006-09-06 15:48:48 +0000272
Stefan Tauner92d6a862013-10-25 00:33:37 +0000273 switch (ich_generation) {
274 case CHIPSET_ICH_UNKNOWN:
275 return ERROR_FATAL;
276 /* Non-SPI-capable */
277 case CHIPSET_ICH:
278 case CHIPSET_ICH2345:
279 break;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000280 /* Some Atom chipsets are special: The second byte of BIOS_CNTL (D9h) contains a prefetch bit similar to
281 * what other SPI-capable chipsets have at DCh. Others like Bay Trail use a memmapped register.
Stefan Tauner92d6a862013-10-25 00:33:37 +0000282 * The Tunnel Creek datasheet contains a lot of details about the SPI controller, among other things it
283 * mentions that the prefetching and caching does only happen for direct memory reads.
284 * Therefore - at least for Tunnel Creek - it should not matter to flashrom because we use the
285 * programmed access only and not memory mapping. */
286 case CHIPSET_TUNNEL_CREEK:
287 case CHIPSET_POULSBO:
288 case CHIPSET_CENTERTON:
289 old = pci_read_byte(dev, bios_cntl + 1);
290 msg_pdbg("BIOS Prefetch Enable: %sabled, ", (old & 1) ? "en" : "dis");
291 break;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000292 case CHIPSET_BAYTRAIL:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000293 case CHIPSET_ICH7:
294 default: /* Future version might behave the same */
Duncan Laurie4095ed72014-08-20 15:39:32 +0000295 if (ich_generation == CHIPSET_BAYTRAIL)
296 old = (mmio_readl(addr) >> 2) & 0x3;
297 else
298 old = (pci_read_byte(dev, bios_cntl) >> 2) & 0x3;
Stefan Tauner92d6a862013-10-25 00:33:37 +0000299 msg_pdbg("SPI Read Configuration: ");
300 if (old == 3)
301 msg_pdbg("invalid prefetching/caching settings, ");
302 else
303 msg_pdbg("prefetching %sabled, caching %sabled, ",
304 (old & 0x2) ? "en" : "dis",
305 (old & 0x1) ? "dis" : "en");
306 }
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000307
Duncan Laurie4095ed72014-08-20 15:39:32 +0000308 if (ich_generation == CHIPSET_BAYTRAIL)
309 wanted = old = mmio_readl(addr);
310 else
311 wanted = old = pci_read_byte(dev, bios_cntl);
312
Stefan Taunerf9a8da52011-06-11 18:16:50 +0000313 /*
314 * Quote from the 6 Series datasheet (Document Number: 324645-004):
315 * "Bit 5: SMM BIOS Write Protect Disable (SMM_BWP)
316 * 1 = BIOS region SMM protection is enabled.
317 * The BIOS Region is not writable unless all processors are in SMM."
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000318 * In earlier chipsets this bit is reserved.
Stefan Reinauer62218c32012-08-26 02:35:13 +0000319 *
320 * Try to unset it in any case.
321 * It won't hurt and makes sense in some cases according to Stefan Reinauer.
Stefan Tauner92d6a862013-10-25 00:33:37 +0000322 *
323 * At least in Centerton aforementioned bit is located at bit 7. It is unspecified in all other Atom
324 * and Desktop chipsets before Ibex Peak/5 Series, but we reset bit 5 anyway.
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000325 */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000326 int smm_bwp_bit;
327 if (ich_generation == CHIPSET_CENTERTON)
328 smm_bwp_bit = 7;
329 else
330 smm_bwp_bit = 5;
331 wanted &= ~(1 << smm_bwp_bit);
Stefan Reinauer62218c32012-08-26 02:35:13 +0000332
Stefan Tauner92d6a862013-10-25 00:33:37 +0000333 /* Tunnel Creek has a cache disable at bit 2 of the lowest BIOS_CNTL byte. */
334 if (ich_generation == CHIPSET_TUNNEL_CREEK)
335 wanted |= (1 << 2);
336
337 wanted |= (1 << 0); /* Set BIOS Write Enable */
338 wanted &= ~(1 << 1); /* Disable lock (futile) */
Stefan Reinauer62218c32012-08-26 02:35:13 +0000339
340 /* Only write the register if it's necessary */
341 if (wanted != old) {
Duncan Laurie4095ed72014-08-20 15:39:32 +0000342 if (ich_generation == CHIPSET_BAYTRAIL) {
343 rmmio_writel(wanted, addr);
344 new = mmio_readl(addr);
345 } else {
346 rpci_write_byte(dev, bios_cntl, wanted);
347 new = pci_read_byte(dev, bios_cntl);
348 }
Stefan Reinauer62218c32012-08-26 02:35:13 +0000349 } else
350 new = old;
351
352 msg_pdbg("\nBIOS_CNTL = 0x%02x: ", new);
353 msg_pdbg("BIOS Lock Enable: %sabled, ", (new & (1 << 1)) ? "en" : "dis");
354 msg_pdbg("BIOS Write Enable: %sabled\n", (new & (1 << 0)) ? "en" : "dis");
Stefan Tauner92d6a862013-10-25 00:33:37 +0000355 if (new & (1 << smm_bwp_bit))
Stefan Taunerc6fa32d2013-01-04 22:54:07 +0000356 msg_pwarn("Warning: BIOS region SMM protection is enabled!\n");
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000357
Stefan Reinauer62218c32012-08-26 02:35:13 +0000358 if (new != wanted)
Stefan Tauner92d6a862013-10-25 00:33:37 +0000359 msg_pwarn("Warning: Setting Bios Control at 0x%x from 0x%02x to 0x%02x failed.\n"
360 "New value is 0x%02x.\n", bios_cntl, old, wanted, new);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000361
Stefan Tauner92d6a862013-10-25 00:33:37 +0000362 /* Return an error if we could not set the write enable only. */
Stefan Reinauer62218c32012-08-26 02:35:13 +0000363 if (!(new & (1 << 0)))
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000364 return -1;
Uwe Hermannffec5f32007-08-23 16:08:21 +0000365
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000366 return 0;
367}
368
Duncan Laurie4095ed72014-08-20 15:39:32 +0000369static int enable_flash_ich_bios_cntl_config_space(struct pci_dev *dev, enum ich_chipset ich_generation,
370 uint8_t bios_cntl)
371{
372 return enable_flash_ich_bios_cntl_common(ich_generation, NULL, dev, bios_cntl);
373}
374
375static int enable_flash_ich_bios_cntl_memmapped(enum ich_chipset ich_generation, void *addr)
376{
377 return enable_flash_ich_bios_cntl_common(ich_generation, addr, NULL, 0);
378}
379
Stefan Tauner92d6a862013-10-25 00:33:37 +0000380static int enable_flash_ich_fwh_decode(struct pci_dev *dev, enum ich_chipset ich_generation)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000381{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000382 uint8_t fwh_sel1 = 0, fwh_sel2 = 0, fwh_dec_en_lo = 0, fwh_dec_en_hi = 0; /* silence compilers */
383 bool implemented = 0;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000384 void *ilb = NULL; /* Only for Baytrail */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000385 switch (ich_generation) {
386 case CHIPSET_ICH:
387 /* FIXME: Unlike later chipsets, ICH and ICH-0 do only support mapping of the top-most 4MB
388 * and therefore do only feature FWH_DEC_EN (E3h, different default too) and FWH_SEL (E8h). */
389 break;
390 case CHIPSET_ICH2345:
Kyösti Mälkki88ee0402013-09-14 23:37:01 +0000391 fwh_sel1 = 0xe8;
392 fwh_sel2 = 0xee;
393 fwh_dec_en_lo = 0xf0;
394 fwh_dec_en_hi = 0xe3;
Stefan Tauner92d6a862013-10-25 00:33:37 +0000395 implemented = 1;
396 break;
397 case CHIPSET_POULSBO:
398 case CHIPSET_TUNNEL_CREEK:
399 /* FIXME: Similar to ICH and ICH-0, Tunnel Creek and Poulsbo do only feature one register each,
400 * FWH_DEC_EN (D7h) and FWH_SEL (D0h). */
401 break;
402 case CHIPSET_CENTERTON:
403 /* FIXME: Similar to above FWH_DEC_EN (D4h) and FWH_SEL (D0h). */
404 break;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000405 case CHIPSET_BAYTRAIL: {
406 uint32_t ilb_base = pci_read_long(dev, 0x50) & 0xfffffe00; /* bits 31:9 */
407 if (ilb_base == 0) {
408 msg_perr("Error: Invalid ILB_BASE_ADDRESS\n");
409 return ERROR_FATAL;
410 }
411 ilb = rphysmap("BYT IBASE", ilb_base, 512);
412 fwh_sel1 = 0x18;
413 fwh_dec_en_lo = 0xd8;
414 fwh_dec_en_hi = 0xd9;
415 implemented = 1;
416 break;
417 }
Stefan Tauner92d6a862013-10-25 00:33:37 +0000418 case CHIPSET_ICH6:
419 case CHIPSET_ICH7:
420 default: /* Future version might behave the same */
421 fwh_sel1 = 0xd0;
422 fwh_sel2 = 0xd4;
423 fwh_dec_en_lo = 0xd8;
424 fwh_dec_en_hi = 0xd9;
425 implemented = 1;
426 break;
Kyösti Mälkki88ee0402013-09-14 23:37:01 +0000427 }
Kyösti Mälkki743babc2013-09-14 23:36:53 +0000428
Stefan Tauner92d6a862013-10-25 00:33:37 +0000429 char *idsel = extract_programmer_param("fwh_idsel");
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000430 if (idsel && strlen(idsel)) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000431 if (!implemented) {
432 msg_perr("Error: fwh_idsel= specified, but (yet) unsupported on this chipset.\n");
433 goto idsel_garbage_out;
434 }
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000435 errno = 0;
436 /* Base 16, nothing else makes sense. */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000437 uint64_t fwh_idsel = (uint64_t)strtoull(idsel, NULL, 16);
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000438 if (errno) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000439 msg_perr("Error: fwh_idsel= specified, but value could not be converted.\n");
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000440 goto idsel_garbage_out;
441 }
Duncan Laurie4095ed72014-08-20 15:39:32 +0000442 uint64_t fwh_mask = 0xffffffff;
443 if (fwh_sel2 > 0)
444 fwh_mask |= (0xffffULL << 32);
445 if (fwh_idsel & ~fwh_mask) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000446 msg_perr("Error: fwh_idsel= specified, but value had unused bits set.\n");
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000447 goto idsel_garbage_out;
448 }
Duncan Laurie4095ed72014-08-20 15:39:32 +0000449 uint64_t fwh_idsel_old;
450 if (ich_generation == CHIPSET_BAYTRAIL) {
451 fwh_idsel_old = mmio_readl(ilb + fwh_sel1);
452 rmmio_writel(fwh_idsel, ilb + fwh_sel1);
453 } else {
Stefan Tauner5c316f92015-02-08 21:57:52 +0000454 fwh_idsel_old = (uint64_t)pci_read_long(dev, fwh_sel1) << 16;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000455 rpci_write_long(dev, fwh_sel1, (fwh_idsel >> 16) & 0xffffffff);
456 if (fwh_sel2 > 0) {
457 fwh_idsel_old |= pci_read_word(dev, fwh_sel2);
458 rpci_write_word(dev, fwh_sel2, fwh_idsel & 0xffff);
459 }
460 }
Stefan Taunereff156e2014-07-13 17:06:11 +0000461 msg_pdbg("Setting IDSEL from 0x%012" PRIx64 " to 0x%012" PRIx64 " for top 16 MB.\n",
Stefan Tauner92d6a862013-10-25 00:33:37 +0000462 fwh_idsel_old, fwh_idsel);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000463 /* FIXME: Decode settings are not changed. */
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000464 } else if (idsel) {
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000465 msg_perr("Error: fwh_idsel= specified, but no value given.\n");
Sylvain "ythier" Hitier3093f8f2011-09-03 11:22:27 +0000466idsel_garbage_out:
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000467 free(idsel);
Tadas Slotkus0e3f1cf2011-09-06 18:49:31 +0000468 return ERROR_FATAL;
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000469 }
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000470 free(idsel);
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000471
Stefan Tauner92d6a862013-10-25 00:33:37 +0000472 if (!implemented) {
Stefan Taunereff156e2014-07-13 17:06:11 +0000473 msg_pdbg2("FWH IDSEL handling is not implemented on this chipset.\n");
Stefan Tauner92d6a862013-10-25 00:33:37 +0000474 return 0;
475 }
476
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000477 /* Ignore all legacy ranges below 1 MB.
478 * We currently only support flashing the chip which responds to
479 * IDSEL=0. To support IDSEL!=0, flashbase and decode size calculations
480 * have to be adjusted.
481 */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000482 int max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0;
483 bool contiguous = 1;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000484 uint32_t fwh_conf;
485 if (ich_generation == CHIPSET_BAYTRAIL)
486 fwh_conf = mmio_readl(ilb + fwh_sel1);
487 else
488 fwh_conf = pci_read_long(dev, fwh_sel1);
489
Stefan Tauner92d6a862013-10-25 00:33:37 +0000490 int i;
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000491 /* FWH_SEL1 */
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000492 for (i = 7; i >= 0; i--) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000493 int tmp = (fwh_conf >> (i * 4)) & 0xf;
Stefan Taunereff156e2014-07-13 17:06:11 +0000494 msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000495 (0x1ff8 + i) * 0x80000,
496 (0x1ff0 + i) * 0x80000,
497 tmp);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000498 if ((tmp == 0) && contiguous) {
499 max_decode_fwh_idsel = (8 - i) * 0x80000;
500 } else {
501 contiguous = 0;
502 }
503 }
Duncan Laurie4095ed72014-08-20 15:39:32 +0000504 if (fwh_sel2 > 0) {
505 /* FWH_SEL2 */
506 fwh_conf = pci_read_word(dev, fwh_sel2);
507 for (i = 3; i >= 0; i--) {
508 int tmp = (fwh_conf >> (i * 4)) & 0xf;
509 msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n",
510 (0xff4 + i) * 0x100000,
511 (0xff0 + i) * 0x100000,
512 tmp);
513 if ((tmp == 0) && contiguous) {
514 max_decode_fwh_idsel = (8 - i) * 0x100000;
515 } else {
516 contiguous = 0;
517 }
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000518 }
519 }
520 contiguous = 1;
521 /* FWH_DEC_EN1 */
Kyösti Mälkki743babc2013-09-14 23:36:53 +0000522 fwh_conf = pci_read_byte(dev, fwh_dec_en_hi);
523 fwh_conf <<= 8;
524 fwh_conf |= pci_read_byte(dev, fwh_dec_en_lo);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000525 for (i = 7; i >= 0; i--) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000526 int tmp = (fwh_conf >> (i + 0x8)) & 0x1;
Stefan Taunereff156e2014-07-13 17:06:11 +0000527 msg_pdbg("0x%08x/0x%08x FWH decode %sabled\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000528 (0x1ff8 + i) * 0x80000,
529 (0x1ff0 + i) * 0x80000,
530 tmp ? "en" : "dis");
Michael Karcher96785392010-01-03 15:09:17 +0000531 if ((tmp == 1) && contiguous) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000532 max_decode_fwh_decode = (8 - i) * 0x80000;
533 } else {
534 contiguous = 0;
535 }
536 }
537 for (i = 3; i >= 0; i--) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000538 int tmp = (fwh_conf >> i) & 0x1;
Stefan Taunereff156e2014-07-13 17:06:11 +0000539 msg_pdbg("0x%08x/0x%08x FWH decode %sabled\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000540 (0xff4 + i) * 0x100000,
541 (0xff0 + i) * 0x100000,
542 tmp ? "en" : "dis");
Michael Karcher96785392010-01-03 15:09:17 +0000543 if ((tmp == 1) && contiguous) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000544 max_decode_fwh_decode = (8 - i) * 0x100000;
545 } else {
546 contiguous = 0;
547 }
548 }
549 max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode);
Stefan Taunereff156e2014-07-13 17:06:11 +0000550 msg_pdbg("Maximum FWH chip size: 0x%x bytes\n", max_rom_decode.fwh);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000551
Kyösti Mälkki743babc2013-09-14 23:36:53 +0000552 return 0;
553}
554
Stefan Tauner92d6a862013-10-25 00:33:37 +0000555static int enable_flash_ich_fwh(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl)
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000556{
Kyösti Mälkki88ee0402013-09-14 23:37:01 +0000557 int err;
558
559 /* Configure FWH IDSEL decoder maps. */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000560 if ((err = enable_flash_ich_fwh_decode(dev, ich_generation)) != 0)
Kyösti Mälkki88ee0402013-09-14 23:37:01 +0000561 return err;
562
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000563 internal_buses_supported = BUS_FWH;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000564 return enable_flash_ich_bios_cntl_config_space(dev, ich_generation, bios_cntl);
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000565}
566
Stefan Tauner92d6a862013-10-25 00:33:37 +0000567static int enable_flash_ich0(struct pci_dev *dev, const char *name)
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000568{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000569 return enable_flash_ich_fwh(dev, CHIPSET_ICH, 0x4e);
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000570}
571
Stefan Tauner92d6a862013-10-25 00:33:37 +0000572static int enable_flash_ich2345(struct pci_dev *dev, const char *name)
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000573{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000574 return enable_flash_ich_fwh(dev, CHIPSET_ICH2345, 0x4e);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000575}
576
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000577static int enable_flash_ich6(struct pci_dev *dev, const char *name)
578{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000579 return enable_flash_ich_fwh(dev, CHIPSET_ICH6, 0xdc);
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000580}
581
Adam Jurkowskie4984102009-12-21 15:30:46 +0000582static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
583{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000584 return enable_flash_ich_fwh(dev, CHIPSET_POULSBO, 0xd8);
Adam Jurkowskie4984102009-12-21 15:30:46 +0000585}
586
Duncan Laurie4095ed72014-08-20 15:39:32 +0000587static void enable_flash_ich_handle_gcs(struct pci_dev *dev, enum ich_chipset ich_generation, uint32_t gcs, bool top_swap)
Ingo Feldschmiddadc0a62011-09-07 19:18:25 +0000588{
Duncan Laurie4095ed72014-08-20 15:39:32 +0000589 msg_pdbg("GCS = 0x%x: ", gcs);
590 msg_pdbg("BIOS Interface Lock-Down: %sabled, ", (gcs & 0x1) ? "en" : "dis");
591
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000592 static const char *const straps_names_EP80579[] = { "SPI", "reserved", "reserved", "LPC" };
593 static const char *const straps_names_ich7_nm10[] = { "reserved", "SPI", "PCI", "LPC" };
Stefan Tauner92d6a862013-10-25 00:33:37 +0000594 static const char *const straps_names_tunnel_creek[] = { "SPI", "LPC" };
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000595 static const char *const straps_names_ich8910[] = { "SPI", "SPI", "PCI", "LPC" };
Helge Wagnera0fce5f2012-07-24 16:33:55 +0000596 static const char *const straps_names_pch567[] = { "LPC", "reserved", "PCI", "SPI" };
Duncan Laurie823096e2014-08-20 15:39:38 +0000597 static const char *const straps_names_pch89_baytrail[] = { "LPC", "reserved", "reserved", "SPI" };
Stefan Tauner92d6a862013-10-25 00:33:37 +0000598 static const char *const straps_names_pch8_lp[] = { "SPI", "LPC" };
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000599 static const char *const straps_names_unknown[] = { "unknown", "unknown", "unknown", "unknown" };
600
Stefan Tauner92d6a862013-10-25 00:33:37 +0000601 const char *const *straps_names;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000602 switch (ich_generation) {
Stefan Taunera8d838d2011-11-06 23:51:09 +0000603 case CHIPSET_ICH7:
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000604 /* EP80579 may need further changes, but this is the least
605 * intrusive way to get correct BOOT Strap printing without
606 * changing the rest of its code path). */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000607 if (dev->device_id == 0x5031)
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000608 straps_names = straps_names_EP80579;
609 else
610 straps_names = straps_names_ich7_nm10;
611 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000612 case CHIPSET_ICH8:
613 case CHIPSET_ICH9:
614 case CHIPSET_ICH10:
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000615 straps_names = straps_names_ich8910;
616 break;
Stefan Tauner92d6a862013-10-25 00:33:37 +0000617 case CHIPSET_TUNNEL_CREEK:
618 straps_names = straps_names_tunnel_creek;
619 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000620 case CHIPSET_5_SERIES_IBEX_PEAK:
621 case CHIPSET_6_SERIES_COUGAR_POINT:
Helge Wagnera0fce5f2012-07-24 16:33:55 +0000622 case CHIPSET_7_SERIES_PANTHER_POINT:
623 straps_names = straps_names_pch567;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000624 break;
Duncan Laurie90eb2262013-03-15 03:12:29 +0000625 case CHIPSET_8_SERIES_LYNX_POINT:
Duncan Laurie823096e2014-08-20 15:39:38 +0000626 case CHIPSET_9_SERIES_WILDCAT_POINT:
Duncan Laurie4095ed72014-08-20 15:39:32 +0000627 case CHIPSET_BAYTRAIL:
Duncan Laurie823096e2014-08-20 15:39:38 +0000628 straps_names = straps_names_pch89_baytrail;
Duncan Laurie90eb2262013-03-15 03:12:29 +0000629 break;
630 case CHIPSET_8_SERIES_LYNX_POINT_LP:
631 straps_names = straps_names_pch8_lp;
632 break;
633 case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet
Stefan Tauner92d6a862013-10-25 00:33:37 +0000634 case CHIPSET_CENTERTON: // FIXME: Datasheet does not mention GCS at all
Duncan Laurie90eb2262013-03-15 03:12:29 +0000635 straps_names = straps_names_unknown;
636 break;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000637 default:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000638 msg_gerr("%s: unknown ICH generation. Please report!\n", __func__);
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000639 straps_names = straps_names_unknown;
640 break;
641 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000642
Duncan Laurie4095ed72014-08-20 15:39:32 +0000643 uint8_t bbs;
644 switch (ich_generation) {
645 case CHIPSET_TUNNEL_CREEK:
646 bbs = (gcs >> 1) & 0x1;
647 break;
648 case CHIPSET_8_SERIES_LYNX_POINT_LP:
649 /* Lynx Point LP uses a single bit for BBS */
650 bbs = (gcs >> 10) & 0x1;
651 break;
652 default:
653 /* Other chipsets use two bits for BBS */
654 bbs = (gcs >> 10) & 0x3;
655 break;
656 }
657 msg_pdbg("Boot BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
658
659 /* Centerton has its TS bit in [GPE0BLK] + 0x30 while the exact location for Tunnel Creek is unknown. */
660 if (ich_generation != CHIPSET_TUNNEL_CREEK && ich_generation != CHIPSET_CENTERTON)
661 msg_pdbg("Top Swap: %s\n", (top_swap) ? "enabled (A16(+) inverted)" : "not enabled");
662}
663
664static int enable_flash_ich_spi(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl)
665{
666
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000667 /* Get physical address of Root Complex Register Block */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000668 uint32_t rcra = pci_read_long(dev, 0xf0) & 0xffffc000;
669 msg_pdbg("Root Complex Register Block address = 0x%x\n", rcra);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000670
671 /* Map RCBA to virtual memory */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000672 void *rcrb = rphysmap("ICH RCRB", rcra, 0x4000);
Stefan Tauner7fb5aa02013-08-14 15:48:44 +0000673 if (rcrb == ERROR_PTR)
Niklas Söderlund5d307202013-09-14 09:02:27 +0000674 return ERROR_FATAL;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000675
Duncan Laurie4095ed72014-08-20 15:39:32 +0000676 enable_flash_ich_handle_gcs(dev, ich_generation, mmio_readl(rcrb + 0x3410), mmio_readb(rcrb + 0x3414));
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000677
Stefan Tauner92d6a862013-10-25 00:33:37 +0000678 /* Handle FWH-related parameters and initialization */
679 int ret_fwh = enable_flash_ich_fwh(dev, ich_generation, bios_cntl);
680 if (ret_fwh == ERROR_FATAL)
681 return ret_fwh;
682
683 /* SPIBAR is at RCRB+0x3020 for ICH[78], Tunnel Creek and Centerton, and RCRB+0x3800 for ICH9. */
684 uint16_t spibar_offset;
685 switch (ich_generation) {
Duncan Laurie4095ed72014-08-20 15:39:32 +0000686 case CHIPSET_BAYTRAIL:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000687 case CHIPSET_ICH_UNKNOWN:
688 return ERROR_FATAL;
689 case CHIPSET_ICH7:
690 case CHIPSET_ICH8:
691 case CHIPSET_TUNNEL_CREEK:
692 case CHIPSET_CENTERTON:
693 spibar_offset = 0x3020;
694 break;
695 case CHIPSET_ICH9:
696 default: /* Future version might behave the same */
697 spibar_offset = 0x3800;
698 break;
699 }
700 msg_pdbg("SPIBAR = 0x%0*" PRIxPTR " + 0x%04x\n", PRIxPTR_WIDTH, (uintptr_t)rcrb, spibar_offset);
701 void *spibar = rcrb + spibar_offset;
702
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000703 /* This adds BUS_SPI */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000704 int ret_spi = ich_init_spi(dev, spibar, ich_generation);
Stefan Tauner50e7c602011-11-08 10:55:54 +0000705 if (ret_spi == ERROR_FATAL)
706 return ret_spi;
707
Stefan Tauner92d6a862013-10-25 00:33:37 +0000708 if (ret_fwh || ret_spi)
709 return ERROR_NONFATAL;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000710
Stefan Tauner92d6a862013-10-25 00:33:37 +0000711 return 0;
712}
713
714static int enable_flash_tunnelcreek(struct pci_dev *dev, const char *name)
715{
716 return enable_flash_ich_spi(dev, CHIPSET_TUNNEL_CREEK, 0xd8);
717}
718
719static int enable_flash_s12x0(struct pci_dev *dev, const char *name)
720{
721 return enable_flash_ich_spi(dev, CHIPSET_CENTERTON, 0xd8);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000722}
Stefan Reinauera9424d52008-06-27 16:28:34 +0000723
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000724static int enable_flash_ich7(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000725{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000726 return enable_flash_ich_spi(dev, CHIPSET_ICH7, 0xdc);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000727}
728
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000729static int enable_flash_ich8(struct pci_dev *dev, const char *name)
730{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000731 return enable_flash_ich_spi(dev, CHIPSET_ICH8, 0xdc);
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000732}
733
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000734static int enable_flash_ich9(struct pci_dev *dev, const char *name)
735{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000736 return enable_flash_ich_spi(dev, CHIPSET_ICH9, 0xdc);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000737}
738
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000739static int enable_flash_ich10(struct pci_dev *dev, const char *name)
740{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000741 return enable_flash_ich_spi(dev, CHIPSET_ICH10, 0xdc);
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000742}
743
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000744/* Ibex Peak aka. 5 series & 3400 series */
745static int enable_flash_pch5(struct pci_dev *dev, const char *name)
746{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000747 return enable_flash_ich_spi(dev, CHIPSET_5_SERIES_IBEX_PEAK, 0xdc);
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000748}
749
750/* Cougar Point aka. 6 series & c200 series */
751static int enable_flash_pch6(struct pci_dev *dev, const char *name)
752{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000753 return enable_flash_ich_spi(dev, CHIPSET_6_SERIES_COUGAR_POINT, 0xdc);
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000754}
755
Stefan Tauner2abab942012-04-27 20:41:23 +0000756/* Panther Point aka. 7 series */
757static int enable_flash_pch7(struct pci_dev *dev, const char *name)
758{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000759 return enable_flash_ich_spi(dev, CHIPSET_7_SERIES_PANTHER_POINT, 0xdc);
Stefan Tauner2abab942012-04-27 20:41:23 +0000760}
761
762/* Lynx Point aka. 8 series */
763static int enable_flash_pch8(struct pci_dev *dev, const char *name)
764{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000765 return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_LYNX_POINT, 0xdc);
Stefan Tauner2abab942012-04-27 20:41:23 +0000766}
767
Stefan Tauner92d6a862013-10-25 00:33:37 +0000768/* Lynx Point LP aka. 8 series low-power */
Duncan Laurie90eb2262013-03-15 03:12:29 +0000769static int enable_flash_pch8_lp(struct pci_dev *dev, const char *name)
770{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000771 return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_LYNX_POINT_LP, 0xdc);
Duncan Laurie90eb2262013-03-15 03:12:29 +0000772}
773
774/* Wellsburg (for Haswell-EP Xeons) */
775static int enable_flash_pch8_wb(struct pci_dev *dev, const char *name)
776{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000777 return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_WELLSBURG, 0xdc);
Duncan Laurie90eb2262013-03-15 03:12:29 +0000778}
779
Duncan Laurie823096e2014-08-20 15:39:38 +0000780/* Wildcat Point */
781static int enable_flash_pch9(struct pci_dev *dev, const char *name)
782{
783 return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT, 0xdc);
784}
785
Duncan Laurie4095ed72014-08-20 15:39:32 +0000786/* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley.
787 * These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately.
788 *
789 * Differences include:
790 * - RCBA at LPC config 0xF0 too but mapped range is only 4 B long instead of 16 kB.
791 * - GCS at [RCRB] + 0 (instead of [RCRB] + 0x3410).
792 * - TS (Top Swap) in GCS (instead of [RCRB] + 0x3414).
793 * - SPIBAR (coined SBASE) at LPC config 0x54 (instead of [RCRB] + 0x3800).
794 * - BIOS_CNTL (coined BCR) at [SPIBAR] + 0xFC (instead of LPC config 0xDC).
795 */
796static int enable_flash_silvermont(struct pci_dev *dev, const char *name)
797{
798 enum ich_chipset ich_generation = CHIPSET_BAYTRAIL;
799
800 /* Get physical address of Root Complex Register Block */
801 uint32_t rcba = pci_read_long(dev, 0xf0) & 0xfffffc00;
802 msg_pdbg("Root Complex Register Block address = 0x%x\n", rcba);
803
804 /* Handle GCS (in RCRB) */
805 void *rcrb = physmap("BYT RCRB", rcba, 4);
806 uint32_t gcs = mmio_readl(rcrb + 0);
807 enable_flash_ich_handle_gcs(dev, ich_generation, gcs, gcs & 0x2);
808 physunmap(rcrb, 4);
809
810 /* Handle fwh_idsel parameter */
811 int ret_fwh = enable_flash_ich_fwh_decode(dev, ich_generation);
812 if (ret_fwh == ERROR_FATAL)
813 return ret_fwh;
814
815 internal_buses_supported = BUS_FWH;
816
817 /* Get physical address of SPI Base Address and map it */
818 uint32_t sbase = pci_read_long(dev, 0x54) & 0xfffffe00;
819 msg_pdbg("SPI_BASE_ADDRESS = 0x%x\n", sbase);
820 void *spibar = rphysmap("BYT SBASE", sbase, 512); /* Last defined address on Bay Trail is 0x100 */
821
822 /* Enable Flash Writes.
823 * Silvermont-based: BCR at SBASE + 0xFC (some bits of BCR are also accessible via BC at IBASE + 0x1C).
824 */
825 enable_flash_ich_bios_cntl_memmapped(ich_generation, spibar + 0xFC);
826
827 int ret_spi = ich_init_spi(dev, spibar, ich_generation);
828 if (ret_spi == ERROR_FATAL)
829 return ret_spi;
830
831 if (ret_fwh || ret_spi)
832 return ERROR_NONFATAL;
833
834 return 0;
835}
836
Michael Karcher89bed6d2010-06-13 10:16:12 +0000837static int via_no_byte_merge(struct pci_dev *dev, const char *name)
838{
839 uint8_t val;
840
841 val = pci_read_byte(dev, 0x71);
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000842 if (val & 0x40) {
Michael Karcher89bed6d2010-06-13 10:16:12 +0000843 msg_pdbg("Disabling byte merging\n");
844 val &= ~0x40;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000845 rpci_write_byte(dev, 0x71, val);
Michael Karcher89bed6d2010-06-13 10:16:12 +0000846 }
847 return NOT_DONE_YET; /* need to find south bridge, too */
848}
849
Uwe Hermann372eeb52007-12-04 21:49:06 +0000850static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000851{
Ollie Lho184a4042005-11-26 21:55:36 +0000852 uint8_t val;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000853
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000854 /* Enable ROM decode range (1MB) FFC00000 - FFFFFFFF. */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000855 rpci_write_byte(dev, 0x41, 0x7f);
Bari Ari9477c4e2008-04-29 13:46:38 +0000856
Uwe Hermannffec5f32007-08-23 16:08:21 +0000857 /* ROM write enable */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000858 val = pci_read_byte(dev, 0x40);
859 val |= 0x10;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000860 rpci_write_byte(dev, 0x40, val);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000861
862 if (pci_read_byte(dev, 0x40) != val) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +0000863 msg_pwarn("\nWarning: Failed to enable flash write on \"%s\"\n", name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000864 return -1;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000865 }
Luc Verhaegen6382b442007-03-02 22:16:38 +0000866
Helge Wagnerdd73d832012-08-24 23:03:46 +0000867 if (dev->device_id == 0x3227) { /* VT8237/VT8237R */
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000868 /* All memory cycles, not just ROM ones, go to LPC. */
869 val = pci_read_byte(dev, 0x59);
870 val &= ~0x80;
871 rpci_write_byte(dev, 0x59, val);
Luc Verhaegen73d21192009-12-23 00:54:26 +0000872 }
873
Uwe Hermanna7e05482007-05-09 10:17:44 +0000874 return 0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000875}
876
Helge Wagnerdd73d832012-08-24 23:03:46 +0000877static int enable_flash_vt_vx(struct pci_dev *dev, const char *name)
878{
879 struct pci_dev *south_north = pci_dev_find(0x1106, 0xa353);
880 if (south_north == NULL) {
881 msg_perr("Could not find South-North Module Interface Control device!\n");
882 return ERROR_FATAL;
883 }
884
885 msg_pdbg("Strapped to ");
886 if ((pci_read_byte(south_north, 0x56) & 0x01) == 0) {
887 msg_pdbg("LPC.\n");
888 return enable_flash_vt823x(dev, name);
889 }
890 msg_pdbg("SPI.\n");
891
892 uint32_t mmio_base;
893 void *mmio_base_physmapped;
894 uint32_t spi_cntl;
895 #define SPI_CNTL_LEN 0x08
896 uint32_t spi0_mm_base = 0;
897 switch(dev->device_id) {
898 case 0x8353: /* VX800/VX820 */
899 spi0_mm_base = pci_read_long(dev, 0xbc) << 8;
900 break;
901 case 0x8409: /* VX855/VX875 */
902 case 0x8410: /* VX900 */
903 mmio_base = pci_read_long(dev, 0xbc) << 8;
904 mmio_base_physmapped = physmap("VIA VX MMIO register", mmio_base, SPI_CNTL_LEN);
Stefan Tauner7fb5aa02013-08-14 15:48:44 +0000905 if (mmio_base_physmapped == ERROR_PTR)
Helge Wagnerdd73d832012-08-24 23:03:46 +0000906 return ERROR_FATAL;
Helge Wagnerdd73d832012-08-24 23:03:46 +0000907
908 /* Offset 0 - Bit 0 holds SPI Bus0 Enable Bit. */
909 spi_cntl = mmio_readl(mmio_base_physmapped) + 0x00;
910 if ((spi_cntl & 0x01) == 0) {
911 msg_pdbg ("SPI Bus0 disabled!\n");
912 physunmap(mmio_base_physmapped, SPI_CNTL_LEN);
913 return ERROR_FATAL;
914 }
915 /* Offset 1-3 has SPI Bus Memory Map Base Address: */
916 spi0_mm_base = spi_cntl & 0xFFFFFF00;
917
918 /* Offset 4 - Bit 0 holds SPI Bus1 Enable Bit. */
919 spi_cntl = mmio_readl(mmio_base_physmapped) + 0x04;
920 if ((spi_cntl & 0x01) == 1)
921 msg_pdbg2("SPI Bus1 is enabled too.\n");
922
923 physunmap(mmio_base_physmapped, SPI_CNTL_LEN);
924 break;
925 default:
926 msg_perr("%s: Unsupported chipset %x:%x!\n", __func__, dev->vendor_id, dev->device_id);
927 return ERROR_FATAL;
928 }
929
930 return via_init_spi(dev, spi0_mm_base);
931}
932
933static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
934{
935 return via_init_spi(dev, pci_read_long(dev, 0xbc) << 8);
936}
937
Uwe Hermann372eeb52007-12-04 21:49:06 +0000938static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000939{
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000940 uint8_t reg8;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000941
Uwe Hermann394131e2008-10-18 21:14:13 +0000942#define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
943#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000944#define CS5530_RESET_CONTROL_REG 0x44 /* F0 index 0x44 */
945#define CS5530_USB_SHADOW_REG 0x43 /* F0 index 0x43 */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000946
Uwe Hermann394131e2008-10-18 21:14:13 +0000947#define LOWER_ROM_ADDRESS_RANGE (1 << 0)
948#define ROM_WRITE_ENABLE (1 << 1)
949#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
950#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000951#define CS5530_ISA_MASTER (1 << 7)
952#define CS5530_ENABLE_SA2320 (1 << 2)
953#define CS5530_ENABLE_SA20 (1 << 6)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000954
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000955 internal_buses_supported = BUS_PARALLEL;
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000956 /* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and
957 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB.
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000958 * FIXME: Should we really touch the low mapping below 1 MB? Flashrom
959 * ignores that region completely.
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000960 * Make the configured ROM areas writable.
961 */
962 reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
963 reg8 |= LOWER_ROM_ADDRESS_RANGE;
964 reg8 |= UPPER_ROM_ADDRESS_RANGE;
965 reg8 |= ROM_WRITE_ENABLE;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000966 rpci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000967
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000968 /* Set positive decode on ROM. */
969 reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
970 reg8 |= BIOS_ROM_POSITIVE_DECODE;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000971 rpci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000972
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000973 reg8 = pci_read_byte(dev, CS5530_RESET_CONTROL_REG);
974 if (reg8 & CS5530_ISA_MASTER) {
975 /* We have A0-A23 available. */
976 max_rom_decode.parallel = 16 * 1024 * 1024;
977 } else {
978 reg8 = pci_read_byte(dev, CS5530_USB_SHADOW_REG);
979 if (reg8 & CS5530_ENABLE_SA2320) {
980 /* We have A0-19, A20-A23 available. */
981 max_rom_decode.parallel = 16 * 1024 * 1024;
982 } else if (reg8 & CS5530_ENABLE_SA20) {
983 /* We have A0-19, A20 available. */
984 max_rom_decode.parallel = 2 * 1024 * 1024;
985 } else {
986 /* A20 and above are not active. */
987 max_rom_decode.parallel = 1024 * 1024;
988 }
989 }
990
Ollie Lhocbbf1252004-03-17 22:22:08 +0000991 return 0;
992}
993
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000994/*
Mart Raudseppe1344da2008-02-08 10:10:57 +0000995 * Geode systems write protect the BIOS via RCONFs (cache settings similar
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000996 * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22.
Mart Raudseppe1344da2008-02-08 10:10:57 +0000997 *
998 * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
999 * To enable write to NOR Boot flash for the benefit of systems that have such
1000 * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
Mart Raudseppe1344da2008-02-08 10:10:57 +00001001 */
Uwe Hermann372eeb52007-12-04 21:49:06 +00001002static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
Lane Brooksd54958a2007-11-13 16:45:22 +00001003{
Uwe Hermann394131e2008-10-18 21:14:13 +00001004#define MSR_RCONF_DEFAULT 0x1808
1005#define MSR_NORF_CTL 0x51400018
Mart Raudsepp0514a5f2008-02-08 09:59:58 +00001006
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001007 msr_t msr;
Lane Brooksd54958a2007-11-13 16:45:22 +00001008
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001009 /* Geode only has a single core */
1010 if (setup_cpu_msr(0))
Lane Brooksd54958a2007-11-13 16:45:22 +00001011 return -1;
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001012
1013 msr = rdmsr(MSR_RCONF_DEFAULT);
1014 if ((msr.hi >> 24) != 0x22) {
1015 msr.hi &= 0xfbffffff;
1016 wrmsr(MSR_RCONF_DEFAULT, msr);
Lane Brooksd54958a2007-11-13 16:45:22 +00001017 }
Mart Raudseppe1344da2008-02-08 10:10:57 +00001018
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001019 msr = rdmsr(MSR_NORF_CTL);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +00001020 /* Raise WE_CS3 bit. */
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001021 msr.lo |= 0x08;
1022 wrmsr(MSR_NORF_CTL, msr);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +00001023
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001024 cleanup_cpu_msr();
Mart Raudsepp0514a5f2008-02-08 09:59:58 +00001025
Uwe Hermann394131e2008-10-18 21:14:13 +00001026#undef MSR_RCONF_DEFAULT
1027#undef MSR_NORF_CTL
Lane Brooksd54958a2007-11-13 16:45:22 +00001028 return 0;
1029}
1030
Uwe Hermann372eeb52007-12-04 21:49:06 +00001031static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001032{
Stefan Taunere34e3e82013-01-01 00:06:51 +00001033 #define SC_REG 0x52
Ollie Lho184a4042005-11-26 21:55:36 +00001034 uint8_t new;
Ollie Lho761bf1b2004-03-20 16:46:10 +00001035
Stefan Taunere34e3e82013-01-01 00:06:51 +00001036 rpci_write_byte(dev, SC_REG, 0xee);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001037
Stefan Taunere34e3e82013-01-01 00:06:51 +00001038 new = pci_read_byte(dev, SC_REG);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001039
Stefan Taunere34e3e82013-01-01 00:06:51 +00001040 if (new != 0xee) { /* FIXME: share this with other code? */
1041 msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", SC_REG, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001042 return -1;
1043 }
Uwe Hermannffec5f32007-08-23 16:08:21 +00001044
Ollie Lhocbbf1252004-03-17 22:22:08 +00001045 return 0;
1046}
1047
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001048/* Works for AMD-768, AMD-8111, VIA VT82C586A/B, VIA VT82C596, VIA VT82C686A/B.
1049 *
1050 * ROM decode control register matrix
1051 * AMD-768 AMD-8111 VT82C586A/B VT82C596 VT82C686A/B
1052 * 7 FFC0_0000h–FFFF_FFFFh <- FFFE0000h-FFFEFFFFh <- <-
1053 * 6 FFB0_0000h–FFBF_FFFFh <- FFF80000h-FFFDFFFFh <- <-
1054 * 5 00E8... <- <- FFF00000h-FFF7FFFFh <-
1055 */
1056static int enable_flash_amd_via(struct pci_dev *dev, const char *name, uint8_t decode_val)
Ollie Lho761bf1b2004-03-20 16:46:10 +00001057{
Stefan Taunere34e3e82013-01-01 00:06:51 +00001058 #define AMD_MAPREG 0x43
1059 #define AMD_ENREG 0x40
Ollie Lho184a4042005-11-26 21:55:36 +00001060 uint8_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +00001061
Stefan Taunere34e3e82013-01-01 00:06:51 +00001062 old = pci_read_byte(dev, AMD_MAPREG);
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001063 new = old | decode_val;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001064 if (new != old) {
Stefan Taunere34e3e82013-01-01 00:06:51 +00001065 rpci_write_byte(dev, AMD_MAPREG, new);
1066 if (pci_read_byte(dev, AMD_MAPREG) != new) {
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001067 msg_pwarn("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n",
Stefan Taunere34e3e82013-01-01 00:06:51 +00001068 AMD_MAPREG, new, name);
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001069 } else
1070 msg_pdbg("Changed ROM decode range to 0x%02x successfully.\n", new);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001071 }
1072
Uwe Hermann190f8492008-10-25 18:03:50 +00001073 /* Enable 'ROM write' bit. */
Stefan Taunere34e3e82013-01-01 00:06:51 +00001074 old = pci_read_byte(dev, AMD_ENREG);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001075 new = old | 0x01;
1076 if (new == old)
1077 return 0;
Stefan Taunere34e3e82013-01-01 00:06:51 +00001078 rpci_write_byte(dev, AMD_ENREG, new);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001079
Stefan Taunere34e3e82013-01-01 00:06:51 +00001080 if (pci_read_byte(dev, AMD_ENREG) != new) {
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001081 msg_pwarn("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n",
Stefan Taunere34e3e82013-01-01 00:06:51 +00001082 AMD_ENREG, new, name);
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001083 return ERROR_NONFATAL;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001084 }
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001085 msg_pdbg2("Set ROM enable bit successfully.\n");
Uwe Hermannffec5f32007-08-23 16:08:21 +00001086
Ollie Lhocbbf1252004-03-17 22:22:08 +00001087 return 0;
1088}
1089
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001090static int enable_flash_amd_768_8111(struct pci_dev *dev, const char *name)
1091{
1092 /* Enable decoding of 0xFFB00000 to 0xFFFFFFFF (5 MB). */
1093 max_rom_decode.lpc = 5 * 1024 * 1024;
1094 return enable_flash_amd_via(dev, name, 0xC0);
1095}
1096
1097static int enable_flash_vt82c586(struct pci_dev *dev, const char *name)
1098{
1099 /* Enable decoding of 0xFFF80000 to 0xFFFFFFFF. (512 kB) */
1100 max_rom_decode.parallel = 512 * 1024;
1101 return enable_flash_amd_via(dev, name, 0xC0);
1102}
1103
1104/* Works for VT82C686A/B too. */
1105static int enable_flash_vt82c596(struct pci_dev *dev, const char *name)
1106{
Stefan Taunerc2eec2c2014-05-03 21:33:01 +00001107 /* Enable decoding of 0xFFF00000 to 0xFFFFFFFF. (1 MB) */
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001108 max_rom_decode.parallel = 1024 * 1024;
1109 return enable_flash_amd_via(dev, name, 0xE0);
1110}
1111
Marc Jones3af487d2008-10-15 17:50:29 +00001112static int enable_flash_sb600(struct pci_dev *dev, const char *name)
1113{
Michael Karcherb05b9e12010-07-22 18:04:19 +00001114 uint32_t prot;
Marc Jones3af487d2008-10-15 17:50:29 +00001115 uint8_t reg;
Michael Karcherb05b9e12010-07-22 18:04:19 +00001116 int ret;
Marc Jones3af487d2008-10-15 17:50:29 +00001117
Jason Wanga3f04be2008-11-28 21:36:51 +00001118 /* Clear ROM protect 0-3. */
1119 for (reg = 0x50; reg < 0x60; reg += 4) {
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001120 prot = pci_read_long(dev, reg);
1121 /* No protection flags for this region?*/
1122 if ((prot & 0x3) == 0)
1123 continue;
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001124 msg_pdbg("Chipset %s%sprotected flash from 0x%08x to 0x%08x, unlocking...",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001125 (prot & 0x2) ? "read " : "",
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001126 (prot & 0x1) ? "write " : "",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001127 (prot & 0xfffff800),
1128 (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001129 prot &= 0xfffffffc;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001130 rpci_write_byte(dev, reg, prot);
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001131 prot = pci_read_long(dev, reg);
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001132 if ((prot & 0x3) != 0) {
1133 msg_perr("Disabling %s%sprotection of flash addresses from 0x%08x to 0x%08x failed.\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001134 (prot & 0x2) ? "read " : "",
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001135 (prot & 0x1) ? "write " : "",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001136 (prot & 0xfffff800),
1137 (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001138 continue;
1139 }
1140 msg_pdbg("done.\n");
Jason Wanga3f04be2008-11-28 21:36:51 +00001141 }
1142
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +00001143 internal_buses_supported = BUS_LPC | BUS_FWH;
Michael Karcherb05b9e12010-07-22 18:04:19 +00001144
1145 ret = sb600_probe_spi(dev);
Jason Wanga3f04be2008-11-28 21:36:51 +00001146
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001147 /* Read ROM strap override register. */
1148 OUTB(0x8f, 0xcd6);
1149 reg = INB(0xcd7);
1150 reg &= 0x0e;
Sean Nelson316a29f2010-05-07 20:09:04 +00001151 msg_pdbg("ROM strap override is %sactive", (reg & 0x02) ? "" : "not ");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001152 if (reg & 0x02) {
1153 switch ((reg & 0x0c) >> 2) {
1154 case 0x00:
Sean Nelson316a29f2010-05-07 20:09:04 +00001155 msg_pdbg(": LPC");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001156 break;
1157 case 0x01:
Sean Nelson316a29f2010-05-07 20:09:04 +00001158 msg_pdbg(": PCI");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001159 break;
1160 case 0x02:
Sean Nelson316a29f2010-05-07 20:09:04 +00001161 msg_pdbg(": FWH");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001162 break;
1163 case 0x03:
Sean Nelson316a29f2010-05-07 20:09:04 +00001164 msg_pdbg(": SPI");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001165 break;
1166 }
1167 }
Sean Nelson316a29f2010-05-07 20:09:04 +00001168 msg_pdbg("\n");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001169
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001170 /* Force enable SPI ROM in SB600 PM register.
1171 * If we enable SPI ROM here, we have to disable it after we leave.
Zheng Bao284a6002009-05-04 22:33:50 +00001172 * But how can we know which ROM we are going to handle? So we have
1173 * to trade off. We only access LPC ROM if we boot via LPC ROM. And
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001174 * only SPI ROM if we boot via SPI ROM. If you want to access SPI on
1175 * boards with LPC straps, you have to use the code below.
Zheng Bao284a6002009-05-04 22:33:50 +00001176 */
1177 /*
Jason Wanga3f04be2008-11-28 21:36:51 +00001178 OUTB(0x8f, 0xcd6);
1179 OUTB(0x0e, 0xcd7);
Zheng Bao284a6002009-05-04 22:33:50 +00001180 */
Marc Jones3af487d2008-10-15 17:50:29 +00001181
Michael Karcherb05b9e12010-07-22 18:04:19 +00001182 return ret;
Marc Jones3af487d2008-10-15 17:50:29 +00001183}
1184
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001185/* sets bit 0 in 0x6d */
1186static int enable_flash_nvidia_common(struct pci_dev *dev, const char *name)
1187{
1188 uint8_t old, new;
1189
1190 old = pci_read_byte(dev, 0x6d);
1191 new = old | 0x01;
1192 if (new == old)
1193 return 0;
1194
1195 rpci_write_byte(dev, 0x6d, new);
1196 if (pci_read_byte(dev, 0x6d) != new) {
1197 msg_pinfo("Setting register 0x6d to 0x%02x on %s failed.\n", new, name);
1198 return 1;
1199 }
1200 return 0;
1201}
1202
Luc Verhaegen90e8e612009-05-26 09:48:28 +00001203static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name)
1204{
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001205 rpci_write_byte(dev, 0x92, 0);
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001206 if (enable_flash_nvidia_common(dev, name))
1207 return ERROR_NONFATAL;
1208 else
1209 return 0;
Luc Verhaegen90e8e612009-05-26 09:48:28 +00001210}
1211
Uwe Hermann372eeb52007-12-04 21:49:06 +00001212static int enable_flash_ck804(struct pci_dev *dev, const char *name)
Yinghai Lu952dfce2005-07-06 17:13:46 +00001213{
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001214 uint32_t segctrl;
1215 uint8_t reg, old, new;
1216 unsigned int err = 0;
Yinghai Lu952dfce2005-07-06 17:13:46 +00001217
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001218 /* 0x8A is special: it is a single byte and only one nibble is touched. */
1219 reg = 0x8A;
1220 segctrl = pci_read_byte(dev, reg);
1221 if ((segctrl & 0x3) != 0x0) {
1222 if ((segctrl & 0xC) != 0x0) {
1223 msg_pinfo("Can not unlock existing protection in register 0x%02x.\n", reg);
1224 err++;
1225 } else {
1226 msg_pdbg("Unlocking protection in register 0x%02x... ", reg);
1227 rpci_write_byte(dev, reg, segctrl & 0xF0);
1228
1229 segctrl = pci_read_byte(dev, reg);
1230 if ((segctrl & 0x3) != 0x0) {
1231 msg_pinfo("Could not unlock protection in register 0x%02x (new value: 0x%x).\n",
1232 reg, segctrl);
1233 err++;
1234 } else
1235 msg_pdbg("OK\n");
1236 }
Jonathan Kollasch9ce498e2011-08-06 12:45:21 +00001237 }
1238
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001239 for (reg = 0x8C; reg <= 0x94; reg += 4) {
1240 segctrl = pci_read_long(dev, reg);
1241 if ((segctrl & 0x33333333) == 0x00000000) {
1242 /* reads and writes are unlocked */
1243 continue;
1244 }
1245 if ((segctrl & 0xCCCCCCCC) != 0x00000000) {
1246 msg_pinfo("Can not unlock existing protection in register 0x%02x.\n", reg);
1247 err++;
1248 continue;
1249 }
1250 msg_pdbg("Unlocking protection in register 0x%02x... ", reg);
1251 rpci_write_long(dev, reg, 0x00000000);
1252
1253 segctrl = pci_read_long(dev, reg);
1254 if ((segctrl & 0x33333333) != 0x00000000) {
1255 msg_pinfo("Could not unlock protection in register 0x%02x (new value: 0x%08x).\n",
1256 reg, segctrl);
1257 err++;
1258 } else
1259 msg_pdbg("OK\n");
1260 }
1261
1262 if (err > 0) {
1263 msg_pinfo("%d locks could not be disabled, disabling writes (reads may also fail).\n", err);
1264 programmer_may_write = 0;
1265 }
1266
1267 reg = 0x88;
1268 old = pci_read_byte(dev, reg);
1269 new = old | 0xC0;
Uwe Hermanna7e05482007-05-09 10:17:44 +00001270 if (new != old) {
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001271 rpci_write_byte(dev, reg, new);
Stefan Taunere34e3e82013-01-01 00:06:51 +00001272 if (pci_read_byte(dev, reg) != new) { /* FIXME: share this with other code? */
1273 msg_pinfo("Setting register 0x%02x to 0x%02x on %s failed.\n", reg, new, name);
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001274 err++;
Uwe Hermanna7e05482007-05-09 10:17:44 +00001275 }
1276 }
Yinghai Lu952dfce2005-07-06 17:13:46 +00001277
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001278 if (enable_flash_nvidia_common(dev, name))
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001279 err++;
1280
1281 if (err > 0)
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001282 return ERROR_NONFATAL;
1283 else
Uwe Hermanna7e05482007-05-09 10:17:44 +00001284 return 0;
Yinghai Lu952dfce2005-07-06 17:13:46 +00001285}
1286
Joshua Roys85835d82010-09-15 14:47:56 +00001287static int enable_flash_osb4(struct pci_dev *dev, const char *name)
1288{
1289 uint8_t tmp;
1290
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +00001291 internal_buses_supported = BUS_PARALLEL;
Joshua Roys85835d82010-09-15 14:47:56 +00001292
1293 tmp = INB(0xc06);
1294 tmp |= 0x1;
1295 OUTB(tmp, 0xc06);
1296
1297 tmp = INB(0xc6f);
1298 tmp |= 0x40;
1299 OUTB(tmp, 0xc6f);
1300
1301 return 0;
1302}
1303
Uwe Hermann372eeb52007-12-04 21:49:06 +00001304/* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
1305static int enable_flash_sb400(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +00001306{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001307 uint8_t tmp;
Stefan Reinauer86de2832006-03-31 11:26:55 +00001308 struct pci_dev *smbusdev;
1309
Uwe Hermann372eeb52007-12-04 21:49:06 +00001310 /* Look for the SMBus device. */
Carl-Daniel Hailfingerf6e3efb2009-05-06 00:35:31 +00001311 smbusdev = pci_dev_find(0x1002, 0x4372);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001312
Uwe Hermanna7e05482007-05-09 10:17:44 +00001313 if (!smbusdev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001314 msg_perr("ERROR: SMBus device not found. Aborting.\n");
Tadas Slotkus0e3f1cf2011-09-06 18:49:31 +00001315 return ERROR_FATAL;
Stefan Reinauer86de2832006-03-31 11:26:55 +00001316 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001317
Uwe Hermann372eeb52007-12-04 21:49:06 +00001318 /* Enable some SMBus stuff. */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001319 tmp = pci_read_byte(smbusdev, 0x79);
1320 tmp |= 0x01;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001321 rpci_write_byte(smbusdev, 0x79, tmp);
Stefan Reinauer86de2832006-03-31 11:26:55 +00001322
Uwe Hermann372eeb52007-12-04 21:49:06 +00001323 /* Change southbridge. */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001324 tmp = pci_read_byte(dev, 0x48);
1325 tmp |= 0x21;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001326 rpci_write_byte(dev, 0x48, tmp);
Stefan Reinauer86de2832006-03-31 11:26:55 +00001327
Uwe Hermann372eeb52007-12-04 21:49:06 +00001328 /* Now become a bit silly. */
Andriy Gapon65c1b862008-05-22 13:22:45 +00001329 tmp = INB(0xc6f);
1330 OUTB(tmp, 0xeb);
1331 OUTB(tmp, 0xeb);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001332 tmp |= 0x40;
Andriy Gapon65c1b862008-05-22 13:22:45 +00001333 OUTB(tmp, 0xc6f);
1334 OUTB(tmp, 0xeb);
1335 OUTB(tmp, 0xeb);
Stefan Reinauer86de2832006-03-31 11:26:55 +00001336
1337 return 0;
1338}
1339
Uwe Hermann372eeb52007-12-04 21:49:06 +00001340static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
Yinghai Luca782972007-01-22 20:21:17 +00001341{
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001342 uint8_t val;
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001343 uint16_t wordval;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001344
Uwe Hermann372eeb52007-12-04 21:49:06 +00001345 /* Set the 0-16 MB enable bits. */
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001346 val = pci_read_byte(dev, 0x88);
1347 val |= 0xff; /* 256K */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001348 rpci_write_byte(dev, 0x88, val);
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001349 val = pci_read_byte(dev, 0x8c);
1350 val |= 0xff; /* 1M */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001351 rpci_write_byte(dev, 0x8c, val);
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001352 wordval = pci_read_word(dev, 0x90);
1353 wordval |= 0x7fff; /* 16M */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001354 rpci_write_word(dev, 0x90, wordval);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001355
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001356 if (enable_flash_nvidia_common(dev, name))
1357 return ERROR_NONFATAL;
1358 else
Uwe Hermanna7e05482007-05-09 10:17:44 +00001359 return 0;
Yinghai Luca782972007-01-22 20:21:17 +00001360}
1361
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001362/*
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001363 * The MCP6x/MCP7x code is based on cleanroom reverse engineering.
1364 * It is assumed that LPC chips need the MCP55 code and SPI chips need the
1365 * code provided in enable_flash_mcp6x_7x_common.
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001366 */
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001367static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001368{
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001369 int ret = 0, want_spi = 0;
Michael Karchercfa674f2010-02-25 11:38:23 +00001370 uint8_t val;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001371
1372 /* dev is the ISA bridge. No idea what the stuff below does. */
Michael Karchercfa674f2010-02-25 11:38:23 +00001373 val = pci_read_byte(dev, 0x8a);
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001374 msg_pdbg("ISA/LPC bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5 "
Michael Karchercfa674f2010-02-25 11:38:23 +00001375 "is %i\n", val, (val >> 6) & 0x1, (val >> 5) & 0x1);
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001376
Michael Karchercfa674f2010-02-25 11:38:23 +00001377 switch ((val >> 5) & 0x3) {
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001378 case 0x0:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001379 ret = enable_flash_mcp55(dev, name);
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +00001380 internal_buses_supported = BUS_LPC;
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001381 msg_pdbg("Flash bus type is LPC\n");
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001382 break;
1383 case 0x2:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001384 want_spi = 1;
1385 /* SPI is added in mcp6x_spi_init if it works.
1386 * Do we really want to disable LPC in this case?
1387 */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +00001388 internal_buses_supported = BUS_NONE;
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001389 msg_pdbg("Flash bus type is SPI\n");
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001390 break;
1391 default:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001392 /* Should not happen. */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +00001393 internal_buses_supported = BUS_NONE;
Stefan Tauner7ba3d6c2014-06-12 21:07:03 +00001394 msg_pwarn("Flash bus type is unknown (none)\n");
1395 msg_pinfo("Please send the log files created by \"flashrom -p internal -o logfile\" to \n"
1396 "flashrom@flashrom.org with \"your board name: flashrom -V\" as the subject to\n"
1397 "help us finish support for your chipset. Thanks.\n");
1398 return ERROR_NONFATAL;
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001399 }
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001400
1401 /* Force enable SPI and disable LPC? Not a good idea. */
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001402#if 0
Michael Karchercfa674f2010-02-25 11:38:23 +00001403 val |= (1 << 6);
1404 val &= ~(1 << 5);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001405 rpci_write_byte(dev, 0x8a, val);
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001406#endif
1407
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001408 if (mcp6x_spi_init(want_spi))
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001409 ret = 1;
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001410
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001411 return ret;
1412}
1413
Uwe Hermann372eeb52007-12-04 21:49:06 +00001414static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001415{
Michael Karchercfa674f2010-02-25 11:38:23 +00001416 uint8_t val;
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001417
Uwe Hermanne823ee02007-06-05 15:02:18 +00001418 /* Set the 4MB enable bit. */
Michael Karchercfa674f2010-02-25 11:38:23 +00001419 val = pci_read_byte(dev, 0x41);
1420 val |= 0x0e;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001421 rpci_write_byte(dev, 0x41, val);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001422
Michael Karchercfa674f2010-02-25 11:38:23 +00001423 val = pci_read_byte(dev, 0x43);
1424 val |= (1 << 4);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001425 rpci_write_byte(dev, 0x43, val);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001426
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001427 return 0;
1428}
1429
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001430/*
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001431 * Usually on the x86 architectures (and on other PC-like platforms like some
1432 * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD
1433 * Elan SC520 only a small piece of the system flash is mapped there, but the
1434 * complete flash is mapped somewhere below 1G. The position can be determined
1435 * by the BOOTCS PAR register.
1436 */
1437static int get_flashbase_sc520(struct pci_dev *dev, const char *name)
1438{
1439 int i, bootcs_found = 0;
1440 uint32_t parx = 0;
1441 void *mmcr;
1442
1443 /* 1. Map MMCR */
Stefan Reinauer0593f212009-01-26 01:10:48 +00001444 mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize());
Niklas Söderlund5d307202013-09-14 09:02:27 +00001445 if (mmcr == ERROR_PTR)
1446 return ERROR_FATAL;
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001447
1448 /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for
1449 * BOOTCS region (PARx[31:29] = 100b)e
1450 */
1451 for (i = 0x88; i <= 0xc4; i += 4) {
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +00001452 parx = mmio_readl(mmcr + i);
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001453 if ((parx >> 29) == 4) {
1454 bootcs_found = 1;
1455 break; /* BOOTCS found */
1456 }
1457 }
1458
1459 /* 3. PARx[25] = 1b --> flashbase[29:16] = PARx[13:0]
1460 * PARx[25] = 0b --> flashbase[29:12] = PARx[17:0]
1461 */
1462 if (bootcs_found) {
1463 if (parx & (1 << 25)) {
1464 parx &= (1 << 14) - 1; /* Mask [13:0] */
1465 flashbase = parx << 16;
1466 } else {
1467 parx &= (1 << 18) - 1; /* Mask [17:0] */
1468 flashbase = parx << 12;
1469 }
1470 } else {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001471 msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. "
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001472 "Assuming flash at 4G.\n");
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001473 }
1474
1475 /* 4. Clean up */
Carl-Daniel Hailfingerbe726812009-08-09 12:44:08 +00001476 physunmap(mmcr, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001477 return 0;
1478}
1479
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001480#endif
1481
Idwer Vollering326a0602011-06-18 18:45:41 +00001482/* Please keep this list numerically sorted by vendor/device ID. */
Uwe Hermann05fab752009-05-16 23:42:17 +00001483const struct penable chipset_enables[] = {
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001484#if defined(__i386__) || defined(__x86_64__)
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001485 {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400},
1486 {0x1002, 0x438d, OK, "AMD", "SB600", enable_flash_sb600},
1487 {0x1002, 0x439d, OK, "AMD", "SB7x0/SB8x0/SB9x0", enable_flash_sb600},
1488 {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100},
1489 {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536},
1490 {0x1022, 0x2090, OK, "AMD", "CS5536", enable_flash_cs5536},
1491 {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520},
1492 {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd_768_8111},
1493 {0x1022, 0x7468, OK, "AMD", "AMD-8111", enable_flash_amd_768_8111},
1494 {0x1022, 0x780e, OK, "AMD", "FCH", enable_flash_sb600},
1495 {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501},
1496 {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496},
1497 {0x1039, 0x0530, OK, "SiS", "530", enable_flash_sis530},
1498 {0x1039, 0x0540, NT, "SiS", "540", enable_flash_sis540},
1499 {0x1039, 0x0620, NT, "SiS", "620", enable_flash_sis530},
1500 {0x1039, 0x0630, NT, "SiS", "630", enable_flash_sis540},
1501 {0x1039, 0x0635, NT, "SiS", "635", enable_flash_sis540},
1502 {0x1039, 0x0640, NT, "SiS", "640", enable_flash_sis540},
1503 {0x1039, 0x0645, NT, "SiS", "645", enable_flash_sis540},
1504 {0x1039, 0x0646, OK, "SiS", "645DX", enable_flash_sis540},
1505 {0x1039, 0x0648, OK, "SiS", "648", enable_flash_sis540},
1506 {0x1039, 0x0650, OK, "SiS", "650", enable_flash_sis540},
1507 {0x1039, 0x0651, OK, "SiS", "651", enable_flash_sis540},
1508 {0x1039, 0x0655, NT, "SiS", "655", enable_flash_sis540},
1509 {0x1039, 0x0661, OK, "SiS", "661", enable_flash_sis540},
1510 {0x1039, 0x0730, OK, "SiS", "730", enable_flash_sis540},
1511 {0x1039, 0x0733, NT, "SiS", "733", enable_flash_sis540},
1512 {0x1039, 0x0735, OK, "SiS", "735", enable_flash_sis540},
1513 {0x1039, 0x0740, NT, "SiS", "740", enable_flash_sis540},
1514 {0x1039, 0x0741, OK, "SiS", "741", enable_flash_sis540},
1515 {0x1039, 0x0745, OK, "SiS", "745", enable_flash_sis540},
1516 {0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis540},
1517 {0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis540},
1518 {0x1039, 0x0755, OK, "SiS", "755", enable_flash_sis540},
1519 {0x1039, 0x5511, NT, "SiS", "5511", enable_flash_sis5511},
1520 {0x1039, 0x5571, NT, "SiS", "5571", enable_flash_sis530},
1521 {0x1039, 0x5591, NT, "SiS", "5591/5592", enable_flash_sis530},
1522 {0x1039, 0x5596, NT, "SiS", "5596", enable_flash_sis5511},
1523 {0x1039, 0x5597, NT, "SiS", "5597/5598/5581/5120", enable_flash_sis530},
1524 {0x1039, 0x5600, NT, "SiS", "600", enable_flash_sis530},
1525 {0x1078, 0x0100, OK, "AMD", "CS5530(A)", enable_flash_cs5530},
1526 {0x10b9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533},
1527 {0x10de, 0x0030, OK, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2},
1528 {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */
1529 {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */
1530 {0x10de, 0x0060, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2},
1531 {0x10de, 0x00e0, OK, "NVIDIA", "NForce3", enable_flash_nvidia_nforce2},
Uwe Hermanneac10162008-03-13 18:52:51 +00001532 /* Slave, should not be here, to fix known bug for A01. */
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001533 {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804},
1534 {0x10de, 0x0260, OK, "NVIDIA", "MCP51", enable_flash_ck804},
1535 {0x10de, 0x0261, OK, "NVIDIA", "MCP51", enable_flash_ck804},
1536 {0x10de, 0x0262, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1537 {0x10de, 0x0263, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1538 {0x10de, 0x0360, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* M57SLI*/
Carl-Daniel Hailfinger33d7b6a2010-05-22 07:27:16 +00001539 /* 10de:0361 is present in Tyan S2915 OEM systems, but not connected to
1540 * the flash chip. Instead, 10de:0364 is connected to the flash chip.
1541 * Until we have PCI device class matching or some fallback mechanism,
1542 * this is needed to get flashrom working on Tyan S2915 and maybe other
1543 * dual-MCP55 boards.
1544 */
1545#if 0
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001546 {0x10de, 0x0361, NT, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
Carl-Daniel Hailfinger33d7b6a2010-05-22 07:27:16 +00001547#endif
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001548 {0x10de, 0x0362, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1549 {0x10de, 0x0363, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1550 {0x10de, 0x0364, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1551 {0x10de, 0x0365, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1552 {0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1553 {0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */
1554 {0x10de, 0x03e0, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1555 {0x10de, 0x03e1, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1556 {0x10de, 0x03e3, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1557 {0x10de, 0x0440, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1558 {0x10de, 0x0441, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1559 {0x10de, 0x0442, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1560 {0x10de, 0x0443, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1561 {0x10de, 0x0548, OK, "NVIDIA", "MCP67", enable_flash_mcp6x_7x},
1562 {0x10de, 0x075c, OK, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x},
1563 {0x10de, 0x075d, OK, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x},
1564 {0x10de, 0x07d7, OK, "NVIDIA", "MCP73", enable_flash_mcp6x_7x},
1565 {0x10de, 0x0aac, OK, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1566 {0x10de, 0x0aad, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1567 {0x10de, 0x0aae, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1568 {0x10de, 0x0aaf, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1569 {0x10de, 0x0d80, NT, "NVIDIA", "MCP89", enable_flash_mcp6x_7x},
Michael Karcher89bed6d2010-06-13 10:16:12 +00001570 /* VIA northbridges */
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001571 {0x1106, 0x0585, NT, "VIA", "VT82C585VPX", via_no_byte_merge},
1572 {0x1106, 0x0595, NT, "VIA", "VT82C595", via_no_byte_merge},
1573 {0x1106, 0x0597, NT, "VIA", "VT82C597", via_no_byte_merge},
1574 {0x1106, 0x0601, NT, "VIA", "VT8601/VT8601A", via_no_byte_merge},
1575 {0x1106, 0x0691, OK, "VIA", "VT82C69x", via_no_byte_merge},
1576 {0x1106, 0x8601, NT, "VIA", "VT8601T", via_no_byte_merge},
Michael Karcher89bed6d2010-06-13 10:16:12 +00001577 /* VIA southbridges */
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001578 {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_vt82c586},
1579 {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_vt82c596},
1580 {0x1106, 0x0686, OK, "VIA", "VT82C686A/B", enable_flash_vt82c596},
1581 {0x1106, 0x3074, OK, "VIA", "VT8233", enable_flash_vt823x},
1582 {0x1106, 0x3147, OK, "VIA", "VT8233A", enable_flash_vt823x},
1583 {0x1106, 0x3177, OK, "VIA", "VT8235", enable_flash_vt823x},
1584 {0x1106, 0x3227, OK, "VIA", "VT8237(R)", enable_flash_vt823x},
1585 {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x},
1586 {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi},
1587 {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x},
1588 {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x},
1589 {0x1106, 0x8353, NT, "VIA", "VX800/VX820", enable_flash_vt_vx},
1590 {0x1106, 0x8409, NT, "VIA", "VX855/VX875", enable_flash_vt_vx},
1591 {0x1106, 0x8410, NT, "VIA", "VX900", enable_flash_vt_vx},
1592 {0x1166, 0x0200, OK, "Broadcom", "OSB4", enable_flash_osb4},
1593 {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000},
1594 {0x17f3, 0x6030, OK, "RDC", "R8610/R3210", enable_flash_rdc_r8610},
1595 {0x8086, 0x0c60, NT, "Intel", "S12x0", enable_flash_s12x0},
Stefan Tauner5c316f92015-02-08 21:57:52 +00001596 {0x8086, 0x0f1c, OK, "Intel", "Bay Trail", enable_flash_silvermont},
Duncan Laurie4095ed72014-08-20 15:39:32 +00001597 {0x8086, 0x0f1d, NT, "Intel", "Bay Trail", enable_flash_silvermont},
1598 {0x8086, 0x0f1e, NT, "Intel", "Bay Trail", enable_flash_silvermont},
1599 {0x8086, 0x0f1f, NT, "Intel", "Bay Trail", enable_flash_silvermont},
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001600 {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4},
1601 {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4},
1602 {0x8086, 0x1c44, DEP, "Intel", "Z68", enable_flash_pch6},
1603 {0x8086, 0x1c46, DEP, "Intel", "P67", enable_flash_pch6},
1604 {0x8086, 0x1c47, NT, "Intel", "UM67", enable_flash_pch6},
1605 {0x8086, 0x1c49, NT, "Intel", "HM65", enable_flash_pch6},
1606 {0x8086, 0x1c4a, DEP, "Intel", "H67", enable_flash_pch6},
1607 {0x8086, 0x1c4b, NT, "Intel", "HM67", enable_flash_pch6},
1608 {0x8086, 0x1c4c, NT, "Intel", "Q65", enable_flash_pch6},
1609 {0x8086, 0x1c4d, NT, "Intel", "QS67", enable_flash_pch6},
1610 {0x8086, 0x1c4e, NT, "Intel", "Q67", enable_flash_pch6},
1611 {0x8086, 0x1c4f, DEP, "Intel", "QM67", enable_flash_pch6},
1612 {0x8086, 0x1c50, NT, "Intel", "B65", enable_flash_pch6},
1613 {0x8086, 0x1c52, NT, "Intel", "C202", enable_flash_pch6},
1614 {0x8086, 0x1c54, DEP, "Intel", "C204", enable_flash_pch6},
1615 {0x8086, 0x1c56, NT, "Intel", "C206", enable_flash_pch6},
1616 {0x8086, 0x1c5c, DEP, "Intel", "H61", enable_flash_pch6},
1617 {0x8086, 0x1d40, DEP, "Intel", "C60x/X79", enable_flash_pch6},
1618 {0x8086, 0x1d41, DEP, "Intel", "C60x/X79", enable_flash_pch6},
1619 {0x8086, 0x1e44, DEP, "Intel", "Z77", enable_flash_pch7},
1620 {0x8086, 0x1e46, NT, "Intel", "Z75", enable_flash_pch7},
1621 {0x8086, 0x1e47, NT, "Intel", "Q77", enable_flash_pch7},
1622 {0x8086, 0x1e48, NT, "Intel", "Q75", enable_flash_pch7},
1623 {0x8086, 0x1e49, DEP, "Intel", "B75", enable_flash_pch7},
1624 {0x8086, 0x1e4a, DEP, "Intel", "H77", enable_flash_pch7},
1625 {0x8086, 0x1e53, NT, "Intel", "C216", enable_flash_pch7},
1626 {0x8086, 0x1e55, DEP, "Intel", "QM77", enable_flash_pch7},
1627 {0x8086, 0x1e56, NT, "Intel", "QS77", enable_flash_pch7},
1628 {0x8086, 0x1e57, DEP, "Intel", "HM77", enable_flash_pch7},
1629 {0x8086, 0x1e58, NT, "Intel", "UM77", enable_flash_pch7},
1630 {0x8086, 0x1e59, NT, "Intel", "HM76", enable_flash_pch7},
1631 {0x8086, 0x1e5d, NT, "Intel", "HM75", enable_flash_pch7},
1632 {0x8086, 0x1e5e, NT, "Intel", "HM70", enable_flash_pch7},
1633 {0x8086, 0x1e5f, DEP, "Intel", "NM70", enable_flash_pch7},
Duncan Laurie4095ed72014-08-20 15:39:32 +00001634 {0x8086, 0x1f38, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont},
1635 {0x8086, 0x1f39, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont},
1636 {0x8086, 0x1f3a, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont},
1637 {0x8086, 0x1f3b, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont},
Stefan Tauner5c316f92015-02-08 21:57:52 +00001638 {0x8086, 0x229c, NT, "Intel", "Braswell", enable_flash_silvermont},
Duncan Laurie4095ed72014-08-20 15:39:32 +00001639 {0x8086, 0x2310, NT, "Intel", "DH89xxCC (Cave Creek)", enable_flash_pch7},
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001640 {0x8086, 0x2390, NT, "Intel", "Coleto Creek", enable_flash_pch7},
1641 {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich0},
1642 {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich0},
1643 {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich2345},
1644 {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich2345},
1645 {0x8086, 0x2450, NT, "Intel", "C-ICH", enable_flash_ich2345},
1646 {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich2345},
1647 {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich2345},
1648 {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich2345},
1649 {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich2345},
1650 {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich2345},
1651 {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich2345},
1652 {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich6},
1653 {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich6},
1654 {0x8086, 0x2642, NT, "Intel", "ICH6W/ICH6RW", enable_flash_ich6},
1655 {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich6},
1656 {0x8086, 0x27b0, OK, "Intel", "ICH7DH", enable_flash_ich7},
1657 {0x8086, 0x27b8, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7},
1658 {0x8086, 0x27b9, OK, "Intel", "ICH7M", enable_flash_ich7},
1659 {0x8086, 0x27bc, OK, "Intel", "NM10", enable_flash_ich7},
1660 {0x8086, 0x27bd, OK, "Intel", "ICH7MDH", enable_flash_ich7},
1661 {0x8086, 0x2810, DEP, "Intel", "ICH8/ICH8R", enable_flash_ich8},
1662 {0x8086, 0x2811, DEP, "Intel", "ICH8M-E", enable_flash_ich8},
1663 {0x8086, 0x2812, DEP, "Intel", "ICH8DH", enable_flash_ich8},
1664 {0x8086, 0x2814, DEP, "Intel", "ICH8DO", enable_flash_ich8},
1665 {0x8086, 0x2815, DEP, "Intel", "ICH8M", enable_flash_ich8},
1666 {0x8086, 0x2910, DEP, "Intel", "ICH9 Eng. Sample", enable_flash_ich9},
1667 {0x8086, 0x2912, DEP, "Intel", "ICH9DH", enable_flash_ich9},
1668 {0x8086, 0x2914, DEP, "Intel", "ICH9DO", enable_flash_ich9},
1669 {0x8086, 0x2916, DEP, "Intel", "ICH9R", enable_flash_ich9},
1670 {0x8086, 0x2917, DEP, "Intel", "ICH9M-E", enable_flash_ich9},
1671 {0x8086, 0x2918, DEP, "Intel", "ICH9", enable_flash_ich9},
1672 {0x8086, 0x2919, DEP, "Intel", "ICH9M", enable_flash_ich9},
1673 {0x8086, 0x3a10, NT, "Intel", "ICH10R Eng. Sample", enable_flash_ich10},
1674 {0x8086, 0x3a14, DEP, "Intel", "ICH10DO", enable_flash_ich10},
1675 {0x8086, 0x3a16, DEP, "Intel", "ICH10R", enable_flash_ich10},
1676 {0x8086, 0x3a18, DEP, "Intel", "ICH10", enable_flash_ich10},
1677 {0x8086, 0x3a1a, DEP, "Intel", "ICH10D", enable_flash_ich10},
1678 {0x8086, 0x3a1e, NT, "Intel", "ICH10 Eng. Sample", enable_flash_ich10},
1679 {0x8086, 0x3b00, NT, "Intel", "3400 Desktop", enable_flash_pch5},
1680 {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_pch5},
1681 {0x8086, 0x3b02, NT, "Intel", "P55", enable_flash_pch5},
1682 {0x8086, 0x3b03, NT, "Intel", "PM55", enable_flash_pch5},
1683 {0x8086, 0x3b06, DEP, "Intel", "H55", enable_flash_pch5},
1684 {0x8086, 0x3b07, DEP, "Intel", "QM57", enable_flash_pch5},
1685 {0x8086, 0x3b08, NT, "Intel", "H57", enable_flash_pch5},
1686 {0x8086, 0x3b09, NT, "Intel", "HM55", enable_flash_pch5},
1687 {0x8086, 0x3b0a, NT, "Intel", "Q57", enable_flash_pch5},
1688 {0x8086, 0x3b0b, NT, "Intel", "HM57", enable_flash_pch5},
1689 {0x8086, 0x3b0d, NT, "Intel", "3400 Mobile SFF", enable_flash_pch5},
1690 {0x8086, 0x3b0e, NT, "Intel", "B55", enable_flash_pch5},
1691 {0x8086, 0x3b0f, DEP, "Intel", "QS57", enable_flash_pch5},
1692 {0x8086, 0x3b12, NT, "Intel", "3400", enable_flash_pch5},
1693 {0x8086, 0x3b14, DEP, "Intel", "3420", enable_flash_pch5},
1694 {0x8086, 0x3b16, NT, "Intel", "3450", enable_flash_pch5},
1695 {0x8086, 0x3b1e, NT, "Intel", "B55", enable_flash_pch5},
1696 {0x8086, 0x5031, OK, "Intel", "EP80579", enable_flash_ich7},
1697 {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4},
1698 {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4},
1699 {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4},
1700 {0x8086, 0x8119, OK, "Intel", "SCH Poulsbo", enable_flash_poulsbo},
Duncan Laurie4095ed72014-08-20 15:39:32 +00001701 {0x8086, 0x8186, OK, "Intel", "Atom E6xx(T) (Tunnel Creek)", enable_flash_tunnelcreek},
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001702 {0x8086, 0x8c40, NT, "Intel", "Lynx Point", enable_flash_pch8},
1703 {0x8086, 0x8c41, NT, "Intel", "Lynx Point Mobile Eng. Sample", enable_flash_pch8},
1704 {0x8086, 0x8c42, NT, "Intel", "Lynx Point Desktop Eng. Sample",enable_flash_pch8},
1705 {0x8086, 0x8c43, NT, "Intel", "Lynx Point", enable_flash_pch8},
1706 {0x8086, 0x8c44, DEP, "Intel", "Z87", enable_flash_pch8},
1707 {0x8086, 0x8c45, NT, "Intel", "Lynx Point", enable_flash_pch8},
1708 {0x8086, 0x8c46, NT, "Intel", "Z85", enable_flash_pch8},
1709 {0x8086, 0x8c47, NT, "Intel", "Lynx Point", enable_flash_pch8},
1710 {0x8086, 0x8c48, NT, "Intel", "Lynx Point", enable_flash_pch8},
1711 {0x8086, 0x8c49, NT, "Intel", "HM86", enable_flash_pch8},
1712 {0x8086, 0x8c4a, DEP, "Intel", "H87", enable_flash_pch8},
1713 {0x8086, 0x8c4b, DEP, "Intel", "HM87", enable_flash_pch8},
1714 {0x8086, 0x8c4c, NT, "Intel", "Q85", enable_flash_pch8},
1715 {0x8086, 0x8c4d, NT, "Intel", "Lynx Point", enable_flash_pch8},
1716 {0x8086, 0x8c4e, NT, "Intel", "Q87", enable_flash_pch8},
1717 {0x8086, 0x8c4f, NT, "Intel", "QM87", enable_flash_pch8},
1718 {0x8086, 0x8c50, DEP, "Intel", "B85", enable_flash_pch8},
1719 {0x8086, 0x8c51, NT, "Intel", "Lynx Point", enable_flash_pch8},
1720 {0x8086, 0x8c52, NT, "Intel", "C222", enable_flash_pch8},
1721 {0x8086, 0x8c53, NT, "Intel", "Lynx Point", enable_flash_pch8},
1722 {0x8086, 0x8c54, NT, "Intel", "C224", enable_flash_pch8},
1723 {0x8086, 0x8c55, NT, "Intel", "Lynx Point", enable_flash_pch8},
1724 {0x8086, 0x8c56, NT, "Intel", "C226", enable_flash_pch8},
1725 {0x8086, 0x8c57, NT, "Intel", "Lynx Point", enable_flash_pch8},
1726 {0x8086, 0x8c58, NT, "Intel", "Lynx Point", enable_flash_pch8},
1727 {0x8086, 0x8c59, NT, "Intel", "Lynx Point", enable_flash_pch8},
1728 {0x8086, 0x8c5a, NT, "Intel", "Lynx Point", enable_flash_pch8},
1729 {0x8086, 0x8c5b, NT, "Intel", "Lynx Point", enable_flash_pch8},
1730 {0x8086, 0x8c5c, NT, "Intel", "H81", enable_flash_pch8},
1731 {0x8086, 0x8c5d, NT, "Intel", "Lynx Point", enable_flash_pch8},
1732 {0x8086, 0x8c5e, NT, "Intel", "Lynx Point", enable_flash_pch8},
1733 {0x8086, 0x8c5f, NT, "Intel", "Lynx Point", enable_flash_pch8},
Stefan Tauner5c316f92015-02-08 21:57:52 +00001734 {0x8086, 0x8cc1, NT, "Intel", "9 Series", enable_flash_pch9},
1735 {0x8086, 0x8cc2, NT, "Intel", "9 Series Engineering Sample", enable_flash_pch9},
1736 {0x8086, 0x8cc3, NT, "Intel", "9 Series", enable_flash_pch9},
1737 {0x8086, 0x8cc4, NT, "Intel", "Z97", enable_flash_pch9},
1738 {0x8086, 0x8cc6, NT, "Intel", "H97", enable_flash_pch9},
1739 {0x8086, 0x8d40, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1740 {0x8086, 0x8d41, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1741 {0x8086, 0x8d42, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1742 {0x8086, 0x8d43, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1743 {0x8086, 0x8d44, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1744 {0x8086, 0x8d45, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1745 {0x8086, 0x8d46, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1746 {0x8086, 0x8d47, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1747 {0x8086, 0x8d48, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1748 {0x8086, 0x8d49, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1749 {0x8086, 0x8d4a, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1750 {0x8086, 0x8d4b, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1751 {0x8086, 0x8d4c, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1752 {0x8086, 0x8d4d, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1753 {0x8086, 0x8d4e, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1754 {0x8086, 0x8d4f, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1755 {0x8086, 0x8d50, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1756 {0x8086, 0x8d51, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1757 {0x8086, 0x8d52, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1758 {0x8086, 0x8d53, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1759 {0x8086, 0x8d54, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1760 {0x8086, 0x8d55, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1761 {0x8086, 0x8d56, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1762 {0x8086, 0x8d57, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1763 {0x8086, 0x8d58, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1764 {0x8086, 0x8d59, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1765 {0x8086, 0x8d5a, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1766 {0x8086, 0x8d5b, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1767 {0x8086, 0x8d5c, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1768 {0x8086, 0x8d5d, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1769 {0x8086, 0x8d5e, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1770 {0x8086, 0x8d5f, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001771 {0x8086, 0x9c41, NT, "Intel", "Lynx Point LP Eng. Sample", enable_flash_pch8_lp},
1772 {0x8086, 0x9c43, NT, "Intel", "Lynx Point LP Premium", enable_flash_pch8_lp},
1773 {0x8086, 0x9c45, NT, "Intel", "Lynx Point LP Mainstream", enable_flash_pch8_lp},
1774 {0x8086, 0x9c47, NT, "Intel", "Lynx Point LP Value", enable_flash_pch8_lp},
Duncan Laurie823096e2014-08-20 15:39:38 +00001775 {0x8086, 0x9cc1, NT, "Intel", "Haswell U Sample", enable_flash_pch9},
1776 {0x8086, 0x9cc2, NT, "Intel", "Broadwell U Sample", enable_flash_pch9},
1777 {0x8086, 0x9cc3, NT, "Intel", "Broadwell U Premium", enable_flash_pch9},
1778 {0x8086, 0x9cc5, NT, "Intel", "Broadwell U Base", enable_flash_pch9},
1779 {0x8086, 0x9cc6, NT, "Intel", "Broadwell Y Sample", enable_flash_pch9},
1780 {0x8086, 0x9cc7, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9},
1781 {0x8086, 0x9cc9, NT, "Intel", "Broadwell Y Base", enable_flash_pch9},
1782 {0x8086, 0x9ccb, NT, "Intel", "Broadwell H", enable_flash_pch9},
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001783#endif
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +00001784 {0},
Ollie Lhocbbf1252004-03-17 22:22:08 +00001785};
Ollie Lho761bf1b2004-03-20 16:46:10 +00001786
Uwe Hermanna7e05482007-05-09 10:17:44 +00001787int chipset_flash_enable(void)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001788{
Peter Huewe73f8ec82011-01-24 19:15:51 +00001789 struct pci_dev *dev = NULL;
Uwe Hermann372eeb52007-12-04 21:49:06 +00001790 int ret = -2; /* Nothing! */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001791 int i;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001792
Uwe Hermann372eeb52007-12-04 21:49:06 +00001793 /* Now let's try to find the chipset we have... */
Uwe Hermann05fab752009-05-16 23:42:17 +00001794 for (i = 0; chipset_enables[i].vendor_name != NULL; i++) {
1795 dev = pci_dev_find(chipset_enables[i].vendor_id,
1796 chipset_enables[i].device_id);
Michael Karcher89bed6d2010-06-13 10:16:12 +00001797 if (!dev)
1798 continue;
1799 if (ret != -2) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00001800 msg_pwarn("Warning: unexpected second chipset match: "
Paul Menzelab6328f2010-10-08 11:03:02 +00001801 "\"%s %s\"\n"
1802 "ignoring, please report lspci and board URL "
1803 "to flashrom@flashrom.org\n"
Stefan Reinauerbf282b12011-03-29 21:41:41 +00001804 "with \'CHIPSET: your board name\' in the "
Paul Menzelab6328f2010-10-08 11:03:02 +00001805 "subject line.\n",
Michael Karcher89bed6d2010-06-13 10:16:12 +00001806 chipset_enables[i].vendor_name,
1807 chipset_enables[i].device_name);
1808 continue;
1809 }
Stefan Taunerec8c2482011-07-21 19:59:34 +00001810 msg_pinfo("Found chipset \"%s %s\"",
1811 chipset_enables[i].vendor_name,
1812 chipset_enables[i].device_name);
Stefan Tauner716e0982011-07-25 20:38:52 +00001813 msg_pdbg(" with PCI ID %04x:%04x",
Carl-Daniel Hailfingerf469c272010-05-22 07:31:50 +00001814 chipset_enables[i].vendor_id,
1815 chipset_enables[i].device_id);
Stefan Tauner5c316f92015-02-08 21:57:52 +00001816 msg_pinfo(".\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +00001817
Stefan Taunerec8c2482011-07-21 19:59:34 +00001818 if (chipset_enables[i].status == NT) {
Stefan Tauner5c316f92015-02-08 21:57:52 +00001819 msg_pinfo("This chipset is marked as untested. If "
Stefan Taunerec8c2482011-07-21 19:59:34 +00001820 "you are using an up-to-date version\nof "
Stefan Tauner2abab942012-04-27 20:41:23 +00001821 "flashrom *and* were (not) able to "
1822 "successfully update your firmware with it,\n"
1823 "then please email a report to "
1824 "flashrom@flashrom.org including a verbose "
1825 "(-V) log.\nThank you!\n");
Stefan Taunerec8c2482011-07-21 19:59:34 +00001826 }
1827 msg_pinfo("Enabling flash write... ");
Uwe Hermann05fab752009-05-16 23:42:17 +00001828 ret = chipset_enables[i].doit(dev,
1829 chipset_enables[i].device_name);
Michael Karcher89bed6d2010-06-13 10:16:12 +00001830 if (ret == NOT_DONE_YET) {
1831 ret = -2;
1832 msg_pinfo("OK - searching further chips.\n");
1833 } else if (ret < 0)
Sean Nelson316a29f2010-05-07 20:09:04 +00001834 msg_pinfo("FAILED!\n");
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001835 else if (ret == 0)
Sean Nelson316a29f2010-05-07 20:09:04 +00001836 msg_pinfo("OK.\n");
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001837 else if (ret == ERROR_NONFATAL)
Michael Karchera4448d92010-07-22 18:04:15 +00001838 msg_pinfo("PROBLEMS, continuing anyway\n");
Tadas Slotkusad470342011-09-03 17:15:00 +00001839 if (ret == ERROR_FATAL) {
1840 msg_perr("FATAL ERROR!\n");
1841 return ret;
1842 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00001843 }
Michael Karcher89bed6d2010-06-13 10:16:12 +00001844
Uwe Hermanna7e05482007-05-09 10:17:44 +00001845 return ret;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001846}