Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 1 | /* |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 2 | * This file is part of the flashrom project. |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 3 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 4 | * Copyright (C) 2000 Silicon Integrated System Corporation |
| 5 | * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de> |
| 6 | * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de> |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 7 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 11 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | /* |
| 23 | * Contains the chipset specific flash enables. |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 24 | */ |
| 25 | |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 26 | #define _LARGEFILE64_SOURCE |
| 27 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 28 | #include <stdio.h> |
| 29 | #include <pci/pci.h> |
| 30 | #include <stdlib.h> |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 31 | #include <sys/types.h> |
| 32 | #include <sys/stat.h> |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 33 | #include <sys/mman.h> |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 34 | #include <fcntl.h> |
| 35 | #include <unistd.h> |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 36 | #include "flash.h" |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 37 | |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 38 | /** |
| 39 | * flashrom defaults to LPC flash devices. If a known SPI controller is found |
| 40 | * and the SPI strappings are set, this will be overwritten by the probing code. |
| 41 | * |
| 42 | * Eventually, this will become an array when multiple flash support works. |
| 43 | */ |
| 44 | |
| 45 | flashbus_t flashbus = BUS_TYPE_LPC; |
| 46 | void *spibar = NULL; |
| 47 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 48 | static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 49 | { |
| 50 | uint8_t tmp; |
| 51 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 52 | /* |
| 53 | * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and |
| 54 | * 0xFFFE0000-0xFFFFFFFF ROM select enable. |
| 55 | */ |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 56 | tmp = pci_read_byte(dev, 0x47); |
| 57 | tmp |= 0x46; |
| 58 | pci_write_byte(dev, 0x47, tmp); |
| 59 | |
| 60 | return 0; |
| 61 | } |
| 62 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 63 | static int enable_flash_sis630(struct pci_dev *dev, const char *name) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 64 | { |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 65 | uint8_t b; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 66 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 67 | /* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */ |
Alex Beregszaszi | c9fb5d9 | 2007-09-11 15:58:18 +0000 | [diff] [blame] | 68 | b = pci_read_byte(dev, 0x40); |
| 69 | pci_write_byte(dev, 0x40, b | 0xb); |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 70 | |
| 71 | /* Flash write enable on SiS 540/630. */ |
Alex Beregszaszi | c9fb5d9 | 2007-09-11 15:58:18 +0000 | [diff] [blame] | 72 | b = pci_read_byte(dev, 0x45); |
| 73 | pci_write_byte(dev, 0x45, b | 0x40); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 74 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 75 | /* The same thing on SiS 950 Super I/O side... */ |
| 76 | |
| 77 | /* First probe for Super I/O on config port 0x2e. */ |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 78 | OUTB(0x87, 0x2e); |
| 79 | OUTB(0x01, 0x2e); |
| 80 | OUTB(0x55, 0x2e); |
| 81 | OUTB(0x55, 0x2e); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 82 | |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 83 | if (INB(0x2f) != 0x87) { |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 84 | /* If that failed, try config port 0x4e. */ |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 85 | OUTB(0x87, 0x4e); |
| 86 | OUTB(0x01, 0x4e); |
| 87 | OUTB(0x55, 0x4e); |
| 88 | OUTB(0xaa, 0x4e); |
| 89 | if (INB(0x4f) != 0x87) { |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 90 | printf("Can not access SiS 950\n"); |
| 91 | return -1; |
| 92 | } |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 93 | OUTB(0x24, 0x4e); |
| 94 | b = INB(0x4f) | 0xfc; |
| 95 | OUTB(0x24, 0x4e); |
| 96 | OUTB(b, 0x4f); |
| 97 | OUTB(0x02, 0x4e); |
| 98 | OUTB(0x02, 0x4f); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 99 | } |
| 100 | |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 101 | OUTB(0x24, 0x2e); |
| 102 | printf("2f is %#x\n", INB(0x2f)); |
| 103 | b = INB(0x2f) | 0xfc; |
| 104 | OUTB(0x24, 0x2e); |
| 105 | OUTB(b, 0x2f); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 106 | |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 107 | OUTB(0x02, 0x2e); |
| 108 | OUTB(0x02, 0x2f); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 109 | |
| 110 | return 0; |
| 111 | } |
| 112 | |
Uwe Hermann | 987942d | 2006-11-07 11:16:21 +0000 | [diff] [blame] | 113 | /* Datasheet: |
| 114 | * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4) |
| 115 | * - URL: http://www.intel.com/design/intarch/datashts/290562.htm |
| 116 | * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf |
| 117 | * - Order Number: 290562-001 |
| 118 | */ |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 119 | static int enable_flash_piix4(struct pci_dev *dev, const char *name) |
Uwe Hermann | ea2c66d | 2006-11-05 18:26:08 +0000 | [diff] [blame] | 120 | { |
| 121 | uint16_t old, new; |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 122 | uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */ |
Uwe Hermann | ea2c66d | 2006-11-05 18:26:08 +0000 | [diff] [blame] | 123 | |
| 124 | old = pci_read_word(dev, xbcs); |
| 125 | |
| 126 | /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 127 | * FFF00000-FFF7FFFF are forwarded to ISA). |
| 128 | * Set bit 7: Extended BIOS Enable (PCI master accesses to |
| 129 | * FFF80000-FFFDFFFF are forwarded to ISA). |
| 130 | * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to |
| 131 | * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top |
| 132 | * of 1 Mbyte, or the aliases at the top of 4 Gbyte |
| 133 | * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#. |
| 134 | * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA. |
| 135 | * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable). |
| 136 | */ |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 137 | new = old | 0x02c4; |
Uwe Hermann | ea2c66d | 2006-11-05 18:26:08 +0000 | [diff] [blame] | 138 | |
| 139 | if (new == old) |
| 140 | return 0; |
| 141 | |
| 142 | pci_write_word(dev, xbcs, new); |
| 143 | |
| 144 | if (pci_read_word(dev, xbcs) != new) { |
| 145 | printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name); |
| 146 | return -1; |
| 147 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 148 | |
Uwe Hermann | ea2c66d | 2006-11-05 18:26:08 +0000 | [diff] [blame] | 149 | return 0; |
| 150 | } |
| 151 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 152 | /* |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 153 | * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet" |
| 154 | * http://download.intel.com/design/chipsets/datashts/30701303.pdf |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 155 | */ |
| 156 | static int enable_flash_ich(struct pci_dev *dev, const char *name, |
| 157 | int bios_cntl) |
Ronald G. Minnich | 6a96741 | 2004-09-28 20:09:06 +0000 | [diff] [blame] | 158 | { |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 159 | uint8_t old, new; |
Stefan Reinauer | eb36647 | 2006-09-06 15:48:48 +0000 | [diff] [blame] | 160 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 161 | /* |
| 162 | * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 163 | * just treating it as 8 bit wide seems to work fine in practice. |
Stefan Reinauer | eb36647 | 2006-09-06 15:48:48 +0000 | [diff] [blame] | 164 | */ |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 165 | old = pci_read_byte(dev, bios_cntl); |
Ronald G. Minnich | 6a96741 | 2004-09-28 20:09:06 +0000 | [diff] [blame] | 166 | |
Uwe Hermann | 793bdcd | 2008-05-22 22:47:04 +0000 | [diff] [blame] | 167 | printf_debug("\nBIOS Lock Enable: %sabled, ", |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 168 | (old & (1 << 1)) ? "en" : "dis"); |
| 169 | printf_debug("BIOS Write Enable: %sabled, ", |
| 170 | (old & (1 << 0)) ? "en" : "dis"); |
| 171 | printf_debug("BIOS_CNTL is 0x%x\n", old); |
| 172 | |
Ronald G. Minnich | 6a96741 | 2004-09-28 20:09:06 +0000 | [diff] [blame] | 173 | new = old | 1; |
| 174 | |
| 175 | if (new == old) |
| 176 | return 0; |
| 177 | |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 178 | pci_write_byte(dev, bios_cntl, new); |
Ronald G. Minnich | 6a96741 | 2004-09-28 20:09:06 +0000 | [diff] [blame] | 179 | |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 180 | if (pci_read_byte(dev, bios_cntl) != new) { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 181 | printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name); |
Ronald G. Minnich | 6a96741 | 2004-09-28 20:09:06 +0000 | [diff] [blame] | 182 | return -1; |
| 183 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 184 | |
Ronald G. Minnich | 6a96741 | 2004-09-28 20:09:06 +0000 | [diff] [blame] | 185 | return 0; |
| 186 | } |
| 187 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 188 | static int enable_flash_ich_4e(struct pci_dev *dev, const char *name) |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 189 | { |
Stefan Reinauer | eb36647 | 2006-09-06 15:48:48 +0000 | [diff] [blame] | 190 | return enable_flash_ich(dev, name, 0x4e); |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 191 | } |
| 192 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 193 | static int enable_flash_ich_dc(struct pci_dev *dev, const char *name) |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 194 | { |
Stefan Reinauer | eb36647 | 2006-09-06 15:48:48 +0000 | [diff] [blame] | 195 | return enable_flash_ich(dev, name, 0xdc); |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 196 | } |
| 197 | |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 198 | #define ICH_STRAP_RSVD 0x00 |
| 199 | #define ICH_STRAP_SPI 0x01 |
| 200 | #define ICH_STRAP_PCI 0x02 |
| 201 | #define ICH_STRAP_LPC 0x03 |
Carl-Daniel Hailfinger | 6dc1d3b | 2008-05-14 14:51:22 +0000 | [diff] [blame] | 202 | |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 203 | static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name) |
| 204 | { |
Rudolf Marek | 3fdbccf | 2008-06-30 21:38:30 +0000 | [diff] [blame] | 205 | uint32_t mmio_base; |
| 206 | |
| 207 | mmio_base = (pci_read_long(dev, 0xbc)) << 8; |
| 208 | printf_debug("MMIO base at = 0x%x\n", mmio_base); |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 209 | spibar = mmap(NULL, 0x70, PROT_READ | PROT_WRITE, MAP_SHARED, |
| 210 | fd_mem, mmio_base); |
Rudolf Marek | 3fdbccf | 2008-06-30 21:38:30 +0000 | [diff] [blame] | 211 | |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 212 | if (spibar == MAP_FAILED) { |
Rudolf Marek | 3fdbccf | 2008-06-30 21:38:30 +0000 | [diff] [blame] | 213 | perror("Can't mmap memory using " MEM_DEV); |
| 214 | exit(1); |
| 215 | } |
| 216 | |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 217 | printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n", |
| 218 | *(uint16_t *) (spibar + 0x6c)); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 219 | |
| 220 | flashbus = BUS_TYPE_VIA_SPI; |
| 221 | |
Rudolf Marek | 3fdbccf | 2008-06-30 21:38:30 +0000 | [diff] [blame] | 222 | return 0; |
| 223 | } |
| 224 | |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 225 | static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, |
| 226 | int ich_generation) |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 227 | { |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 228 | int ret, i; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 229 | uint8_t old, new, bbs, buc; |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 230 | uint16_t spibar_offset; |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 231 | uint32_t tmp, gcs; |
Carl-Daniel Hailfinger | 6dc1d3b | 2008-05-14 14:51:22 +0000 | [diff] [blame] | 232 | void *rcrb; |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 233 | static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" }; |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 234 | |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 235 | /* Enable Flash Writes */ |
| 236 | ret = enable_flash_ich_dc(dev, name); |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 237 | |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 238 | /* Get physical address of Root Complex Register Block */ |
| 239 | tmp = pci_read_long(dev, 0xf0) & 0xffffc000; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 240 | printf_debug("\nRoot Complex Register Block address = 0x%x\n", tmp); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 241 | |
| 242 | /* Map RCBA to virtual memory */ |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 243 | rcrb = mmap(0, 0x4000, PROT_READ | PROT_WRITE, MAP_SHARED, fd_mem, |
| 244 | (off_t) tmp); |
Carl-Daniel Hailfinger | 6dc1d3b | 2008-05-14 14:51:22 +0000 | [diff] [blame] | 245 | if (rcrb == MAP_FAILED) { |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 246 | perror("Can't mmap memory using " MEM_DEV); |
| 247 | exit(1); |
| 248 | } |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 249 | |
Carl-Daniel Hailfinger | 6dc1d3b | 2008-05-14 14:51:22 +0000 | [diff] [blame] | 250 | gcs = *(volatile uint32_t *)(rcrb + 0x3410); |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 251 | printf_debug("GCS = 0x%x: ", gcs); |
| 252 | printf_debug("BIOS Interface Lock-Down: %sabled, ", |
| 253 | (gcs & 0x1) ? "en" : "dis"); |
| 254 | bbs = (gcs >> 10) & 0x3; |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 255 | printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]); |
Carl-Daniel Hailfinger | 6dc1d3b | 2008-05-14 14:51:22 +0000 | [diff] [blame] | 256 | |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 257 | buc = *(volatile uint8_t *)(rcrb + 0x3414); |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 258 | printf_debug("Top Swap : %s\n", |
| 259 | (buc & 1) ? "enabled (A16 inverted)" : "not enabled"); |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 260 | |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 261 | /* It seems the ICH7 does not support SPI and LPC chips at the same |
| 262 | * time. At least not with our current code. So we prevent searching |
| 263 | * on ICH7 when the southbridge is strapped to LPC |
| 264 | */ |
| 265 | |
| 266 | if (ich_generation == 7 && bbs == ICH_STRAP_LPC) { |
| 267 | /* No further SPI initialization required */ |
| 268 | return ret; |
| 269 | } |
| 270 | |
| 271 | switch (ich_generation) { |
| 272 | case 7: |
| 273 | flashbus = BUS_TYPE_ICH7_SPI; |
| 274 | spibar_offset = 0x3020; |
| 275 | break; |
| 276 | case 8: |
| 277 | flashbus = BUS_TYPE_ICH9_SPI; |
| 278 | spibar_offset = 0x3020; |
| 279 | break; |
| 280 | case 9: |
Carl-Daniel Hailfinger | 28ec74b | 2008-10-10 20:54:41 +0000 | [diff] [blame] | 281 | case 10: |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 282 | default: /* Future version might behave the same */ |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 283 | flashbus = BUS_TYPE_ICH9_SPI; |
| 284 | spibar_offset = 0x3800; |
| 285 | break; |
| 286 | } |
| 287 | |
Carl-Daniel Hailfinger | 6dc1d3b | 2008-05-14 14:51:22 +0000 | [diff] [blame] | 288 | /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */ |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 289 | printf_debug("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset); |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 290 | |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 291 | /* Assign Virtual Address */ |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 292 | spibar = rcrb + spibar_offset; |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 293 | |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 294 | switch (flashbus) { |
| 295 | case BUS_TYPE_ICH7_SPI: |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 296 | printf_debug("0x00: 0x%04x (SPIS)\n", |
| 297 | *(uint16_t *) (spibar + 0)); |
| 298 | printf_debug("0x02: 0x%04x (SPIC)\n", |
| 299 | *(uint16_t *) (spibar + 2)); |
| 300 | printf_debug("0x04: 0x%08x (SPIA)\n", |
| 301 | *(uint32_t *) (spibar + 4)); |
| 302 | for (i = 0; i < 8; i++) { |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 303 | int offs; |
| 304 | offs = 8 + (i * 8); |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 305 | printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs, |
| 306 | *(uint32_t *) (spibar + offs), i); |
| 307 | printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, |
| 308 | *(uint32_t *) (spibar + offs + 4), i); |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 309 | } |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 310 | printf_debug("0x50: 0x%08x (BBAR)\n", |
| 311 | *(uint32_t *) (spibar + 0x50)); |
| 312 | printf_debug("0x54: 0x%04x (PREOP)\n", |
| 313 | *(uint16_t *) (spibar + 0x54)); |
| 314 | printf_debug("0x56: 0x%04x (OPTYPE)\n", |
| 315 | *(uint16_t *) (spibar + 0x56)); |
| 316 | printf_debug("0x58: 0x%08x (OPMENU)\n", |
| 317 | *(uint32_t *) (spibar + 0x58)); |
| 318 | printf_debug("0x5c: 0x%08x (OPMENU+4)\n", |
| 319 | *(uint32_t *) (spibar + 0x5c)); |
| 320 | for (i = 0; i < 4; i++) { |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 321 | int offs; |
| 322 | offs = 0x60 + (i * 4); |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 323 | printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs, |
| 324 | *(uint32_t *) (spibar + offs), i); |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 325 | } |
| 326 | printf_debug("\n"); |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 327 | if ((*(uint16_t *) spibar) & (1 << 15)) { |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 328 | printf("WARNING: SPI Configuration Lockdown activated.\n"); |
| 329 | } |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 330 | break; |
| 331 | case BUS_TYPE_ICH9_SPI: |
| 332 | /* TODO: Add dumping function for ICH8/ICH9, or drop the |
| 333 | * whole SPIBAR dumping from chipset_enable.c - There's |
| 334 | * inteltool for this task already. |
| 335 | */ |
| 336 | break; |
| 337 | default: |
| 338 | /* Nothing */ |
| 339 | break; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 340 | } |
| 341 | |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 342 | old = pci_read_byte(dev, 0xdc); |
| 343 | printf_debug("SPI Read Configuration: "); |
| 344 | new = (old >> 2) & 0x3; |
| 345 | switch (new) { |
| 346 | case 0: |
| 347 | case 1: |
| 348 | case 2: |
| 349 | printf_debug("prefetching %sabled, caching %sabled, ", |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 350 | (new & 0x2) ? "en" : "dis", |
| 351 | (new & 0x1) ? "dis" : "en"); |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 352 | break; |
| 353 | default: |
| 354 | printf_debug("invalid prefetching/caching settings, "); |
| 355 | break; |
| 356 | } |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 357 | |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 358 | return ret; |
| 359 | } |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 360 | |
Carl-Daniel Hailfinger | 1b18b3c | 2008-05-16 14:39:39 +0000 | [diff] [blame] | 361 | static int enable_flash_ich7(struct pci_dev *dev, const char *name) |
Carl-Daniel Hailfinger | 6dc1d3b | 2008-05-14 14:51:22 +0000 | [diff] [blame] | 362 | { |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 363 | return enable_flash_ich_dc_spi(dev, name, 7); |
Carl-Daniel Hailfinger | 6dc1d3b | 2008-05-14 14:51:22 +0000 | [diff] [blame] | 364 | } |
| 365 | |
Carl-Daniel Hailfinger | 1b18b3c | 2008-05-16 14:39:39 +0000 | [diff] [blame] | 366 | static int enable_flash_ich8(struct pci_dev *dev, const char *name) |
| 367 | { |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 368 | return enable_flash_ich_dc_spi(dev, name, 8); |
Carl-Daniel Hailfinger | 1b18b3c | 2008-05-16 14:39:39 +0000 | [diff] [blame] | 369 | } |
| 370 | |
Carl-Daniel Hailfinger | 6dc1d3b | 2008-05-14 14:51:22 +0000 | [diff] [blame] | 371 | static int enable_flash_ich9(struct pci_dev *dev, const char *name) |
| 372 | { |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 373 | return enable_flash_ich_dc_spi(dev, name, 9); |
Carl-Daniel Hailfinger | 6dc1d3b | 2008-05-14 14:51:22 +0000 | [diff] [blame] | 374 | } |
| 375 | |
Carl-Daniel Hailfinger | 28ec74b | 2008-10-10 20:54:41 +0000 | [diff] [blame] | 376 | static int enable_flash_ich10(struct pci_dev *dev, const char *name) |
| 377 | { |
| 378 | return enable_flash_ich_dc_spi(dev, name, 10); |
| 379 | } |
| 380 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 381 | static int enable_flash_vt823x(struct pci_dev *dev, const char *name) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 382 | { |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 383 | uint8_t val; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 384 | |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 385 | /* enable ROM decode range (1MB) FFC00000 - FFFFFFFF */ |
Bari Ari | 9477c4e | 2008-04-29 13:46:38 +0000 | [diff] [blame] | 386 | pci_write_byte(dev, 0x41, 0x7f); |
| 387 | |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 388 | /* ROM write enable */ |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 389 | val = pci_read_byte(dev, 0x40); |
| 390 | val |= 0x10; |
| 391 | pci_write_byte(dev, 0x40, val); |
| 392 | |
| 393 | if (pci_read_byte(dev, 0x40) != val) { |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 394 | printf("\nWARNING: Failed to enable ROM Write on \"%s\"\n", |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 395 | name); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 396 | return -1; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 397 | } |
Luc Verhaegen | 6382b44 | 2007-03-02 22:16:38 +0000 | [diff] [blame] | 398 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 399 | return 0; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 400 | } |
| 401 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 402 | static int enable_flash_cs5530(struct pci_dev *dev, const char *name) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 403 | { |
Uwe Hermann | f4a673b | 2007-06-06 21:35:45 +0000 | [diff] [blame] | 404 | uint8_t reg8; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 405 | |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 406 | #define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */ |
| 407 | #define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */ |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 408 | |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 409 | #define LOWER_ROM_ADDRESS_RANGE (1 << 0) |
| 410 | #define ROM_WRITE_ENABLE (1 << 1) |
| 411 | #define UPPER_ROM_ADDRESS_RANGE (1 << 2) |
| 412 | #define BIOS_ROM_POSITIVE_DECODE (1 << 5) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 413 | |
Uwe Hermann | f4a673b | 2007-06-06 21:35:45 +0000 | [diff] [blame] | 414 | /* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and |
| 415 | * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB. |
| 416 | * Make the configured ROM areas writable. |
| 417 | */ |
| 418 | reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG); |
| 419 | reg8 |= LOWER_ROM_ADDRESS_RANGE; |
| 420 | reg8 |= UPPER_ROM_ADDRESS_RANGE; |
| 421 | reg8 |= ROM_WRITE_ENABLE; |
| 422 | pci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 423 | |
Uwe Hermann | f4a673b | 2007-06-06 21:35:45 +0000 | [diff] [blame] | 424 | /* Set positive decode on ROM. */ |
| 425 | reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2); |
| 426 | reg8 |= BIOS_ROM_POSITIVE_DECODE; |
| 427 | pci_write_byte(dev, DECODE_CONTROL_REG2, reg8); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 428 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 429 | return 0; |
| 430 | } |
| 431 | |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 432 | /** |
| 433 | * Geode systems write protect the BIOS via RCONFs (cache settings similar |
| 434 | * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22. Reading and |
| 435 | * writing to MSRs, however requires instructions rdmsr/wrmsr, which are |
| 436 | * ring0 privileged instructions so only the kernel can do the read/write. |
| 437 | * This function, therefore, requires that the msr kernel module be loaded |
| 438 | * to access these instructions from user space using device /dev/cpu/0/msr. |
| 439 | * |
| 440 | * This hard-coded location could have potential problems on SMP machines |
| 441 | * since it assumes cpu0, but it is safe on the Geode which is not SMP. |
| 442 | * |
| 443 | * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL. |
| 444 | * To enable write to NOR Boot flash for the benefit of systems that have such |
| 445 | * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select). |
| 446 | * |
| 447 | * This is probably not portable beyond Linux. |
| 448 | */ |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 449 | static int enable_flash_cs5536(struct pci_dev *dev, const char *name) |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 450 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 451 | #define MSR_RCONF_DEFAULT 0x1808 |
| 452 | #define MSR_NORF_CTL 0x51400018 |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 453 | |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 454 | int fd_msr; |
| 455 | unsigned char buf[8]; |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 456 | |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 457 | fd_msr = open("/dev/cpu/0/msr", O_RDWR); |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 458 | if (!fd_msr) { |
| 459 | perror("open msr"); |
| 460 | return -1; |
| 461 | } |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 462 | |
| 463 | if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) { |
| 464 | perror("lseek64"); |
Mart Raudsepp | 3697ac7 | 2008-02-11 14:32:45 +0000 | [diff] [blame] | 465 | printf("Cannot operate on MSR. Did you run 'modprobe msr'?\n"); |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 466 | close(fd_msr); |
| 467 | return -1; |
| 468 | } |
| 469 | |
| 470 | if (read(fd_msr, buf, 8) != 8) { |
Mart Raudsepp | 3697ac7 | 2008-02-11 14:32:45 +0000 | [diff] [blame] | 471 | perror("read msr"); |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 472 | close(fd_msr); |
| 473 | return -1; |
| 474 | } |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 475 | |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 476 | if (buf[7] != 0x22) { |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 477 | buf[7] &= 0xfb; |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 478 | if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, |
| 479 | SEEK_SET) == -1) { |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 480 | perror("lseek64"); |
| 481 | close(fd_msr); |
| 482 | return -1; |
| 483 | } |
| 484 | |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 485 | if (write(fd_msr, buf, 8) < 0) { |
| 486 | perror("msr write"); |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 487 | close(fd_msr); |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 488 | return -1; |
| 489 | } |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 490 | } |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 491 | |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 492 | if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) { |
| 493 | perror("lseek64"); |
| 494 | close(fd_msr); |
| 495 | return -1; |
| 496 | } |
| 497 | |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 498 | if (read(fd_msr, buf, 8) != 8) { |
| 499 | perror("read msr"); |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 500 | close(fd_msr); |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 501 | return -1; |
| 502 | } |
| 503 | |
| 504 | /* Raise WE_CS3 bit. */ |
| 505 | buf[0] |= 0x08; |
| 506 | |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 507 | if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) { |
| 508 | perror("lseek64"); |
| 509 | close(fd_msr); |
| 510 | return -1; |
| 511 | } |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 512 | if (write(fd_msr, buf, 8) < 0) { |
| 513 | perror("msr write"); |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 514 | close(fd_msr); |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 515 | return -1; |
| 516 | } |
| 517 | |
| 518 | close(fd_msr); |
| 519 | |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 520 | #undef MSR_RCONF_DEFAULT |
| 521 | #undef MSR_NORF_CTL |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 522 | return 0; |
| 523 | } |
| 524 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 525 | static int enable_flash_sc1100(struct pci_dev *dev, const char *name) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 526 | { |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 527 | uint8_t new; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 528 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 529 | pci_write_byte(dev, 0x52, 0xee); |
| 530 | |
| 531 | new = pci_read_byte(dev, 0x52); |
| 532 | |
| 533 | if (new != 0xee) { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 534 | printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 535 | return -1; |
| 536 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 537 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 538 | return 0; |
| 539 | } |
| 540 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 541 | static int enable_flash_sis5595(struct pci_dev *dev, const char *name) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 542 | { |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 543 | uint8_t new, newer; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 544 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 545 | new = pci_read_byte(dev, 0x45); |
| 546 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 547 | new &= (~0x20); /* Clear bit 5. */ |
| 548 | new |= 0x4; /* Set bit 2. */ |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 549 | |
| 550 | pci_write_byte(dev, 0x45, new); |
| 551 | |
| 552 | newer = pci_read_byte(dev, 0x45); |
| 553 | if (newer != new) { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 554 | printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 555 | printf("Stuck at 0x%x\n", newer); |
| 556 | return -1; |
| 557 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 558 | |
Urja Rannikko | a88daa7 | 2008-10-18 13:54:30 +0000 | [diff] [blame] | 559 | /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */ |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 560 | new = pci_read_byte(dev, 0x40); |
Urja Rannikko | a88daa7 | 2008-10-18 13:54:30 +0000 | [diff] [blame] | 561 | new &= 0xFB; |
| 562 | new |= 0x3; |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 563 | pci_write_byte(dev, 0x40, new); |
| 564 | newer = pci_read_byte(dev, 0x40); |
Urja Rannikko | a88daa7 | 2008-10-18 13:54:30 +0000 | [diff] [blame] | 565 | if (newer != new) { |
| 566 | printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); |
| 567 | printf("Stuck at 0x%x\n", newer); |
| 568 | return -1; |
| 569 | } |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 570 | return 0; |
| 571 | } |
| 572 | |
Uwe Hermann | 190f849 | 2008-10-25 18:03:50 +0000 | [diff] [blame^] | 573 | /* Works for AMD-8111, VIA VT82C586A/B, VIA VT82C686A/B. */ |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 574 | static int enable_flash_amd8111(struct pci_dev *dev, const char *name) |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 575 | { |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 576 | uint8_t old, new; |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 577 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 578 | /* Enable decoding at 0xffb00000 to 0xffffffff. */ |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 579 | old = pci_read_byte(dev, 0x43); |
Ollie Lho | d11f361 | 2004-12-07 17:19:04 +0000 | [diff] [blame] | 580 | new = old | 0xC0; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 581 | if (new != old) { |
| 582 | pci_write_byte(dev, 0x43, new); |
| 583 | if (pci_read_byte(dev, 0x43) != new) { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 584 | printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 585 | } |
| 586 | } |
| 587 | |
Uwe Hermann | 190f849 | 2008-10-25 18:03:50 +0000 | [diff] [blame^] | 588 | /* Enable 'ROM write' bit. */ |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 589 | old = pci_read_byte(dev, 0x40); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 590 | new = old | 0x01; |
| 591 | if (new == old) |
| 592 | return 0; |
| 593 | pci_write_byte(dev, 0x40, new); |
| 594 | |
| 595 | if (pci_read_byte(dev, 0x40) != new) { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 596 | printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 597 | return -1; |
| 598 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 599 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 600 | return 0; |
| 601 | } |
| 602 | |
Marc Jones | 3af487d | 2008-10-15 17:50:29 +0000 | [diff] [blame] | 603 | static int enable_flash_sb600(struct pci_dev *dev, const char *name) |
| 604 | { |
| 605 | uint32_t old, new; |
| 606 | uint8_t reg; |
| 607 | |
| 608 | /* Clear ROM Protect 0-3 */ |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 609 | for (reg = 0x50; reg < 0x60; reg += 4) { |
Marc Jones | 3af487d | 2008-10-15 17:50:29 +0000 | [diff] [blame] | 610 | old = pci_read_long(dev, reg); |
| 611 | new = old & 0xFFFFFFFC; |
| 612 | if (new != old) { |
| 613 | pci_write_byte(dev, reg, new); |
| 614 | if (pci_read_long(dev, reg) != new) { |
| 615 | printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x50, new, name); |
| 616 | } |
| 617 | } |
| 618 | } |
| 619 | |
| 620 | return 0; |
| 621 | } |
| 622 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 623 | static int enable_flash_ck804(struct pci_dev *dev, const char *name) |
Yinghai Lu | 952dfce | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 624 | { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 625 | uint8_t old, new; |
Yinghai Lu | 952dfce | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 626 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 627 | old = pci_read_byte(dev, 0x88); |
| 628 | new = old | 0xc0; |
| 629 | if (new != old) { |
| 630 | pci_write_byte(dev, 0x88, new); |
| 631 | if (pci_read_byte(dev, 0x88) != new) { |
| 632 | printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name); |
| 633 | } |
| 634 | } |
Yinghai Lu | 952dfce | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 635 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 636 | old = pci_read_byte(dev, 0x6d); |
| 637 | new = old | 0x01; |
| 638 | if (new == old) |
| 639 | return 0; |
| 640 | pci_write_byte(dev, 0x6d, new); |
| 641 | |
| 642 | if (pci_read_byte(dev, 0x6d) != new) { |
| 643 | printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name); |
| 644 | return -1; |
| 645 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 646 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 647 | return 0; |
Yinghai Lu | 952dfce | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 648 | } |
| 649 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 650 | /* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */ |
| 651 | static int enable_flash_sb400(struct pci_dev *dev, const char *name) |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 652 | { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 653 | uint8_t tmp; |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 654 | struct pci_filter f; |
| 655 | struct pci_dev *smbusdev; |
| 656 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 657 | /* Look for the SMBus device. */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 658 | pci_filter_init((struct pci_access *)0, &f); |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 659 | f.vendor = 0x1002; |
| 660 | f.device = 0x4372; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 661 | |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 662 | for (smbusdev = pacc->devices; smbusdev; smbusdev = smbusdev->next) { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 663 | if (pci_filter_match(&f, smbusdev)) |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 664 | break; |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 665 | } |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 666 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 667 | if (!smbusdev) { |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 668 | fprintf(stderr, "ERROR: SMBus device not found. Aborting.\n"); |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 669 | exit(1); |
| 670 | } |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 671 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 672 | /* Enable some SMBus stuff. */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 673 | tmp = pci_read_byte(smbusdev, 0x79); |
| 674 | tmp |= 0x01; |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 675 | pci_write_byte(smbusdev, 0x79, tmp); |
| 676 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 677 | /* Change southbridge. */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 678 | tmp = pci_read_byte(dev, 0x48); |
| 679 | tmp |= 0x21; |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 680 | pci_write_byte(dev, 0x48, tmp); |
| 681 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 682 | /* Now become a bit silly. */ |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 683 | tmp = INB(0xc6f); |
| 684 | OUTB(tmp, 0xeb); |
| 685 | OUTB(tmp, 0xeb); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 686 | tmp |= 0x40; |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 687 | OUTB(tmp, 0xc6f); |
| 688 | OUTB(tmp, 0xeb); |
| 689 | OUTB(tmp, 0xeb); |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 690 | |
| 691 | return 0; |
| 692 | } |
| 693 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 694 | static int enable_flash_mcp55(struct pci_dev *dev, const char *name) |
Yinghai Lu | ca78297 | 2007-01-22 20:21:17 +0000 | [diff] [blame] | 695 | { |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 696 | uint8_t old, new, byte; |
| 697 | uint16_t word; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 698 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 699 | /* Set the 0-16 MB enable bits. */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 700 | byte = pci_read_byte(dev, 0x88); |
| 701 | byte |= 0xff; /* 256K */ |
| 702 | pci_write_byte(dev, 0x88, byte); |
| 703 | byte = pci_read_byte(dev, 0x8c); |
| 704 | byte |= 0xff; /* 1M */ |
| 705 | pci_write_byte(dev, 0x8c, byte); |
| 706 | word = pci_read_word(dev, 0x90); |
Carl-Daniel Hailfinger | dca0ab1 | 2007-10-17 22:30:07 +0000 | [diff] [blame] | 707 | word |= 0x7fff; /* 16M */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 708 | pci_write_word(dev, 0x90, word); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 709 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 710 | old = pci_read_byte(dev, 0x6d); |
| 711 | new = old | 0x01; |
| 712 | if (new == old) |
| 713 | return 0; |
| 714 | pci_write_byte(dev, 0x6d, new); |
Yinghai Lu | ca78297 | 2007-01-22 20:21:17 +0000 | [diff] [blame] | 715 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 716 | if (pci_read_byte(dev, 0x6d) != new) { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 717 | printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 718 | return -1; |
| 719 | } |
Yinghai Lu | ca78297 | 2007-01-22 20:21:17 +0000 | [diff] [blame] | 720 | |
| 721 | return 0; |
Yinghai Lu | ca78297 | 2007-01-22 20:21:17 +0000 | [diff] [blame] | 722 | } |
| 723 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 724 | static int enable_flash_ht1000(struct pci_dev *dev, const char *name) |
Stefan Reinauer | c868b9e | 2007-06-05 10:28:39 +0000 | [diff] [blame] | 725 | { |
Uwe Hermann | e823ee0 | 2007-06-05 15:02:18 +0000 | [diff] [blame] | 726 | uint8_t byte; |
Stefan Reinauer | c868b9e | 2007-06-05 10:28:39 +0000 | [diff] [blame] | 727 | |
Uwe Hermann | e823ee0 | 2007-06-05 15:02:18 +0000 | [diff] [blame] | 728 | /* Set the 4MB enable bit. */ |
Stefan Reinauer | c868b9e | 2007-06-05 10:28:39 +0000 | [diff] [blame] | 729 | byte = pci_read_byte(dev, 0x41); |
| 730 | byte |= 0x0e; |
| 731 | pci_write_byte(dev, 0x41, byte); |
| 732 | |
| 733 | byte = pci_read_byte(dev, 0x43); |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 734 | byte |= (1 << 4); |
Stefan Reinauer | c868b9e | 2007-06-05 10:28:39 +0000 | [diff] [blame] | 735 | pci_write_byte(dev, 0x43, byte); |
| 736 | |
Stefan Reinauer | c868b9e | 2007-06-05 10:28:39 +0000 | [diff] [blame] | 737 | return 0; |
| 738 | } |
| 739 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 740 | typedef struct penable { |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 741 | uint16_t vendor, device; |
| 742 | const char *name; |
| 743 | int (*doit) (struct pci_dev *dev, const char *name); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 744 | } FLASH_ENABLE; |
| 745 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 746 | static const FLASH_ENABLE enables[] = { |
Uwe Hermann | eac1016 | 2008-03-13 18:52:51 +0000 | [diff] [blame] | 747 | {0x1039, 0x0630, "SiS630", enable_flash_sis630}, |
| 748 | {0x8086, 0x7110, "Intel PIIX4/4E/4M", enable_flash_piix4}, |
| 749 | {0x8086, 0x7198, "Intel 440MX", enable_flash_piix4}, |
| 750 | {0x8086, 0x2410, "Intel ICH", enable_flash_ich_4e}, |
| 751 | {0x8086, 0x2420, "Intel ICH0", enable_flash_ich_4e}, |
| 752 | {0x8086, 0x2440, "Intel ICH2", enable_flash_ich_4e}, |
| 753 | {0x8086, 0x244c, "Intel ICH2-M", enable_flash_ich_4e}, |
| 754 | {0x8086, 0x2480, "Intel ICH3-S", enable_flash_ich_4e}, |
| 755 | {0x8086, 0x248c, "Intel ICH3-M", enable_flash_ich_4e}, |
| 756 | {0x8086, 0x24c0, "Intel ICH4/ICH4-L", enable_flash_ich_4e}, |
| 757 | {0x8086, 0x24cc, "Intel ICH4-M", enable_flash_ich_4e}, |
| 758 | {0x8086, 0x24d0, "Intel ICH5/ICH5R", enable_flash_ich_4e}, |
Claus Gindhart | a00e2a0 | 2008-05-14 12:22:38 +0000 | [diff] [blame] | 759 | {0x8086, 0x25a1, "Intel 6300ESB", enable_flash_ich_4e}, |
Uwe Hermann | eac1016 | 2008-03-13 18:52:51 +0000 | [diff] [blame] | 760 | {0x8086, 0x2640, "Intel ICH6/ICH6R", enable_flash_ich_dc}, |
| 761 | {0x8086, 0x2641, "Intel ICH6-M", enable_flash_ich_dc}, |
Ed Swierk | cd2ed47 | 2008-08-20 20:31:41 +0000 | [diff] [blame] | 762 | {0x8086, 0x5031, "Intel EP80579", enable_flash_ich_dc}, |
Carl-Daniel Hailfinger | 1b18b3c | 2008-05-16 14:39:39 +0000 | [diff] [blame] | 763 | {0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich7}, |
| 764 | {0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich7}, |
| 765 | {0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich7}, |
| 766 | {0x8086, 0x27bd, "Intel ICH7MDH", enable_flash_ich7}, |
| 767 | {0x8086, 0x2810, "Intel ICH8/ICH8R", enable_flash_ich8}, |
| 768 | {0x8086, 0x2811, "Intel ICH8M-E", enable_flash_ich8}, |
| 769 | {0x8086, 0x2812, "Intel ICH8DH", enable_flash_ich8}, |
| 770 | {0x8086, 0x2814, "Intel ICH8DO", enable_flash_ich8}, |
| 771 | {0x8086, 0x2815, "Intel ICH8M", enable_flash_ich8}, |
Carl-Daniel Hailfinger | 6dc1d3b | 2008-05-14 14:51:22 +0000 | [diff] [blame] | 772 | {0x8086, 0x2912, "Intel ICH9DH", enable_flash_ich9}, |
| 773 | {0x8086, 0x2914, "Intel ICH9DO", enable_flash_ich9}, |
| 774 | {0x8086, 0x2916, "Intel ICH9R", enable_flash_ich9}, |
| 775 | {0x8086, 0x2917, "Intel ICH9M-E", enable_flash_ich9}, |
| 776 | {0x8086, 0x2918, "Intel ICH9", enable_flash_ich9}, |
| 777 | {0x8086, 0x2919, "Intel ICH9M", enable_flash_ich9}, |
Carl-Daniel Hailfinger | 28ec74b | 2008-10-10 20:54:41 +0000 | [diff] [blame] | 778 | {0x8086, 0x3a14, "Intel ICH10DO", enable_flash_ich10}, |
| 779 | {0x8086, 0x3a16, "Intel ICH10R", enable_flash_ich10}, |
| 780 | {0x8086, 0x3a18, "Intel ICH10", enable_flash_ich10}, |
| 781 | {0x8086, 0x3a1a, "Intel ICH10D", enable_flash_ich10}, |
Uwe Hermann | eac1016 | 2008-03-13 18:52:51 +0000 | [diff] [blame] | 782 | {0x1106, 0x8231, "VIA VT8231", enable_flash_vt823x}, |
| 783 | {0x1106, 0x3177, "VIA VT8235", enable_flash_vt823x}, |
| 784 | {0x1106, 0x3227, "VIA VT8237", enable_flash_vt823x}, |
Rudolf Marek | 3fdbccf | 2008-06-30 21:38:30 +0000 | [diff] [blame] | 785 | {0x1106, 0x3372, "VIA VT8237S", enable_flash_vt8237s_spi}, |
Uwe Hermann | eac1016 | 2008-03-13 18:52:51 +0000 | [diff] [blame] | 786 | {0x1106, 0x8324, "VIA CX700", enable_flash_vt823x}, |
Uwe Hermann | 190f849 | 2008-10-25 18:03:50 +0000 | [diff] [blame^] | 787 | {0x1106, 0x0586, "VIA VT82C586A/B", enable_flash_amd8111}, |
| 788 | {0x1106, 0x0686, "VIA VT82C686A/B", enable_flash_amd8111}, |
Uwe Hermann | eac1016 | 2008-03-13 18:52:51 +0000 | [diff] [blame] | 789 | {0x1078, 0x0100, "AMD CS5530(A)", enable_flash_cs5530}, |
| 790 | {0x100b, 0x0510, "AMD SC1100", enable_flash_sc1100}, |
| 791 | {0x1039, 0x0008, "SiS5595", enable_flash_sis5595}, |
| 792 | {0x1022, 0x2080, "AMD CS5536", enable_flash_cs5536}, |
| 793 | {0x1022, 0x7468, "AMD8111", enable_flash_amd8111}, |
Marc Jones | 3af487d | 2008-10-15 17:50:29 +0000 | [diff] [blame] | 794 | {0x1002, 0x438D, "ATI(AMD) SB600", enable_flash_sb600}, |
Uwe Hermann | eac1016 | 2008-03-13 18:52:51 +0000 | [diff] [blame] | 795 | {0x10B9, 0x1533, "ALi M1533", enable_flash_ali_m1533}, |
| 796 | {0x10de, 0x0050, "NVIDIA CK804", enable_flash_ck804}, /* LPC */ |
| 797 | {0x10de, 0x0051, "NVIDIA CK804", enable_flash_ck804}, /* Pro */ |
| 798 | /* Slave, should not be here, to fix known bug for A01. */ |
| 799 | {0x10de, 0x00d3, "NVIDIA CK804", enable_flash_ck804}, |
| 800 | {0x10de, 0x0260, "NVIDIA MCP51", enable_flash_ck804}, |
| 801 | {0x10de, 0x0261, "NVIDIA MCP51", enable_flash_ck804}, |
| 802 | {0x10de, 0x0262, "NVIDIA MCP51", enable_flash_ck804}, |
| 803 | {0x10de, 0x0263, "NVIDIA MCP51", enable_flash_ck804}, |
| 804 | {0x10de, 0x0360, "NVIDIA MCP55", enable_flash_mcp55}, /* M57SLI*/ |
| 805 | {0x10de, 0x0361, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ |
| 806 | {0x10de, 0x0362, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ |
| 807 | {0x10de, 0x0363, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ |
| 808 | {0x10de, 0x0364, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ |
| 809 | {0x10de, 0x0365, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ |
| 810 | {0x10de, 0x0366, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ |
| 811 | {0x10de, 0x0367, "NVIDIA MCP55", enable_flash_mcp55}, /* Pro */ |
Stefan Reinauer | 7f27464 | 2008-07-05 09:48:30 +0000 | [diff] [blame] | 812 | {0x10de, 0x0548, "NVIDIA MCP67", enable_flash_mcp55}, |
Uwe Hermann | eac1016 | 2008-03-13 18:52:51 +0000 | [diff] [blame] | 813 | {0x1002, 0x4377, "ATI SB400", enable_flash_sb400}, |
| 814 | {0x1166, 0x0205, "Broadcom HT-1000", enable_flash_ht1000}, |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 815 | }; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 816 | |
Uwe Hermann | e5ac164 | 2008-03-12 11:54:51 +0000 | [diff] [blame] | 817 | void print_supported_chipsets(void) |
| 818 | { |
| 819 | int i; |
| 820 | |
| 821 | printf("\nSupported chipsets:\n\n"); |
| 822 | |
| 823 | for (i = 0; i < ARRAY_SIZE(enables); i++) |
| 824 | printf("%s (%04x:%04x)\n", enables[i].name, |
| 825 | enables[i].vendor, enables[i].device); |
| 826 | } |
| 827 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 828 | int chipset_flash_enable(void) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 829 | { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 830 | struct pci_dev *dev = 0; |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 831 | int ret = -2; /* Nothing! */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 832 | int i; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 833 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 834 | /* Now let's try to find the chipset we have... */ |
Uwe Hermann | e5ac164 | 2008-03-12 11:54:51 +0000 | [diff] [blame] | 835 | for (i = 0; i < ARRAY_SIZE(enables); i++) { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 836 | dev = pci_dev_find(enables[i].vendor, enables[i].device); |
| 837 | if (dev) |
| 838 | break; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 839 | } |
| 840 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 841 | if (dev) { |
Uwe Hermann | a502dce | 2007-10-17 23:55:15 +0000 | [diff] [blame] | 842 | printf("Found chipset \"%s\", enabling flash write... ", |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 843 | enables[i].name); |
| 844 | |
| 845 | ret = enables[i].doit(dev, enables[i].name); |
| 846 | if (ret) |
Uwe Hermann | a502dce | 2007-10-17 23:55:15 +0000 | [diff] [blame] | 847 | printf("FAILED!\n"); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 848 | else |
Uwe Hermann | ac30934 | 2007-10-10 17:42:20 +0000 | [diff] [blame] | 849 | printf("OK.\n"); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 850 | } |
| 851 | |
| 852 | return ret; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 853 | } |