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Ollie Lho184a4042005-11-26 21:55:36 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ollie Lho184a4042005-11-26 21:55:36 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
6 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Ollie Lho184a4042005-11-26 21:55:36 +00007 *
Uwe Hermannd1107642007-08-29 17:52:32 +00008 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
Ollie Lho184a4042005-11-26 21:55:36 +000011 *
Uwe Hermannd1107642007-08-29 17:52:32 +000012 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22/*
23 * Contains the chipset specific flash enables.
Ollie Lho184a4042005-11-26 21:55:36 +000024 */
25
Lane Brooksd54958a2007-11-13 16:45:22 +000026#define _LARGEFILE64_SOURCE
27
Ollie Lhocbbf1252004-03-17 22:22:08 +000028#include <stdio.h>
29#include <pci/pci.h>
30#include <stdlib.h>
Lane Brooksd54958a2007-11-13 16:45:22 +000031#include <sys/types.h>
32#include <sys/stat.h>
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +000033#include <sys/mman.h>
Lane Brooksd54958a2007-11-13 16:45:22 +000034#include <fcntl.h>
35#include <unistd.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000036#include "flash.h"
Stefan Reinauer86de2832006-03-31 11:26:55 +000037
Uwe Hermann372eeb52007-12-04 21:49:06 +000038static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
Luc Verhaegen6b141752007-05-20 16:16:13 +000039{
40 uint8_t tmp;
41
Uwe Hermann372eeb52007-12-04 21:49:06 +000042 /*
43 * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
44 * 0xFFFE0000-0xFFFFFFFF ROM select enable.
45 */
Luc Verhaegen6b141752007-05-20 16:16:13 +000046 tmp = pci_read_byte(dev, 0x47);
47 tmp |= 0x46;
48 pci_write_byte(dev, 0x47, tmp);
49
50 return 0;
51}
52
Uwe Hermann372eeb52007-12-04 21:49:06 +000053static int enable_flash_sis630(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +000054{
Uwe Hermann372eeb52007-12-04 21:49:06 +000055 uint8_t b;
Ollie Lhocbbf1252004-03-17 22:22:08 +000056
Uwe Hermann372eeb52007-12-04 21:49:06 +000057 /* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
Alex Beregszaszic9fb5d92007-09-11 15:58:18 +000058 b = pci_read_byte(dev, 0x40);
59 pci_write_byte(dev, 0x40, b | 0xb);
Uwe Hermann372eeb52007-12-04 21:49:06 +000060
61 /* Flash write enable on SiS 540/630. */
Alex Beregszaszic9fb5d92007-09-11 15:58:18 +000062 b = pci_read_byte(dev, 0x45);
63 pci_write_byte(dev, 0x45, b | 0x40);
Ollie Lhocbbf1252004-03-17 22:22:08 +000064
Uwe Hermann372eeb52007-12-04 21:49:06 +000065 /* The same thing on SiS 950 Super I/O side... */
66
67 /* First probe for Super I/O on config port 0x2e. */
Ollie Lhocbbf1252004-03-17 22:22:08 +000068 outb(0x87, 0x2e);
69 outb(0x01, 0x2e);
70 outb(0x55, 0x2e);
71 outb(0x55, 0x2e);
72
73 if (inb(0x2f) != 0x87) {
Uwe Hermann372eeb52007-12-04 21:49:06 +000074 /* If that failed, try config port 0x4e. */
Ollie Lhocbbf1252004-03-17 22:22:08 +000075 outb(0x87, 0x4e);
76 outb(0x01, 0x4e);
77 outb(0x55, 0x4e);
78 outb(0xaa, 0x4e);
79 if (inb(0x4f) != 0x87) {
80 printf("Can not access SiS 950\n");
81 return -1;
82 }
83 outb(0x24, 0x4e);
84 b = inb(0x4f) | 0xfc;
85 outb(0x24, 0x4e);
86 outb(b, 0x4f);
87 outb(0x02, 0x4e);
Ollie Lho761bf1b2004-03-20 16:46:10 +000088 outb(0x02, 0x4f);
Ollie Lhocbbf1252004-03-17 22:22:08 +000089 }
90
91 outb(0x24, 0x2e);
92 printf("2f is %#x\n", inb(0x2f));
93 b = inb(0x2f) | 0xfc;
94 outb(0x24, 0x2e);
95 outb(b, 0x2f);
96
97 outb(0x02, 0x2e);
98 outb(0x02, 0x2f);
99
100 return 0;
101}
102
Uwe Hermann987942d2006-11-07 11:16:21 +0000103/* Datasheet:
104 * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
105 * - URL: http://www.intel.com/design/intarch/datashts/290562.htm
106 * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
107 * - Order Number: 290562-001
108 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000109static int enable_flash_piix4(struct pci_dev *dev, const char *name)
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000110{
111 uint16_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000112 uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000113
114 old = pci_read_word(dev, xbcs);
115
116 /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
Uwe Hermanna7e05482007-05-09 10:17:44 +0000117 * FFF00000-FFF7FFFF are forwarded to ISA).
118 * Set bit 7: Extended BIOS Enable (PCI master accesses to
119 * FFF80000-FFFDFFFF are forwarded to ISA).
120 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
121 * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
122 * of 1 Mbyte, or the aliases at the top of 4 Gbyte
123 * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
124 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
125 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
126 */
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000127 new = old | 0x2c4;
128
129 if (new == old)
130 return 0;
131
132 pci_write_word(dev, xbcs, new);
133
134 if (pci_read_word(dev, xbcs) != new) {
135 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name);
136 return -1;
137 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000138
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000139 return 0;
140}
141
Uwe Hermann372eeb52007-12-04 21:49:06 +0000142/*
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000143 * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet"
144 * http://download.intel.com/design/chipsets/datashts/30701303.pdf
Uwe Hermann372eeb52007-12-04 21:49:06 +0000145 */
146static int enable_flash_ich(struct pci_dev *dev, const char *name,
147 int bios_cntl)
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000148{
Ollie Lho184a4042005-11-26 21:55:36 +0000149 uint8_t old, new;
Stefan Reinauereb366472006-09-06 15:48:48 +0000150
Uwe Hermann372eeb52007-12-04 21:49:06 +0000151 /*
152 * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but
Uwe Hermanna7e05482007-05-09 10:17:44 +0000153 * just treating it as 8 bit wide seems to work fine in practice.
Stefan Reinauereb366472006-09-06 15:48:48 +0000154 */
Stefan Reinauer86de2832006-03-31 11:26:55 +0000155 old = pci_read_byte(dev, bios_cntl);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000156
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000157 printf_debug("BIOS Lock Enable: %sabled, ",
158 (old & (1 << 1)) ? "en" : "dis");
159 printf_debug("BIOS Write Enable: %sabled, ",
160 (old & (1 << 0)) ? "en" : "dis");
161 printf_debug("BIOS_CNTL is 0x%x\n", old);
162
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000163 new = old | 1;
164
165 if (new == old)
166 return 0;
167
Stefan Reinauer86de2832006-03-31 11:26:55 +0000168 pci_write_byte(dev, bios_cntl, new);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000169
Stefan Reinauer86de2832006-03-31 11:26:55 +0000170 if (pci_read_byte(dev, bios_cntl) != new) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000171 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000172 return -1;
173 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000174
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000175 return 0;
176}
177
Uwe Hermann372eeb52007-12-04 21:49:06 +0000178static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000179{
Stefan Reinauereb366472006-09-06 15:48:48 +0000180 return enable_flash_ich(dev, name, 0x4e);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000181}
182
Uwe Hermann372eeb52007-12-04 21:49:06 +0000183static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000184{
Stefan Reinauereb366472006-09-06 15:48:48 +0000185 return enable_flash_ich(dev, name, 0xdc);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000186}
187
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000188static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name)
189{
190 uint8_t old, new, bbs;
191 uint32_t tmp, gcs;
192 void *rcba;
193
194 /* Root Complex Base Address Register (RCBA) */
195 tmp = pci_read_long(dev, 0xf0);
196 tmp &= 0xffffc000;
197 printf_debug("Root Complex Base Address Register = 0x%x\n", tmp);
198 rcba = mmap(0, 0x3510, PROT_READ, MAP_SHARED, fd_mem, (off_t)tmp);
199 if (rcba == MAP_FAILED) {
200 perror("Can't mmap memory using " MEM_DEV);
201 exit(1);
202 }
203 printf_debug("GCS address = 0x%x\n", tmp + 0x3410);
204 gcs = *(volatile uint32_t *)(rcba + 0x3410);
205 printf_debug("GCS = 0x%x: ", gcs);
206 printf_debug("BIOS Interface Lock-Down: %sabled, ",
207 (gcs & 0x1) ? "en" : "dis");
208 bbs = (gcs >> 10) & 0x3;
209 printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs,
210 (bbs == 0x3) ? "LPC" : ((bbs == 0x2) ? "PCI" : "SPI"));
Carl-Daniel Hailfingerb36a0712008-03-18 00:54:10 +0000211 /* SPIBAR is at RCBA+0x3020 for ICH[78] and RCBA+0x3800 for ICH9. */
212 /* printf_debug("SPIBAR = 0x%x\n", tmp + 0x3020); */
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000213 /* TODO: Dump the SPI config regs */
214 munmap(rcba, 0x3510);
215
216 old = pci_read_byte(dev, 0xdc);
217 printf_debug("SPI Read Configuration: ");
218 new = (old >> 2) & 0x3;
219 switch (new) {
220 case 0:
221 case 1:
222 case 2:
223 printf_debug("prefetching %sabled, caching %sabled, ",
224 (new & 0x2) ? "en" : "dis", (new & 0x1) ? "dis" : "en");
225 break;
226 default:
227 printf_debug("invalid prefetching/caching settings, ");
228 break;
229 }
230 return enable_flash_ich_dc(dev, name);
231}
232
Uwe Hermann372eeb52007-12-04 21:49:06 +0000233static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000234{
Ollie Lho184a4042005-11-26 21:55:36 +0000235 uint8_t val;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000236
Bari Ari9477c4e2008-04-29 13:46:38 +0000237 /* enable ROM decode range (1MB) FFC00000 - FFFFFFFF*/
238 pci_write_byte(dev, 0x41, 0x7f);
239
Uwe Hermannffec5f32007-08-23 16:08:21 +0000240 /* ROM write enable */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000241 val = pci_read_byte(dev, 0x40);
242 val |= 0x10;
243 pci_write_byte(dev, 0x40, val);
244
245 if (pci_read_byte(dev, 0x40) != val) {
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000246 printf("\nWARNING: Failed to enable ROM Write on \"%s\"\n",
Uwe Hermanna7e05482007-05-09 10:17:44 +0000247 name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000248 return -1;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000249 }
Luc Verhaegen6382b442007-03-02 22:16:38 +0000250
Uwe Hermanna7e05482007-05-09 10:17:44 +0000251 return 0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000252}
253
Uwe Hermann372eeb52007-12-04 21:49:06 +0000254static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000255{
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000256 uint8_t reg8;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000257
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000258 #define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
259 #define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000260
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000261 #define LOWER_ROM_ADDRESS_RANGE (1 << 0)
262 #define ROM_WRITE_ENABLE (1 << 1)
263 #define UPPER_ROM_ADDRESS_RANGE (1 << 2)
264 #define BIOS_ROM_POSITIVE_DECODE (1 << 5)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000265
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000266 /* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and
267 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB.
268 * Make the configured ROM areas writable.
269 */
270 reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
271 reg8 |= LOWER_ROM_ADDRESS_RANGE;
272 reg8 |= UPPER_ROM_ADDRESS_RANGE;
273 reg8 |= ROM_WRITE_ENABLE;
274 pci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000275
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000276 /* Set positive decode on ROM. */
277 reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
278 reg8 |= BIOS_ROM_POSITIVE_DECODE;
279 pci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000280
Ollie Lhocbbf1252004-03-17 22:22:08 +0000281 return 0;
282}
283
Mart Raudseppe1344da2008-02-08 10:10:57 +0000284/**
285 * Geode systems write protect the BIOS via RCONFs (cache settings similar
286 * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22. Reading and
287 * writing to MSRs, however requires instructions rdmsr/wrmsr, which are
288 * ring0 privileged instructions so only the kernel can do the read/write.
289 * This function, therefore, requires that the msr kernel module be loaded
290 * to access these instructions from user space using device /dev/cpu/0/msr.
291 *
292 * This hard-coded location could have potential problems on SMP machines
293 * since it assumes cpu0, but it is safe on the Geode which is not SMP.
294 *
295 * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
296 * To enable write to NOR Boot flash for the benefit of systems that have such
297 * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
298 *
299 * This is probably not portable beyond Linux.
300 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000301static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
Lane Brooksd54958a2007-11-13 16:45:22 +0000302{
Mart Raudseppe1344da2008-02-08 10:10:57 +0000303 #define MSR_RCONF_DEFAULT 0x1808
304 #define MSR_NORF_CTL 0x51400018
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000305
Lane Brooksd54958a2007-11-13 16:45:22 +0000306 int fd_msr;
307 unsigned char buf[8];
Lane Brooksd54958a2007-11-13 16:45:22 +0000308
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000309 fd_msr = open("/dev/cpu/0/msr", O_RDWR);
Lane Brooksd54958a2007-11-13 16:45:22 +0000310 if (!fd_msr) {
311 perror("open msr");
312 return -1;
313 }
Mart Raudseppe1344da2008-02-08 10:10:57 +0000314
315 if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) {
316 perror("lseek64");
Mart Raudsepp3697ac72008-02-11 14:32:45 +0000317 printf("Cannot operate on MSR. Did you run 'modprobe msr'?\n");
Mart Raudseppe1344da2008-02-08 10:10:57 +0000318 close(fd_msr);
319 return -1;
320 }
321
322 if (read(fd_msr, buf, 8) != 8) {
Mart Raudsepp3697ac72008-02-11 14:32:45 +0000323 perror("read msr");
Mart Raudseppe1344da2008-02-08 10:10:57 +0000324 close(fd_msr);
325 return -1;
326 }
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000327
Lane Brooksd54958a2007-11-13 16:45:22 +0000328 if (buf[7] != 0x22) {
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000329 buf[7] &= 0xfb;
Mart Raudseppe1344da2008-02-08 10:10:57 +0000330 if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) {
331 perror("lseek64");
332 close(fd_msr);
333 return -1;
334 }
335
Lane Brooksd54958a2007-11-13 16:45:22 +0000336 if (write(fd_msr, buf, 8) < 0) {
337 perror("msr write");
Mart Raudseppe1344da2008-02-08 10:10:57 +0000338 close(fd_msr);
Lane Brooksd54958a2007-11-13 16:45:22 +0000339 return -1;
340 }
Lane Brooksd54958a2007-11-13 16:45:22 +0000341 }
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000342
Mart Raudseppe1344da2008-02-08 10:10:57 +0000343 if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) {
344 perror("lseek64");
345 close(fd_msr);
346 return -1;
347 }
348
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000349 if (read(fd_msr, buf, 8) != 8) {
350 perror("read msr");
Mart Raudseppe1344da2008-02-08 10:10:57 +0000351 close(fd_msr);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000352 return -1;
353 }
354
355 /* Raise WE_CS3 bit. */
356 buf[0] |= 0x08;
357
Mart Raudseppe1344da2008-02-08 10:10:57 +0000358 if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) {
359 perror("lseek64");
360 close(fd_msr);
361 return -1;
362 }
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000363 if (write(fd_msr, buf, 8) < 0) {
364 perror("msr write");
Mart Raudseppe1344da2008-02-08 10:10:57 +0000365 close(fd_msr);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000366 return -1;
367 }
368
369 close(fd_msr);
370
Mart Raudseppe1344da2008-02-08 10:10:57 +0000371 #undef MSR_RCONF_DEFAULT
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000372 #undef MSR_NORF_CTL
Lane Brooksd54958a2007-11-13 16:45:22 +0000373 return 0;
374}
375
Uwe Hermann372eeb52007-12-04 21:49:06 +0000376static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000377{
Ollie Lho184a4042005-11-26 21:55:36 +0000378 uint8_t new;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000379
Ollie Lhocbbf1252004-03-17 22:22:08 +0000380 pci_write_byte(dev, 0x52, 0xee);
381
382 new = pci_read_byte(dev, 0x52);
383
384 if (new != 0xee) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000385 printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000386 return -1;
387 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000388
Ollie Lhocbbf1252004-03-17 22:22:08 +0000389 return 0;
390}
391
Uwe Hermann372eeb52007-12-04 21:49:06 +0000392static int enable_flash_sis5595(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000393{
Ollie Lho184a4042005-11-26 21:55:36 +0000394 uint8_t new, newer;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000395
Ollie Lhocbbf1252004-03-17 22:22:08 +0000396 new = pci_read_byte(dev, 0x45);
397
Uwe Hermann372eeb52007-12-04 21:49:06 +0000398 new &= (~0x20); /* Clear bit 5. */
399 new |= 0x4; /* Set bit 2. */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000400
401 pci_write_byte(dev, 0x45, new);
402
403 newer = pci_read_byte(dev, 0x45);
404 if (newer != new) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000405 printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000406 printf("Stuck at 0x%x\n", newer);
407 return -1;
408 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000409
Ollie Lhocbbf1252004-03-17 22:22:08 +0000410 return 0;
411}
412
Uwe Hermann372eeb52007-12-04 21:49:06 +0000413static int enable_flash_amd8111(struct pci_dev *dev, const char *name)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000414{
Ollie Lho184a4042005-11-26 21:55:36 +0000415 uint8_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000416
Uwe Hermann372eeb52007-12-04 21:49:06 +0000417 /* Enable decoding at 0xffb00000 to 0xffffffff. */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000418 old = pci_read_byte(dev, 0x43);
Ollie Lhod11f3612004-12-07 17:19:04 +0000419 new = old | 0xC0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000420 if (new != old) {
421 pci_write_byte(dev, 0x43, new);
422 if (pci_read_byte(dev, 0x43) != new) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000423 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000424 }
425 }
426
Ollie Lho761bf1b2004-03-20 16:46:10 +0000427 old = pci_read_byte(dev, 0x40);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000428 new = old | 0x01;
429 if (new == old)
430 return 0;
431 pci_write_byte(dev, 0x40, new);
432
433 if (pci_read_byte(dev, 0x40) != new) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000434 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000435 return -1;
436 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000437
Ollie Lhocbbf1252004-03-17 22:22:08 +0000438 return 0;
439}
440
Uwe Hermann372eeb52007-12-04 21:49:06 +0000441static int enable_flash_ck804(struct pci_dev *dev, const char *name)
Yinghai Lu952dfce2005-07-06 17:13:46 +0000442{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000443 uint8_t old, new;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000444
Uwe Hermanna7e05482007-05-09 10:17:44 +0000445 old = pci_read_byte(dev, 0x88);
446 new = old | 0xc0;
447 if (new != old) {
448 pci_write_byte(dev, 0x88, new);
449 if (pci_read_byte(dev, 0x88) != new) {
450 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name);
451 }
452 }
Yinghai Lu952dfce2005-07-06 17:13:46 +0000453
Uwe Hermanna7e05482007-05-09 10:17:44 +0000454 old = pci_read_byte(dev, 0x6d);
455 new = old | 0x01;
456 if (new == old)
457 return 0;
458 pci_write_byte(dev, 0x6d, new);
459
460 if (pci_read_byte(dev, 0x6d) != new) {
461 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
462 return -1;
463 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000464
Uwe Hermanna7e05482007-05-09 10:17:44 +0000465 return 0;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000466}
467
Uwe Hermann372eeb52007-12-04 21:49:06 +0000468/* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
469static int enable_flash_sb400(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000470{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000471 uint8_t tmp;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000472 struct pci_filter f;
473 struct pci_dev *smbusdev;
474
Uwe Hermann372eeb52007-12-04 21:49:06 +0000475 /* Look for the SMBus device. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000476 pci_filter_init((struct pci_access *)0, &f);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000477 f.vendor = 0x1002;
478 f.device = 0x4372;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000479
Stefan Reinauer86de2832006-03-31 11:26:55 +0000480 for (smbusdev = pacc->devices; smbusdev; smbusdev = smbusdev->next) {
481 if (pci_filter_match(&f, smbusdev)) {
482 break;
483 }
484 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000485
Uwe Hermanna7e05482007-05-09 10:17:44 +0000486 if (!smbusdev) {
Uwe Hermann372eeb52007-12-04 21:49:06 +0000487 fprintf(stderr, "ERROR: SMBus device not found. Aborting.\n");
Stefan Reinauer86de2832006-03-31 11:26:55 +0000488 exit(1);
489 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000490
Uwe Hermann372eeb52007-12-04 21:49:06 +0000491 /* Enable some SMBus stuff. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000492 tmp = pci_read_byte(smbusdev, 0x79);
493 tmp |= 0x01;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000494 pci_write_byte(smbusdev, 0x79, tmp);
495
Uwe Hermann372eeb52007-12-04 21:49:06 +0000496 /* Change southbridge. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000497 tmp = pci_read_byte(dev, 0x48);
498 tmp |= 0x21;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000499 pci_write_byte(dev, 0x48, tmp);
500
Uwe Hermann372eeb52007-12-04 21:49:06 +0000501 /* Now become a bit silly. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000502 tmp = inb(0xc6f);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000503 outb(tmp, 0xeb);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000504 outb(tmp, 0xeb);
505 tmp |= 0x40;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000506 outb(tmp, 0xc6f);
507 outb(tmp, 0xeb);
508 outb(tmp, 0xeb);
509
510 return 0;
511}
512
Uwe Hermann372eeb52007-12-04 21:49:06 +0000513static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
Yinghai Luca782972007-01-22 20:21:17 +0000514{
Uwe Hermann372eeb52007-12-04 21:49:06 +0000515 uint8_t old, new, byte;
516 uint16_t word;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000517
Uwe Hermann372eeb52007-12-04 21:49:06 +0000518 /* Set the 0-16 MB enable bits. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000519 byte = pci_read_byte(dev, 0x88);
520 byte |= 0xff; /* 256K */
521 pci_write_byte(dev, 0x88, byte);
522 byte = pci_read_byte(dev, 0x8c);
523 byte |= 0xff; /* 1M */
524 pci_write_byte(dev, 0x8c, byte);
525 word = pci_read_word(dev, 0x90);
Carl-Daniel Hailfingerdca0ab12007-10-17 22:30:07 +0000526 word |= 0x7fff; /* 16M */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000527 pci_write_word(dev, 0x90, word);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000528
Uwe Hermanna7e05482007-05-09 10:17:44 +0000529 old = pci_read_byte(dev, 0x6d);
530 new = old | 0x01;
531 if (new == old)
532 return 0;
533 pci_write_byte(dev, 0x6d, new);
Yinghai Luca782972007-01-22 20:21:17 +0000534
Uwe Hermanna7e05482007-05-09 10:17:44 +0000535 if (pci_read_byte(dev, 0x6d) != new) {
536 printf
537 ("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
538 0x6d, new, name);
539 return -1;
540 }
Yinghai Luca782972007-01-22 20:21:17 +0000541
542 return 0;
Yinghai Luca782972007-01-22 20:21:17 +0000543}
544
Uwe Hermann372eeb52007-12-04 21:49:06 +0000545static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000546{
Uwe Hermanne823ee02007-06-05 15:02:18 +0000547 uint8_t byte;
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000548
Uwe Hermanne823ee02007-06-05 15:02:18 +0000549 /* Set the 4MB enable bit. */
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000550 byte = pci_read_byte(dev, 0x41);
551 byte |= 0x0e;
552 pci_write_byte(dev, 0x41, byte);
553
554 byte = pci_read_byte(dev, 0x43);
Uwe Hermannffec5f32007-08-23 16:08:21 +0000555 byte |= (1 << 4);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000556 pci_write_byte(dev, 0x43, byte);
557
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000558 return 0;
559}
560
Ollie Lhocbbf1252004-03-17 22:22:08 +0000561typedef struct penable {
Uwe Hermann372eeb52007-12-04 21:49:06 +0000562 uint16_t vendor, device;
563 const char *name;
564 int (*doit) (struct pci_dev *dev, const char *name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000565} FLASH_ENABLE;
566
Uwe Hermann372eeb52007-12-04 21:49:06 +0000567static const FLASH_ENABLE enables[] = {
Uwe Hermanneac10162008-03-13 18:52:51 +0000568 {0x1039, 0x0630, "SiS630", enable_flash_sis630},
569 {0x8086, 0x7110, "Intel PIIX4/4E/4M", enable_flash_piix4},
570 {0x8086, 0x7198, "Intel 440MX", enable_flash_piix4},
571 {0x8086, 0x2410, "Intel ICH", enable_flash_ich_4e},
572 {0x8086, 0x2420, "Intel ICH0", enable_flash_ich_4e},
573 {0x8086, 0x2440, "Intel ICH2", enable_flash_ich_4e},
574 {0x8086, 0x244c, "Intel ICH2-M", enable_flash_ich_4e},
575 {0x8086, 0x2480, "Intel ICH3-S", enable_flash_ich_4e},
576 {0x8086, 0x248c, "Intel ICH3-M", enable_flash_ich_4e},
577 {0x8086, 0x24c0, "Intel ICH4/ICH4-L", enable_flash_ich_4e},
578 {0x8086, 0x24cc, "Intel ICH4-M", enable_flash_ich_4e},
579 {0x8086, 0x24d0, "Intel ICH5/ICH5R", enable_flash_ich_4e},
580 {0x8086, 0x2640, "Intel ICH6/ICH6R", enable_flash_ich_dc},
581 {0x8086, 0x2641, "Intel ICH6-M", enable_flash_ich_dc},
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000582 {0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich_dc_spi},
583 {0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich_dc_spi},
584 {0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich_dc_spi},
585 {0x8086, 0x27bd, "Intel ICH7MDH", enable_flash_ich_dc_spi},
586 {0x8086, 0x2810, "Intel ICH8/ICH8R", enable_flash_ich_dc_spi},
587 {0x8086, 0x2811, "Intel ICH8M-E", enable_flash_ich_dc_spi},
588 {0x8086, 0x2812, "Intel ICH8DH", enable_flash_ich_dc_spi},
589 {0x8086, 0x2814, "Intel ICH8DO", enable_flash_ich_dc_spi},
590 {0x8086, 0x2815, "Intel ICH8M", enable_flash_ich_dc_spi},
Carl-Daniel Hailfingerb36a0712008-03-18 00:54:10 +0000591 {0x8086, 0x2912, "Intel ICH9DH", enable_flash_ich_dc_spi},
592 {0x8086, 0x2914, "Intel ICH9DO", enable_flash_ich_dc_spi},
593 {0x8086, 0x2916, "Intel ICH9R", enable_flash_ich_dc_spi},
594 {0x8086, 0x2917, "Intel ICH9M-E", enable_flash_ich_dc_spi},
595 {0x8086, 0x2918, "Intel ICH9", enable_flash_ich_dc_spi},
596 {0x8086, 0x2919, "Intel ICH9M", enable_flash_ich_dc_spi},
Uwe Hermanneac10162008-03-13 18:52:51 +0000597 {0x1106, 0x8231, "VIA VT8231", enable_flash_vt823x},
598 {0x1106, 0x3177, "VIA VT8235", enable_flash_vt823x},
599 {0x1106, 0x3227, "VIA VT8237", enable_flash_vt823x},
600 {0x1106, 0x8324, "VIA CX700", enable_flash_vt823x},
601 {0x1106, 0x0686, "VIA VT82C686", enable_flash_amd8111},
602 {0x1078, 0x0100, "AMD CS5530(A)", enable_flash_cs5530},
603 {0x100b, 0x0510, "AMD SC1100", enable_flash_sc1100},
604 {0x1039, 0x0008, "SiS5595", enable_flash_sis5595},
605 {0x1022, 0x2080, "AMD CS5536", enable_flash_cs5536},
606 {0x1022, 0x7468, "AMD8111", enable_flash_amd8111},
607 {0x10B9, 0x1533, "ALi M1533", enable_flash_ali_m1533},
608 {0x10de, 0x0050, "NVIDIA CK804", enable_flash_ck804}, /* LPC */
609 {0x10de, 0x0051, "NVIDIA CK804", enable_flash_ck804}, /* Pro */
610 /* Slave, should not be here, to fix known bug for A01. */
611 {0x10de, 0x00d3, "NVIDIA CK804", enable_flash_ck804},
612 {0x10de, 0x0260, "NVIDIA MCP51", enable_flash_ck804},
613 {0x10de, 0x0261, "NVIDIA MCP51", enable_flash_ck804},
614 {0x10de, 0x0262, "NVIDIA MCP51", enable_flash_ck804},
615 {0x10de, 0x0263, "NVIDIA MCP51", enable_flash_ck804},
616 {0x10de, 0x0360, "NVIDIA MCP55", enable_flash_mcp55}, /* M57SLI*/
617 {0x10de, 0x0361, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
618 {0x10de, 0x0362, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
619 {0x10de, 0x0363, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
620 {0x10de, 0x0364, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
621 {0x10de, 0x0365, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
622 {0x10de, 0x0366, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
623 {0x10de, 0x0367, "NVIDIA MCP55", enable_flash_mcp55}, /* Pro */
624 {0x1002, 0x4377, "ATI SB400", enable_flash_sb400},
625 {0x1166, 0x0205, "Broadcom HT-1000", enable_flash_ht1000},
Ollie Lhocbbf1252004-03-17 22:22:08 +0000626};
Ollie Lho761bf1b2004-03-20 16:46:10 +0000627
Uwe Hermanne5ac1642008-03-12 11:54:51 +0000628void print_supported_chipsets(void)
629{
630 int i;
631
632 printf("\nSupported chipsets:\n\n");
633
634 for (i = 0; i < ARRAY_SIZE(enables); i++)
635 printf("%s (%04x:%04x)\n", enables[i].name,
636 enables[i].vendor, enables[i].device);
637}
638
Uwe Hermanna7e05482007-05-09 10:17:44 +0000639int chipset_flash_enable(void)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000640{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000641 struct pci_dev *dev = 0;
Uwe Hermann372eeb52007-12-04 21:49:06 +0000642 int ret = -2; /* Nothing! */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000643 int i;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000644
Uwe Hermann372eeb52007-12-04 21:49:06 +0000645 /* Now let's try to find the chipset we have... */
Uwe Hermanne5ac1642008-03-12 11:54:51 +0000646 for (i = 0; i < ARRAY_SIZE(enables); i++) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000647 dev = pci_dev_find(enables[i].vendor, enables[i].device);
648 if (dev)
649 break;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000650 }
651
Uwe Hermanna7e05482007-05-09 10:17:44 +0000652 if (dev) {
Uwe Hermanna502dce2007-10-17 23:55:15 +0000653 printf("Found chipset \"%s\", enabling flash write... ",
Uwe Hermanna7e05482007-05-09 10:17:44 +0000654 enables[i].name);
655
656 ret = enables[i].doit(dev, enables[i].name);
657 if (ret)
Uwe Hermanna502dce2007-10-17 23:55:15 +0000658 printf("FAILED!\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +0000659 else
Uwe Hermannac309342007-10-10 17:42:20 +0000660 printf("OK.\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +0000661 }
662
663 return ret;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000664}