Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 1 | /* |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 2 | * This file is part of the flashrom project. |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 3 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 4 | * Copyright (C) 2000 Silicon Integrated System Corporation |
| 5 | * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de> |
| 6 | * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de> |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 7 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 11 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | /* |
| 23 | * Contains the chipset specific flash enables. |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 24 | */ |
| 25 | |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 26 | #define _LARGEFILE64_SOURCE |
| 27 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 28 | #include <stdio.h> |
| 29 | #include <pci/pci.h> |
| 30 | #include <stdlib.h> |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 31 | #include <sys/types.h> |
| 32 | #include <sys/stat.h> |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 33 | #include <sys/mman.h> |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 34 | #include <fcntl.h> |
| 35 | #include <unistd.h> |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 36 | #include "flash.h" |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 37 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 38 | static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 39 | { |
| 40 | uint8_t tmp; |
| 41 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 42 | /* |
| 43 | * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and |
| 44 | * 0xFFFE0000-0xFFFFFFFF ROM select enable. |
| 45 | */ |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 46 | tmp = pci_read_byte(dev, 0x47); |
| 47 | tmp |= 0x46; |
| 48 | pci_write_byte(dev, 0x47, tmp); |
| 49 | |
| 50 | return 0; |
| 51 | } |
| 52 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 53 | static int enable_flash_sis630(struct pci_dev *dev, const char *name) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 54 | { |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 55 | uint8_t b; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 56 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 57 | /* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */ |
Alex Beregszaszi | c9fb5d9 | 2007-09-11 15:58:18 +0000 | [diff] [blame] | 58 | b = pci_read_byte(dev, 0x40); |
| 59 | pci_write_byte(dev, 0x40, b | 0xb); |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 60 | |
| 61 | /* Flash write enable on SiS 540/630. */ |
Alex Beregszaszi | c9fb5d9 | 2007-09-11 15:58:18 +0000 | [diff] [blame] | 62 | b = pci_read_byte(dev, 0x45); |
| 63 | pci_write_byte(dev, 0x45, b | 0x40); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 64 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 65 | /* The same thing on SiS 950 Super I/O side... */ |
| 66 | |
| 67 | /* First probe for Super I/O on config port 0x2e. */ |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 68 | outb(0x87, 0x2e); |
| 69 | outb(0x01, 0x2e); |
| 70 | outb(0x55, 0x2e); |
| 71 | outb(0x55, 0x2e); |
| 72 | |
| 73 | if (inb(0x2f) != 0x87) { |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 74 | /* If that failed, try config port 0x4e. */ |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 75 | outb(0x87, 0x4e); |
| 76 | outb(0x01, 0x4e); |
| 77 | outb(0x55, 0x4e); |
| 78 | outb(0xaa, 0x4e); |
| 79 | if (inb(0x4f) != 0x87) { |
| 80 | printf("Can not access SiS 950\n"); |
| 81 | return -1; |
| 82 | } |
| 83 | outb(0x24, 0x4e); |
| 84 | b = inb(0x4f) | 0xfc; |
| 85 | outb(0x24, 0x4e); |
| 86 | outb(b, 0x4f); |
| 87 | outb(0x02, 0x4e); |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 88 | outb(0x02, 0x4f); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 89 | } |
| 90 | |
| 91 | outb(0x24, 0x2e); |
| 92 | printf("2f is %#x\n", inb(0x2f)); |
| 93 | b = inb(0x2f) | 0xfc; |
| 94 | outb(0x24, 0x2e); |
| 95 | outb(b, 0x2f); |
| 96 | |
| 97 | outb(0x02, 0x2e); |
| 98 | outb(0x02, 0x2f); |
| 99 | |
| 100 | return 0; |
| 101 | } |
| 102 | |
Uwe Hermann | 987942d | 2006-11-07 11:16:21 +0000 | [diff] [blame] | 103 | /* Datasheet: |
| 104 | * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4) |
| 105 | * - URL: http://www.intel.com/design/intarch/datashts/290562.htm |
| 106 | * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf |
| 107 | * - Order Number: 290562-001 |
| 108 | */ |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 109 | static int enable_flash_piix4(struct pci_dev *dev, const char *name) |
Uwe Hermann | ea2c66d | 2006-11-05 18:26:08 +0000 | [diff] [blame] | 110 | { |
| 111 | uint16_t old, new; |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 112 | uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */ |
Uwe Hermann | ea2c66d | 2006-11-05 18:26:08 +0000 | [diff] [blame] | 113 | |
| 114 | old = pci_read_word(dev, xbcs); |
| 115 | |
| 116 | /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 117 | * FFF00000-FFF7FFFF are forwarded to ISA). |
| 118 | * Set bit 7: Extended BIOS Enable (PCI master accesses to |
| 119 | * FFF80000-FFFDFFFF are forwarded to ISA). |
| 120 | * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to |
| 121 | * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top |
| 122 | * of 1 Mbyte, or the aliases at the top of 4 Gbyte |
| 123 | * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#. |
| 124 | * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA. |
| 125 | * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable). |
| 126 | */ |
Uwe Hermann | ea2c66d | 2006-11-05 18:26:08 +0000 | [diff] [blame] | 127 | new = old | 0x2c4; |
| 128 | |
| 129 | if (new == old) |
| 130 | return 0; |
| 131 | |
| 132 | pci_write_word(dev, xbcs, new); |
| 133 | |
| 134 | if (pci_read_word(dev, xbcs) != new) { |
| 135 | printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name); |
| 136 | return -1; |
| 137 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 138 | |
Uwe Hermann | ea2c66d | 2006-11-05 18:26:08 +0000 | [diff] [blame] | 139 | return 0; |
| 140 | } |
| 141 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 142 | /* |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 143 | * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet" |
| 144 | * http://download.intel.com/design/chipsets/datashts/30701303.pdf |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 145 | */ |
| 146 | static int enable_flash_ich(struct pci_dev *dev, const char *name, |
| 147 | int bios_cntl) |
Ronald G. Minnich | 6a96741 | 2004-09-28 20:09:06 +0000 | [diff] [blame] | 148 | { |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 149 | uint8_t old, new; |
Stefan Reinauer | eb36647 | 2006-09-06 15:48:48 +0000 | [diff] [blame] | 150 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 151 | /* |
| 152 | * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 153 | * just treating it as 8 bit wide seems to work fine in practice. |
Stefan Reinauer | eb36647 | 2006-09-06 15:48:48 +0000 | [diff] [blame] | 154 | */ |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 155 | old = pci_read_byte(dev, bios_cntl); |
Ronald G. Minnich | 6a96741 | 2004-09-28 20:09:06 +0000 | [diff] [blame] | 156 | |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 157 | printf_debug("BIOS Lock Enable: %sabled, ", |
| 158 | (old & (1 << 1)) ? "en" : "dis"); |
| 159 | printf_debug("BIOS Write Enable: %sabled, ", |
| 160 | (old & (1 << 0)) ? "en" : "dis"); |
| 161 | printf_debug("BIOS_CNTL is 0x%x\n", old); |
| 162 | |
Ronald G. Minnich | 6a96741 | 2004-09-28 20:09:06 +0000 | [diff] [blame] | 163 | new = old | 1; |
| 164 | |
| 165 | if (new == old) |
| 166 | return 0; |
| 167 | |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 168 | pci_write_byte(dev, bios_cntl, new); |
Ronald G. Minnich | 6a96741 | 2004-09-28 20:09:06 +0000 | [diff] [blame] | 169 | |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 170 | if (pci_read_byte(dev, bios_cntl) != new) { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 171 | printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name); |
Ronald G. Minnich | 6a96741 | 2004-09-28 20:09:06 +0000 | [diff] [blame] | 172 | return -1; |
| 173 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 174 | |
Ronald G. Minnich | 6a96741 | 2004-09-28 20:09:06 +0000 | [diff] [blame] | 175 | return 0; |
| 176 | } |
| 177 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 178 | static int enable_flash_ich_4e(struct pci_dev *dev, const char *name) |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 179 | { |
Stefan Reinauer | eb36647 | 2006-09-06 15:48:48 +0000 | [diff] [blame] | 180 | return enable_flash_ich(dev, name, 0x4e); |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 181 | } |
| 182 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 183 | static int enable_flash_ich_dc(struct pci_dev *dev, const char *name) |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 184 | { |
Stefan Reinauer | eb36647 | 2006-09-06 15:48:48 +0000 | [diff] [blame] | 185 | return enable_flash_ich(dev, name, 0xdc); |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 186 | } |
| 187 | |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 188 | static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name) |
| 189 | { |
| 190 | uint8_t old, new, bbs; |
| 191 | uint32_t tmp, gcs; |
| 192 | void *rcba; |
| 193 | |
| 194 | /* Root Complex Base Address Register (RCBA) */ |
| 195 | tmp = pci_read_long(dev, 0xf0); |
| 196 | tmp &= 0xffffc000; |
| 197 | printf_debug("Root Complex Base Address Register = 0x%x\n", tmp); |
| 198 | rcba = mmap(0, 0x3510, PROT_READ, MAP_SHARED, fd_mem, (off_t)tmp); |
| 199 | if (rcba == MAP_FAILED) { |
| 200 | perror("Can't mmap memory using " MEM_DEV); |
| 201 | exit(1); |
| 202 | } |
| 203 | printf_debug("GCS address = 0x%x\n", tmp + 0x3410); |
| 204 | gcs = *(volatile uint32_t *)(rcba + 0x3410); |
| 205 | printf_debug("GCS = 0x%x: ", gcs); |
| 206 | printf_debug("BIOS Interface Lock-Down: %sabled, ", |
| 207 | (gcs & 0x1) ? "en" : "dis"); |
| 208 | bbs = (gcs >> 10) & 0x3; |
| 209 | printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, |
| 210 | (bbs == 0x3) ? "LPC" : ((bbs == 0x2) ? "PCI" : "SPI")); |
Carl-Daniel Hailfinger | b36a071 | 2008-03-18 00:54:10 +0000 | [diff] [blame] | 211 | /* SPIBAR is at RCBA+0x3020 for ICH[78] and RCBA+0x3800 for ICH9. */ |
| 212 | /* printf_debug("SPIBAR = 0x%x\n", tmp + 0x3020); */ |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 213 | /* TODO: Dump the SPI config regs */ |
| 214 | munmap(rcba, 0x3510); |
| 215 | |
| 216 | old = pci_read_byte(dev, 0xdc); |
| 217 | printf_debug("SPI Read Configuration: "); |
| 218 | new = (old >> 2) & 0x3; |
| 219 | switch (new) { |
| 220 | case 0: |
| 221 | case 1: |
| 222 | case 2: |
| 223 | printf_debug("prefetching %sabled, caching %sabled, ", |
| 224 | (new & 0x2) ? "en" : "dis", (new & 0x1) ? "dis" : "en"); |
| 225 | break; |
| 226 | default: |
| 227 | printf_debug("invalid prefetching/caching settings, "); |
| 228 | break; |
| 229 | } |
| 230 | return enable_flash_ich_dc(dev, name); |
| 231 | } |
| 232 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 233 | static int enable_flash_vt823x(struct pci_dev *dev, const char *name) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 234 | { |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 235 | uint8_t val; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 236 | |
Bari Ari | 9477c4e | 2008-04-29 13:46:38 +0000 | [diff] [blame^] | 237 | /* enable ROM decode range (1MB) FFC00000 - FFFFFFFF*/ |
| 238 | pci_write_byte(dev, 0x41, 0x7f); |
| 239 | |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 240 | /* ROM write enable */ |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 241 | val = pci_read_byte(dev, 0x40); |
| 242 | val |= 0x10; |
| 243 | pci_write_byte(dev, 0x40, val); |
| 244 | |
| 245 | if (pci_read_byte(dev, 0x40) != val) { |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 246 | printf("\nWARNING: Failed to enable ROM Write on \"%s\"\n", |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 247 | name); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 248 | return -1; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 249 | } |
Luc Verhaegen | 6382b44 | 2007-03-02 22:16:38 +0000 | [diff] [blame] | 250 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 251 | return 0; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 252 | } |
| 253 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 254 | static int enable_flash_cs5530(struct pci_dev *dev, const char *name) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 255 | { |
Uwe Hermann | f4a673b | 2007-06-06 21:35:45 +0000 | [diff] [blame] | 256 | uint8_t reg8; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 257 | |
Uwe Hermann | f4a673b | 2007-06-06 21:35:45 +0000 | [diff] [blame] | 258 | #define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */ |
| 259 | #define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */ |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 260 | |
Uwe Hermann | f4a673b | 2007-06-06 21:35:45 +0000 | [diff] [blame] | 261 | #define LOWER_ROM_ADDRESS_RANGE (1 << 0) |
| 262 | #define ROM_WRITE_ENABLE (1 << 1) |
| 263 | #define UPPER_ROM_ADDRESS_RANGE (1 << 2) |
| 264 | #define BIOS_ROM_POSITIVE_DECODE (1 << 5) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 265 | |
Uwe Hermann | f4a673b | 2007-06-06 21:35:45 +0000 | [diff] [blame] | 266 | /* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and |
| 267 | * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB. |
| 268 | * Make the configured ROM areas writable. |
| 269 | */ |
| 270 | reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG); |
| 271 | reg8 |= LOWER_ROM_ADDRESS_RANGE; |
| 272 | reg8 |= UPPER_ROM_ADDRESS_RANGE; |
| 273 | reg8 |= ROM_WRITE_ENABLE; |
| 274 | pci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 275 | |
Uwe Hermann | f4a673b | 2007-06-06 21:35:45 +0000 | [diff] [blame] | 276 | /* Set positive decode on ROM. */ |
| 277 | reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2); |
| 278 | reg8 |= BIOS_ROM_POSITIVE_DECODE; |
| 279 | pci_write_byte(dev, DECODE_CONTROL_REG2, reg8); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 280 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 281 | return 0; |
| 282 | } |
| 283 | |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 284 | /** |
| 285 | * Geode systems write protect the BIOS via RCONFs (cache settings similar |
| 286 | * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22. Reading and |
| 287 | * writing to MSRs, however requires instructions rdmsr/wrmsr, which are |
| 288 | * ring0 privileged instructions so only the kernel can do the read/write. |
| 289 | * This function, therefore, requires that the msr kernel module be loaded |
| 290 | * to access these instructions from user space using device /dev/cpu/0/msr. |
| 291 | * |
| 292 | * This hard-coded location could have potential problems on SMP machines |
| 293 | * since it assumes cpu0, but it is safe on the Geode which is not SMP. |
| 294 | * |
| 295 | * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL. |
| 296 | * To enable write to NOR Boot flash for the benefit of systems that have such |
| 297 | * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select). |
| 298 | * |
| 299 | * This is probably not portable beyond Linux. |
| 300 | */ |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 301 | static int enable_flash_cs5536(struct pci_dev *dev, const char *name) |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 302 | { |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 303 | #define MSR_RCONF_DEFAULT 0x1808 |
| 304 | #define MSR_NORF_CTL 0x51400018 |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 305 | |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 306 | int fd_msr; |
| 307 | unsigned char buf[8]; |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 308 | |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 309 | fd_msr = open("/dev/cpu/0/msr", O_RDWR); |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 310 | if (!fd_msr) { |
| 311 | perror("open msr"); |
| 312 | return -1; |
| 313 | } |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 314 | |
| 315 | if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) { |
| 316 | perror("lseek64"); |
Mart Raudsepp | 3697ac7 | 2008-02-11 14:32:45 +0000 | [diff] [blame] | 317 | printf("Cannot operate on MSR. Did you run 'modprobe msr'?\n"); |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 318 | close(fd_msr); |
| 319 | return -1; |
| 320 | } |
| 321 | |
| 322 | if (read(fd_msr, buf, 8) != 8) { |
Mart Raudsepp | 3697ac7 | 2008-02-11 14:32:45 +0000 | [diff] [blame] | 323 | perror("read msr"); |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 324 | close(fd_msr); |
| 325 | return -1; |
| 326 | } |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 327 | |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 328 | if (buf[7] != 0x22) { |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 329 | buf[7] &= 0xfb; |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 330 | if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) { |
| 331 | perror("lseek64"); |
| 332 | close(fd_msr); |
| 333 | return -1; |
| 334 | } |
| 335 | |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 336 | if (write(fd_msr, buf, 8) < 0) { |
| 337 | perror("msr write"); |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 338 | close(fd_msr); |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 339 | return -1; |
| 340 | } |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 341 | } |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 342 | |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 343 | if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) { |
| 344 | perror("lseek64"); |
| 345 | close(fd_msr); |
| 346 | return -1; |
| 347 | } |
| 348 | |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 349 | if (read(fd_msr, buf, 8) != 8) { |
| 350 | perror("read msr"); |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 351 | close(fd_msr); |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 352 | return -1; |
| 353 | } |
| 354 | |
| 355 | /* Raise WE_CS3 bit. */ |
| 356 | buf[0] |= 0x08; |
| 357 | |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 358 | if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) { |
| 359 | perror("lseek64"); |
| 360 | close(fd_msr); |
| 361 | return -1; |
| 362 | } |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 363 | if (write(fd_msr, buf, 8) < 0) { |
| 364 | perror("msr write"); |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 365 | close(fd_msr); |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 366 | return -1; |
| 367 | } |
| 368 | |
| 369 | close(fd_msr); |
| 370 | |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 371 | #undef MSR_RCONF_DEFAULT |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 372 | #undef MSR_NORF_CTL |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 373 | return 0; |
| 374 | } |
| 375 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 376 | static int enable_flash_sc1100(struct pci_dev *dev, const char *name) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 377 | { |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 378 | uint8_t new; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 379 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 380 | pci_write_byte(dev, 0x52, 0xee); |
| 381 | |
| 382 | new = pci_read_byte(dev, 0x52); |
| 383 | |
| 384 | if (new != 0xee) { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 385 | printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 386 | return -1; |
| 387 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 388 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 389 | return 0; |
| 390 | } |
| 391 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 392 | static int enable_flash_sis5595(struct pci_dev *dev, const char *name) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 393 | { |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 394 | uint8_t new, newer; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 395 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 396 | new = pci_read_byte(dev, 0x45); |
| 397 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 398 | new &= (~0x20); /* Clear bit 5. */ |
| 399 | new |= 0x4; /* Set bit 2. */ |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 400 | |
| 401 | pci_write_byte(dev, 0x45, new); |
| 402 | |
| 403 | newer = pci_read_byte(dev, 0x45); |
| 404 | if (newer != new) { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 405 | printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 406 | printf("Stuck at 0x%x\n", newer); |
| 407 | return -1; |
| 408 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 409 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 410 | return 0; |
| 411 | } |
| 412 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 413 | static int enable_flash_amd8111(struct pci_dev *dev, const char *name) |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 414 | { |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 415 | uint8_t old, new; |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 416 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 417 | /* Enable decoding at 0xffb00000 to 0xffffffff. */ |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 418 | old = pci_read_byte(dev, 0x43); |
Ollie Lho | d11f361 | 2004-12-07 17:19:04 +0000 | [diff] [blame] | 419 | new = old | 0xC0; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 420 | if (new != old) { |
| 421 | pci_write_byte(dev, 0x43, new); |
| 422 | if (pci_read_byte(dev, 0x43) != new) { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 423 | printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 424 | } |
| 425 | } |
| 426 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 427 | old = pci_read_byte(dev, 0x40); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 428 | new = old | 0x01; |
| 429 | if (new == old) |
| 430 | return 0; |
| 431 | pci_write_byte(dev, 0x40, new); |
| 432 | |
| 433 | if (pci_read_byte(dev, 0x40) != new) { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 434 | printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 435 | return -1; |
| 436 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 437 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 438 | return 0; |
| 439 | } |
| 440 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 441 | static int enable_flash_ck804(struct pci_dev *dev, const char *name) |
Yinghai Lu | 952dfce | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 442 | { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 443 | uint8_t old, new; |
Yinghai Lu | 952dfce | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 444 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 445 | old = pci_read_byte(dev, 0x88); |
| 446 | new = old | 0xc0; |
| 447 | if (new != old) { |
| 448 | pci_write_byte(dev, 0x88, new); |
| 449 | if (pci_read_byte(dev, 0x88) != new) { |
| 450 | printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name); |
| 451 | } |
| 452 | } |
Yinghai Lu | 952dfce | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 453 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 454 | old = pci_read_byte(dev, 0x6d); |
| 455 | new = old | 0x01; |
| 456 | if (new == old) |
| 457 | return 0; |
| 458 | pci_write_byte(dev, 0x6d, new); |
| 459 | |
| 460 | if (pci_read_byte(dev, 0x6d) != new) { |
| 461 | printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name); |
| 462 | return -1; |
| 463 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 464 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 465 | return 0; |
Yinghai Lu | 952dfce | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 466 | } |
| 467 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 468 | /* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */ |
| 469 | static int enable_flash_sb400(struct pci_dev *dev, const char *name) |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 470 | { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 471 | uint8_t tmp; |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 472 | struct pci_filter f; |
| 473 | struct pci_dev *smbusdev; |
| 474 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 475 | /* Look for the SMBus device. */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 476 | pci_filter_init((struct pci_access *)0, &f); |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 477 | f.vendor = 0x1002; |
| 478 | f.device = 0x4372; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 479 | |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 480 | for (smbusdev = pacc->devices; smbusdev; smbusdev = smbusdev->next) { |
| 481 | if (pci_filter_match(&f, smbusdev)) { |
| 482 | break; |
| 483 | } |
| 484 | } |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 485 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 486 | if (!smbusdev) { |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 487 | fprintf(stderr, "ERROR: SMBus device not found. Aborting.\n"); |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 488 | exit(1); |
| 489 | } |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 490 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 491 | /* Enable some SMBus stuff. */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 492 | tmp = pci_read_byte(smbusdev, 0x79); |
| 493 | tmp |= 0x01; |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 494 | pci_write_byte(smbusdev, 0x79, tmp); |
| 495 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 496 | /* Change southbridge. */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 497 | tmp = pci_read_byte(dev, 0x48); |
| 498 | tmp |= 0x21; |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 499 | pci_write_byte(dev, 0x48, tmp); |
| 500 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 501 | /* Now become a bit silly. */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 502 | tmp = inb(0xc6f); |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 503 | outb(tmp, 0xeb); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 504 | outb(tmp, 0xeb); |
| 505 | tmp |= 0x40; |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 506 | outb(tmp, 0xc6f); |
| 507 | outb(tmp, 0xeb); |
| 508 | outb(tmp, 0xeb); |
| 509 | |
| 510 | return 0; |
| 511 | } |
| 512 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 513 | static int enable_flash_mcp55(struct pci_dev *dev, const char *name) |
Yinghai Lu | ca78297 | 2007-01-22 20:21:17 +0000 | [diff] [blame] | 514 | { |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 515 | uint8_t old, new, byte; |
| 516 | uint16_t word; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 517 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 518 | /* Set the 0-16 MB enable bits. */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 519 | byte = pci_read_byte(dev, 0x88); |
| 520 | byte |= 0xff; /* 256K */ |
| 521 | pci_write_byte(dev, 0x88, byte); |
| 522 | byte = pci_read_byte(dev, 0x8c); |
| 523 | byte |= 0xff; /* 1M */ |
| 524 | pci_write_byte(dev, 0x8c, byte); |
| 525 | word = pci_read_word(dev, 0x90); |
Carl-Daniel Hailfinger | dca0ab1 | 2007-10-17 22:30:07 +0000 | [diff] [blame] | 526 | word |= 0x7fff; /* 16M */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 527 | pci_write_word(dev, 0x90, word); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 528 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 529 | old = pci_read_byte(dev, 0x6d); |
| 530 | new = old | 0x01; |
| 531 | if (new == old) |
| 532 | return 0; |
| 533 | pci_write_byte(dev, 0x6d, new); |
Yinghai Lu | ca78297 | 2007-01-22 20:21:17 +0000 | [diff] [blame] | 534 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 535 | if (pci_read_byte(dev, 0x6d) != new) { |
| 536 | printf |
| 537 | ("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", |
| 538 | 0x6d, new, name); |
| 539 | return -1; |
| 540 | } |
Yinghai Lu | ca78297 | 2007-01-22 20:21:17 +0000 | [diff] [blame] | 541 | |
| 542 | return 0; |
Yinghai Lu | ca78297 | 2007-01-22 20:21:17 +0000 | [diff] [blame] | 543 | } |
| 544 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 545 | static int enable_flash_ht1000(struct pci_dev *dev, const char *name) |
Stefan Reinauer | c868b9e | 2007-06-05 10:28:39 +0000 | [diff] [blame] | 546 | { |
Uwe Hermann | e823ee0 | 2007-06-05 15:02:18 +0000 | [diff] [blame] | 547 | uint8_t byte; |
Stefan Reinauer | c868b9e | 2007-06-05 10:28:39 +0000 | [diff] [blame] | 548 | |
Uwe Hermann | e823ee0 | 2007-06-05 15:02:18 +0000 | [diff] [blame] | 549 | /* Set the 4MB enable bit. */ |
Stefan Reinauer | c868b9e | 2007-06-05 10:28:39 +0000 | [diff] [blame] | 550 | byte = pci_read_byte(dev, 0x41); |
| 551 | byte |= 0x0e; |
| 552 | pci_write_byte(dev, 0x41, byte); |
| 553 | |
| 554 | byte = pci_read_byte(dev, 0x43); |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 555 | byte |= (1 << 4); |
Stefan Reinauer | c868b9e | 2007-06-05 10:28:39 +0000 | [diff] [blame] | 556 | pci_write_byte(dev, 0x43, byte); |
| 557 | |
Stefan Reinauer | c868b9e | 2007-06-05 10:28:39 +0000 | [diff] [blame] | 558 | return 0; |
| 559 | } |
| 560 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 561 | typedef struct penable { |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 562 | uint16_t vendor, device; |
| 563 | const char *name; |
| 564 | int (*doit) (struct pci_dev *dev, const char *name); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 565 | } FLASH_ENABLE; |
| 566 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 567 | static const FLASH_ENABLE enables[] = { |
Uwe Hermann | eac1016 | 2008-03-13 18:52:51 +0000 | [diff] [blame] | 568 | {0x1039, 0x0630, "SiS630", enable_flash_sis630}, |
| 569 | {0x8086, 0x7110, "Intel PIIX4/4E/4M", enable_flash_piix4}, |
| 570 | {0x8086, 0x7198, "Intel 440MX", enable_flash_piix4}, |
| 571 | {0x8086, 0x2410, "Intel ICH", enable_flash_ich_4e}, |
| 572 | {0x8086, 0x2420, "Intel ICH0", enable_flash_ich_4e}, |
| 573 | {0x8086, 0x2440, "Intel ICH2", enable_flash_ich_4e}, |
| 574 | {0x8086, 0x244c, "Intel ICH2-M", enable_flash_ich_4e}, |
| 575 | {0x8086, 0x2480, "Intel ICH3-S", enable_flash_ich_4e}, |
| 576 | {0x8086, 0x248c, "Intel ICH3-M", enable_flash_ich_4e}, |
| 577 | {0x8086, 0x24c0, "Intel ICH4/ICH4-L", enable_flash_ich_4e}, |
| 578 | {0x8086, 0x24cc, "Intel ICH4-M", enable_flash_ich_4e}, |
| 579 | {0x8086, 0x24d0, "Intel ICH5/ICH5R", enable_flash_ich_4e}, |
| 580 | {0x8086, 0x2640, "Intel ICH6/ICH6R", enable_flash_ich_dc}, |
| 581 | {0x8086, 0x2641, "Intel ICH6-M", enable_flash_ich_dc}, |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 582 | {0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich_dc_spi}, |
| 583 | {0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich_dc_spi}, |
| 584 | {0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich_dc_spi}, |
| 585 | {0x8086, 0x27bd, "Intel ICH7MDH", enable_flash_ich_dc_spi}, |
| 586 | {0x8086, 0x2810, "Intel ICH8/ICH8R", enable_flash_ich_dc_spi}, |
| 587 | {0x8086, 0x2811, "Intel ICH8M-E", enable_flash_ich_dc_spi}, |
| 588 | {0x8086, 0x2812, "Intel ICH8DH", enable_flash_ich_dc_spi}, |
| 589 | {0x8086, 0x2814, "Intel ICH8DO", enable_flash_ich_dc_spi}, |
| 590 | {0x8086, 0x2815, "Intel ICH8M", enable_flash_ich_dc_spi}, |
Carl-Daniel Hailfinger | b36a071 | 2008-03-18 00:54:10 +0000 | [diff] [blame] | 591 | {0x8086, 0x2912, "Intel ICH9DH", enable_flash_ich_dc_spi}, |
| 592 | {0x8086, 0x2914, "Intel ICH9DO", enable_flash_ich_dc_spi}, |
| 593 | {0x8086, 0x2916, "Intel ICH9R", enable_flash_ich_dc_spi}, |
| 594 | {0x8086, 0x2917, "Intel ICH9M-E", enable_flash_ich_dc_spi}, |
| 595 | {0x8086, 0x2918, "Intel ICH9", enable_flash_ich_dc_spi}, |
| 596 | {0x8086, 0x2919, "Intel ICH9M", enable_flash_ich_dc_spi}, |
Uwe Hermann | eac1016 | 2008-03-13 18:52:51 +0000 | [diff] [blame] | 597 | {0x1106, 0x8231, "VIA VT8231", enable_flash_vt823x}, |
| 598 | {0x1106, 0x3177, "VIA VT8235", enable_flash_vt823x}, |
| 599 | {0x1106, 0x3227, "VIA VT8237", enable_flash_vt823x}, |
| 600 | {0x1106, 0x8324, "VIA CX700", enable_flash_vt823x}, |
| 601 | {0x1106, 0x0686, "VIA VT82C686", enable_flash_amd8111}, |
| 602 | {0x1078, 0x0100, "AMD CS5530(A)", enable_flash_cs5530}, |
| 603 | {0x100b, 0x0510, "AMD SC1100", enable_flash_sc1100}, |
| 604 | {0x1039, 0x0008, "SiS5595", enable_flash_sis5595}, |
| 605 | {0x1022, 0x2080, "AMD CS5536", enable_flash_cs5536}, |
| 606 | {0x1022, 0x7468, "AMD8111", enable_flash_amd8111}, |
| 607 | {0x10B9, 0x1533, "ALi M1533", enable_flash_ali_m1533}, |
| 608 | {0x10de, 0x0050, "NVIDIA CK804", enable_flash_ck804}, /* LPC */ |
| 609 | {0x10de, 0x0051, "NVIDIA CK804", enable_flash_ck804}, /* Pro */ |
| 610 | /* Slave, should not be here, to fix known bug for A01. */ |
| 611 | {0x10de, 0x00d3, "NVIDIA CK804", enable_flash_ck804}, |
| 612 | {0x10de, 0x0260, "NVIDIA MCP51", enable_flash_ck804}, |
| 613 | {0x10de, 0x0261, "NVIDIA MCP51", enable_flash_ck804}, |
| 614 | {0x10de, 0x0262, "NVIDIA MCP51", enable_flash_ck804}, |
| 615 | {0x10de, 0x0263, "NVIDIA MCP51", enable_flash_ck804}, |
| 616 | {0x10de, 0x0360, "NVIDIA MCP55", enable_flash_mcp55}, /* M57SLI*/ |
| 617 | {0x10de, 0x0361, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ |
| 618 | {0x10de, 0x0362, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ |
| 619 | {0x10de, 0x0363, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ |
| 620 | {0x10de, 0x0364, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ |
| 621 | {0x10de, 0x0365, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ |
| 622 | {0x10de, 0x0366, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ |
| 623 | {0x10de, 0x0367, "NVIDIA MCP55", enable_flash_mcp55}, /* Pro */ |
| 624 | {0x1002, 0x4377, "ATI SB400", enable_flash_sb400}, |
| 625 | {0x1166, 0x0205, "Broadcom HT-1000", enable_flash_ht1000}, |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 626 | }; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 627 | |
Uwe Hermann | e5ac164 | 2008-03-12 11:54:51 +0000 | [diff] [blame] | 628 | void print_supported_chipsets(void) |
| 629 | { |
| 630 | int i; |
| 631 | |
| 632 | printf("\nSupported chipsets:\n\n"); |
| 633 | |
| 634 | for (i = 0; i < ARRAY_SIZE(enables); i++) |
| 635 | printf("%s (%04x:%04x)\n", enables[i].name, |
| 636 | enables[i].vendor, enables[i].device); |
| 637 | } |
| 638 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 639 | int chipset_flash_enable(void) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 640 | { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 641 | struct pci_dev *dev = 0; |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 642 | int ret = -2; /* Nothing! */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 643 | int i; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 644 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 645 | /* Now let's try to find the chipset we have... */ |
Uwe Hermann | e5ac164 | 2008-03-12 11:54:51 +0000 | [diff] [blame] | 646 | for (i = 0; i < ARRAY_SIZE(enables); i++) { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 647 | dev = pci_dev_find(enables[i].vendor, enables[i].device); |
| 648 | if (dev) |
| 649 | break; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 650 | } |
| 651 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 652 | if (dev) { |
Uwe Hermann | a502dce | 2007-10-17 23:55:15 +0000 | [diff] [blame] | 653 | printf("Found chipset \"%s\", enabling flash write... ", |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 654 | enables[i].name); |
| 655 | |
| 656 | ret = enables[i].doit(dev, enables[i].name); |
| 657 | if (ret) |
Uwe Hermann | a502dce | 2007-10-17 23:55:15 +0000 | [diff] [blame] | 658 | printf("FAILED!\n"); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 659 | else |
Uwe Hermann | ac30934 | 2007-10-10 17:42:20 +0000 | [diff] [blame] | 660 | printf("OK.\n"); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 661 | } |
| 662 | |
| 663 | return ret; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 664 | } |