blob: bb18b4d65cd3607cf208c0e4ab2d89b099a92561 [file] [log] [blame]
Ollie Lho184a4042005-11-26 21:55:36 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ollie Lho184a4042005-11-26 21:55:36 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
Stefan Reinauer8fa64812009-08-12 09:27:45 +00005 * Copyright (C) 2005-2009 coresystems GmbH
Uwe Hermannd1107642007-08-29 17:52:32 +00006 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00007 * Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger
Adam Jurkowskie4984102009-12-21 15:30:46 +00008 * Copyright (C) 2009 Kontron Modular Computers GmbH
Ollie Lho184a4042005-11-26 21:55:36 +00009 *
Uwe Hermannd1107642007-08-29 17:52:32 +000010 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
Ollie Lho184a4042005-11-26 21:55:36 +000013 *
Uwe Hermannd1107642007-08-29 17:52:32 +000014 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24/*
25 * Contains the chipset specific flash enables.
Ollie Lho184a4042005-11-26 21:55:36 +000026 */
27
Lane Brooksd54958a2007-11-13 16:45:22 +000028#define _LARGEFILE64_SOURCE
29
Ollie Lhocbbf1252004-03-17 22:22:08 +000030#include <stdlib.h>
Uwe Hermanne8ba5382009-05-22 11:37:27 +000031#include <string.h>
Lane Brooksd54958a2007-11-13 16:45:22 +000032#include <sys/types.h>
Carl-Daniel Hailfingerdcef67e2010-06-21 23:20:15 +000033#include <unistd.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000034#include "flash.h"
Stefan Reinauer86de2832006-03-31 11:26:55 +000035
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000036#if defined(__i386__) || defined(__x86_64__)
37
Michael Karcher89bed6d2010-06-13 10:16:12 +000038#define NOT_DONE_YET 1
39
Uwe Hermann372eeb52007-12-04 21:49:06 +000040static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
Luc Verhaegen6b141752007-05-20 16:16:13 +000041{
42 uint8_t tmp;
43
Uwe Hermann372eeb52007-12-04 21:49:06 +000044 /*
45 * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
46 * 0xFFFE0000-0xFFFFFFFF ROM select enable.
47 */
Luc Verhaegen6b141752007-05-20 16:16:13 +000048 tmp = pci_read_byte(dev, 0x47);
49 tmp |= 0x46;
50 pci_write_byte(dev, 0x47, tmp);
51
52 return 0;
53}
54
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000055static int enable_flash_sis85c496(struct pci_dev *dev, const char *name)
56{
57 uint8_t tmp;
58
59 tmp = pci_read_byte(dev, 0xd0);
60 tmp |= 0xf8;
61 pci_write_byte(dev, 0xd0, tmp);
62
63 return 0;
64}
65
66static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name)
67{
68 uint8_t new, newer;
69
70 /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */
71 /* This is 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
72 new = pci_read_byte(dev, 0x40);
73 new &= (~0x04); /* No idea why we clear bit 2. */
74 new |= 0xb; /* 0x3 for some chipsets, bit 7 seems to be don't care. */
75 pci_write_byte(dev, 0x40, new);
76 newer = pci_read_byte(dev, 0x40);
77 if (newer != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +000078 msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
79 msg_pinfo("Stuck at 0x%x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000080 return -1;
81 }
82 return 0;
83}
84
85static struct pci_dev *find_southbridge(uint16_t vendor, const char *name)
86{
87 struct pci_dev *sbdev;
88
89 sbdev = pci_dev_find_vendorclass(vendor, 0x0601);
90 if (!sbdev)
91 sbdev = pci_dev_find_vendorclass(vendor, 0x0680);
92 if (!sbdev)
93 sbdev = pci_dev_find_vendorclass(vendor, 0x0000);
94 if (!sbdev)
Sean Nelson316a29f2010-05-07 20:09:04 +000095 msg_perr("No southbridge found for %s!\n", name);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000096 if (sbdev)
Sean Nelson316a29f2010-05-07 20:09:04 +000097 msg_pdbg("Found southbridge %04x:%04x at %02x:%02x:%01x\n",
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000098 sbdev->vendor_id, sbdev->device_id,
99 sbdev->bus, sbdev->dev, sbdev->func);
100 return sbdev;
101}
102
103static int enable_flash_sis501(struct pci_dev *dev, const char *name)
104{
105 uint8_t tmp;
106 int ret = 0;
107 struct pci_dev *sbdev;
108
109 sbdev = find_southbridge(dev->vendor_id, name);
110 if (!sbdev)
111 return -1;
112
113 ret = enable_flash_sis_mapping(sbdev, name);
114
115 tmp = sio_read(0x22, 0x80);
116 tmp &= (~0x20);
117 tmp |= 0x4;
118 sio_write(0x22, 0x80, tmp);
119
120 tmp = sio_read(0x22, 0x70);
121 tmp &= (~0x20);
122 tmp |= 0x4;
123 sio_write(0x22, 0x70, tmp);
124
125 return ret;
126}
127
128static int enable_flash_sis5511(struct pci_dev *dev, const char *name)
129{
130 uint8_t tmp;
131 int ret = 0;
132 struct pci_dev *sbdev;
133
134 sbdev = find_southbridge(dev->vendor_id, name);
135 if (!sbdev)
136 return -1;
137
138 ret = enable_flash_sis_mapping(sbdev, name);
139
140 tmp = sio_read(0x22, 0x50);
141 tmp &= (~0x20);
142 tmp |= 0x4;
143 sio_write(0x22, 0x50, tmp);
144
145 return ret;
146}
147
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000148static int enable_flash_sis530(struct pci_dev *dev, const char *name)
149{
150 uint8_t new, newer;
151 int ret = 0;
152 struct pci_dev *sbdev;
153
154 sbdev = find_southbridge(dev->vendor_id, name);
155 if (!sbdev)
156 return -1;
157
158 ret = enable_flash_sis_mapping(sbdev, name);
159
160 new = pci_read_byte(sbdev, 0x45);
161 new &= (~0x20);
162 new |= 0x4;
163 pci_write_byte(sbdev, 0x45, new);
Luc Verhaegen9cce2f52010-01-10 15:01:08 +0000164 newer = pci_read_byte(sbdev, 0x45);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000165 if (newer != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000166 msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
167 msg_pinfo("Stuck at 0x%x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000168 ret = -1;
169 }
170
171 return ret;
172}
173
174static int enable_flash_sis540(struct pci_dev *dev, const char *name)
175{
176 uint8_t new, newer;
177 int ret = 0;
178 struct pci_dev *sbdev;
179
180 sbdev = find_southbridge(dev->vendor_id, name);
181 if (!sbdev)
182 return -1;
183
184 ret = enable_flash_sis_mapping(sbdev, name);
185
186 new = pci_read_byte(sbdev, 0x45);
187 new &= (~0x80);
188 new |= 0x40;
189 pci_write_byte(sbdev, 0x45, new);
Luc Verhaegen9cce2f52010-01-10 15:01:08 +0000190 newer = pci_read_byte(sbdev, 0x45);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000191 if (newer != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000192 msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
193 msg_pinfo("Stuck at 0x%x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000194 ret = -1;
195 }
196
197 return ret;
198}
199
Uwe Hermann987942d2006-11-07 11:16:21 +0000200/* Datasheet:
201 * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
202 * - URL: http://www.intel.com/design/intarch/datashts/290562.htm
203 * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
204 * - Order Number: 290562-001
205 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000206static int enable_flash_piix4(struct pci_dev *dev, const char *name)
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000207{
208 uint16_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000209 uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000210
Maciej Pijankaa661e152009-12-08 17:26:24 +0000211 buses_supported = CHIP_BUSTYPE_PARALLEL;
212
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000213 old = pci_read_word(dev, xbcs);
214
215 /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
Uwe Hermanna7e05482007-05-09 10:17:44 +0000216 * FFF00000-FFF7FFFF are forwarded to ISA).
Uwe Hermannc556d322008-10-28 11:50:05 +0000217 * Note: This bit is reserved on PIIX/PIIX3/MPIIX.
Uwe Hermanna7e05482007-05-09 10:17:44 +0000218 * Set bit 7: Extended BIOS Enable (PCI master accesses to
219 * FFF80000-FFFDFFFF are forwarded to ISA).
220 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
221 * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
222 * of 1 Mbyte, or the aliases at the top of 4 Gbyte
223 * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
224 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
225 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
226 */
Uwe Hermannc556d322008-10-28 11:50:05 +0000227 if (dev->device_id == 0x122e || dev->device_id == 0x7000
228 || dev->device_id == 0x1234)
229 new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */
Uwe Hermann87203452008-10-26 18:40:42 +0000230 else
231 new = old | 0x02c4;
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000232
233 if (new == old)
234 return 0;
235
236 pci_write_word(dev, xbcs, new);
237
238 if (pci_read_word(dev, xbcs) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000239 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name);
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000240 return -1;
241 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000242
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000243 return 0;
244}
245
Uwe Hermann372eeb52007-12-04 21:49:06 +0000246/*
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000247 * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet"
248 * http://download.intel.com/design/chipsets/datashts/30701303.pdf
Uwe Hermann372eeb52007-12-04 21:49:06 +0000249 */
250static int enable_flash_ich(struct pci_dev *dev, const char *name,
251 int bios_cntl)
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000252{
Ollie Lho184a4042005-11-26 21:55:36 +0000253 uint8_t old, new;
Stefan Reinauereb366472006-09-06 15:48:48 +0000254
Uwe Hermann372eeb52007-12-04 21:49:06 +0000255 /*
256 * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but
Uwe Hermanna7e05482007-05-09 10:17:44 +0000257 * just treating it as 8 bit wide seems to work fine in practice.
Stefan Reinauereb366472006-09-06 15:48:48 +0000258 */
Stefan Reinauer86de2832006-03-31 11:26:55 +0000259 old = pci_read_byte(dev, bios_cntl);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000260
Sean Nelson316a29f2010-05-07 20:09:04 +0000261 msg_pdbg("\nBIOS Lock Enable: %sabled, ",
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000262 (old & (1 << 1)) ? "en" : "dis");
Sean Nelson316a29f2010-05-07 20:09:04 +0000263 msg_pdbg("BIOS Write Enable: %sabled, ",
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000264 (old & (1 << 0)) ? "en" : "dis");
Sean Nelson316a29f2010-05-07 20:09:04 +0000265 msg_pdbg("BIOS_CNTL is 0x%x\n", old);
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000266
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000267 new = old | 1;
268
269 if (new == old)
270 return 0;
271
Stefan Reinauer86de2832006-03-31 11:26:55 +0000272 pci_write_byte(dev, bios_cntl, new);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000273
Stefan Reinauer86de2832006-03-31 11:26:55 +0000274 if (pci_read_byte(dev, bios_cntl) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000275 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000276 return -1;
277 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000278
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000279 return 0;
280}
281
Uwe Hermann372eeb52007-12-04 21:49:06 +0000282static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000283{
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000284 /*
285 * Note: ICH5 has registers similar to FWH_SEL1, FWH_SEL2 and
286 * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and
287 * FB_DEC_EN2.
288 */
Carl-Daniel Hailfinger7f9922d2010-06-20 11:04:26 +0000289 buses_supported = CHIP_BUSTYPE_FWH;
Stefan Reinauereb366472006-09-06 15:48:48 +0000290 return enable_flash_ich(dev, name, 0x4e);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000291}
292
Uwe Hermann372eeb52007-12-04 21:49:06 +0000293static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000294{
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000295 uint32_t fwh_conf;
296 int i;
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000297 char *idsel = NULL;
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000298 int tmp;
299 int max_decode_fwh_idsel = 0;
300 int max_decode_fwh_decode = 0;
301 int contiguous = 1;
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000302
Carl-Daniel Hailfinger2b6dcb32010-07-08 10:13:37 +0000303 idsel = extract_programmer_param("fwh_idsel");
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000304 if (idsel && strlen(idsel)) {
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000305 fwh_conf = (uint32_t)strtoul(idsel, NULL, 0);
306
307 /* FIXME: Need to undo this on shutdown. */
Sean Nelson316a29f2010-05-07 20:09:04 +0000308 msg_pinfo("\nSetting IDSEL=0x%x for top 16 MB", fwh_conf);
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000309 pci_write_long(dev, 0xd0, fwh_conf);
310 pci_write_word(dev, 0xd4, fwh_conf);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000311 /* FIXME: Decode settings are not changed. */
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000312 } else if (idsel) {
313 msg_perr("Error: idsel= specified, but no number given.\n");
314 free(idsel);
315 /* FIXME: Return failure here once internal_init() starts
316 * to care about the return value of the chipset enable.
317 */
318 exit(1);
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000319 }
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000320 free(idsel);
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000321
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000322 /* Ignore all legacy ranges below 1 MB.
323 * We currently only support flashing the chip which responds to
324 * IDSEL=0. To support IDSEL!=0, flashbase and decode size calculations
325 * have to be adjusted.
326 */
327 /* FWH_SEL1 */
328 fwh_conf = pci_read_long(dev, 0xd0);
329 for (i = 7; i >= 0; i--) {
330 tmp = (fwh_conf >> (i * 4)) & 0xf;
Sean Nelson316a29f2010-05-07 20:09:04 +0000331 msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000332 (0x1ff8 + i) * 0x80000,
333 (0x1ff0 + i) * 0x80000,
334 tmp);
335 if ((tmp == 0) && contiguous) {
336 max_decode_fwh_idsel = (8 - i) * 0x80000;
337 } else {
338 contiguous = 0;
339 }
340 }
341 /* FWH_SEL2 */
342 fwh_conf = pci_read_word(dev, 0xd4);
343 for (i = 3; i >= 0; i--) {
344 tmp = (fwh_conf >> (i * 4)) & 0xf;
Sean Nelson316a29f2010-05-07 20:09:04 +0000345 msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000346 (0xff4 + i) * 0x100000,
347 (0xff0 + i) * 0x100000,
348 tmp);
349 if ((tmp == 0) && contiguous) {
350 max_decode_fwh_idsel = (8 - i) * 0x100000;
351 } else {
352 contiguous = 0;
353 }
354 }
355 contiguous = 1;
356 /* FWH_DEC_EN1 */
357 fwh_conf = pci_read_word(dev, 0xd8);
358 for (i = 7; i >= 0; i--) {
359 tmp = (fwh_conf >> (i + 0x8)) & 0x1;
Sean Nelson316a29f2010-05-07 20:09:04 +0000360 msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled",
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000361 (0x1ff8 + i) * 0x80000,
362 (0x1ff0 + i) * 0x80000,
363 tmp ? "en" : "dis");
Michael Karcher96785392010-01-03 15:09:17 +0000364 if ((tmp == 1) && contiguous) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000365 max_decode_fwh_decode = (8 - i) * 0x80000;
366 } else {
367 contiguous = 0;
368 }
369 }
370 for (i = 3; i >= 0; i--) {
371 tmp = (fwh_conf >> i) & 0x1;
Sean Nelson316a29f2010-05-07 20:09:04 +0000372 msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled",
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000373 (0xff4 + i) * 0x100000,
374 (0xff0 + i) * 0x100000,
375 tmp ? "en" : "dis");
Michael Karcher96785392010-01-03 15:09:17 +0000376 if ((tmp == 1) && contiguous) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000377 max_decode_fwh_decode = (8 - i) * 0x100000;
378 } else {
379 contiguous = 0;
380 }
381 }
382 max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode);
Sean Nelson316a29f2010-05-07 20:09:04 +0000383 msg_pdbg("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000384
385 /* If we're called by enable_flash_ich_dc_spi, it will override
386 * buses_supported anyway.
387 */
388 buses_supported = CHIP_BUSTYPE_FWH;
Stefan Reinauereb366472006-09-06 15:48:48 +0000389 return enable_flash_ich(dev, name, 0xdc);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000390}
391
Adam Jurkowskie4984102009-12-21 15:30:46 +0000392static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
393{
394 uint16_t old, new;
395 int err;
396
397 if ((err = enable_flash_ich(dev, name, 0xd8)) != 0)
398 return err;
399
400 old = pci_read_byte(dev, 0xd9);
Sean Nelson316a29f2010-05-07 20:09:04 +0000401 msg_pdbg("BIOS Prefetch Enable: %sabled, ",
Adam Jurkowskie4984102009-12-21 15:30:46 +0000402 (old & 1) ? "en" : "dis");
403 new = old & ~1;
404
405 if (new != old)
406 pci_write_byte(dev, 0xd9, new);
407
Carl-Daniel Hailfinger7f9922d2010-06-20 11:04:26 +0000408 buses_supported = CHIP_BUSTYPE_FWH;
Adam Jurkowskie4984102009-12-21 15:30:46 +0000409 return 0;
410}
411
412
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000413#define ICH_STRAP_RSVD 0x00
414#define ICH_STRAP_SPI 0x01
415#define ICH_STRAP_PCI 0x02
416#define ICH_STRAP_LPC 0x03
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000417
Uwe Hermann394131e2008-10-18 21:14:13 +0000418static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
419{
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000420 /* Do we really need no write enable? */
Michael Karchera4448d92010-07-22 18:04:15 +0000421 return via_init_spi(dev);
Joshua Roysf93b36a2010-07-01 17:45:54 +0000422}
423
Uwe Hermann394131e2008-10-18 21:14:13 +0000424static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
425 int ich_generation)
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000426{
Michael Karchera4448d92010-07-22 18:04:15 +0000427 int ret;
428 uint8_t bbs, buc;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000429 uint32_t tmp, gcs;
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000430 void *rcrb;
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000431 //TODO: These names are incorrect for EP80579. For that, the solution would look like the commented line
432 //static const char *straps_names[] = {"SPI", "reserved", "reserved", "LPC" };
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000433 static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" };
Uwe Hermann394131e2008-10-18 21:14:13 +0000434
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000435 /* Enable Flash Writes */
436 ret = enable_flash_ich_dc(dev, name);
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000437
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000438 /* Get physical address of Root Complex Register Block */
439 tmp = pci_read_long(dev, 0xf0) & 0xffffc000;
Sean Nelson316a29f2010-05-07 20:09:04 +0000440 msg_pdbg("\nRoot Complex Register Block address = 0x%x\n", tmp);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000441
442 /* Map RCBA to virtual memory */
Stefan Reinauer0593f212009-01-26 01:10:48 +0000443 rcrb = physmap("ICH RCRB", tmp, 0x4000);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000444
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000445 gcs = mmio_readl(rcrb + 0x3410);
Sean Nelson316a29f2010-05-07 20:09:04 +0000446 msg_pdbg("GCS = 0x%x: ", gcs);
447 msg_pdbg("BIOS Interface Lock-Down: %sabled, ",
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000448 (gcs & 0x1) ? "en" : "dis");
449 bbs = (gcs >> 10) & 0x3;
Sean Nelson316a29f2010-05-07 20:09:04 +0000450 msg_pdbg("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000451
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000452 buc = mmio_readb(rcrb + 0x3414);
Sean Nelson316a29f2010-05-07 20:09:04 +0000453 msg_pdbg("Top Swap : %s\n",
Uwe Hermann394131e2008-10-18 21:14:13 +0000454 (buc & 1) ? "enabled (A16 inverted)" : "not enabled");
Stefan Reinauera9424d52008-06-27 16:28:34 +0000455
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000456 /* It seems the ICH7 does not support SPI and LPC chips at the same
457 * time. At least not with our current code. So we prevent searching
458 * on ICH7 when the southbridge is strapped to LPC
459 */
460
Michael Karchera4448d92010-07-22 18:04:15 +0000461 buses_supported = CHIP_BUSTYPE_FWH;
462 if (ich_generation == 7) {
463 if(bbs == ICH_STRAP_LPC) {
464 /* No further SPI initialization required */
465 return ret;
466 }
467 else
468 /* Disable LPC/FWH if strapped to PCI or SPI */
469 buses_supported = 0;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000470 }
471
Michael Karchera4448d92010-07-22 18:04:15 +0000472 /* this adds CHIP_BUSTYPE_SPI */
473 if (ich_init_spi(dev, tmp, rcrb, ich_generation) != 0) {
474 if (!ret)
475 ret = ERROR_NONFATAL;
476 }
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000477
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000478 return ret;
479}
Stefan Reinauera9424d52008-06-27 16:28:34 +0000480
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000481static int enable_flash_ich7(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000482{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000483 return enable_flash_ich_dc_spi(dev, name, 7);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000484}
485
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000486static int enable_flash_ich8(struct pci_dev *dev, const char *name)
487{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000488 return enable_flash_ich_dc_spi(dev, name, 8);
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000489}
490
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000491static int enable_flash_ich9(struct pci_dev *dev, const char *name)
492{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000493 return enable_flash_ich_dc_spi(dev, name, 9);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000494}
495
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000496static int enable_flash_ich10(struct pci_dev *dev, const char *name)
497{
498 return enable_flash_ich_dc_spi(dev, name, 10);
499}
500
Michael Karcher89bed6d2010-06-13 10:16:12 +0000501static void via_do_byte_merge(void * arg)
502{
503 struct pci_dev * dev = arg;
504 uint8_t val;
505
506 msg_pdbg("Re-enabling byte merging\n");
507 val = pci_read_byte(dev, 0x71);
508 val |= 0x40;
509 pci_write_byte(dev, 0x71, val);
510}
511
512static int via_no_byte_merge(struct pci_dev *dev, const char *name)
513{
514 uint8_t val;
515
516 val = pci_read_byte(dev, 0x71);
517 if (val & 0x40)
518 {
519 msg_pdbg("Disabling byte merging\n");
520 val &= ~0x40;
521 pci_write_byte(dev, 0x71, val);
522 register_shutdown(via_do_byte_merge, dev);
523 }
524 return NOT_DONE_YET; /* need to find south bridge, too */
525}
526
Uwe Hermann372eeb52007-12-04 21:49:06 +0000527static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000528{
Ollie Lho184a4042005-11-26 21:55:36 +0000529 uint8_t val;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000530
Uwe Hermann394131e2008-10-18 21:14:13 +0000531 /* enable ROM decode range (1MB) FFC00000 - FFFFFFFF */
Bari Ari9477c4e2008-04-29 13:46:38 +0000532 pci_write_byte(dev, 0x41, 0x7f);
533
Uwe Hermannffec5f32007-08-23 16:08:21 +0000534 /* ROM write enable */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000535 val = pci_read_byte(dev, 0x40);
536 val |= 0x10;
537 pci_write_byte(dev, 0x40, val);
538
539 if (pci_read_byte(dev, 0x40) != val) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000540 msg_pinfo("\nWARNING: Failed to enable flash write on \"%s\"\n",
Uwe Hermanna7e05482007-05-09 10:17:44 +0000541 name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000542 return -1;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000543 }
Luc Verhaegen6382b442007-03-02 22:16:38 +0000544
Luc Verhaegen73d21192009-12-23 00:54:26 +0000545 if (dev->device_id == 0x3227) { /* VT8237R */
546 /* All memory cycles, not just ROM ones, go to LPC. */
547 val = pci_read_byte(dev, 0x59);
548 val &= ~0x80;
549 pci_write_byte(dev, 0x59, val);
550 }
551
Uwe Hermanna7e05482007-05-09 10:17:44 +0000552 return 0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000553}
554
Uwe Hermann372eeb52007-12-04 21:49:06 +0000555static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000556{
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000557 uint8_t reg8;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000558
Uwe Hermann394131e2008-10-18 21:14:13 +0000559#define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
560#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000561#define CS5530_RESET_CONTROL_REG 0x44 /* F0 index 0x44 */
562#define CS5530_USB_SHADOW_REG 0x43 /* F0 index 0x43 */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000563
Uwe Hermann394131e2008-10-18 21:14:13 +0000564#define LOWER_ROM_ADDRESS_RANGE (1 << 0)
565#define ROM_WRITE_ENABLE (1 << 1)
566#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
567#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000568#define CS5530_ISA_MASTER (1 << 7)
569#define CS5530_ENABLE_SA2320 (1 << 2)
570#define CS5530_ENABLE_SA20 (1 << 6)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000571
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000572 buses_supported = CHIP_BUSTYPE_PARALLEL;
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000573 /* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and
574 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB.
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000575 * FIXME: Should we really touch the low mapping below 1 MB? Flashrom
576 * ignores that region completely.
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000577 * Make the configured ROM areas writable.
578 */
579 reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
580 reg8 |= LOWER_ROM_ADDRESS_RANGE;
581 reg8 |= UPPER_ROM_ADDRESS_RANGE;
582 reg8 |= ROM_WRITE_ENABLE;
583 pci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000584
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000585 /* Set positive decode on ROM. */
586 reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
587 reg8 |= BIOS_ROM_POSITIVE_DECODE;
588 pci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000589
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000590 reg8 = pci_read_byte(dev, CS5530_RESET_CONTROL_REG);
591 if (reg8 & CS5530_ISA_MASTER) {
592 /* We have A0-A23 available. */
593 max_rom_decode.parallel = 16 * 1024 * 1024;
594 } else {
595 reg8 = pci_read_byte(dev, CS5530_USB_SHADOW_REG);
596 if (reg8 & CS5530_ENABLE_SA2320) {
597 /* We have A0-19, A20-A23 available. */
598 max_rom_decode.parallel = 16 * 1024 * 1024;
599 } else if (reg8 & CS5530_ENABLE_SA20) {
600 /* We have A0-19, A20 available. */
601 max_rom_decode.parallel = 2 * 1024 * 1024;
602 } else {
603 /* A20 and above are not active. */
604 max_rom_decode.parallel = 1024 * 1024;
605 }
606 }
607
Ollie Lhocbbf1252004-03-17 22:22:08 +0000608 return 0;
609}
610
Mart Raudseppe1344da2008-02-08 10:10:57 +0000611/**
612 * Geode systems write protect the BIOS via RCONFs (cache settings similar
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000613 * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22.
Mart Raudseppe1344da2008-02-08 10:10:57 +0000614 *
615 * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
616 * To enable write to NOR Boot flash for the benefit of systems that have such
617 * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
Mart Raudseppe1344da2008-02-08 10:10:57 +0000618 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000619static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
Lane Brooksd54958a2007-11-13 16:45:22 +0000620{
Uwe Hermann394131e2008-10-18 21:14:13 +0000621#define MSR_RCONF_DEFAULT 0x1808
622#define MSR_NORF_CTL 0x51400018
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000623
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000624 msr_t msr;
Lane Brooksd54958a2007-11-13 16:45:22 +0000625
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000626 /* Geode only has a single core */
627 if (setup_cpu_msr(0))
Lane Brooksd54958a2007-11-13 16:45:22 +0000628 return -1;
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000629
630 msr = rdmsr(MSR_RCONF_DEFAULT);
631 if ((msr.hi >> 24) != 0x22) {
632 msr.hi &= 0xfbffffff;
633 wrmsr(MSR_RCONF_DEFAULT, msr);
Lane Brooksd54958a2007-11-13 16:45:22 +0000634 }
Mart Raudseppe1344da2008-02-08 10:10:57 +0000635
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000636 msr = rdmsr(MSR_NORF_CTL);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000637 /* Raise WE_CS3 bit. */
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000638 msr.lo |= 0x08;
639 wrmsr(MSR_NORF_CTL, msr);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000640
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000641 cleanup_cpu_msr();
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000642
Uwe Hermann394131e2008-10-18 21:14:13 +0000643#undef MSR_RCONF_DEFAULT
644#undef MSR_NORF_CTL
Lane Brooksd54958a2007-11-13 16:45:22 +0000645 return 0;
646}
647
Uwe Hermann372eeb52007-12-04 21:49:06 +0000648static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000649{
Ollie Lho184a4042005-11-26 21:55:36 +0000650 uint8_t new;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000651
Ollie Lhocbbf1252004-03-17 22:22:08 +0000652 pci_write_byte(dev, 0x52, 0xee);
653
654 new = pci_read_byte(dev, 0x52);
655
656 if (new != 0xee) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000657 msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000658 return -1;
659 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000660
Ollie Lhocbbf1252004-03-17 22:22:08 +0000661 return 0;
662}
663
Uwe Hermann190f8492008-10-25 18:03:50 +0000664/* Works for AMD-8111, VIA VT82C586A/B, VIA VT82C686A/B. */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000665static int enable_flash_amd8111(struct pci_dev *dev, const char *name)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000666{
Ollie Lho184a4042005-11-26 21:55:36 +0000667 uint8_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000668
Uwe Hermann372eeb52007-12-04 21:49:06 +0000669 /* Enable decoding at 0xffb00000 to 0xffffffff. */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000670 old = pci_read_byte(dev, 0x43);
Ollie Lhod11f3612004-12-07 17:19:04 +0000671 new = old | 0xC0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000672 if (new != old) {
673 pci_write_byte(dev, 0x43, new);
674 if (pci_read_byte(dev, 0x43) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000675 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000676 }
677 }
678
Uwe Hermann190f8492008-10-25 18:03:50 +0000679 /* Enable 'ROM write' bit. */
Ollie Lho761bf1b2004-03-20 16:46:10 +0000680 old = pci_read_byte(dev, 0x40);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000681 new = old | 0x01;
682 if (new == old)
683 return 0;
684 pci_write_byte(dev, 0x40, new);
685
686 if (pci_read_byte(dev, 0x40) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000687 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000688 return -1;
689 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000690
Ollie Lhocbbf1252004-03-17 22:22:08 +0000691 return 0;
692}
693
Marc Jones3af487d2008-10-15 17:50:29 +0000694static int enable_flash_sb600(struct pci_dev *dev, const char *name)
695{
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000696 uint32_t tmp, prot;
Marc Jones3af487d2008-10-15 17:50:29 +0000697 uint8_t reg;
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000698 struct pci_dev *smbus_dev;
699 int has_spi = 1;
Marc Jones3af487d2008-10-15 17:50:29 +0000700
Jason Wanga3f04be2008-11-28 21:36:51 +0000701 /* Clear ROM protect 0-3. */
702 for (reg = 0x50; reg < 0x60; reg += 4) {
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000703 prot = pci_read_long(dev, reg);
704 /* No protection flags for this region?*/
705 if ((prot & 0x3) == 0)
706 continue;
Sean Nelson316a29f2010-05-07 20:09:04 +0000707 msg_pinfo("SB600 %s%sprotected from %u to %u\n",
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000708 (prot & 0x1) ? "write " : "",
709 (prot & 0x2) ? "read " : "",
710 (prot & 0xfffffc00),
711 (prot & 0xfffffc00) + ((prot & 0x3ff) << 8));
712 prot &= 0xfffffffc;
713 pci_write_byte(dev, reg, prot);
714 prot = pci_read_long(dev, reg);
Carl-Daniel Hailfinger9bb88ac2009-05-06 13:51:44 +0000715 if (prot & 0x3)
Sean Nelson316a29f2010-05-07 20:09:04 +0000716 msg_perr("SB600 %s%sunprotect failed from %u to %u\n",
Carl-Daniel Hailfinger9bb88ac2009-05-06 13:51:44 +0000717 (prot & 0x1) ? "write " : "",
718 (prot & 0x2) ? "read " : "",
719 (prot & 0xfffffc00),
720 (prot & 0xfffffc00) + ((prot & 0x3ff) << 8));
Jason Wanga3f04be2008-11-28 21:36:51 +0000721 }
722
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000723 /* Read SPI_BaseAddr */
724 tmp = pci_read_long(dev, 0xa0);
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000725 tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */
Sean Nelson316a29f2010-05-07 20:09:04 +0000726 msg_pdbg("SPI base address is at 0x%x\n", tmp);
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000727
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000728 /* If the BAR has address 0, it is unlikely SPI is used. */
729 if (!tmp)
730 has_spi = 0;
731
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000732 if (has_spi) {
733 /* Physical memory has to be mapped at page (4k) boundaries. */
734 sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000,
735 0x1000);
736 /* The low bits of the SPI base address are used as offset into
737 * the mapped page.
738 */
739 sb600_spibar += tmp & 0xfff;
740
741 tmp = pci_read_long(dev, 0xa0);
Sean Nelson316a29f2010-05-07 20:09:04 +0000742 msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, "
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000743 "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1,
744 (tmp & 0x4) >> 2);
745 tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2;
Sean Nelson316a29f2010-05-07 20:09:04 +0000746 msg_pdbg("PrefetchEnSPIFromIMC=%i, ", tmp);
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000747
748 tmp = pci_read_byte(dev, 0xbb);
Sean Nelson316a29f2010-05-07 20:09:04 +0000749 msg_pdbg("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n",
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000750 tmp & 0x1, (tmp & 0x20) >> 5);
751 tmp = mmio_readl(sb600_spibar);
Sean Nelson316a29f2010-05-07 20:09:04 +0000752 msg_pdbg("SpiArbEnable=%i, SpiAccessMacRomEn=%i, "
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000753 "SpiHostAccessRomEn=%i, ArbWaitCount=%i, "
754 "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n",
755 (tmp >> 19) & 0x1, (tmp >> 22) & 0x1,
756 (tmp >> 23) & 0x1, (tmp >> 24) & 0x7,
757 (tmp >> 27) & 0x1, (tmp >> 28) & 0x1);
758 }
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000759
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000760 /* Look for the SMBus device. */
761 smbus_dev = pci_dev_find(0x1002, 0x4385);
762
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000763 if (has_spi && !smbus_dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000764 msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n");
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000765 has_spi = 0;
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000766 }
767 if (has_spi) {
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000768 /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */
769 /* GPIO11/SPI_DO and GPIO12/SPI_DI status */
770 reg = pci_read_byte(smbus_dev, 0xAB);
771 reg &= 0xC0;
Sean Nelson316a29f2010-05-07 20:09:04 +0000772 msg_pdbg("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO");
773 msg_pdbg("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI");
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000774 if (reg != 0x00)
775 has_spi = 0;
776 /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */
777 reg = pci_read_byte(smbus_dev, 0x83);
778 reg &= 0xC0;
Sean Nelson316a29f2010-05-07 20:09:04 +0000779 msg_pdbg("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD");
780 msg_pdbg("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000781 /* SPI_HOLD is not used on all boards, filter it out. */
782 if ((reg & 0x80) != 0x00)
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000783 has_spi = 0;
784 /* GPIO47/SPI_CLK status */
785 reg = pci_read_byte(smbus_dev, 0xA7);
786 reg &= 0x40;
Sean Nelson316a29f2010-05-07 20:09:04 +0000787 msg_pdbg("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK");
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000788 if (reg != 0x00)
789 has_spi = 0;
790 }
791
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000792 buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH;
793 if (has_spi) {
794 buses_supported |= CHIP_BUSTYPE_SPI;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000795 spi_controller = SPI_CONTROLLER_SB600;
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000796 }
Jason Wanga3f04be2008-11-28 21:36:51 +0000797
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000798 /* Read ROM strap override register. */
799 OUTB(0x8f, 0xcd6);
800 reg = INB(0xcd7);
801 reg &= 0x0e;
Sean Nelson316a29f2010-05-07 20:09:04 +0000802 msg_pdbg("ROM strap override is %sactive", (reg & 0x02) ? "" : "not ");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000803 if (reg & 0x02) {
804 switch ((reg & 0x0c) >> 2) {
805 case 0x00:
Sean Nelson316a29f2010-05-07 20:09:04 +0000806 msg_pdbg(": LPC");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000807 break;
808 case 0x01:
Sean Nelson316a29f2010-05-07 20:09:04 +0000809 msg_pdbg(": PCI");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000810 break;
811 case 0x02:
Sean Nelson316a29f2010-05-07 20:09:04 +0000812 msg_pdbg(": FWH");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000813 break;
814 case 0x03:
Sean Nelson316a29f2010-05-07 20:09:04 +0000815 msg_pdbg(": SPI");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000816 break;
817 }
818 }
Sean Nelson316a29f2010-05-07 20:09:04 +0000819 msg_pdbg("\n");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000820
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000821 /* Force enable SPI ROM in SB600 PM register.
822 * If we enable SPI ROM here, we have to disable it after we leave.
Zheng Bao284a6002009-05-04 22:33:50 +0000823 * But how can we know which ROM we are going to handle? So we have
824 * to trade off. We only access LPC ROM if we boot via LPC ROM. And
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000825 * only SPI ROM if we boot via SPI ROM. If you want to access SPI on
826 * boards with LPC straps, you have to use the code below.
Zheng Bao284a6002009-05-04 22:33:50 +0000827 */
828 /*
Jason Wanga3f04be2008-11-28 21:36:51 +0000829 OUTB(0x8f, 0xcd6);
830 OUTB(0x0e, 0xcd7);
Zheng Bao284a6002009-05-04 22:33:50 +0000831 */
Marc Jones3af487d2008-10-15 17:50:29 +0000832
833 return 0;
834}
835
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000836static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name)
837{
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000838 uint8_t tmp;
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000839
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000840 pci_write_byte(dev, 0x92, 0);
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000841
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000842 tmp = pci_read_byte(dev, 0x6d);
843 tmp |= 0x01;
844 pci_write_byte(dev, 0x6d, tmp);
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000845
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000846 return 0;
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000847}
848
Uwe Hermann372eeb52007-12-04 21:49:06 +0000849static int enable_flash_ck804(struct pci_dev *dev, const char *name)
Yinghai Lu952dfce2005-07-06 17:13:46 +0000850{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000851 uint8_t old, new;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000852
Uwe Hermanna7e05482007-05-09 10:17:44 +0000853 old = pci_read_byte(dev, 0x88);
854 new = old | 0xc0;
855 if (new != old) {
856 pci_write_byte(dev, 0x88, new);
857 if (pci_read_byte(dev, 0x88) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000858 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000859 }
860 }
Yinghai Lu952dfce2005-07-06 17:13:46 +0000861
Uwe Hermanna7e05482007-05-09 10:17:44 +0000862 old = pci_read_byte(dev, 0x6d);
863 new = old | 0x01;
864 if (new == old)
865 return 0;
866 pci_write_byte(dev, 0x6d, new);
867
868 if (pci_read_byte(dev, 0x6d) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000869 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000870 return -1;
871 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000872
Uwe Hermanna7e05482007-05-09 10:17:44 +0000873 return 0;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000874}
875
Uwe Hermann372eeb52007-12-04 21:49:06 +0000876/* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
877static int enable_flash_sb400(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000878{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000879 uint8_t tmp;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000880 struct pci_dev *smbusdev;
881
Uwe Hermann372eeb52007-12-04 21:49:06 +0000882 /* Look for the SMBus device. */
Carl-Daniel Hailfingerf6e3efb2009-05-06 00:35:31 +0000883 smbusdev = pci_dev_find(0x1002, 0x4372);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000884
Uwe Hermanna7e05482007-05-09 10:17:44 +0000885 if (!smbusdev) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000886 msg_perr("ERROR: SMBus device not found. Aborting.\n");
Stefan Reinauer86de2832006-03-31 11:26:55 +0000887 exit(1);
888 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000889
Uwe Hermann372eeb52007-12-04 21:49:06 +0000890 /* Enable some SMBus stuff. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000891 tmp = pci_read_byte(smbusdev, 0x79);
892 tmp |= 0x01;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000893 pci_write_byte(smbusdev, 0x79, tmp);
894
Uwe Hermann372eeb52007-12-04 21:49:06 +0000895 /* Change southbridge. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000896 tmp = pci_read_byte(dev, 0x48);
897 tmp |= 0x21;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000898 pci_write_byte(dev, 0x48, tmp);
899
Uwe Hermann372eeb52007-12-04 21:49:06 +0000900 /* Now become a bit silly. */
Andriy Gapon65c1b862008-05-22 13:22:45 +0000901 tmp = INB(0xc6f);
902 OUTB(tmp, 0xeb);
903 OUTB(tmp, 0xeb);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000904 tmp |= 0x40;
Andriy Gapon65c1b862008-05-22 13:22:45 +0000905 OUTB(tmp, 0xc6f);
906 OUTB(tmp, 0xeb);
907 OUTB(tmp, 0xeb);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000908
909 return 0;
910}
911
Uwe Hermann372eeb52007-12-04 21:49:06 +0000912static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
Yinghai Luca782972007-01-22 20:21:17 +0000913{
Michael Karcher4e2fb0e2010-01-12 23:29:26 +0000914 uint8_t old, new, val;
915 uint16_t wordval;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000916
Uwe Hermann372eeb52007-12-04 21:49:06 +0000917 /* Set the 0-16 MB enable bits. */
Michael Karcher4e2fb0e2010-01-12 23:29:26 +0000918 val = pci_read_byte(dev, 0x88);
919 val |= 0xff; /* 256K */
920 pci_write_byte(dev, 0x88, val);
921 val = pci_read_byte(dev, 0x8c);
922 val |= 0xff; /* 1M */
923 pci_write_byte(dev, 0x8c, val);
924 wordval = pci_read_word(dev, 0x90);
925 wordval |= 0x7fff; /* 16M */
926 pci_write_word(dev, 0x90, wordval);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000927
Uwe Hermanna7e05482007-05-09 10:17:44 +0000928 old = pci_read_byte(dev, 0x6d);
929 new = old | 0x01;
930 if (new == old)
931 return 0;
932 pci_write_byte(dev, 0x6d, new);
Yinghai Luca782972007-01-22 20:21:17 +0000933
Uwe Hermanna7e05482007-05-09 10:17:44 +0000934 if (pci_read_byte(dev, 0x6d) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000935 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000936 return -1;
937 }
Yinghai Luca782972007-01-22 20:21:17 +0000938
939 return 0;
Yinghai Luca782972007-01-22 20:21:17 +0000940}
941
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000942/* This is a shot in the dark. Even if the code is totally bogus for some
943 * chipsets, users will at least start to send in reports.
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000944 */
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000945static int enable_flash_mcp6x_7x_common(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000946{
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000947 int ret = 0;
Michael Karchercfa674f2010-02-25 11:38:23 +0000948 uint8_t val;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000949 uint16_t status;
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000950 char *busname;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000951 uint32_t mcp_spibaraddr;
952 void *mcp_spibar;
953 struct pci_dev *smbusdev;
954
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000955 msg_pinfo("This chipset is not really supported yet. Guesswork...\n");
956
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000957 /* dev is the ISA bridge. No idea what the stuff below does. */
Michael Karchercfa674f2010-02-25 11:38:23 +0000958 val = pci_read_byte(dev, 0x8a);
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000959 msg_pdbg("ISA/LPC bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5 "
Michael Karchercfa674f2010-02-25 11:38:23 +0000960 "is %i\n", val, (val >> 6) & 0x1, (val >> 5) & 0x1);
961 switch ((val >> 5) & 0x3) {
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000962 case 0x0:
963 buses_supported = CHIP_BUSTYPE_LPC;
964 break;
965 case 0x2:
966 buses_supported = CHIP_BUSTYPE_SPI;
967 break;
968 default:
969 buses_supported = CHIP_BUSTYPE_UNKNOWN;
970 break;
971 }
972 busname = flashbuses_to_text(buses_supported);
973 msg_pdbg("Guessed flash bus type is %s\n", busname);
974 free(busname);
975
976 /* Force enable SPI and disable LPC? Not a good idea. */
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000977#if 0
Michael Karchercfa674f2010-02-25 11:38:23 +0000978 val |= (1 << 6);
979 val &= ~(1 << 5);
980 pci_write_byte(dev, 0x8a, val);
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000981#endif
982
983 /* Look for the SMBus device (SMBus PCI class) */
984 smbusdev = pci_dev_find_vendorclass(0x10de, 0x0c05);
985 if (!smbusdev) {
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000986 if (buses_supported & CHIP_BUSTYPE_SPI) {
987 msg_perr("ERROR: SMBus device not found. Not enabling "
988 "SPI.\n");
989 buses_supported &= ~CHIP_BUSTYPE_SPI;
990 ret = 1;
991 } else {
992 msg_pinfo("Odd. SMBus device not found.\n");
993 }
994 goto out_msg;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000995 }
996 msg_pdbg("Found SMBus device %04x:%04x at %02x:%02x:%01x\n",
997 smbusdev->vendor_id, smbusdev->device_id,
998 smbusdev->bus, smbusdev->dev, smbusdev->func);
999
1000 /* Locate the BAR where the SPI interface lives. */
1001 mcp_spibaraddr = pci_read_long(smbusdev, 0x74);
1002 msg_pdbg("SPI BAR is at 0x%08x, ", mcp_spibaraddr);
1003 /* We hope this has native alignment. We know the SPI interface (well,
1004 * a set of GPIOs that is connected to SPI flash) is at offset 0x530,
1005 * so we expect a size of at least 0x800. Clear the lower bits.
1006 * It is entirely possible that the BAR is 64k big and the low bits are
1007 * reserved for an entirely different purpose.
1008 */
1009 mcp_spibaraddr &= ~0x7ff;
1010 msg_pdbg("after clearing low bits BAR is at 0x%08x\n", mcp_spibaraddr);
1011
1012 /* Accessing a NULL pointer BAR is evil. Don't do it. */
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001013 if (mcp_spibaraddr && (buses_supported == CHIP_BUSTYPE_SPI)) {
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001014 /* Map the BAR. Bytewise/wordwise access at 0x530 and 0x540. */
1015 mcp_spibar = physmap("MCP67 SPI", mcp_spibaraddr, 0x544);
1016
1017/* Guessed. If this is correct, migrate to a separate MCP67 SPI driver. */
1018#define MCP67_SPI_CS (1 << 1)
1019#define MCP67_SPI_SCK (1 << 2)
1020#define MCP67_SPI_MOSI (1 << 3)
1021#define MCP67_SPI_MISO (1 << 4)
1022#define MCP67_SPI_ENABLE (1 << 0)
1023#define MCP67_SPI_IDLE (1 << 8)
1024
1025 status = mmio_readw(mcp_spibar + 0x530);
1026 msg_pdbg("SPI control is 0x%04x, enable=%i, idle=%i\n",
1027 status, status & 0x1, (status >> 8) & 0x1);
1028 /* FIXME: Remove the physunmap once the SPI driver exists. */
1029 physunmap(mcp_spibar, 0x544);
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001030 } else if (!mcp_spibaraddr && (buses_supported & CHIP_BUSTYPE_SPI)) {
1031 msg_pdbg("Strange. MCP SPI BAR is invalid.\n");
1032 buses_supported &= ~CHIP_BUSTYPE_SPI;
1033 ret = 1;
1034 } else if (mcp_spibaraddr && !(buses_supported & CHIP_BUSTYPE_SPI)) {
1035 msg_pdbg("Strange. MCP SPI BAR is valid, but chipset apparently"
1036 " doesn't have SPI enabled.\n");
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001037 } else {
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001038 msg_pdbg("MCP SPI is not used.\n");
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001039 }
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001040out_msg:
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001041 msg_pinfo("Please send the output of \"flashrom -V\" to "
1042 "flashrom@flashrom.org to help us finish support for your "
1043 "chipset. Thanks.\n");
1044
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001045 return ret;
1046}
1047
1048/**
1049 * The MCP61/MCP67 code is guesswork based on cleanroom reverse engineering.
1050 * Due to that, it only reads info and doesn't change any settings.
1051 * It is assumed that LPC chips need the MCP55 code and SPI chips need the
1052 * code provided in enable_flash_mcp6x_7x_common. Until we know for sure, call
1053 * enable_flash_mcp55 from this function only if enable_flash_mcp6x_7x_common
1054 * indicates the flash chip is LPC. Warning: enable_flash_mcp55
1055 * might make SPI flash inaccessible. The same caveat applies to SPI init
1056 * for LPC flash.
1057 */
1058static int enable_flash_mcp67(struct pci_dev *dev, const char *name)
1059{
1060 int result = 0;
1061
1062 result = enable_flash_mcp6x_7x_common(dev, name);
1063 if (result)
1064 return result;
1065
1066 /* Not sure if this is correct. No docs as usual. */
1067 switch (buses_supported) {
1068 case CHIP_BUSTYPE_LPC:
1069 result = enable_flash_mcp55(dev, name);
1070 break;
1071 case CHIP_BUSTYPE_SPI:
1072 msg_pinfo("SPI on this chipset is not supported yet.\n");
1073 buses_supported = CHIP_BUSTYPE_NONE;
1074 break;
1075 default:
1076 msg_pinfo("Something went wrong with bus type detection.\n");
1077 buses_supported = CHIP_BUSTYPE_NONE;
1078 break;
1079 }
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001080
1081 return result;
1082}
1083
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001084static int enable_flash_mcp7x(struct pci_dev *dev, const char *name)
1085{
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001086 int result = 0;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001087
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001088 result = enable_flash_mcp6x_7x_common(dev, name);
1089 if (result)
1090 return result;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001091
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001092 /* Not sure if this is correct. No docs as usual. */
1093 switch (buses_supported) {
1094 case CHIP_BUSTYPE_LPC:
1095 msg_pinfo("LPC on this chipset is not supported yet.\n");
1096 break;
1097 case CHIP_BUSTYPE_SPI:
1098 msg_pinfo("SPI on this chipset is not supported yet.\n");
1099 buses_supported = CHIP_BUSTYPE_NONE;
1100 break;
1101 default:
1102 msg_pinfo("Something went wrong with bus type detection.\n");
1103 buses_supported = CHIP_BUSTYPE_NONE;
1104 break;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001105 }
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001106
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001107 return result;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001108}
1109
Uwe Hermann372eeb52007-12-04 21:49:06 +00001110static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001111{
Michael Karchercfa674f2010-02-25 11:38:23 +00001112 uint8_t val;
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001113
Uwe Hermanne823ee02007-06-05 15:02:18 +00001114 /* Set the 4MB enable bit. */
Michael Karchercfa674f2010-02-25 11:38:23 +00001115 val = pci_read_byte(dev, 0x41);
1116 val |= 0x0e;
1117 pci_write_byte(dev, 0x41, val);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001118
Michael Karchercfa674f2010-02-25 11:38:23 +00001119 val = pci_read_byte(dev, 0x43);
1120 val |= (1 << 4);
1121 pci_write_byte(dev, 0x43, val);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001122
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001123 return 0;
1124}
1125
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001126/**
1127 * Usually on the x86 architectures (and on other PC-like platforms like some
1128 * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD
1129 * Elan SC520 only a small piece of the system flash is mapped there, but the
1130 * complete flash is mapped somewhere below 1G. The position can be determined
1131 * by the BOOTCS PAR register.
1132 */
1133static int get_flashbase_sc520(struct pci_dev *dev, const char *name)
1134{
1135 int i, bootcs_found = 0;
1136 uint32_t parx = 0;
1137 void *mmcr;
1138
1139 /* 1. Map MMCR */
Stefan Reinauer0593f212009-01-26 01:10:48 +00001140 mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001141
1142 /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for
1143 * BOOTCS region (PARx[31:29] = 100b)e
1144 */
1145 for (i = 0x88; i <= 0xc4; i += 4) {
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +00001146 parx = mmio_readl(mmcr + i);
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001147 if ((parx >> 29) == 4) {
1148 bootcs_found = 1;
1149 break; /* BOOTCS found */
1150 }
1151 }
1152
1153 /* 3. PARx[25] = 1b --> flashbase[29:16] = PARx[13:0]
1154 * PARx[25] = 0b --> flashbase[29:12] = PARx[17:0]
1155 */
1156 if (bootcs_found) {
1157 if (parx & (1 << 25)) {
1158 parx &= (1 << 14) - 1; /* Mask [13:0] */
1159 flashbase = parx << 16;
1160 } else {
1161 parx &= (1 << 18) - 1; /* Mask [17:0] */
1162 flashbase = parx << 12;
1163 }
1164 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +00001165 msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. Assuming flash at 4G\n");
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001166 }
1167
1168 /* 4. Clean up */
Carl-Daniel Hailfingerbe726812009-08-09 12:44:08 +00001169 physunmap(mmcr, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001170 return 0;
1171}
1172
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001173#endif
1174
Uwe Hermann4179d292009-05-08 17:50:51 +00001175/* Please keep this list alphabetically sorted by vendor/device. */
Uwe Hermann05fab752009-05-16 23:42:17 +00001176const struct penable chipset_enables[] = {
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001177#if defined(__i386__) || defined(__x86_64__)
Uwe Hermann4179d292009-05-08 17:50:51 +00001178 {0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533},
1179 {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111},
1180 {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111},
1181 {0x1078, 0x0100, OK, "AMD", "CS5530(A)", enable_flash_cs5530},
1182 {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536},
Nils Jacobse715c7b2009-09-23 02:09:23 +00001183 {0x1022, 0x2090, OK, "AMD", "CS5536", enable_flash_cs5536},
Uwe Hermann4179d292009-05-08 17:50:51 +00001184 {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520},
1185 {0x1002, 0x438D, OK, "AMD", "SB600", enable_flash_sb600},
Carl-Daniel Hailfinger174962d2009-09-01 22:13:42 +00001186 {0x1002, 0x439d, OK, "AMD", "SB700/SB710/SB750", enable_flash_sb600},
Uwe Hermann4179d292009-05-08 17:50:51 +00001187 {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100},
1188 {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400},
1189 {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000},
Carl-Daniel Hailfinger797a8342009-11-26 16:51:39 +00001190 {0x8086, 0x3b00, NT, "Intel", "3400 Desktop", enable_flash_ich10},
1191 {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_ich10},
1192 {0x8086, 0x3b0d, NT, "Intel", "3400 Mobile SFF", enable_flash_ich10},
Uwe Hermannb0039912009-05-07 13:24:49 +00001193 {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4},
Uwe Hermann4179d292009-05-08 17:50:51 +00001194 {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich_4e},
1195 {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich_dc},
1196 {0x8086, 0x5031, OK, "Intel", "EP80579", enable_flash_ich7},
Uwe Hermannb0039912009-05-07 13:24:49 +00001197 {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich_4e},
Uwe Hermann4179d292009-05-08 17:50:51 +00001198 {0x8086, 0x3a18, OK, "Intel", "ICH10", enable_flash_ich10},
1199 {0x8086, 0x3a1a, OK, "Intel", "ICH10D", enable_flash_ich10},
1200 {0x8086, 0x3a14, OK, "Intel", "ICH10DO", enable_flash_ich10},
1201 {0x8086, 0x3a16, OK, "Intel", "ICH10R", enable_flash_ich10},
Uwe Hermannb0039912009-05-07 13:24:49 +00001202 {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich_4e},
1203 {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +00001204 {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich_4e},
Uwe Hermann4179d292009-05-08 17:50:51 +00001205 {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +00001206 {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich_4e},
1207 {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich_4e},
1208 {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +00001209 {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich_dc},
1210 {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich_dc},
Uwe Hermannb0039912009-05-07 13:24:49 +00001211 {0x8086, 0x27b0, OK, "Intel", "ICH7DH", enable_flash_ich7},
1212 {0x8086, 0x27b8, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7},
1213 {0x8086, 0x27b9, OK, "Intel", "ICH7M", enable_flash_ich7},
1214 {0x8086, 0x27bd, OK, "Intel", "ICH7MDH", enable_flash_ich7},
David Hendricksdb7c1532010-01-19 02:19:27 +00001215 {0x8086, 0x27bc, OK, "Intel", "NM10", enable_flash_ich7},
Uwe Hermann4179d292009-05-08 17:50:51 +00001216 {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +00001217 {0x8086, 0x2812, OK, "Intel", "ICH8DH", enable_flash_ich8},
1218 {0x8086, 0x2814, OK, "Intel", "ICH8DO", enable_flash_ich8},
Uwe Hermann4179d292009-05-08 17:50:51 +00001219 {0x8086, 0x2810, OK, "Intel", "ICH8/ICH8R", enable_flash_ich8},
Uwe Hermannb0039912009-05-07 13:24:49 +00001220 {0x8086, 0x2815, OK, "Intel", "ICH8M", enable_flash_ich8},
Uwe Hermann4179d292009-05-08 17:50:51 +00001221 {0x8086, 0x2811, OK, "Intel", "ICH8M-E", enable_flash_ich8},
1222 {0x8086, 0x2918, OK, "Intel", "ICH9", enable_flash_ich9},
Uwe Hermannb0039912009-05-07 13:24:49 +00001223 {0x8086, 0x2912, OK, "Intel", "ICH9DH", enable_flash_ich9},
1224 {0x8086, 0x2914, OK, "Intel", "ICH9DO", enable_flash_ich9},
Uwe Hermannb0039912009-05-07 13:24:49 +00001225 {0x8086, 0x2919, OK, "Intel", "ICH9M", enable_flash_ich9},
Uwe Hermann4179d292009-05-08 17:50:51 +00001226 {0x8086, 0x2917, OK, "Intel", "ICH9M-E", enable_flash_ich9},
1227 {0x8086, 0x2916, OK, "Intel", "ICH9R", enable_flash_ich9},
Carl-Daniel Hailfinger95baaad2009-08-21 17:26:13 +00001228 {0x8086, 0x2910, OK, "Intel", "ICH9 Engineering Sample", enable_flash_ich9},
Uwe Hermann4179d292009-05-08 17:50:51 +00001229 {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4},
1230 {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4},
1231 {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4},
1232 {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4},
Adam Jurkowskie4984102009-12-21 15:30:46 +00001233 {0x8086, 0x8119, OK, "Intel", "Poulsbo", enable_flash_poulsbo},
Luc Verhaegenaad7e672009-10-06 11:32:21 +00001234 {0x10de, 0x0030, OK, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2},
Uwe Hermannb0039912009-05-07 13:24:49 +00001235 {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */
1236 {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */
Luc Verhaegen90e8e612009-05-26 09:48:28 +00001237 {0x10de, 0x0060, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2},
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001238 {0x10de, 0x00e0, OK, "NVIDIA", "NForce3", enable_flash_nvidia_nforce2},
Uwe Hermanneac10162008-03-13 18:52:51 +00001239 /* Slave, should not be here, to fix known bug for A01. */
Uwe Hermannb0039912009-05-07 13:24:49 +00001240 {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804},
1241 {0x10de, 0x0260, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1242 {0x10de, 0x0261, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1243 {0x10de, 0x0262, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1244 {0x10de, 0x0263, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1245 {0x10de, 0x0360, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* M57SLI*/
Carl-Daniel Hailfinger33d7b6a2010-05-22 07:27:16 +00001246 /* 10de:0361 is present in Tyan S2915 OEM systems, but not connected to
1247 * the flash chip. Instead, 10de:0364 is connected to the flash chip.
1248 * Until we have PCI device class matching or some fallback mechanism,
1249 * this is needed to get flashrom working on Tyan S2915 and maybe other
1250 * dual-MCP55 boards.
1251 */
1252#if 0
1253 {0x10de, 0x0361, NT, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1254#endif
Uwe Hermannb0039912009-05-07 13:24:49 +00001255 {0x10de, 0x0362, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1256 {0x10de, 0x0363, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1257 {0x10de, 0x0364, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1258 {0x10de, 0x0365, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1259 {0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1260 {0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001261 {0x10de, 0x03e0, NT, "NVIDIA", "MCP61", enable_flash_mcp67},
1262 {0x10de, 0x03e1, NT, "NVIDIA", "MCP61", enable_flash_mcp67},
1263 {0x10de, 0x03e2, NT, "NVIDIA", "MCP61", enable_flash_mcp67},
1264 {0x10de, 0x03e3, NT, "NVIDIA", "MCP61", enable_flash_mcp67},
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001265 {0x10de, 0x0440, NT, "NVIDIA", "MCP65", enable_flash_mcp7x},
1266 {0x10de, 0x0441, NT, "NVIDIA", "MCP65", enable_flash_mcp7x},
1267 {0x10de, 0x0442, NT, "NVIDIA", "MCP65", enable_flash_mcp7x},
1268 {0x10de, 0x0443, NT, "NVIDIA", "MCP65", enable_flash_mcp7x},
1269 {0x10de, 0x0548, OK, "NVIDIA", "MCP67", enable_flash_mcp67},
1270 {0x10de, 0x075c, NT, "NVIDIA", "MCP78S", enable_flash_mcp7x},
1271 {0x10de, 0x075d, NT, "NVIDIA", "MCP78S", enable_flash_mcp7x},
1272 {0x10de, 0x07d7, NT, "NVIDIA", "MCP73", enable_flash_mcp7x},
1273 {0x10de, 0x0aac, NT, "NVIDIA", "MCP79", enable_flash_mcp7x},
1274 {0x10de, 0x0aad, NT, "NVIDIA", "MCP79", enable_flash_mcp7x},
1275 {0x10de, 0x0aae, NT, "NVIDIA", "MCP79", enable_flash_mcp7x},
1276 {0x10de, 0x0aaf, NT, "NVIDIA", "MCP79", enable_flash_mcp7x},
Carl-Daniel Hailfinger6a0269e2009-11-15 17:20:21 +00001277 {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496},
1278 {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501},
1279 {0x1039, 0x5511, NT, "SiS", "5511", enable_flash_sis5511},
Luc Verhaegen9cce2f52010-01-10 15:01:08 +00001280 {0x1039, 0x5596, NT, "SiS", "5596", enable_flash_sis5511},
Carl-Daniel Hailfinger6a0269e2009-11-15 17:20:21 +00001281 {0x1039, 0x5571, NT, "SiS", "5571", enable_flash_sis530},
1282 {0x1039, 0x5591, NT, "SiS", "5591/5592", enable_flash_sis530},
1283 {0x1039, 0x5597, NT, "SiS", "5597/5598/5581/5120", enable_flash_sis530},
1284 {0x1039, 0x0530, NT, "SiS", "530", enable_flash_sis530},
1285 {0x1039, 0x5600, NT, "SiS", "600", enable_flash_sis530},
1286 {0x1039, 0x0620, NT, "SiS", "620", enable_flash_sis530},
1287 {0x1039, 0x0540, NT, "SiS", "540", enable_flash_sis540},
Luc Verhaegen9892ca62009-12-09 07:43:13 +00001288 {0x1039, 0x0630, NT, "SiS", "630", enable_flash_sis540},
1289 {0x1039, 0x0635, NT, "SiS", "635", enable_flash_sis540},
1290 {0x1039, 0x0640, NT, "SiS", "640", enable_flash_sis540},
1291 {0x1039, 0x0645, NT, "SiS", "645", enable_flash_sis540},
1292 {0x1039, 0x0646, NT, "SiS", "645DX", enable_flash_sis540},
1293 {0x1039, 0x0648, NT, "SiS", "648", enable_flash_sis540},
1294 {0x1039, 0x0650, NT, "SiS", "650", enable_flash_sis540},
1295 {0x1039, 0x0651, NT, "SiS", "651", enable_flash_sis540},
1296 {0x1039, 0x0655, NT, "SiS", "655", enable_flash_sis540},
1297 {0x1039, 0x0730, NT, "SiS", "730", enable_flash_sis540},
1298 {0x1039, 0x0733, NT, "SiS", "733", enable_flash_sis540},
1299 {0x1039, 0x0735, OK, "SiS", "735", enable_flash_sis540},
1300 {0x1039, 0x0740, NT, "SiS", "740", enable_flash_sis540},
1301 {0x1039, 0x0745, NT, "SiS", "745", enable_flash_sis540},
1302 {0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis540},
1303 {0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis540},
1304 {0x1039, 0x0755, NT, "SiS", "755", enable_flash_sis540},
Michael Karcher89bed6d2010-06-13 10:16:12 +00001305 /* VIA northbridges */
1306 {0x1106, 0x0585, NT, "VIA", "VT82C585VPX", via_no_byte_merge},
1307 {0x1106, 0x0595, NT, "VIA", "VT82C595", via_no_byte_merge},
1308 {0x1106, 0x0597, NT, "VIA", "VT82C597", via_no_byte_merge},
1309 {0x1106, 0x0691, NT, "VIA", "VT82C69x", via_no_byte_merge}, /* 691, 693a, 694t, 694x checked */
1310 {0x1106, 0x0601, NT, "VIA", "VT8601/VT8601A", via_no_byte_merge},
1311 {0x1106, 0x8601, NT, "VIA", "VT8601T", via_no_byte_merge},
1312 /* VIA southbridges */
Uwe Hermann4179d292009-05-08 17:50:51 +00001313 {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x},
1314 {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x},
Mateusz Murawskie6abef02009-06-18 12:42:46 +00001315 {0x1106, 0x3074, NT, "VIA", "VT8233", enable_flash_vt823x},
Raúl Sorianocd8404d2009-12-23 21:29:18 +00001316 {0x1106, 0x3147, OK, "VIA", "VT8233A", enable_flash_vt823x},
Uwe Hermann4179d292009-05-08 17:50:51 +00001317 {0x1106, 0x3177, OK, "VIA", "VT8235", enable_flash_vt823x},
1318 {0x1106, 0x3227, OK, "VIA", "VT8237", enable_flash_vt823x},
1319 {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x},
1320 {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi},
Arjan Koers8dfea832009-06-15 00:03:37 +00001321 {0x1106, 0x8353, OK, "VIA", "VX800", enable_flash_vt8237s_spi},
Uwe Hermann3e0774d2009-09-25 01:05:06 +00001322 {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111},
Uwe Hermann4179d292009-05-08 17:50:51 +00001323 {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111},
1324 {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111},
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001325#endif
Uwe Hermann05fab752009-05-16 23:42:17 +00001326 {},
Ollie Lhocbbf1252004-03-17 22:22:08 +00001327};
Ollie Lho761bf1b2004-03-20 16:46:10 +00001328
Uwe Hermanna7e05482007-05-09 10:17:44 +00001329int chipset_flash_enable(void)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001330{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001331 struct pci_dev *dev = 0;
Uwe Hermann372eeb52007-12-04 21:49:06 +00001332 int ret = -2; /* Nothing! */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001333 int i;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001334
Uwe Hermann372eeb52007-12-04 21:49:06 +00001335 /* Now let's try to find the chipset we have... */
Uwe Hermann05fab752009-05-16 23:42:17 +00001336 for (i = 0; chipset_enables[i].vendor_name != NULL; i++) {
1337 dev = pci_dev_find(chipset_enables[i].vendor_id,
1338 chipset_enables[i].device_id);
Michael Karcher89bed6d2010-06-13 10:16:12 +00001339 if (!dev)
1340 continue;
1341 if (ret != -2) {
1342 msg_pinfo("WARNING: unexpected second chipset match: "
1343 "\"%s %s\"\nignoring, please report lspci and "
1344 "board URL to flashrom@flashrom.org!\n",
1345 chipset_enables[i].vendor_name,
1346 chipset_enables[i].device_name);
1347 continue;
1348 }
Sean Nelson316a29f2010-05-07 20:09:04 +00001349 msg_pinfo("Found chipset \"%s %s\", enabling flash write... ",
Uwe Hermann05fab752009-05-16 23:42:17 +00001350 chipset_enables[i].vendor_name,
1351 chipset_enables[i].device_name);
Carl-Daniel Hailfingerf469c272010-05-22 07:31:50 +00001352 msg_pdbg("chipset PCI ID is %04x:%04x, ",
1353 chipset_enables[i].vendor_id,
1354 chipset_enables[i].device_id);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001355
Uwe Hermann05fab752009-05-16 23:42:17 +00001356 ret = chipset_enables[i].doit(dev,
1357 chipset_enables[i].device_name);
Michael Karcher89bed6d2010-06-13 10:16:12 +00001358 if (ret == NOT_DONE_YET) {
1359 ret = -2;
1360 msg_pinfo("OK - searching further chips.\n");
1361 } else if (ret < 0)
Sean Nelson316a29f2010-05-07 20:09:04 +00001362 msg_pinfo("FAILED!\n");
Michael Karcher89bed6d2010-06-13 10:16:12 +00001363 else if(ret == 0)
Sean Nelson316a29f2010-05-07 20:09:04 +00001364 msg_pinfo("OK.\n");
Michael Karchera4448d92010-07-22 18:04:15 +00001365 else if(ret == ERROR_NONFATAL)
1366 msg_pinfo("PROBLEMS, continuing anyway\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +00001367 }
Michael Karcher89bed6d2010-06-13 10:16:12 +00001368
Sean Nelson316a29f2010-05-07 20:09:04 +00001369 msg_pinfo("This chipset supports the following protocols: %s.\n",
Uwe Hermann9899cad2009-06-28 21:47:57 +00001370 flashbuses_to_text(buses_supported));
Uwe Hermanna7e05482007-05-09 10:17:44 +00001371
1372 return ret;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001373}