Add a bunch of new/tested stuff and various small changes 7
- add Asus Crosshair IV Extreme to the list of supported boards
http://www.flashrom.org/pipermail/flashrom/2011-August/007640.html
- add Biostar N68S3+ to the list of supported boards
http://www.flashrom.org/pipermail/flashrom/2011-September/007788.html
- add P7H55-M LX to the list of supported boards
although flashrom works correctly, it is marked as not ok, because flashing the
vendor image will break the LAN interface.
- add GA-X58A-UD7 to the list of supported boards
http://paste.flashrom.org/view.php?id=739
- add Asus P4P800-VM to print.c
(has a working board enable)
- add Asus K8V-X to print.c
reported by florz
http://paste.flashrom.org/view.php?id=742
- add Intel D865GLC to print.c as non-working (ICH5 with BIOS lock enable)
reported by jmd on IRC
http://paste.flashrom.org/view.php?id=775
- add Intel DH67CF to print.c as non-working (H67 with BIOS lock enable and locked ME region)
http://www.flashrom.org/pipermail/flashrom/2011-September/007789.html
- add ECS P4M800PRO-M (V1.0A) to the list of supported boards
reported by dweg on IRC (hot flashed a SST49LF040B, original was W39V040B)
- add X8DTU-6TF+ to print.c (needs ME unlocking)
http://www.flashrom.org/pipermail/flashrom/2011-August/007553.html
- add Shuttle FH67 (used in the SH67H3 barebone) to the list of supported boards
http://www.flashrom.org/pipermail/flashrom/2011-August/007749.html
- add Tyan S2912 to the list of supported boards
reported by erlan on IRC
- add ZOTAC GeForce 8200 to the list of supported boards
http://www.flashrom.org/pipermail/flashrom/2011-August/007612.html
- mark AT25DF321A as TEST_OK_PROBE
http://www.flashrom.org/pipermail/flashrom/2011-August/007553.html
- mark 28F001BN/BX-T as TEST_OK_PR
http://www.flashrom.org/pipermail/flashrom/2011-July/007208.html
- rename MX29F002
http://patchwork.coreboot.org/patch/2794/
- mark SST39SF040 as fully tested
reported by Florian 'florz' Zumbiehl
http://paste.flashrom.org/view.php?id=742
- mark SST49LF040B as fully tested
reported by dweg on IRC and later by Armin on the ml:
http://www.flashrom.org/pipermail/flashrom/2011-August/007764.html
- mark H55 chipset as OK
http://www.flashrom.org/pipermail/flashrom/2011-July/007432.html
- mark H67 chipset as OK
http://www.flashrom.org/pipermail/flashrom/2011-August/007749.html
- mark a MCP61 version as OK
http://www.flashrom.org/pipermail/flashrom/2011-September/007788.html
- add preliminary X79 (patsburg) PCI IDs
0x1d40 was reported already as working (not archived in our pipermail?)
http://marc.info/?l=flashrom&m=130683026218257&w=2
- mark "82557/8/9/0/1 Ethernet Pro 100" in nicintel.c as working
http://www.flashrom.org/pipermail/flashrom/2011-August/007480.html
- rename some chips that had gratuitous "probing" suffixes:
- SST25VF010.REMS
- SST25VF040.REMS
- M25P05.RES
- M25P10.RES
some other chip names with suffixes are needed due to lack of support
for multiple probe functions per chip. this is explained here:
http://www.flashrom.org/pipermail/flashrom/2011-August/007597.html
- remove unneeded nicintel_spi-related function declarations in programmer.h
- typos and whitespace fixes
- fix Asus P4P800-E Deluxe detection
The original board enable was added before DMI matching and used
the IDs of a Promise controller as secondary PCI ID set. The
controller could be disabled in the BIOS which would make the
board not match. This patch uses the SMBus controller instead and
adds a DMI pattern. This was
Tested-by: Michael Schneider <vdrportal_midas at gmx dot de>
Corresponding to flashrom svn r1425.
- add "Sealed-case PC" to the list of chassis type (as indicating "not a laptop")
This is
Acked-by: Idwer Vollering <vidwer@gmail.com>
the fix for the typo unusued -> unused is
Signed-off-by: Sylvain "ythier" Hitier <sylvain.hitier@gmail.com>
everything else is
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
And everything was reviewed and
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
diff --git a/chipset_enable.c b/chipset_enable.c
index 336ad2e..eb4031b 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -327,7 +327,7 @@
}
if (fwh_idsel & 0xffff000000000000ULL) {
msg_perr("Error: fwh_idsel= specified, but value had "
- "unusued bits set.\n");
+ "unused bits set.\n");
goto idsel_garbage_out;
}
fwh_idsel_old = pci_read_long(dev, 0xd0);
@@ -341,7 +341,7 @@
/* FIXME: Decode settings are not changed. */
} else if (idsel) {
msg_perr("Error: fwh_idsel= specified, but no value given.\n");
-idsel_garbage_out:
+idsel_garbage_out:
free(idsel);
/* FIXME: Return failure here once internal_init() starts
* to care about the return value of the chipset enable.
@@ -846,8 +846,8 @@
if (new != old) {
rpci_write_byte(dev, 0x88, new);
if (pci_read_byte(dev, 0x88) != new) {
- msg_pinfo("Setting register to set 0x%x to 0x%x on %s "
- "failed (WARNING ONLY).\n", 0x88, new, name);
+ msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
+ "(WARNING ONLY).\n", 0x88, new, name);
}
}
@@ -1152,7 +1152,7 @@
{0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
{0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */
{0x10de, 0x03e0, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
- {0x10de, 0x03e1, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
+ {0x10de, 0x03e1, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
{0x10de, 0x03e2, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
{0x10de, 0x03e3, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
{0x10de, 0x0440, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
@@ -1196,7 +1196,7 @@
{0x8086, 0x1c46, NT, "Intel", "P67", enable_flash_pch6},
{0x8086, 0x1c47, NT, "Intel", "UM67", enable_flash_pch6},
{0x8086, 0x1c49, NT, "Intel", "HM65", enable_flash_pch6},
- {0x8086, 0x1c4a, NT, "Intel", "H67", enable_flash_pch6},
+ {0x8086, 0x1c4a, OK, "Intel", "H67", enable_flash_pch6},
{0x8086, 0x1c4b, NT, "Intel", "HM67", enable_flash_pch6},
{0x8086, 0x1c4c, NT, "Intel", "Q65", enable_flash_pch6},
{0x8086, 0x1c4d, NT, "Intel", "QS67", enable_flash_pch6},
@@ -1207,6 +1207,8 @@
{0x8086, 0x1c54, NT, "Intel", "C204", enable_flash_pch6},
{0x8086, 0x1c56, NT, "Intel", "C206", enable_flash_pch6},
{0x8086, 0x1c5c, NT, "Intel", "H61", enable_flash_pch6},
+ {0x8086, 0x1d40, OK, "Intel", "X79", enable_flash_ich10}, /* FIXME: when datasheet is available */
+ {0x8086, 0x1d41, NT, "Intel", "X79", enable_flash_ich10}, /* FIXME: when datasheet is available */
{0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich_4e},
{0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich_4e},
{0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich_4e},
@@ -1249,7 +1251,7 @@
{0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_pch5},
{0x8086, 0x3b02, NT, "Intel", "P55", enable_flash_pch5},
{0x8086, 0x3b03, NT, "Intel", "PM55", enable_flash_pch5},
- {0x8086, 0x3b06, NT, "Intel", "H55", enable_flash_pch5},
+ {0x8086, 0x3b06, OK, "Intel", "H55", enable_flash_pch5},
{0x8086, 0x3b07, OK, "Intel", "QM57", enable_flash_pch5},
{0x8086, 0x3b08, NT, "Intel", "H57", enable_flash_pch5},
{0x8086, 0x3b09, NT, "Intel", "HM55", enable_flash_pch5},