blob: b4555b92af1f6f65a354bc9436d31903fbb83abb [file] [log] [blame]
Dominik Geyerb46acba2008-05-16 12:55:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2008 Stefan Wildemann <stefan.wildemann@kontron.com>
5 * Copyright (C) 2008 Claus Gindhart <claus.gindhart@kontron.com>
6 * Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com>
Stefan Reinauera9424d52008-06-27 16:28:34 +00007 * Copyright (C) 2008 coresystems GmbH <info@coresystems.de>
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +00008 * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
Stefan Tauner8b391b82011-08-09 01:49:34 +00009 * Copyright (C) 2011 Stefan Tauner
Dominik Geyerb46acba2008-05-16 12:55:55 +000010 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
Dominik Geyerb46acba2008-05-16 12:55:55 +000020 */
21
Dominik Geyerb46acba2008-05-16 12:55:55 +000022#include <string.h>
Felix Singer8cfc7372022-08-19 03:10:29 +020023#include <stdbool.h>
Stefan Taunerd0c5dc22011-10-20 12:57:14 +000024#include <stdlib.h>
Dominik Geyerb46acba2008-05-16 12:55:55 +000025#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000026#include "programmer.h"
Thomas Heijligen74b4aa02021-12-14 17:52:30 +010027#include "hwaccess_physmap.h"
Dominik Geyerb46acba2008-05-16 12:55:55 +000028#include "spi.h"
Stefan Tauner1e146392011-09-15 23:52:55 +000029#include "ich_descriptors.h"
Dominik Geyerb46acba2008-05-16 12:55:55 +000030
Nico Huberd2d39932019-01-18 16:49:37 +010031/* Apollo Lake */
32#define APL_REG_FREG12 0xe0 /* 32 Bytes Flash Region 12 */
33
Nico Huberd54e4f42017-03-23 23:45:47 +010034/* Sunrise Point */
35
36/* Added HSFS Status bits */
37#define HSFS_WRSDIS_OFF 11 /* 11: Flash Configuration Lock-Down */
38#define HSFS_WRSDIS (0x1 << HSFS_WRSDIS_OFF)
39#define HSFS_PRR34_LOCKDN_OFF 12 /* 12: PRR3 PRR4 Lock-Down */
40#define HSFS_PRR34_LOCKDN (0x1 << HSFS_PRR34_LOCKDN_OFF)
41/* HSFS_BERASE vanished */
42
43/*
44 * HSFC and HSFS 16-bit registers are combined into the 32-bit
45 * BIOS_HSFSTS_CTL register in the Sunrise Point datasheet,
46 * however we still treat them separately in order to reuse code.
47 */
48
49/* Changed HSFC Control bits */
50#define PCH100_HSFC_FCYCLE_OFF (17 - 16) /* 1-4: FLASH Cycle */
51#define PCH100_HSFC_FCYCLE (0xf << PCH100_HSFC_FCYCLE_OFF)
52/* New HSFC Control bit */
53#define HSFC_WET_OFF (21 - 16) /* 5: Write Enable Type */
54#define HSFC_WET (0x1 << HSFC_WET_OFF)
55
56#define PCH100_FADDR_FLA 0x07ffffff
57
58#define PCH100_REG_DLOCK 0x0c /* 32 Bits Discrete Lock Bits */
59#define DLOCK_BMWAG_LOCKDN_OFF 0
60#define DLOCK_BMWAG_LOCKDN (0x1 << DLOCK_BMWAG_LOCKDN_OFF)
61#define DLOCK_BMRAG_LOCKDN_OFF 1
62#define DLOCK_BMRAG_LOCKDN (0x1 << DLOCK_BMRAG_LOCKDN_OFF)
63#define DLOCK_SBMWAG_LOCKDN_OFF 2
64#define DLOCK_SBMWAG_LOCKDN (0x1 << DLOCK_SBMWAG_LOCKDN_OFF)
65#define DLOCK_SBMRAG_LOCKDN_OFF 3
66#define DLOCK_SBMRAG_LOCKDN (0x1 << DLOCK_SBMRAG_LOCKDN_OFF)
67#define DLOCK_PR0_LOCKDN_OFF 8
68#define DLOCK_PR0_LOCKDN (0x1 << DLOCK_PR0_LOCKDN_OFF)
69#define DLOCK_PR1_LOCKDN_OFF 9
70#define DLOCK_PR1_LOCKDN (0x1 << DLOCK_PR1_LOCKDN_OFF)
71#define DLOCK_PR2_LOCKDN_OFF 10
72#define DLOCK_PR2_LOCKDN (0x1 << DLOCK_PR2_LOCKDN_OFF)
73#define DLOCK_PR3_LOCKDN_OFF 11
74#define DLOCK_PR3_LOCKDN (0x1 << DLOCK_PR3_LOCKDN_OFF)
75#define DLOCK_PR4_LOCKDN_OFF 12
76#define DLOCK_PR4_LOCKDN (0x1 << DLOCK_PR4_LOCKDN_OFF)
77#define DLOCK_SSEQ_LOCKDN_OFF 16
78#define DLOCK_SSEQ_LOCKDN (0x1 << DLOCK_SSEQ_LOCKDN_OFF)
79
80#define PCH100_REG_FPR0 0x84 /* 32 Bits Protected Range 0 */
81#define PCH100_REG_GPR0 0x98 /* 32 Bits Global Protected Range 0 */
82
83#define PCH100_REG_SSFSC 0xA0 /* 32 Bits Status (8) + Control (24) */
84#define PCH100_REG_PREOP 0xA4 /* 16 Bits */
85#define PCH100_REG_OPTYPE 0xA6 /* 16 Bits */
86#define PCH100_REG_OPMENU 0xA8 /* 64 Bits */
87
Stefan Reinauera9424d52008-06-27 16:28:34 +000088/* ICH9 controller register definition */
Stefan Tauner55206942011-06-11 09:53:22 +000089#define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */
90#define HSFS_FDONE_OFF 0 /* 0: Flash Cycle Done */
91#define HSFS_FDONE (0x1 << HSFS_FDONE_OFF)
92#define HSFS_FCERR_OFF 1 /* 1: Flash Cycle Error */
93#define HSFS_FCERR (0x1 << HSFS_FCERR_OFF)
94#define HSFS_AEL_OFF 2 /* 2: Access Error Log */
95#define HSFS_AEL (0x1 << HSFS_AEL_OFF)
96#define HSFS_BERASE_OFF 3 /* 3-4: Block/Sector Erase Size */
97#define HSFS_BERASE (0x3 << HSFS_BERASE_OFF)
98#define HSFS_SCIP_OFF 5 /* 5: SPI Cycle In Progress */
99#define HSFS_SCIP (0x1 << HSFS_SCIP_OFF)
100 /* 6-12: reserved */
101#define HSFS_FDOPSS_OFF 13 /* 13: Flash Descriptor Override Pin-Strap Status */
102#define HSFS_FDOPSS (0x1 << HSFS_FDOPSS_OFF)
103#define HSFS_FDV_OFF 14 /* 14: Flash Descriptor Valid */
104#define HSFS_FDV (0x1 << HSFS_FDV_OFF)
105#define HSFS_FLOCKDN_OFF 15 /* 15: Flash Configuration Lock-Down */
106#define HSFS_FLOCKDN (0x1 << HSFS_FLOCKDN_OFF)
107
108#define ICH9_REG_HSFC 0x06 /* 16 Bits Hardware Sequencing Flash Control */
109#define HSFC_FGO_OFF 0 /* 0: Flash Cycle Go */
110#define HSFC_FGO (0x1 << HSFC_FGO_OFF)
111#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */
112#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
113 /* 3-7: reserved */
114#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
115#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)
116 /* 14: reserved */
117#define HSFC_SME_OFF 15 /* 15: SPI SMI# Enable */
118#define HSFC_SME (0x1 << HSFC_SME_OFF)
119
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000120#define ICH9_REG_FADDR 0x08 /* 32 Bits */
Nico Huberd54e4f42017-03-23 23:45:47 +0100121#define ICH9_FADDR_FLA 0x01ffffff
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000122#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000123
Stefan Tauner29c80832011-06-12 08:14:10 +0000124#define ICH9_REG_FRAP 0x50 /* 32 Bytes Flash Region Access Permissions */
125#define ICH9_REG_FREG0 0x54 /* 32 Bytes Flash Region 0 */
126
127#define ICH9_REG_PR0 0x74 /* 32 Bytes Protected Range 0 */
Stefan Taunerbf69aaa2011-09-17 21:21:48 +0000128#define PR_WP_OFF 31 /* 31: write protection enable */
129#define PR_RP_OFF 15 /* 15: read protection enable */
Stefan Tauner29c80832011-06-12 08:14:10 +0000130
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000131#define ICH9_REG_SSFS 0x90 /* 08 Bits */
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000132#define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */
133#define SSFS_SCIP (0x1 << SSFS_SCIP_OFF)
134#define SSFS_FDONE_OFF 2 /* Cycle Done Status */
135#define SSFS_FDONE (0x1 << SSFS_FDONE_OFF)
136#define SSFS_FCERR_OFF 3 /* Flash Cycle Error */
137#define SSFS_FCERR (0x1 << SSFS_FCERR_OFF)
138#define SSFS_AEL_OFF 4 /* Access Error Log */
139#define SSFS_AEL (0x1 << SSFS_AEL_OFF)
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000140/* The following bits are reserved in SSFS: 1,5-7. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000141#define SSFS_RESERVED_MASK 0x000000e2
Stefan Reinauera9424d52008-06-27 16:28:34 +0000142
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000143#define ICH9_REG_SSFC 0x91 /* 24 Bits */
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000144/* We combine SSFS and SSFC to one 32-bit word,
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000145 * therefore SSFC bits are off by 8. */
146 /* 0: reserved */
147#define SSFC_SCGO_OFF (1 + 8) /* 1: SPI Cycle Go */
148#define SSFC_SCGO (0x1 << SSFC_SCGO_OFF)
149#define SSFC_ACS_OFF (2 + 8) /* 2: Atomic Cycle Sequence */
150#define SSFC_ACS (0x1 << SSFC_ACS_OFF)
151#define SSFC_SPOP_OFF (3 + 8) /* 3: Sequence Prefix Opcode Pointer */
152#define SSFC_SPOP (0x1 << SSFC_SPOP_OFF)
153#define SSFC_COP_OFF (4 + 8) /* 4-6: Cycle Opcode Pointer */
154#define SSFC_COP (0x7 << SSFC_COP_OFF)
155 /* 7: reserved */
156#define SSFC_DBC_OFF (8 + 8) /* 8-13: Data Byte Count */
157#define SSFC_DBC (0x3f << SSFC_DBC_OFF)
158#define SSFC_DS_OFF (14 + 8) /* 14: Data Cycle */
159#define SSFC_DS (0x1 << SSFC_DS_OFF)
160#define SSFC_SME_OFF (15 + 8) /* 15: SPI SMI# Enable */
161#define SSFC_SME (0x1 << SSFC_SME_OFF)
162#define SSFC_SCF_OFF (16 + 8) /* 16-18: SPI Cycle Frequency */
163#define SSFC_SCF (0x7 << SSFC_SCF_OFF)
164#define SSFC_SCF_20MHZ 0x00000000
165#define SSFC_SCF_33MHZ 0x01000000
166 /* 19-23: reserved */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000167#define SSFC_RESERVED_MASK 0xf8008100
Stefan Reinauera9424d52008-06-27 16:28:34 +0000168
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000169#define ICH9_REG_PREOP 0x94 /* 16 Bits */
170#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */
171#define ICH9_REG_OPMENU 0x98 /* 64 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000172
Stefan Tauner29c80832011-06-12 08:14:10 +0000173#define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */
174#define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */
175
Stefan Tauner1e146392011-09-15 23:52:55 +0000176#define ICH8_REG_VSCC 0xC1 /* 32 Bits Vendor Specific Component Capabilities */
177#define ICH9_REG_LVSCC 0xC4 /* 32 Bits Host Lower Vendor Specific Component Capabilities */
178#define ICH9_REG_UVSCC 0xC8 /* 32 Bits Host Upper Vendor Specific Component Capabilities */
179/* The individual fields of the VSCC registers are defined in the file
180 * ich_descriptors.h. The reason is that the same layout is also used in the
181 * flash descriptor to define the properties of the different flash chips
182 * supported. The BIOS (or the ME?) is responsible to populate the ICH registers
183 * with the information from the descriptor on startup depending on the actual
184 * chip(s) detected. */
185
Stefan Taunerbd649e42011-07-01 00:39:16 +0000186#define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */
187#define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */
188#define FPB_FPBA (0x1FFF << FPB_FPBA_OFF)
189
Dominik Geyerb46acba2008-05-16 12:55:55 +0000190// ICH9R SPI commands
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000191#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
192#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
193#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
194#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
Dominik Geyerb46acba2008-05-16 12:55:55 +0000195
Stefan Reinauera9424d52008-06-27 16:28:34 +0000196// ICH7 registers
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000197#define ICH7_REG_SPIS 0x00 /* 16 Bits */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000198#define SPIS_SCIP 0x0001
199#define SPIS_GRANT 0x0002
200#define SPIS_CDS 0x0004
201#define SPIS_FCERR 0x0008
202#define SPIS_RESERVED_MASK 0x7ff0
Stefan Reinauera9424d52008-06-27 16:28:34 +0000203
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000204/* VIA SPI is compatible with ICH7, but maxdata
205 to transfer is 16 bytes.
206
207 DATA byte count on ICH7 is 8:13, on VIA 8:11
208
209 bit 12 is port select CS0 CS1
210 bit 13 is FAST READ enable
211 bit 7 is used with fast read and one shot controls CS de-assert?
212*/
213
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000214#define ICH7_REG_SPIC 0x02 /* 16 Bits */
215#define SPIC_SCGO 0x0002
216#define SPIC_ACS 0x0004
217#define SPIC_SPOP 0x0008
218#define SPIC_DS 0x4000
Stefan Reinauera9424d52008-06-27 16:28:34 +0000219
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000220#define ICH7_REG_SPIA 0x04 /* 32 Bits */
221#define ICH7_REG_SPID0 0x08 /* 64 Bytes */
222#define ICH7_REG_PREOP 0x54 /* 16 Bits */
223#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */
224#define ICH7_REG_OPMENU 0x58 /* 64 Bits */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000225
Nico Huber7590d1a2016-05-03 13:38:28 +0200226enum ich_access_protection {
227 NO_PROT = 0,
228 READ_PROT = 1,
229 WRITE_PROT = 2,
230 LOCKED = 3,
231};
232
FENG yu ningc05a2952008-12-08 18:16:58 +0000233/* ICH SPI configuration lock-down. May be set during chipset enabling. */
Felix Singer8cfc7372022-08-19 03:10:29 +0200234static bool ichspi_lock = false;
FENG yu ningc05a2952008-12-08 18:16:58 +0000235
Stefan Taunera8d838d2011-11-06 23:51:09 +0000236static enum ich_chipset ich_generation = CHIPSET_ICH_UNKNOWN;
Nico Hubered098d62017-04-21 23:47:08 +0200237static uint32_t ichspi_bbar;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000238
Michael Karchera4448d92010-07-22 18:04:15 +0000239static void *ich_spibar = NULL;
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000240
Dominik Geyerb46acba2008-05-16 12:55:55 +0000241typedef struct _OPCODE {
242 uint8_t opcode; //This commands spi opcode
243 uint8_t spi_type; //This commands spi type
244 uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1
245} OPCODE;
246
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000247/* Suggested opcode definition:
Dominik Geyerb46acba2008-05-16 12:55:55 +0000248 * Preop 1: Write Enable
249 * Preop 2: Write Status register enable
250 *
251 * OP 0: Write address
252 * OP 1: Read Address
253 * OP 2: ERASE block
254 * OP 3: Read Status register
255 * OP 4: Read ID
256 * OP 5: Write Status register
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000257 * OP 6: chip private (read JEDEC id)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000258 * OP 7: Chip erase
259 */
260typedef struct _OPCODES {
261 uint8_t preop[2];
262 OPCODE opcode[8];
263} OPCODES;
264
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000265static OPCODES *curopcodes = NULL;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000266
267/* HW access functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000268static uint32_t REGREAD32(int X)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000269{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000270 return mmio_readl(ich_spibar + X);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000271}
272
Uwe Hermann09e04f72009-05-16 22:36:00 +0000273static uint16_t REGREAD16(int X)
Stefan Reinauera9424d52008-06-27 16:28:34 +0000274{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000275 return mmio_readw(ich_spibar + X);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000276}
277
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000278static uint16_t REGREAD8(int X)
279{
280 return mmio_readb(ich_spibar + X);
281}
282
Stefan Taunerccd92a12011-07-01 00:39:01 +0000283#define REGWRITE32(off, val) mmio_writel(val, ich_spibar+(off))
284#define REGWRITE16(off, val) mmio_writew(val, ich_spibar+(off))
285#define REGWRITE8(off, val) mmio_writeb(val, ich_spibar+(off))
Dominik Geyerb46acba2008-05-16 12:55:55 +0000286
Dominik Geyerb46acba2008-05-16 12:55:55 +0000287/* Common SPI functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000288static int find_opcode(OPCODES *op, uint8_t opcode);
289static int find_preop(OPCODES *op, uint8_t preop);
FENG yu ningf041e9b2008-12-15 02:32:11 +0000290static int generate_opcodes(OPCODES * op);
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000291static int program_opcodes(OPCODES *op, int enable_undo);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000292static int run_opcode(const struct flashctx *flash, OPCODE op, uint32_t offset,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000293 uint8_t datalength, uint8_t * data);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000294
FENG yu ningf041e9b2008-12-15 02:32:11 +0000295/* for pairing opcodes with their required preop */
296struct preop_opcode_pair {
297 uint8_t preop;
298 uint8_t opcode;
299};
300
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000301/* List of opcodes which need preopcodes and matching preopcodes. Unused. */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000302const struct preop_opcode_pair pops[] = {
FENG yu ningf041e9b2008-12-15 02:32:11 +0000303 {JEDEC_WREN, JEDEC_BYTE_PROGRAM},
304 {JEDEC_WREN, JEDEC_SE}, /* sector erase */
305 {JEDEC_WREN, JEDEC_BE_52}, /* block erase */
306 {JEDEC_WREN, JEDEC_BE_D8}, /* block erase */
307 {JEDEC_WREN, JEDEC_CE_60}, /* chip erase */
308 {JEDEC_WREN, JEDEC_CE_C7}, /* chip erase */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000309 /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */
310 {JEDEC_WREN, JEDEC_WRSR},
FENG yu ningf041e9b2008-12-15 02:32:11 +0000311 {JEDEC_EWSR, JEDEC_WRSR},
312 {0,}
313};
314
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000315/* Reasonable default configuration. Needs ad-hoc modifications if we
316 * encounter unlisted opcodes. Fun.
317 */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000318static OPCODES O_ST_M25P = {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000319 {
320 JEDEC_WREN,
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000321 JEDEC_EWSR,
322 },
Dominik Geyerb46acba2008-05-16 12:55:55 +0000323 {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000324 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000325 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
David Hendricks15f539c2010-08-26 21:27:17 -0700326 {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000327 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
Carl-Daniel Hailfinger15aa7c62009-05-26 21:25:08 +0000328 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000329 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000330 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000331 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
332 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000333};
334
Helge Wagner738e2522010-10-05 22:06:05 +0000335/* List of opcodes with their corresponding spi_type
336 * It is used to reprogram the chipset OPCODE table on-the-fly if an opcode
337 * is needed which is currently not in the chipset OPCODE table
338 */
339static OPCODE POSSIBLE_OPCODES[] = {
340 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
341 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
342 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
343 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
344 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
345 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
346 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
347 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
348 {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Sector erase
349 {JEDEC_BE_52, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Block erase
350 {JEDEC_AAI_WORD_PROGRAM, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Auto Address Increment
351};
352
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000353static OPCODES O_EXISTING = {};
FENG yu ningc05a2952008-12-08 18:16:58 +0000354
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000355/* pretty printing functions */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000356static void prettyprint_opcodes(OPCODES *ops)
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000357{
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000358 OPCODE oc;
359 const char *t;
360 const char *a;
361 uint8_t i;
362 static const char *const spi_type[4] = {
363 "read w/o addr",
364 "write w/o addr",
365 "read w/ addr",
366 "write w/ addr"
367 };
368 static const char *const atomic_type[3] = {
369 "none",
370 " 0 ",
371 " 1 "
372 };
373
374 if (ops == NULL)
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000375 return;
376
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000377 msg_pdbg2(" OP Type Pre-OP\n");
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000378 for (i = 0; i < 8; i++) {
379 oc = ops->opcode[i];
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000380 t = (oc.spi_type > 3) ? "invalid" : spi_type[oc.spi_type];
381 a = (oc.atomic > 2) ? "invalid" : atomic_type[oc.atomic];
382 msg_pdbg2("op[%d]: 0x%02x, %s, %s\n", i, oc.opcode, t, a);
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000383 }
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000384 msg_pdbg2("Pre-OP 0: 0x%02x, Pre-OP 1: 0x%02x\n", ops->preop[0],
385 ops->preop[1]);
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000386}
387
Nico Huberd54e4f42017-03-23 23:45:47 +0100388#define _pprint_reg(bit, mask, off, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & mask) >> off)
389#define pprint_reg(reg, bit, val, sep) _pprint_reg(bit, reg##_##bit, reg##_##bit##_OFF, val, sep)
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000390
Stefan Tauner55206942011-06-11 09:53:22 +0000391static void prettyprint_ich9_reg_hsfs(uint16_t reg_val)
392{
393 msg_pdbg("HSFS: ");
394 pprint_reg(HSFS, FDONE, reg_val, ", ");
395 pprint_reg(HSFS, FCERR, reg_val, ", ");
396 pprint_reg(HSFS, AEL, reg_val, ", ");
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200397 switch (ich_generation) {
398 case CHIPSET_100_SERIES_SUNRISE_POINT:
399 case CHIPSET_C620_SERIES_LEWISBURG:
400 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +0200401 case CHIPSET_500_SERIES_TIGER_POINT:
Werner Zehe57d4e42022-01-03 09:44:29 +0100402 case CHIPSET_ELKHART_LAKE:
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200403 break;
404 default:
Nico Huberd54e4f42017-03-23 23:45:47 +0100405 pprint_reg(HSFS, BERASE, reg_val, ", ");
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200406 break;
Nico Huberd54e4f42017-03-23 23:45:47 +0100407 }
Stefan Tauner55206942011-06-11 09:53:22 +0000408 pprint_reg(HSFS, SCIP, reg_val, ", ");
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200409 switch (ich_generation) {
410 case CHIPSET_100_SERIES_SUNRISE_POINT:
411 case CHIPSET_C620_SERIES_LEWISBURG:
412 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +0200413 case CHIPSET_500_SERIES_TIGER_POINT:
Werner Zehe57d4e42022-01-03 09:44:29 +0100414 case CHIPSET_ELKHART_LAKE:
Nico Huberd54e4f42017-03-23 23:45:47 +0100415 pprint_reg(HSFS, PRR34_LOCKDN, reg_val, ", ");
416 pprint_reg(HSFS, WRSDIS, reg_val, ", ");
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200417 break;
418 default:
419 break;
Nico Huberd54e4f42017-03-23 23:45:47 +0100420 }
Stefan Tauner55206942011-06-11 09:53:22 +0000421 pprint_reg(HSFS, FDOPSS, reg_val, ", ");
422 pprint_reg(HSFS, FDV, reg_val, ", ");
423 pprint_reg(HSFS, FLOCKDN, reg_val, "\n");
424}
425
426static void prettyprint_ich9_reg_hsfc(uint16_t reg_val)
427{
428 msg_pdbg("HSFC: ");
429 pprint_reg(HSFC, FGO, reg_val, ", ");
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200430 switch (ich_generation) {
431 case CHIPSET_100_SERIES_SUNRISE_POINT:
432 case CHIPSET_C620_SERIES_LEWISBURG:
433 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +0200434 case CHIPSET_500_SERIES_TIGER_POINT:
Werner Zehe57d4e42022-01-03 09:44:29 +0100435 case CHIPSET_ELKHART_LAKE:
Nico Huberd54e4f42017-03-23 23:45:47 +0100436 _pprint_reg(HSFC, PCH100_HSFC_FCYCLE, PCH100_HSFC_FCYCLE_OFF, reg_val, ", ");
437 pprint_reg(HSFC, WET, reg_val, ", ");
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200438 break;
439 default:
440 pprint_reg(HSFC, FCYCLE, reg_val, ", ");
441 break;
Nico Huberd54e4f42017-03-23 23:45:47 +0100442 }
Stefan Tauner55206942011-06-11 09:53:22 +0000443 pprint_reg(HSFC, FDBC, reg_val, ", ");
444 pprint_reg(HSFC, SME, reg_val, "\n");
445}
446
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000447static void prettyprint_ich9_reg_ssfs(uint32_t reg_val)
448{
449 msg_pdbg("SSFS: ");
450 pprint_reg(SSFS, SCIP, reg_val, ", ");
451 pprint_reg(SSFS, FDONE, reg_val, ", ");
452 pprint_reg(SSFS, FCERR, reg_val, ", ");
453 pprint_reg(SSFS, AEL, reg_val, "\n");
454}
455
456static void prettyprint_ich9_reg_ssfc(uint32_t reg_val)
457{
458 msg_pdbg("SSFC: ");
459 pprint_reg(SSFC, SCGO, reg_val, ", ");
460 pprint_reg(SSFC, ACS, reg_val, ", ");
461 pprint_reg(SSFC, SPOP, reg_val, ", ");
462 pprint_reg(SSFC, COP, reg_val, ", ");
463 pprint_reg(SSFC, DBC, reg_val, ", ");
464 pprint_reg(SSFC, SME, reg_val, ", ");
465 pprint_reg(SSFC, SCF, reg_val, "\n");
466}
467
Nico Huberd54e4f42017-03-23 23:45:47 +0100468static void prettyprint_pch100_reg_dlock(const uint32_t reg_val)
469{
470 msg_pdbg("DLOCK: ");
471 pprint_reg(DLOCK, BMWAG_LOCKDN, reg_val, ", ");
472 pprint_reg(DLOCK, BMRAG_LOCKDN, reg_val, ", ");
473 pprint_reg(DLOCK, SBMWAG_LOCKDN, reg_val, ", ");
474 pprint_reg(DLOCK, SBMRAG_LOCKDN, reg_val, ",\n ");
475 pprint_reg(DLOCK, PR0_LOCKDN, reg_val, ", ");
476 pprint_reg(DLOCK, PR1_LOCKDN, reg_val, ", ");
477 pprint_reg(DLOCK, PR2_LOCKDN, reg_val, ", ");
478 pprint_reg(DLOCK, PR3_LOCKDN, reg_val, ", ");
479 pprint_reg(DLOCK, PR4_LOCKDN, reg_val, ",\n ");
480 pprint_reg(DLOCK, SSEQ_LOCKDN, reg_val, "\n");
481}
482
483static struct {
484 size_t reg_ssfsc;
485 size_t reg_preop;
486 size_t reg_optype;
487 size_t reg_opmenu;
488} swseq_data;
489
Helge Wagner738e2522010-10-05 22:06:05 +0000490static uint8_t lookup_spi_type(uint8_t opcode)
491{
Nico Huber519be662018-12-23 20:03:35 +0100492 unsigned int a;
Helge Wagner738e2522010-10-05 22:06:05 +0000493
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000494 for (a = 0; a < ARRAY_SIZE(POSSIBLE_OPCODES); a++) {
Helge Wagner738e2522010-10-05 22:06:05 +0000495 if (POSSIBLE_OPCODES[a].opcode == opcode)
496 return POSSIBLE_OPCODES[a].spi_type;
497 }
498
499 return 0xFF;
500}
501
502static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt)
503{
504 uint8_t spi_type;
505
506 spi_type = lookup_spi_type(opcode);
507 if (spi_type > 3) {
508 /* Try to guess spi type from read/write sizes.
509 * The following valid writecnt/readcnt combinations exist:
510 * writecnt = 4, readcnt >= 0
511 * writecnt = 1, readcnt >= 0
512 * writecnt >= 4, readcnt = 0
513 * writecnt >= 1, readcnt = 0
514 * writecnt >= 1 is guaranteed for all commands.
515 */
516 if (readcnt == 0)
517 /* if readcnt=0 and writecount >= 4, we don't know if it is WRITE_NO_ADDRESS
518 * or WRITE_WITH_ADDRESS. But if we use WRITE_NO_ADDRESS and the first 3 data
519 * bytes are actual the address, they go to the bus anyhow
520 */
521 spi_type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
522 else if (writecnt == 1) // and readcnt is > 0
523 spi_type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
524 else if (writecnt == 4) // and readcnt is > 0
525 spi_type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
Stefan Taunerdc704ed2012-05-06 15:11:26 +0000526 else // we have an invalid case
527 return SPI_INVALID_LENGTH;
Helge Wagner738e2522010-10-05 22:06:05 +0000528 }
Stefan Taunerdc704ed2012-05-06 15:11:26 +0000529 int oppos = 2; // use original JEDEC_BE_D8 offset
530 curopcodes->opcode[oppos].opcode = opcode;
531 curopcodes->opcode[oppos].spi_type = spi_type;
532 program_opcodes(curopcodes, 0);
533 oppos = find_opcode(curopcodes, opcode);
Stefan Taunerd94d25d2012-07-28 03:17:15 +0000534 msg_pdbg2("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos);
Stefan Taunerdc704ed2012-05-06 15:11:26 +0000535 return oppos;
Helge Wagner738e2522010-10-05 22:06:05 +0000536}
537
Uwe Hermann09e04f72009-05-16 22:36:00 +0000538static int find_opcode(OPCODES *op, uint8_t opcode)
FENG yu ningc05a2952008-12-08 18:16:58 +0000539{
540 int a;
541
Stefan Tauner50e7c602011-11-08 10:55:54 +0000542 if (op == NULL) {
543 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
544 return -1;
545 }
546
FENG yu ningc05a2952008-12-08 18:16:58 +0000547 for (a = 0; a < 8; a++) {
548 if (op->opcode[a].opcode == opcode)
549 return a;
550 }
551
552 return -1;
553}
554
Uwe Hermann09e04f72009-05-16 22:36:00 +0000555static int find_preop(OPCODES *op, uint8_t preop)
FENG yu ningc05a2952008-12-08 18:16:58 +0000556{
557 int a;
558
Stefan Tauner50e7c602011-11-08 10:55:54 +0000559 if (op == NULL) {
560 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
561 return -1;
562 }
563
FENG yu ningc05a2952008-12-08 18:16:58 +0000564 for (a = 0; a < 2; a++) {
565 if (op->preop[a] == preop)
566 return a;
567 }
568
569 return -1;
570}
571
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000572/* Create a struct OPCODES based on what we find in the locked down chipset. */
FENG yu ningf041e9b2008-12-15 02:32:11 +0000573static int generate_opcodes(OPCODES * op)
FENG yu ningc05a2952008-12-08 18:16:58 +0000574{
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000575 int a;
FENG yu ningc05a2952008-12-08 18:16:58 +0000576 uint16_t preop, optype;
577 uint32_t opmenu[2];
FENG yu ningc05a2952008-12-08 18:16:58 +0000578
579 if (op == NULL) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000580 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
FENG yu ningc05a2952008-12-08 18:16:58 +0000581 return -1;
582 }
583
Stefan Taunera8d838d2011-11-06 23:51:09 +0000584 switch (ich_generation) {
585 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000586 case CHIPSET_TUNNEL_CREEK:
587 case CHIPSET_CENTERTON:
FENG yu ningc05a2952008-12-08 18:16:58 +0000588 preop = REGREAD16(ICH7_REG_PREOP);
589 optype = REGREAD16(ICH7_REG_OPTYPE);
590 opmenu[0] = REGREAD32(ICH7_REG_OPMENU);
591 opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4);
592 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000593 case CHIPSET_ICH8:
594 default: /* Future version might behave the same */
Nico Huberd54e4f42017-03-23 23:45:47 +0100595 preop = REGREAD16(swseq_data.reg_preop);
596 optype = REGREAD16(swseq_data.reg_optype);
597 opmenu[0] = REGREAD32(swseq_data.reg_opmenu);
598 opmenu[1] = REGREAD32(swseq_data.reg_opmenu + 4);
FENG yu ningc05a2952008-12-08 18:16:58 +0000599 break;
FENG yu ningc05a2952008-12-08 18:16:58 +0000600 }
601
602 op->preop[0] = (uint8_t) preop;
603 op->preop[1] = (uint8_t) (preop >> 8);
604
605 for (a = 0; a < 8; a++) {
606 op->opcode[a].spi_type = (uint8_t) (optype & 0x3);
607 optype >>= 2;
608 }
609
610 for (a = 0; a < 4; a++) {
611 op->opcode[a].opcode = (uint8_t) (opmenu[0] & 0xff);
612 opmenu[0] >>= 8;
613 }
614
615 for (a = 4; a < 8; a++) {
616 op->opcode[a].opcode = (uint8_t) (opmenu[1] & 0xff);
617 opmenu[1] >>= 8;
618 }
619
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000620 /* No preopcodes used by default. */
621 for (a = 0; a < 8; a++)
FENG yu ningc05a2952008-12-08 18:16:58 +0000622 op->opcode[a].atomic = 0;
623
FENG yu ningc05a2952008-12-08 18:16:58 +0000624 return 0;
625}
626
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000627static int program_opcodes(OPCODES *op, int enable_undo)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000628{
629 uint8_t a;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000630 uint16_t preop, optype;
631 uint32_t opmenu[2];
Dominik Geyerb46acba2008-05-16 12:55:55 +0000632
633 /* Program Prefix Opcodes */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000634 /* 0:7 Prefix Opcode 1 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000635 preop = (op->preop[0]);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000636 /* 8:16 Prefix Opcode 2 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000637 preop |= ((uint16_t) op->preop[1]) << 8;
Uwe Hermann394131e2008-10-18 21:14:13 +0000638
Stefan Reinauera9424d52008-06-27 16:28:34 +0000639 /* Program Opcode Types 0 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000640 optype = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000641 for (a = 0; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000642 optype |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000643 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000644
Stefan Reinauera9424d52008-06-27 16:28:34 +0000645 /* Program Allowable Opcodes 0 - 3 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000646 opmenu[0] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000647 for (a = 0; a < 4; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000648 opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000649 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000650
Stefan Tauner92d6a862013-10-25 00:33:37 +0000651 /* Program Allowable Opcodes 4 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000652 opmenu[1] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000653 for (a = 4; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000654 opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000655 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000656
Stefan Taunerd94d25d2012-07-28 03:17:15 +0000657 msg_pdbg2("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]);
Stefan Taunera8d838d2011-11-06 23:51:09 +0000658 switch (ich_generation) {
659 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000660 case CHIPSET_TUNNEL_CREEK:
661 case CHIPSET_CENTERTON:
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000662 /* Register undo only for enable_undo=1, i.e. first call. */
663 if (enable_undo) {
664 rmmio_valw(ich_spibar + ICH7_REG_PREOP);
665 rmmio_valw(ich_spibar + ICH7_REG_OPTYPE);
666 rmmio_vall(ich_spibar + ICH7_REG_OPMENU);
667 rmmio_vall(ich_spibar + ICH7_REG_OPMENU + 4);
668 }
669 mmio_writew(preop, ich_spibar + ICH7_REG_PREOP);
670 mmio_writew(optype, ich_spibar + ICH7_REG_OPTYPE);
671 mmio_writel(opmenu[0], ich_spibar + ICH7_REG_OPMENU);
672 mmio_writel(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000673 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000674 case CHIPSET_ICH8:
675 default: /* Future version might behave the same */
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000676 /* Register undo only for enable_undo=1, i.e. first call. */
677 if (enable_undo) {
Nico Huberd54e4f42017-03-23 23:45:47 +0100678 rmmio_valw(ich_spibar + swseq_data.reg_preop);
679 rmmio_valw(ich_spibar + swseq_data.reg_optype);
680 rmmio_vall(ich_spibar + swseq_data.reg_opmenu);
681 rmmio_vall(ich_spibar + swseq_data.reg_opmenu + 4);
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000682 }
Nico Huberd54e4f42017-03-23 23:45:47 +0100683 mmio_writew(preop, ich_spibar + swseq_data.reg_preop);
684 mmio_writew(optype, ich_spibar + swseq_data.reg_optype);
685 mmio_writel(opmenu[0], ich_spibar + swseq_data.reg_opmenu);
686 mmio_writel(opmenu[1], ich_spibar + swseq_data.reg_opmenu + 4);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000687 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000688 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000689
690 return 0;
691}
692
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000693/*
Stefan Tauner50e7c602011-11-08 10:55:54 +0000694 * Returns -1 if at least one mandatory opcode is inaccessible, 0 otherwise.
695 * FIXME: this should also check for
696 * - at least one probing opcode (RDID (incl. AT25F variants?), REMS, RES?)
697 * - at least one erasing opcode (lots.)
698 * - at least one program opcode (BYTE_PROGRAM, AAI_WORD_PROGRAM, ...?)
699 * - necessary preops? (EWSR, WREN, ...?)
700 */
Richard Hughes93e16252018-12-19 11:54:47 +0000701static int ich_missing_opcodes(void)
Stefan Tauner50e7c602011-11-08 10:55:54 +0000702{
703 uint8_t ops[] = {
704 JEDEC_READ,
705 JEDEC_RDSR,
706 0
707 };
708 int i = 0;
709 while (ops[i] != 0) {
710 msg_pspew("checking for opcode 0x%02x\n", ops[i]);
711 if (find_opcode(curopcodes, ops[i]) == -1)
712 return -1;
713 i++;
714 }
715 return 0;
716}
717
718/*
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000719 * Try to set BBAR (BIOS Base Address Register), but read back the value in case
720 * it didn't stick.
721 */
Stefan Taunera8d838d2011-11-06 23:51:09 +0000722static void ich_set_bbar(uint32_t min_addr)
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000723{
Stefan Taunere27b2d42011-07-01 00:39:09 +0000724 int bbar_off;
Stefan Tauner7783f312011-09-17 21:21:42 +0000725 switch (ich_generation) {
Stefan Taunera8d838d2011-11-06 23:51:09 +0000726 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000727 case CHIPSET_TUNNEL_CREEK:
728 case CHIPSET_CENTERTON:
Stefan Taunere27b2d42011-07-01 00:39:09 +0000729 bbar_off = 0x50;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000730 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000731 case CHIPSET_ICH8:
Duncan Laurie4095ed72014-08-20 15:39:32 +0000732 case CHIPSET_BAYTRAIL:
733 msg_pdbg("BBAR offset is unknown!\n");
Stefan Tauner7783f312011-09-17 21:21:42 +0000734 return;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000735 case CHIPSET_ICH9:
Stefan Tauner7783f312011-09-17 21:21:42 +0000736 default: /* Future version might behave the same */
Stefan Taunere27b2d42011-07-01 00:39:09 +0000737 bbar_off = ICH9_REG_BBAR;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000738 break;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000739 }
Elyes HAOUAS124ef382018-03-27 12:15:09 +0200740
Stefan Taunere27b2d42011-07-01 00:39:09 +0000741 ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & ~BBAR_MASK;
742 if (ichspi_bbar) {
743 msg_pdbg("Reserved bits in BBAR not zero: 0x%08x\n",
744 ichspi_bbar);
745 }
746 min_addr &= BBAR_MASK;
747 ichspi_bbar |= min_addr;
748 rmmio_writel(ichspi_bbar, ich_spibar + bbar_off);
749 ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & BBAR_MASK;
750
751 /* We don't have any option except complaining. And if the write
752 * failed, the restore will fail as well, so no problem there.
753 */
754 if (ichspi_bbar != min_addr)
Stefan Tauner7783f312011-09-17 21:21:42 +0000755 msg_perr("Setting BBAR to 0x%08x failed! New value: 0x%08x.\n",
756 min_addr, ichspi_bbar);
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000757}
758
Stefan Tauner8b391b82011-08-09 01:49:34 +0000759/* Read len bytes from the fdata/spid register into the data array.
760 *
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000761 * Note that using len > flash->mst->spi.max_data_read will return garbage or
Stefan Tauner8b391b82011-08-09 01:49:34 +0000762 * may even crash.
763 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000764static void ich_read_data(uint8_t *data, int len, int reg0_off)
Elyes HAOUAS124ef382018-03-27 12:15:09 +0200765{
Stefan Tauner8b391b82011-08-09 01:49:34 +0000766 int i;
767 uint32_t temp32 = 0;
768
769 for (i = 0; i < len; i++) {
770 if ((i % 4) == 0)
771 temp32 = REGREAD32(reg0_off + i);
772
773 data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
774 }
775}
776
777/* Fill len bytes from the data array into the fdata/spid registers.
778 *
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000779 * Note that using len > flash->mst->spi.max_data_write will trash the registers
Stefan Tauner8b391b82011-08-09 01:49:34 +0000780 * following the data registers.
781 */
782static void ich_fill_data(const uint8_t *data, int len, int reg0_off)
783{
784 uint32_t temp32 = 0;
785 int i;
786
787 if (len <= 0)
788 return;
789
790 for (i = 0; i < len; i++) {
791 if ((i % 4) == 0)
792 temp32 = 0;
793
794 temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
795
796 if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
797 REGWRITE32(reg0_off + (i - (i % 4)), temp32);
798 }
799 i--;
800 if ((i % 4) != 3) /* Write remaining data to regs. */
801 REGWRITE32(reg0_off + (i - (i % 4)), temp32);
802}
803
FENG yu ningf041e9b2008-12-15 02:32:11 +0000804/* This function generates OPCODES from or programs OPCODES to ICH according to
805 * the chipset's SPI configuration lock.
FENG yu ningc05a2952008-12-08 18:16:58 +0000806 *
FENG yu ningf041e9b2008-12-15 02:32:11 +0000807 * It should be called before ICH sends any spi command.
FENG yu ningc05a2952008-12-08 18:16:58 +0000808 */
Michael Karchera4448d92010-07-22 18:04:15 +0000809static int ich_init_opcodes(void)
FENG yu ningc05a2952008-12-08 18:16:58 +0000810{
811 int rc = 0;
812 OPCODES *curopcodes_done;
813
814 if (curopcodes)
815 return 0;
816
817 if (ichspi_lock) {
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000818 msg_pdbg("Reading OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000819 curopcodes_done = &O_EXISTING;
FENG yu ningf041e9b2008-12-15 02:32:11 +0000820 rc = generate_opcodes(curopcodes_done);
FENG yu ningc05a2952008-12-08 18:16:58 +0000821 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000822 msg_pdbg("Programming OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000823 curopcodes_done = &O_ST_M25P;
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000824 rc = program_opcodes(curopcodes_done, 1);
FENG yu ningc05a2952008-12-08 18:16:58 +0000825 }
826
827 if (rc) {
828 curopcodes = NULL;
Sean Nelson316a29f2010-05-07 20:09:04 +0000829 msg_perr("failed\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000830 return 1;
831 } else {
832 curopcodes = curopcodes_done;
Sean Nelson316a29f2010-05-07 20:09:04 +0000833 msg_pdbg("done\n");
Stefan Tauner8b391b82011-08-09 01:49:34 +0000834 prettyprint_opcodes(curopcodes);
FENG yu ningc05a2952008-12-08 18:16:58 +0000835 return 0;
836 }
837}
838
Stefan Reinauer43119562008-11-02 19:51:50 +0000839static int ich7_run_opcode(OPCODE op, uint32_t offset,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000840 uint8_t datalength, uint8_t * data, int maxdata)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000841{
Felix Singer8cfc7372022-08-19 03:10:29 +0200842 bool write_cmd = false;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000843 int timeout;
Stefan Tauner8b391b82011-08-09 01:49:34 +0000844 uint32_t temp32;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000845 uint16_t temp16;
Stefan Reinauer43119562008-11-02 19:51:50 +0000846 uint64_t opmenu;
847 int opcode_index;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000848
849 /* Is it a write command? */
850 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
851 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
Felix Singer8cfc7372022-08-19 03:10:29 +0200852 write_cmd = true;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000853 }
854
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000855 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
856 while ((REGREAD16(ICH7_REG_SPIS) & SPIS_SCIP) && --timeout) {
857 programmer_delay(10);
858 }
859 if (!timeout) {
860 msg_perr("Error: SCIP never cleared!\n");
861 return 1;
862 }
863
Stefan Tauner10b3e222011-07-01 00:39:23 +0000864 /* Program offset in flash into SPIA while preserving reserved bits. */
865 temp32 = REGREAD32(ICH7_REG_SPIA) & ~0x00FFFFFF;
866 REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF) | temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000867
Stefan Tauner10b3e222011-07-01 00:39:23 +0000868 /* Program data into SPID0 to N */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000869 if (write_cmd && (datalength != 0))
870 ich_fill_data(data, datalength, ICH7_REG_SPID0);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000871
872 /* Assemble SPIS */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000873 temp16 = REGREAD16(ICH7_REG_SPIS);
874 /* keep reserved bits */
875 temp16 &= SPIS_RESERVED_MASK;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000876 /* clear error status registers */
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000877 temp16 |= (SPIS_CDS | SPIS_FCERR);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000878 REGWRITE16(ICH7_REG_SPIS, temp16);
879
880 /* Assemble SPIC */
881 temp16 = 0;
882
883 if (datalength != 0) {
884 temp16 |= SPIC_DS;
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000885 temp16 |= ((uint32_t) ((datalength - 1) & (maxdata - 1))) << 8;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000886 }
887
888 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000889 opmenu = REGREAD32(ICH7_REG_OPMENU);
890 opmenu |= ((uint64_t)REGREAD32(ICH7_REG_OPMENU + 4)) << 32;
891
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000892 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
893 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000894 break;
895 }
896 opmenu >>= 8;
897 }
898 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000899 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +0000900 return 1;
901 }
902 temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000903
Michael Karcher136125a2011-04-29 22:11:36 +0000904 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
905 /* Handle Atomic. Atomic commands include three steps:
906 - sending the preop (mainly EWSR or WREN)
907 - sending the main command
908 - waiting for the busy bit (WIP) to be cleared
909 This means the timeout must be sufficient for chip erase
910 of slow high-capacity chips.
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000911 */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000912 switch (op.atomic) {
913 case 2:
914 /* Select second preop. */
915 temp16 |= SPIC_SPOP;
Richard Hughesdb7482b2018-12-19 12:04:30 +0000916 /* Fall through. */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000917 case 1:
918 /* Atomic command (preop+op) */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000919 temp16 |= SPIC_ACS;
Michael Karcher136125a2011-04-29 22:11:36 +0000920 timeout = 100 * 1000 * 60; /* 60 seconds */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000921 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000922 }
923
924 /* Start */
925 temp16 |= SPIC_SCGO;
926
927 /* write it */
928 REGWRITE16(ICH7_REG_SPIC, temp16);
929
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000930 /* Wait for Cycle Done Status or Flash Cycle Error. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000931 while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) &&
932 --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000933 programmer_delay(10);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000934 }
935 if (!timeout) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000936 msg_perr("timeout, ICH7_REG_SPIS=0x%04x\n",
937 REGREAD16(ICH7_REG_SPIS));
938 return 1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000939 }
940
Sean Nelson316a29f2010-05-07 20:09:04 +0000941 /* FIXME: make sure we do not needlessly cause transaction errors. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000942 temp16 = REGREAD16(ICH7_REG_SPIS);
943 if (temp16 & SPIS_FCERR) {
Stefan Tauner8ed29342011-04-29 23:53:09 +0000944 msg_perr("Transaction error!\n");
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000945 /* keep reserved bits */
946 temp16 &= SPIS_RESERVED_MASK;
947 REGWRITE16(ICH7_REG_SPIS, temp16 | SPIS_FCERR);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000948 return 1;
949 }
950
Stefan Tauner8b391b82011-08-09 01:49:34 +0000951 if ((!write_cmd) && (datalength != 0))
952 ich_read_data(data, datalength, ICH7_REG_SPID0);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000953
954 return 0;
955}
956
Stefan Reinauer43119562008-11-02 19:51:50 +0000957static int ich9_run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000958 uint8_t datalength, uint8_t * data)
959{
Felix Singer8cfc7372022-08-19 03:10:29 +0200960 bool write_cmd = false;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000961 int timeout;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000962 uint32_t temp32;
Stefan Reinauer43119562008-11-02 19:51:50 +0000963 uint64_t opmenu;
964 int opcode_index;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000965
966 /* Is it a write command? */
967 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
968 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
Felix Singer8cfc7372022-08-19 03:10:29 +0200969 write_cmd = true;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000970 }
971
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000972 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
Nico Huberd54e4f42017-03-23 23:45:47 +0100973 while ((REGREAD8(swseq_data.reg_ssfsc) & SSFS_SCIP) && --timeout) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000974 programmer_delay(10);
975 }
976 if (!timeout) {
977 msg_perr("Error: SCIP never cleared!\n");
978 return 1;
979 }
980
Stefan Tauner10b3e222011-07-01 00:39:23 +0000981 /* Program offset in flash into FADDR while preserve the reserved bits
Martin Rothf6c1cb12022-03-15 10:55:25 -0600982 * and clearing the 25. address bit which is only usable in hwseq. */
Stefan Tauner10b3e222011-07-01 00:39:23 +0000983 temp32 = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF;
984 REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF) | temp32);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000985
986 /* Program data into FDATA0 to N */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000987 if (write_cmd && (datalength != 0))
988 ich_fill_data(data, datalength, ICH9_REG_FDATA0);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000989
990 /* Assemble SSFS + SSFC */
Nico Huberd54e4f42017-03-23 23:45:47 +0100991 temp32 = REGREAD32(swseq_data.reg_ssfsc);
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000992 /* Keep reserved bits only */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000993 temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000994 /* Clear cycle done and cycle error status registers */
995 temp32 |= (SSFS_FDONE | SSFS_FCERR);
Nico Huberd54e4f42017-03-23 23:45:47 +0100996 REGWRITE32(swseq_data.reg_ssfsc, temp32);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000997
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000998 /* Use 20 MHz */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000999 temp32 |= SSFC_SCF_20MHZ;
1000
Stefan Taunerc0aaf952011-05-19 02:58:17 +00001001 /* Set data byte count (DBC) and data cycle bit (DS) */
Dominik Geyerb46acba2008-05-16 12:55:55 +00001002 if (datalength != 0) {
1003 uint32_t datatemp;
1004 temp32 |= SSFC_DS;
Stefan Tauner0c1ec452011-06-11 09:53:09 +00001005 datatemp = ((((uint32_t)datalength - 1) << SSFC_DBC_OFF) &
1006 SSFC_DBC);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001007 temp32 |= datatemp;
1008 }
1009
1010 /* Select opcode */
Nico Huber8b2152d2017-08-31 13:18:49 +02001011 opmenu = REGREAD32(swseq_data.reg_opmenu);
1012 opmenu |= ((uint64_t)REGREAD32(swseq_data.reg_opmenu + 4)) << 32;
Stefan Reinauer43119562008-11-02 19:51:50 +00001013
Uwe Hermann7b2969b2009-04-15 10:52:49 +00001014 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
1015 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +00001016 break;
1017 }
1018 opmenu >>= 8;
1019 }
1020 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001021 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +00001022 return 1;
1023 }
1024 temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001025
Michael Karcher136125a2011-04-29 22:11:36 +00001026 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
1027 /* Handle Atomic. Atomic commands include three steps:
1028 - sending the preop (mainly EWSR or WREN)
1029 - sending the main command
1030 - waiting for the busy bit (WIP) to be cleared
1031 This means the timeout must be sufficient for chip erase
1032 of slow high-capacity chips.
Stefan Taunerc0aaf952011-05-19 02:58:17 +00001033 */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001034 switch (op.atomic) {
1035 case 2:
1036 /* Select second preop. */
1037 temp32 |= SSFC_SPOP;
Richard Hughesdb7482b2018-12-19 12:04:30 +00001038 /* Fall through. */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001039 case 1:
1040 /* Atomic command (preop+op) */
Dominik Geyerb46acba2008-05-16 12:55:55 +00001041 temp32 |= SSFC_ACS;
Michael Karcher136125a2011-04-29 22:11:36 +00001042 timeout = 100 * 1000 * 60; /* 60 seconds */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001043 break;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001044 }
1045
1046 /* Start */
1047 temp32 |= SSFC_SCGO;
1048
1049 /* write it */
Nico Huberd54e4f42017-03-23 23:45:47 +01001050 REGWRITE32(swseq_data.reg_ssfsc, temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001051
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001052 /* Wait for Cycle Done Status or Flash Cycle Error. */
Nico Huberd54e4f42017-03-23 23:45:47 +01001053 while (((REGREAD32(swseq_data.reg_ssfsc) & (SSFS_FDONE | SSFS_FCERR)) == 0) &&
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001054 --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +00001055 programmer_delay(10);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +00001056 }
1057 if (!timeout) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001058 msg_perr("timeout, REG_SSFS=0x%08x\n",
1059 REGREAD32(swseq_data.reg_ssfsc));
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001060 return 1;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001061 }
1062
Sean Nelson316a29f2010-05-07 20:09:04 +00001063 /* FIXME make sure we do not needlessly cause transaction errors. */
Nico Huberd54e4f42017-03-23 23:45:47 +01001064 temp32 = REGREAD32(swseq_data.reg_ssfsc);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001065 if (temp32 & SSFS_FCERR) {
Stefan Tauner8ed29342011-04-29 23:53:09 +00001066 msg_perr("Transaction error!\n");
Stefan Tauner2a8b2622011-06-11 09:53:16 +00001067 prettyprint_ich9_reg_ssfs(temp32);
1068 prettyprint_ich9_reg_ssfc(temp32);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001069 /* keep reserved bits */
1070 temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
1071 /* Clear the transaction error. */
Nico Huberd54e4f42017-03-23 23:45:47 +01001072 REGWRITE32(swseq_data.reg_ssfsc, temp32 | SSFS_FCERR);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001073 return 1;
1074 }
1075
Stefan Tauner8b391b82011-08-09 01:49:34 +00001076 if ((!write_cmd) && (datalength != 0))
1077 ich_read_data(data, datalength, ICH9_REG_FDATA0);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001078
1079 return 0;
1080}
1081
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001082static int run_opcode(const struct flashctx *flash, OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +00001083 uint8_t datalength, uint8_t * data)
1084{
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001085 /* max_data_read == max_data_write for all Intel/VIA SPI masters */
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001086 uint8_t maxlength = flash->mst->spi.max_data_read;
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001087
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +00001088 if (ich_generation == CHIPSET_ICH_UNKNOWN) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001089 msg_perr("%s: unsupported chipset\n", __func__);
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001090 return -1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +00001091 }
Stefan Reinauera9424d52008-06-27 16:28:34 +00001092
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001093 if (datalength > maxlength) {
1094 msg_perr("%s: Internal command size error for "
1095 "opcode 0x%02x, got datalength=%i, want <=%i\n",
1096 __func__, op.opcode, datalength, maxlength);
1097 return SPI_INVALID_LENGTH;
1098 }
1099
Stefan Taunera8d838d2011-11-06 23:51:09 +00001100 switch (ich_generation) {
1101 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +00001102 case CHIPSET_TUNNEL_CREEK:
1103 case CHIPSET_CENTERTON:
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001104 return ich7_run_opcode(op, offset, datalength, data, maxlength);
Stefan Taunera8d838d2011-11-06 23:51:09 +00001105 case CHIPSET_ICH8:
1106 default: /* Future version might behave the same */
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001107 return ich9_run_opcode(op, offset, datalength, data);
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001108 }
Stefan Reinauera9424d52008-06-27 16:28:34 +00001109}
1110
Edward O'Callaghan5eca4272020-04-12 17:27:53 +10001111static int ich_spi_send_command(const struct flashctx *flash, unsigned int writecnt,
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001112 unsigned int readcnt,
1113 const unsigned char *writearr,
1114 unsigned char *readarr)
Dominik Geyerb46acba2008-05-16 12:55:55 +00001115{
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001116 int result;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001117 int opcode_index = -1;
1118 const unsigned char cmd = *writearr;
1119 OPCODE *opcode;
1120 uint32_t addr = 0;
1121 uint8_t *data;
1122 int count;
1123
Dominik Geyerb46acba2008-05-16 12:55:55 +00001124 /* find cmd in opcodes-table */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001125 opcode_index = find_opcode(curopcodes, cmd);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001126 if (opcode_index == -1) {
Helge Wagner738e2522010-10-05 22:06:05 +00001127 if (!ichspi_lock)
1128 opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt);
Stefan Taunerdc704ed2012-05-06 15:11:26 +00001129 if (opcode_index == SPI_INVALID_LENGTH) {
1130 msg_pdbg("OPCODE 0x%02x has unsupported length, will not execute.\n", cmd);
1131 return SPI_INVALID_LENGTH;
1132 } else if (opcode_index == -1) {
Stefan Tauner355cbfd2011-05-28 02:37:14 +00001133 msg_pdbg("Invalid OPCODE 0x%02x, will not execute.\n",
1134 cmd);
Helge Wagner738e2522010-10-05 22:06:05 +00001135 return SPI_INVALID_OPCODE;
1136 }
Dominik Geyerb46acba2008-05-16 12:55:55 +00001137 }
1138
1139 opcode = &(curopcodes->opcode[opcode_index]);
1140
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001141 /* The following valid writecnt/readcnt combinations exist:
1142 * writecnt = 4, readcnt >= 0
1143 * writecnt = 1, readcnt >= 0
1144 * writecnt >= 4, readcnt = 0
1145 * writecnt >= 1, readcnt = 0
1146 * writecnt >= 1 is guaranteed for all commands.
1147 */
1148 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) &&
1149 (writecnt != 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001150 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001151 "0x%02x, got writecnt=%i, want =4\n", __func__, cmd,
1152 writecnt);
1153 return SPI_INVALID_LENGTH;
1154 }
1155 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_NO_ADDRESS) &&
1156 (writecnt != 1)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001157 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001158 "0x%02x, got writecnt=%i, want =1\n", __func__, cmd,
1159 writecnt);
1160 return SPI_INVALID_LENGTH;
1161 }
1162 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) &&
1163 (writecnt < 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001164 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001165 "0x%02x, got writecnt=%i, want >=4\n", __func__, cmd,
1166 writecnt);
1167 return SPI_INVALID_LENGTH;
1168 }
1169 if (((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1170 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) &&
1171 (readcnt)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001172 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001173 "0x%02x, got readcnt=%i, want =0\n", __func__, cmd,
1174 readcnt);
1175 return SPI_INVALID_LENGTH;
1176 }
1177
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001178 /* Translate read/write array/count.
1179 * The maximum data length is identical for the maximum read length and
1180 * for the maximum write length excluding opcode and address. Opcode and
1181 * address are stored in separate registers, not in the data registers
1182 * and are thus not counted towards data length. The only exception
1183 * applies if the opcode definition (un)intentionally classifies said
1184 * opcode incorrectly as non-address opcode or vice versa. */
Dominik Geyerb46acba2008-05-16 12:55:55 +00001185 if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001186 data = (uint8_t *) (writearr + 1);
1187 count = writecnt - 1;
1188 } else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
1189 data = (uint8_t *) (writearr + 4);
1190 count = writecnt - 4;
1191 } else {
1192 data = (uint8_t *) readarr;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001193 count = readcnt;
1194 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001195
Nico Hubered098d62017-04-21 23:47:08 +02001196 /* if opcode-type requires an address */
1197 if (cmd == JEDEC_REMS || cmd == JEDEC_RES) {
1198 addr = ichspi_bbar;
1199 } else if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS ||
1200 opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
1201 /* BBAR may cut part of the chip off at the lower end. */
1202 const uint32_t valid_base = ichspi_bbar & ((flash->chip->total_size * 1024) - 1);
1203 const uint32_t addr_offset = ichspi_bbar - valid_base;
1204 /* Highest address we can program is (2^24 - 1). */
1205 const uint32_t valid_end = (1 << 24) - addr_offset;
1206
1207 addr = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
1208 const uint32_t addr_end = addr + count;
1209
1210 if (addr < valid_base ||
1211 addr_end < addr || /* integer overflow check */
1212 addr_end > valid_end) {
1213 msg_perr("%s: Addressed region 0x%06x-0x%06x not in allowed range 0x%06x-0x%06x\n",
1214 __func__, addr, addr_end - 1, valid_base, valid_end - 1);
1215 return SPI_INVALID_ADDRESS;
1216 }
1217 addr += addr_offset;
1218 }
1219
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001220 result = run_opcode(flash, *opcode, addr, count, data);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001221 if (result) {
Stefan Tauner8ed29342011-04-29 23:53:09 +00001222 msg_pdbg("Running OPCODE 0x%02x failed ", opcode->opcode);
1223 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1224 (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS)) {
1225 msg_pdbg("at address 0x%06x ", addr);
1226 }
1227 msg_pdbg("(payload length was %d).\n", count);
1228
1229 /* Print out the data array if it contains data to write.
1230 * Errors are detected before the received data is read back into
1231 * the array so it won't make sense to print it then. */
1232 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1233 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) {
1234 int i;
1235 msg_pspew("The data was:\n");
Stefan Taunerf382e352011-11-08 11:55:24 +00001236 for (i = 0; i < count; i++){
Stefan Tauner8ed29342011-04-29 23:53:09 +00001237 msg_pspew("%3d: 0x%02x\n", i, data[i]);
1238 }
1239 }
Dominik Geyerb46acba2008-05-16 12:55:55 +00001240 }
1241
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001242 return result;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001243}
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001244
Stefan Tauner50e7c602011-11-08 10:55:54 +00001245static struct hwseq_data {
1246 uint32_t size_comp0;
1247 uint32_t size_comp1;
Nico Huberd54e4f42017-03-23 23:45:47 +01001248 uint32_t addr_mask;
1249 bool only_4k;
1250 uint32_t hsfc_fcycle;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001251} hwseq_data;
1252
Nico Huberd54e4f42017-03-23 23:45:47 +01001253/* Sets FLA in FADDR to (addr & hwseq_data.addr_mask) without touching other bits. */
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001254static void ich_hwseq_set_addr(uint32_t addr)
1255{
Nico Huberd54e4f42017-03-23 23:45:47 +01001256 uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~hwseq_data.addr_mask;
1257 REGWRITE32(ICH9_REG_FADDR, (addr & hwseq_data.addr_mask) | addr_old);
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001258}
1259
1260/* Sets FADDR.FLA to 'addr' and returns the erase block size in bytes
1261 * of the block containing this address. May return nonsense if the address is
1262 * not valid. The erase block size for a specific address depends on the flash
1263 * partition layout as specified by FPB and the partition properties as defined
1264 * by UVSCC and LVSCC respectively. An alternative to implement this method
1265 * would be by querying FPB and the respective VSCC register directly.
1266 */
1267static uint32_t ich_hwseq_get_erase_block_size(unsigned int addr)
1268{
Elyes HAOUAS29e46d02019-06-09 17:38:25 +02001269 uint8_t enc_berase;
1270 static const uint32_t dec_berase[4] = {
1271 256,
1272 4 * 1024,
1273 8 * 1024,
1274 64 * 1024
1275 };
1276
Nico Huberd54e4f42017-03-23 23:45:47 +01001277 if (hwseq_data.only_4k) {
1278 return 4 * 1024;
Nico Huberd54e4f42017-03-23 23:45:47 +01001279 }
Elyes HAOUAS29e46d02019-06-09 17:38:25 +02001280
1281 ich_hwseq_set_addr(addr);
1282 enc_berase = (REGREAD16(ICH9_REG_HSFS) & HSFS_BERASE) >> HSFS_BERASE_OFF;
1283 return dec_berase[enc_berase];
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001284}
1285
1286/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.
1287 Resets all error flags in HSFS.
1288 Returns 0 if the cycle completes successfully without errors within
1289 timeout us, 1 on errors. */
Subrata Banik7cb43952022-03-16 20:40:42 +05301290static int ich_hwseq_wait_for_cycle_complete(unsigned int len)
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001291{
Subrata Banik7cb43952022-03-16 20:40:42 +05301292 /*
1293 * The SPI bus may be busy due to performing operations from other masters, hence
1294 * introduce the long timeout of 30s to cover the worst case scenarios as well.
1295 */
1296 unsigned int timeout_us = 30 * 1000 * 1000;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001297 uint16_t hsfs;
1298 uint32_t addr;
1299
Subrata Banik7cb43952022-03-16 20:40:42 +05301300 timeout_us /= 8; /* scale timeout duration to counter */
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001301 while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) &
1302 (HSFS_FDONE | HSFS_FCERR)) == 0) &&
Subrata Banik7cb43952022-03-16 20:40:42 +05301303 --timeout_us) {
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001304 programmer_delay(8);
1305 }
1306 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
Subrata Banik7cb43952022-03-16 20:40:42 +05301307 if (!timeout_us) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001308 addr = REGREAD32(ICH9_REG_FADDR) & hwseq_data.addr_mask;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001309 msg_perr("Timeout error between offset 0x%08x and "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001310 "0x%08x (= 0x%08x + %d)!\n",
1311 addr, addr + len - 1, addr, len - 1);
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001312 prettyprint_ich9_reg_hsfs(hsfs);
1313 prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC));
1314 return 1;
1315 }
1316
1317 if (hsfs & HSFS_FCERR) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001318 addr = REGREAD32(ICH9_REG_FADDR) & hwseq_data.addr_mask;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001319 msg_perr("Transaction error between offset 0x%08x and "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001320 "0x%08x (= 0x%08x + %d)!\n",
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001321 addr, addr + len - 1, addr, len - 1);
1322 prettyprint_ich9_reg_hsfs(hsfs);
1323 prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC));
1324 return 1;
1325 }
1326 return 0;
1327}
Stefan Tauner50e7c602011-11-08 10:55:54 +00001328
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001329static int ich_hwseq_probe(struct flashctx *flash)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001330{
1331 uint32_t total_size, boundary;
1332 uint32_t erase_size_low, size_low, erase_size_high, size_high;
1333 struct block_eraser *eraser;
1334
1335 total_size = hwseq_data.size_comp0 + hwseq_data.size_comp1;
Stefan Tauner5c316f92015-02-08 21:57:52 +00001336 msg_cdbg("Hardware sequencing reports %d attached SPI flash chip",
Stefan Tauner50e7c602011-11-08 10:55:54 +00001337 (hwseq_data.size_comp1 != 0) ? 2 : 1);
1338 if (hwseq_data.size_comp1 != 0)
1339 msg_cdbg("s with a combined");
1340 else
1341 msg_cdbg(" with a");
1342 msg_cdbg(" density of %d kB.\n", total_size / 1024);
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001343 flash->chip->total_size = total_size / 1024;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001344
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001345 eraser = &(flash->chip->block_erasers[0]);
Nico Huberd54e4f42017-03-23 23:45:47 +01001346 if (!hwseq_data.only_4k)
1347 boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12;
1348 else
1349 boundary = 0;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001350 size_high = total_size - boundary;
1351 erase_size_high = ich_hwseq_get_erase_block_size(boundary);
1352
1353 if (boundary == 0) {
Stefan Tauner5c316f92015-02-08 21:57:52 +00001354 msg_cdbg2("There is only one partition containing the whole "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001355 "address space (0x%06x - 0x%06x).\n", 0, size_high-1);
1356 eraser->eraseblocks[0].size = erase_size_high;
1357 eraser->eraseblocks[0].count = size_high / erase_size_high;
Stefan Tauner5c316f92015-02-08 21:57:52 +00001358 msg_cdbg2("There are %d erase blocks with %d B each.\n",
Stefan Tauner50e7c602011-11-08 10:55:54 +00001359 size_high / erase_size_high, erase_size_high);
1360 } else {
Stefan Tauner5c316f92015-02-08 21:57:52 +00001361 msg_cdbg2("The flash address space (0x%06x - 0x%06x) is divided "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001362 "at address 0x%06x in two partitions.\n",
Stefan Taunerdbac46c2013-08-13 22:10:41 +00001363 0, total_size-1, boundary);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001364 size_low = total_size - size_high;
1365 erase_size_low = ich_hwseq_get_erase_block_size(0);
1366
1367 eraser->eraseblocks[0].size = erase_size_low;
1368 eraser->eraseblocks[0].count = size_low / erase_size_low;
1369 msg_cdbg("The first partition ranges from 0x%06x to 0x%06x.\n",
1370 0, size_low-1);
1371 msg_cdbg("In that range are %d erase blocks with %d B each.\n",
1372 size_low / erase_size_low, erase_size_low);
1373
1374 eraser->eraseblocks[1].size = erase_size_high;
1375 eraser->eraseblocks[1].count = size_high / erase_size_high;
1376 msg_cdbg("The second partition ranges from 0x%06x to 0x%06x.\n",
Stefan Taunerdbac46c2013-08-13 22:10:41 +00001377 boundary, total_size-1);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001378 msg_cdbg("In that range are %d erase blocks with %d B each.\n",
1379 size_high / erase_size_high, erase_size_high);
1380 }
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001381 flash->chip->tested = TEST_OK_PREW;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001382 return 1;
1383}
1384
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001385static int ich_hwseq_block_erase(struct flashctx *flash, unsigned int addr,
1386 unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001387{
1388 uint32_t erase_block;
1389 uint16_t hsfc;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001390
1391 erase_block = ich_hwseq_get_erase_block_size(addr);
1392 if (len != erase_block) {
1393 msg_cerr("Erase block size for address 0x%06x is %d B, "
1394 "but requested erase block size is %d B. "
1395 "Not erasing anything.\n", addr, erase_block, len);
1396 return -1;
1397 }
1398
1399 /* Although the hardware supports this (it would erase the whole block
1400 * containing the address) we play safe here. */
1401 if (addr % erase_block != 0) {
1402 msg_cerr("Erase address 0x%06x is not aligned to the erase "
1403 "block boundary (any multiple of %d). "
1404 "Not erasing anything.\n", addr, erase_block);
1405 return -1;
1406 }
1407
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001408 if (addr + len > flash->chip->total_size * 1024) {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001409 msg_perr("Request to erase some inaccessible memory address(es)"
1410 " (addr=0x%x, len=%d). "
1411 "Not erasing anything.\n", addr, len);
1412 return -1;
1413 }
1414
1415 msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr);
Stefan Tauner7608d362014-08-05 23:28:47 +00001416 ich_hwseq_set_addr(addr);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001417
1418 /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */
1419 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1420
1421 hsfc = REGREAD16(ICH9_REG_HSFC);
Nico Huberd54e4f42017-03-23 23:45:47 +01001422 hsfc &= ~hwseq_data.hsfc_fcycle; /* clear operation */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001423 hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */
1424 hsfc |= HSFC_FGO; /* start */
1425 msg_pdbg("HSFC used for block erasing: ");
1426 prettyprint_ich9_reg_hsfc(hsfc);
1427 REGWRITE16(ICH9_REG_HSFC, hsfc);
1428
Subrata Banik7cb43952022-03-16 20:40:42 +05301429 if (ich_hwseq_wait_for_cycle_complete(len))
Stefan Tauner50e7c602011-11-08 10:55:54 +00001430 return -1;
1431 return 0;
1432}
1433
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001434static int ich_hwseq_read(struct flashctx *flash, uint8_t *buf,
1435 unsigned int addr, unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001436{
1437 uint16_t hsfc;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001438 uint8_t block_len;
1439
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001440 if (addr + len > flash->chip->total_size * 1024) {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001441 msg_perr("Request to read from an inaccessible memory address "
1442 "(addr=0x%x, len=%d).\n", addr, len);
1443 return -1;
1444 }
1445
1446 msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr);
1447 /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
1448 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1449
1450 while (len > 0) {
Stefan Tauner7608d362014-08-05 23:28:47 +00001451 /* Obey programmer limit... */
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001452 block_len = min(len, flash->mst->opaque.max_data_read);
Stefan Tauner7608d362014-08-05 23:28:47 +00001453 /* as well as flash chip page borders as demanded in the Intel datasheets. */
1454 block_len = min(block_len, 256 - (addr & 0xFF));
1455
Stefan Tauner50e7c602011-11-08 10:55:54 +00001456 ich_hwseq_set_addr(addr);
1457 hsfc = REGREAD16(ICH9_REG_HSFC);
Nico Huberd54e4f42017-03-23 23:45:47 +01001458 hsfc &= ~hwseq_data.hsfc_fcycle; /* set read operation */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001459 hsfc &= ~HSFC_FDBC; /* clear byte count */
1460 /* set byte count */
1461 hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
1462 hsfc |= HSFC_FGO; /* start */
1463 REGWRITE16(ICH9_REG_HSFC, hsfc);
1464
Subrata Banik7cb43952022-03-16 20:40:42 +05301465 if (ich_hwseq_wait_for_cycle_complete(block_len))
Stefan Tauner50e7c602011-11-08 10:55:54 +00001466 return 1;
1467 ich_read_data(buf, block_len, ICH9_REG_FDATA0);
1468 addr += block_len;
1469 buf += block_len;
1470 len -= block_len;
1471 }
1472 return 0;
1473}
1474
Mark Marshallf20b7be2014-05-09 21:16:21 +00001475static int ich_hwseq_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001476{
1477 uint16_t hsfc;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001478 uint8_t block_len;
1479
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001480 if (addr + len > flash->chip->total_size * 1024) {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001481 msg_perr("Request to write to an inaccessible memory address "
1482 "(addr=0x%x, len=%d).\n", addr, len);
1483 return -1;
1484 }
1485
1486 msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr);
1487 /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
1488 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1489
1490 while (len > 0) {
1491 ich_hwseq_set_addr(addr);
Stefan Tauner7608d362014-08-05 23:28:47 +00001492 /* Obey programmer limit... */
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001493 block_len = min(len, flash->mst->opaque.max_data_write);
Stefan Tauner7608d362014-08-05 23:28:47 +00001494 /* as well as flash chip page borders as demanded in the Intel datasheets. */
1495 block_len = min(block_len, 256 - (addr & 0xFF));
Stefan Tauner50e7c602011-11-08 10:55:54 +00001496 ich_fill_data(buf, block_len, ICH9_REG_FDATA0);
1497 hsfc = REGREAD16(ICH9_REG_HSFC);
Nico Huberd54e4f42017-03-23 23:45:47 +01001498 hsfc &= ~hwseq_data.hsfc_fcycle; /* clear operation */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001499 hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */
1500 hsfc &= ~HSFC_FDBC; /* clear byte count */
1501 /* set byte count */
1502 hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
1503 hsfc |= HSFC_FGO; /* start */
1504 REGWRITE16(ICH9_REG_HSFC, hsfc);
1505
Subrata Banik7cb43952022-03-16 20:40:42 +05301506 if (ich_hwseq_wait_for_cycle_complete(block_len))
Stefan Tauner50e7c602011-11-08 10:55:54 +00001507 return -1;
1508 addr += block_len;
1509 buf += block_len;
1510 len -= block_len;
1511 }
1512 return 0;
1513}
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001514
Edward O'Callaghan5eca4272020-04-12 17:27:53 +10001515static int ich_spi_send_multicommand(const struct flashctx *flash,
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001516 struct spi_command *cmds)
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001517{
1518 int ret = 0;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001519 int i;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001520 int oppos, preoppos;
1521 for (; (cmds->writecnt || cmds->readcnt) && !ret; cmds++) {
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001522 if ((cmds + 1)->writecnt || (cmds + 1)->readcnt) {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001523 /* Next command is valid. */
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001524 preoppos = find_preop(curopcodes, cmds->writearr[0]);
1525 oppos = find_opcode(curopcodes, (cmds + 1)->writearr[0]);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001526 if ((oppos == -1) && (preoppos != -1)) {
1527 /* Current command is listed as preopcode in
1528 * ICH struct OPCODES, but next command is not
1529 * listed as opcode in that struct.
1530 * Check for command sanity, then
1531 * try to reprogram the ICH opcode list.
1532 */
1533 if (find_preop(curopcodes,
1534 (cmds + 1)->writearr[0]) != -1) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001535 msg_perr("%s: Two subsequent "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001536 "preopcodes 0x%02x and 0x%02x, "
1537 "ignoring the first.\n",
1538 __func__, cmds->writearr[0],
1539 (cmds + 1)->writearr[0]);
1540 continue;
1541 }
1542 /* If the chipset is locked down, we'll fail
1543 * during execution of the next command anyway.
1544 * No need to bother with fixups.
1545 */
1546 if (!ichspi_lock) {
Helge Wagner738e2522010-10-05 22:06:05 +00001547 oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt);
1548 if (oppos == -1)
1549 continue;
1550 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001551 continue;
1552 }
1553 }
1554 if ((oppos != -1) && (preoppos != -1)) {
1555 /* Current command is listed as preopcode in
1556 * ICH struct OPCODES and next command is listed
1557 * as opcode in that struct. Match them up.
1558 */
1559 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001560 continue;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001561 }
1562 /* If none of the above if-statements about oppos or
1563 * preoppos matched, this is a normal opcode.
1564 */
1565 }
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001566 ret = ich_spi_send_command(flash, cmds->writecnt, cmds->readcnt,
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001567 cmds->writearr, cmds->readarr);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001568 /* Reset the type of all opcodes to non-atomic. */
1569 for (i = 0; i < 8; i++)
1570 curopcodes->opcode[i].atomic = 0;
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001571 }
1572 return ret;
1573}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001574
Nikolai Artemieve7a41e32022-11-28 17:40:56 +11001575static bool ich_spi_probe_opcode(const struct flashctx *flash, uint8_t opcode)
Aarya Chaumal0cea7532022-07-04 18:21:50 +05301576{
1577 return find_opcode(curopcodes, opcode) >= 0;
1578}
1579
Michael Karchera4448d92010-07-22 18:04:15 +00001580#define ICH_BMWAG(x) ((x >> 24) & 0xff)
1581#define ICH_BMRAG(x) ((x >> 16) & 0xff)
1582#define ICH_BRWA(x) ((x >> 8) & 0xff)
1583#define ICH_BRRA(x) ((x >> 0) & 0xff)
1584
Nico Huber7590d1a2016-05-03 13:38:28 +02001585static const enum ich_access_protection access_perms_to_protection[] = {
1586 LOCKED, WRITE_PROT, READ_PROT, NO_PROT
1587};
1588static const char *const access_names[] = {
1589 "locked", "read-only", "write-only", "read-write"
1590};
1591
Nico Huber519be662018-12-23 20:03:35 +01001592static enum ich_access_protection ich9_handle_frap(uint32_t frap, unsigned int i)
Michael Karchera4448d92010-07-22 18:04:15 +00001593{
Nico Huberaa91d5c2017-08-19 17:04:21 +02001594 const int rwperms_unknown = ARRAY_SIZE(access_names);
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001595 static const char *const region_names[] = {
Michael Karchera4448d92010-07-22 18:04:15 +00001596 "Flash Descriptor", "BIOS", "Management Engine",
Nico Huberd2d39932019-01-18 16:49:37 +01001597 "Gigabit Ethernet", "Platform Data", "Device Expansion",
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001598 "BIOS2", "unknown", "EC/BMC",
Michael Karchera4448d92010-07-22 18:04:15 +00001599 };
Nico Huberd54e4f42017-03-23 23:45:47 +01001600 const char *const region_name = i < ARRAY_SIZE(region_names) ? region_names[i] : "unknown";
1601
Michael Karchera4448d92010-07-22 18:04:15 +00001602 uint32_t base, limit;
Nico Huberaa91d5c2017-08-19 17:04:21 +02001603 int rwperms;
Nico Huberd2d39932019-01-18 16:49:37 +01001604 const int offset = i < 12
1605 ? ICH9_REG_FREG0 + i * 4
1606 : APL_REG_FREG12 + (i - 12) * 4;
Michael Karchera4448d92010-07-22 18:04:15 +00001607 uint32_t freg = mmio_readl(ich_spibar + offset);
1608
Nico Huberaa91d5c2017-08-19 17:04:21 +02001609 if (i < 8) {
1610 rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) |
1611 (((ICH_BRRA(frap) >> i) & 1) << 0);
1612 } else {
1613 /* Datasheets don't define any access bits for regions > 7. We
1614 can't rely on the actual descriptor settings either as there
1615 are several overrides for them (those by other masters are
1616 not even readable by us, *shrug*). */
1617 rwperms = rwperms_unknown;
1618 }
1619
Michael Karchera4448d92010-07-22 18:04:15 +00001620 base = ICH_FREG_BASE(freg);
1621 limit = ICH_FREG_LIMIT(freg);
Stefan Taunere3adea02012-08-27 15:12:36 +00001622 if (base > limit || (freg == 0 && i > 0)) {
Michael Karchera4448d92010-07-22 18:04:15 +00001623 /* this FREG is disabled */
Nico Huber519be662018-12-23 20:03:35 +01001624 msg_pdbg2("0x%02X: 0x%08x FREG%u: %s region is unused.\n",
Nico Huberd54e4f42017-03-23 23:45:47 +01001625 offset, freg, i, region_name);
Nico Huber7590d1a2016-05-03 13:38:28 +02001626 return NO_PROT;
Stefan Tauner5210e722012-02-16 01:13:00 +00001627 }
1628 msg_pdbg("0x%02X: 0x%08x ", offset, freg);
1629 if (rwperms == 0x3) {
Nico Huber519be662018-12-23 20:03:35 +01001630 msg_pdbg("FREG%u: %s region (0x%08x-0x%08x) is %s.\n", i,
Nico Huber0bb3f712017-03-29 16:44:33 +02001631 region_name, base, limit, access_names[rwperms]);
Nico Huber7590d1a2016-05-03 13:38:28 +02001632 return NO_PROT;
Michael Karchera4448d92010-07-22 18:04:15 +00001633 }
Nico Huberaa91d5c2017-08-19 17:04:21 +02001634 if (rwperms == rwperms_unknown) {
Nico Huber519be662018-12-23 20:03:35 +01001635 msg_pdbg("FREG%u: %s region (0x%08x-0x%08x) has unknown permissions.\n",
Nico Huberaa91d5c2017-08-19 17:04:21 +02001636 i, region_name, base, limit);
Nico Huber7590d1a2016-05-03 13:38:28 +02001637 return NO_PROT;
Nico Huberaa91d5c2017-08-19 17:04:21 +02001638 }
Michael Karchera4448d92010-07-22 18:04:15 +00001639
Nico Huber519be662018-12-23 20:03:35 +01001640 msg_pinfo("FREG%u: %s region (0x%08x-0x%08x) is %s.\n", i,
Nico Huber0bb3f712017-03-29 16:44:33 +02001641 region_name, base, limit, access_names[rwperms]);
Nico Huber7590d1a2016-05-03 13:38:28 +02001642 return access_perms_to_protection[rwperms];
Michael Karchera4448d92010-07-22 18:04:15 +00001643}
1644
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001645 /* In contrast to FRAP and the master section of the descriptor the bits
1646 * in the PR registers have an inverted meaning. The bits in FRAP
1647 * indicate read and write access _grant_. Here they indicate read
1648 * and write _protection_ respectively. If both bits are 0 the address
1649 * bits are ignored.
1650 */
1651#define ICH_PR_PERMS(pr) (((~((pr) >> PR_RP_OFF) & 1) << 0) | \
1652 ((~((pr) >> PR_WP_OFF) & 1) << 1))
1653
Nico Huber519be662018-12-23 20:03:35 +01001654static enum ich_access_protection ich9_handle_pr(const size_t reg_pr0, unsigned int i)
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001655{
Nico Huberd54e4f42017-03-23 23:45:47 +01001656 uint8_t off = reg_pr0 + (i * 4);
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001657 uint32_t pr = mmio_readl(ich_spibar + off);
Stefan Tauner5210e722012-02-16 01:13:00 +00001658 unsigned int rwperms = ICH_PR_PERMS(pr);
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001659
Nico Huberd54e4f42017-03-23 23:45:47 +01001660 /* From 5 on we have GPR registers and start from 0 again. */
1661 const char *const prefix = i >= 5 ? "G" : "";
1662 if (i >= 5)
1663 i -= 5;
1664
Stefan Tauner5210e722012-02-16 01:13:00 +00001665 if (rwperms == 0x3) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001666 msg_pdbg2("0x%02X: 0x%08x (%sPR%u is unused)\n", off, pr, prefix, i);
Nico Huber7590d1a2016-05-03 13:38:28 +02001667 return NO_PROT;
Stefan Tauner5210e722012-02-16 01:13:00 +00001668 }
1669
1670 msg_pdbg("0x%02X: 0x%08x ", off, pr);
Nico Huberd54e4f42017-03-23 23:45:47 +01001671 msg_pwarn("%sPR%u: Warning: 0x%08x-0x%08x is %s.\n", prefix, i, ICH_FREG_BASE(pr),
Nico Huber0bb3f712017-03-29 16:44:33 +02001672 ICH_FREG_LIMIT(pr), access_names[rwperms]);
Nico Huber7590d1a2016-05-03 13:38:28 +02001673 return access_perms_to_protection[rwperms];
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001674}
1675
Stefan Tauner75da80c2011-09-17 22:21:55 +00001676/* Set/Clear the read and write protection enable bits of PR register @i
1677 * according to @read_prot and @write_prot. */
Nico Huberd54e4f42017-03-23 23:45:47 +01001678static void ich9_set_pr(const size_t reg_pr0, int i, int read_prot, int write_prot)
Stefan Tauner75da80c2011-09-17 22:21:55 +00001679{
Nico Huberd54e4f42017-03-23 23:45:47 +01001680 void *addr = ich_spibar + reg_pr0 + (i * 4);
Stefan Tauner75da80c2011-09-17 22:21:55 +00001681 uint32_t old = mmio_readl(addr);
1682 uint32_t new;
1683
1684 msg_gspew("PR%u is 0x%08x", i, old);
1685 new = old & ~((1 << PR_RP_OFF) | (1 << PR_WP_OFF));
1686 if (read_prot)
1687 new |= (1 << PR_RP_OFF);
1688 if (write_prot)
1689 new |= (1 << PR_WP_OFF);
1690 if (old == new) {
1691 msg_gspew(" already.\n");
1692 return;
1693 }
1694 msg_gspew(", trying to set it to 0x%08x ", new);
1695 rmmio_writel(new, addr);
1696 msg_gspew("resulted in 0x%08x.\n", mmio_readl(addr));
1697}
1698
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001699static const struct spi_master spi_master_ich7 = {
Thomas Heijligen43040f22022-06-23 14:38:35 +02001700 .max_data_read = 64,
1701 .max_data_write = 64,
1702 .command = ich_spi_send_command,
1703 .multicommand = ich_spi_send_multicommand,
1704 .read = default_spi_read,
1705 .write_256 = default_spi_write_256,
Aarya Chaumal0cea7532022-07-04 18:21:50 +05301706 .probe_opcode = ich_spi_probe_opcode,
Michael Karcherb9dbe482011-05-11 17:07:07 +00001707};
1708
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001709static const struct spi_master spi_master_ich9 = {
Thomas Heijligen43040f22022-06-23 14:38:35 +02001710 .max_data_read = 64,
1711 .max_data_write = 64,
1712 .command = ich_spi_send_command,
1713 .multicommand = ich_spi_send_multicommand,
1714 .read = default_spi_read,
1715 .write_256 = default_spi_write_256,
Aarya Chaumal0cea7532022-07-04 18:21:50 +05301716 .probe_opcode = ich_spi_probe_opcode,
Michael Karcherb9dbe482011-05-11 17:07:07 +00001717};
1718
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001719static const struct opaque_master opaque_master_ich_hwseq = {
Thomas Heijligen43040f22022-06-23 14:38:35 +02001720 .max_data_read = 64,
1721 .max_data_write = 64,
1722 .probe = ich_hwseq_probe,
1723 .read = ich_hwseq_read,
1724 .write = ich_hwseq_write,
1725 .erase = ich_hwseq_block_erase,
Stefan Tauner50e7c602011-11-08 10:55:54 +00001726};
1727
Nico Huber560111e2017-04-26 12:27:17 +02001728int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
Michael Karchera4448d92010-07-22 18:04:15 +00001729{
Nico Huber519be662018-12-23 20:03:35 +01001730 unsigned int i;
Stefan Tauner92d6a862013-10-25 00:33:37 +00001731 uint16_t tmp2;
Michael Karchera4448d92010-07-22 18:04:15 +00001732 uint32_t tmp;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001733 char *arg;
Stefan Tauner5210e722012-02-16 01:13:00 +00001734 int ich_spi_rw_restricted = 0;
Felix Singer8cfc7372022-08-19 03:10:29 +02001735 bool desc_valid = false;
Angel Pons7e134562021-06-07 13:29:13 +02001736 struct ich_descriptors desc = { 0 };
Stefan Tauner50e7c602011-11-08 10:55:54 +00001737 enum ich_spi_mode {
1738 ich_auto,
1739 ich_hwseq,
1740 ich_swseq
1741 } ich_spi_mode = ich_auto;
Nico Huberd54e4f42017-03-23 23:45:47 +01001742 size_t num_freg, num_pr, reg_pr0;
Michael Karchera4448d92010-07-22 18:04:15 +00001743
Stefan Taunera8d838d2011-11-06 23:51:09 +00001744 ich_generation = ich_gen;
Stefan Tauner92d6a862013-10-25 00:33:37 +00001745 ich_spibar = spibar;
Michael Karchera4448d92010-07-22 18:04:15 +00001746
Nico Huberd54e4f42017-03-23 23:45:47 +01001747 /* Moving registers / bits */
Nico Huberd2d39932019-01-18 16:49:37 +01001748 switch (ich_generation) {
1749 case CHIPSET_100_SERIES_SUNRISE_POINT:
1750 case CHIPSET_C620_SERIES_LEWISBURG:
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001751 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +02001752 case CHIPSET_500_SERIES_TIGER_POINT:
Nico Huberd2d39932019-01-18 16:49:37 +01001753 case CHIPSET_APOLLO_LAKE:
Angel Pons4db0fdf2020-07-10 17:04:10 +02001754 case CHIPSET_GEMINI_LAKE:
Werner Zehe57d4e42022-01-03 09:44:29 +01001755 case CHIPSET_ELKHART_LAKE:
David Hendricksa5216362017-08-08 20:02:22 -07001756 num_pr = 6; /* Includes GPR0 */
1757 reg_pr0 = PCH100_REG_FPR0;
1758 swseq_data.reg_ssfsc = PCH100_REG_SSFSC;
1759 swseq_data.reg_preop = PCH100_REG_PREOP;
1760 swseq_data.reg_optype = PCH100_REG_OPTYPE;
1761 swseq_data.reg_opmenu = PCH100_REG_OPMENU;
1762 hwseq_data.addr_mask = PCH100_FADDR_FLA;
1763 hwseq_data.only_4k = true;
1764 hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE;
Nico Huberd2d39932019-01-18 16:49:37 +01001765 break;
1766 default:
Nico Huberd54e4f42017-03-23 23:45:47 +01001767 num_pr = 5;
1768 reg_pr0 = ICH9_REG_PR0;
1769 swseq_data.reg_ssfsc = ICH9_REG_SSFS;
1770 swseq_data.reg_preop = ICH9_REG_PREOP;
1771 swseq_data.reg_optype = ICH9_REG_OPTYPE;
1772 swseq_data.reg_opmenu = ICH9_REG_OPMENU;
1773 hwseq_data.addr_mask = ICH9_FADDR_FLA;
1774 hwseq_data.only_4k = false;
1775 hwseq_data.hsfc_fcycle = HSFC_FCYCLE;
Nico Huberd2d39932019-01-18 16:49:37 +01001776 break;
1777 }
1778 switch (ich_generation) {
1779 case CHIPSET_100_SERIES_SUNRISE_POINT:
1780 num_freg = 10;
1781 break;
1782 case CHIPSET_C620_SERIES_LEWISBURG:
1783 num_freg = 12; /* 12 MMIO regs, but 16 regions in FD spec */
1784 break;
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001785 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +02001786 case CHIPSET_500_SERIES_TIGER_POINT:
Nico Huberd2d39932019-01-18 16:49:37 +01001787 case CHIPSET_APOLLO_LAKE:
Angel Pons4db0fdf2020-07-10 17:04:10 +02001788 case CHIPSET_GEMINI_LAKE:
Werner Zehe57d4e42022-01-03 09:44:29 +01001789 case CHIPSET_ELKHART_LAKE:
Nico Huberd2d39932019-01-18 16:49:37 +01001790 num_freg = 16;
1791 break;
1792 default:
1793 num_freg = 5;
1794 break;
Nico Huberd54e4f42017-03-23 23:45:47 +01001795 }
1796
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001797 switch (ich_generation) {
Stefan Taunera8d838d2011-11-06 23:51:09 +00001798 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +00001799 case CHIPSET_TUNNEL_CREEK:
1800 case CHIPSET_CENTERTON:
Michael Karchera4448d92010-07-22 18:04:15 +00001801 msg_pdbg("0x00: 0x%04x (SPIS)\n",
1802 mmio_readw(ich_spibar + 0));
1803 msg_pdbg("0x02: 0x%04x (SPIC)\n",
1804 mmio_readw(ich_spibar + 2));
1805 msg_pdbg("0x04: 0x%08x (SPIA)\n",
1806 mmio_readl(ich_spibar + 4));
Michael Karchera4448d92010-07-22 18:04:15 +00001807 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
1808 msg_pdbg("0x50: 0x%08x (BBAR)\n",
1809 ichspi_bbar);
1810 msg_pdbg("0x54: 0x%04x (PREOP)\n",
1811 mmio_readw(ich_spibar + 0x54));
1812 msg_pdbg("0x56: 0x%04x (OPTYPE)\n",
1813 mmio_readw(ich_spibar + 0x56));
1814 msg_pdbg("0x58: 0x%08x (OPMENU)\n",
1815 mmio_readl(ich_spibar + 0x58));
1816 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n",
1817 mmio_readl(ich_spibar + 0x5c));
Stefan Tauner122dd122011-07-24 15:34:56 +00001818 for (i = 0; i < 3; i++) {
Michael Karchera4448d92010-07-22 18:04:15 +00001819 int offs;
1820 offs = 0x60 + (i * 4);
Nico Huber519be662018-12-23 20:03:35 +01001821 msg_pdbg("0x%02x: 0x%08x (PBR%u)\n", offs,
Michael Karchera4448d92010-07-22 18:04:15 +00001822 mmio_readl(ich_spibar + offs), i);
1823 }
Michael Karchera4448d92010-07-22 18:04:15 +00001824 if (mmio_readw(ich_spibar) & (1 << 15)) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00001825 msg_pwarn("WARNING: SPI Configuration Lockdown activated.\n");
Felix Singer8cfc7372022-08-19 03:10:29 +02001826 ichspi_lock = true;
Michael Karchera4448d92010-07-22 18:04:15 +00001827 }
Stefan Tauner745f6bb2011-11-13 15:17:10 +00001828 ich_init_opcodes();
Stefan Taunera8d838d2011-11-06 23:51:09 +00001829 ich_set_bbar(0);
Nico Huber5e08e3e2021-05-11 17:38:14 +02001830 register_spi_master(&spi_master_ich7, NULL);
Michael Karchera4448d92010-07-22 18:04:15 +00001831 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +00001832 case CHIPSET_ICH8:
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001833 default: /* Future version might behave the same */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001834 arg = extract_programmer_param("ich_spi_mode");
1835 if (arg && !strcmp(arg, "hwseq")) {
1836 ich_spi_mode = ich_hwseq;
1837 msg_pspew("user selected hwseq\n");
1838 } else if (arg && !strcmp(arg, "swseq")) {
1839 ich_spi_mode = ich_swseq;
1840 msg_pspew("user selected swseq\n");
1841 } else if (arg && !strcmp(arg, "auto")) {
1842 msg_pspew("user selected auto\n");
1843 ich_spi_mode = ich_auto;
1844 } else if (arg && !strlen(arg)) {
1845 msg_perr("Missing argument for ich_spi_mode.\n");
1846 free(arg);
1847 return ERROR_FATAL;
1848 } else if (arg) {
1849 msg_perr("Unknown argument for ich_spi_mode: %s\n",
1850 arg);
1851 free(arg);
1852 return ERROR_FATAL;
1853 }
1854 free(arg);
1855
Stefan Tauner29c80832011-06-12 08:14:10 +00001856 tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS);
Michael Karchera4448d92010-07-22 18:04:15 +00001857 msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2);
Stefan Tauner55206942011-06-11 09:53:22 +00001858 prettyprint_ich9_reg_hsfs(tmp2);
Stefan Tauner29c80832011-06-12 08:14:10 +00001859 if (tmp2 & HSFS_FLOCKDN) {
Nico Huber7590d1a2016-05-03 13:38:28 +02001860 msg_pinfo("SPI Configuration is locked down.\n");
Felix Singer8cfc7372022-08-19 03:10:29 +02001861 ichspi_lock = true;
Stefan Tauner55206942011-06-11 09:53:22 +00001862 }
Stefan Tauner1e146392011-09-15 23:52:55 +00001863 if (tmp2 & HSFS_FDV)
Felix Singer8cfc7372022-08-19 03:10:29 +02001864 desc_valid = true;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001865 if (!(tmp2 & HSFS_FDOPSS) && desc_valid)
Stefan Taunerd7d423b2012-10-20 09:13:16 +00001866 msg_pinfo("The Flash Descriptor Override Strap-Pin is set. Restrictions implied by\n"
1867 "the Master Section of the flash descriptor are NOT in effect. Please note\n"
1868 "that Protected Range (PR) restrictions still apply.\n");
Stefan Tauner745f6bb2011-11-13 15:17:10 +00001869 ich_init_opcodes();
Stefan Tauner55206942011-06-11 09:53:22 +00001870
Stefan Taunerf382e352011-11-08 11:55:24 +00001871 if (desc_valid) {
1872 tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC);
1873 msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2);
1874 prettyprint_ich9_reg_hsfc(tmp2);
1875 }
Michael Karchera4448d92010-07-22 18:04:15 +00001876
Stefan Tauner5ffe65b2011-07-07 04:10:57 +00001877 tmp = mmio_readl(ich_spibar + ICH9_REG_FADDR);
Stefan Taunereb582572012-09-21 12:52:50 +00001878 msg_pdbg2("0x08: 0x%08x (FADDR)\n", tmp);
Michael Karchera4448d92010-07-22 18:04:15 +00001879
Nico Huberd2d39932019-01-18 16:49:37 +01001880 switch (ich_gen) {
1881 case CHIPSET_100_SERIES_SUNRISE_POINT:
1882 case CHIPSET_C620_SERIES_LEWISBURG:
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001883 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +02001884 case CHIPSET_500_SERIES_TIGER_POINT:
Nico Huberd2d39932019-01-18 16:49:37 +01001885 case CHIPSET_APOLLO_LAKE:
Angel Pons4db0fdf2020-07-10 17:04:10 +02001886 case CHIPSET_GEMINI_LAKE:
Werner Zehe57d4e42022-01-03 09:44:29 +01001887 case CHIPSET_ELKHART_LAKE:
Nico Huberd2d39932019-01-18 16:49:37 +01001888 tmp = mmio_readl(ich_spibar + PCH100_REG_DLOCK);
1889 msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp);
1890 prettyprint_pch100_reg_dlock(tmp);
1891 break;
1892 default:
1893 break;
Nico Huberd54e4f42017-03-23 23:45:47 +01001894 }
1895
Stefan Taunerf382e352011-11-08 11:55:24 +00001896 if (desc_valid) {
1897 tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP);
1898 msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp);
1899 msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp));
1900 msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp));
1901 msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp));
1902 msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp));
1903
Stefan Tauner5210e722012-02-16 01:13:00 +00001904 /* Handle FREGx and FRAP registers */
Nico Huberd54e4f42017-03-23 23:45:47 +01001905 for (i = 0; i < num_freg; i++)
Stefan Tauner5210e722012-02-16 01:13:00 +00001906 ich_spi_rw_restricted |= ich9_handle_frap(tmp, i);
Stefan Tauner27cb34b2013-06-01 00:06:12 +00001907 if (ich_spi_rw_restricted)
Nico Huberc3b02dc2023-08-12 01:13:45 +02001908 msg_pinfo("Not all flash regions are freely accessible by flashprog. This is "
Stefan Tauner4c723152016-01-14 22:47:55 +00001909 "most likely\ndue to an active ME. Please see "
Nico Huberc3b02dc2023-08-12 01:13:45 +02001910 "https://flashprog.org/ME for details.\n");
Stefan Taunerf382e352011-11-08 11:55:24 +00001911 }
Michael Karchera4448d92010-07-22 18:04:15 +00001912
Stefan Taunereb582572012-09-21 12:52:50 +00001913 /* Handle PR registers */
Nico Huberd54e4f42017-03-23 23:45:47 +01001914 for (i = 0; i < num_pr; i++) {
Stefan Tauner5210e722012-02-16 01:13:00 +00001915 /* if not locked down try to disable PR locks first */
1916 if (!ichspi_lock)
Nico Huberd54e4f42017-03-23 23:45:47 +01001917 ich9_set_pr(reg_pr0, i, 0, 0);
1918 ich_spi_rw_restricted |= ich9_handle_pr(reg_pr0, i);
Stefan Tauner5210e722012-02-16 01:13:00 +00001919 }
1920
Nico Huber7590d1a2016-05-03 13:38:28 +02001921 switch (ich_spi_rw_restricted) {
1922 case WRITE_PROT:
1923 msg_pwarn("At least some flash regions are write protected. For write operations,\n"
1924 "you should use a flash layout and include only writable regions. See\n"
1925 "manpage for more details.\n");
1926 break;
1927 case READ_PROT:
1928 case LOCKED:
1929 msg_pwarn("At least some flash regions are read protected. You have to use a flash\n"
1930 "layout and include only accessible regions. For write operations, you'll\n"
1931 "additionally need the --noverify-all switch. See manpage for more details.\n"
1932 );
1933 break;
Stefan Tauner5210e722012-02-16 01:13:00 +00001934 }
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001935
Nico Huberd54e4f42017-03-23 23:45:47 +01001936 tmp = mmio_readl(ich_spibar + swseq_data.reg_ssfsc);
1937 msg_pdbg("0x%zx: 0x%02x (SSFS)\n", swseq_data.reg_ssfsc, tmp & 0xff);
Stefan Tauner2a8b2622011-06-11 09:53:16 +00001938 prettyprint_ich9_reg_ssfs(tmp);
Stefan Tauner29c80832011-06-12 08:14:10 +00001939 if (tmp & SSFS_FCERR) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001940 msg_pdbg("Clearing SSFS.FCERR\n");
Nico Huberd54e4f42017-03-23 23:45:47 +01001941 mmio_writeb(SSFS_FCERR, ich_spibar + swseq_data.reg_ssfsc);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001942 }
Nico Huberd54e4f42017-03-23 23:45:47 +01001943 msg_pdbg("0x%zx: 0x%06x (SSFC)\n", swseq_data.reg_ssfsc + 1, tmp >> 8);
Stefan Tauner2a8b2622011-06-11 09:53:16 +00001944 prettyprint_ich9_reg_ssfc(tmp);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001945
Nico Huberd54e4f42017-03-23 23:45:47 +01001946 msg_pdbg("0x%zx: 0x%04x (PREOP)\n",
1947 swseq_data.reg_preop, mmio_readw(ich_spibar + swseq_data.reg_preop));
1948 msg_pdbg("0x%zx: 0x%04x (OPTYPE)\n",
1949 swseq_data.reg_optype, mmio_readw(ich_spibar + swseq_data.reg_optype));
1950 msg_pdbg("0x%zx: 0x%08x (OPMENU)\n",
1951 swseq_data.reg_opmenu, mmio_readl(ich_spibar + swseq_data.reg_opmenu));
1952 msg_pdbg("0x%zx: 0x%08x (OPMENU+4)\n",
1953 swseq_data.reg_opmenu + 4, mmio_readl(ich_spibar + swseq_data.reg_opmenu + 4));
Nico Huberd2d39932019-01-18 16:49:37 +01001954
1955 if (desc_valid) {
1956 switch (ich_gen) {
1957 case CHIPSET_ICH8:
1958 case CHIPSET_100_SERIES_SUNRISE_POINT:
1959 case CHIPSET_C620_SERIES_LEWISBURG:
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001960 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +02001961 case CHIPSET_500_SERIES_TIGER_POINT:
Nico Huberd2d39932019-01-18 16:49:37 +01001962 case CHIPSET_APOLLO_LAKE:
Angel Pons4db0fdf2020-07-10 17:04:10 +02001963 case CHIPSET_GEMINI_LAKE:
Werner Zehe57d4e42022-01-03 09:44:29 +01001964 case CHIPSET_ELKHART_LAKE:
Nico Huberd2d39932019-01-18 16:49:37 +01001965 case CHIPSET_BAYTRAIL:
1966 break;
1967 default:
Duncan Laurie4095ed72014-08-20 15:39:32 +00001968 ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR);
Nico Huberd2d39932019-01-18 16:49:37 +01001969 msg_pdbg("0x%x: 0x%08x (BBAR)\n", ICH9_REG_BBAR, ichspi_bbar);
Duncan Laurie4095ed72014-08-20 15:39:32 +00001970 ich_set_bbar(0);
Nico Huberd2d39932019-01-18 16:49:37 +01001971 break;
Duncan Laurie4095ed72014-08-20 15:39:32 +00001972 }
Stefan Taunerbd649e42011-07-01 00:39:16 +00001973
Nico Huberd2d39932019-01-18 16:49:37 +01001974 if (ich_gen == CHIPSET_ICH8) {
1975 tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC);
1976 msg_pdbg("0x%x: 0x%08x (VSCC)\n", ICH8_REG_VSCC, tmp);
1977 msg_pdbg("VSCC: ");
Nico Huberc3b02dc2023-08-12 01:13:45 +02001978 prettyprint_ich_reg_vscc(tmp, FLASHPROG_MSG_DEBUG, true);
Nico Huberd2d39932019-01-18 16:49:37 +01001979 } else {
Stefan Taunerf382e352011-11-08 11:55:24 +00001980 tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC);
Nico Huberd2d39932019-01-18 16:49:37 +01001981 msg_pdbg("0x%x: 0x%08x (LVSCC)\n", ICH9_REG_LVSCC, tmp);
Stefan Taunerf382e352011-11-08 11:55:24 +00001982 msg_pdbg("LVSCC: ");
Nico Huberc3b02dc2023-08-12 01:13:45 +02001983 prettyprint_ich_reg_vscc(tmp, FLASHPROG_MSG_DEBUG, true);
Stefan Tauner1e146392011-09-15 23:52:55 +00001984
Stefan Taunerf382e352011-11-08 11:55:24 +00001985 tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC);
Nico Huberd2d39932019-01-18 16:49:37 +01001986 msg_pdbg("0x%x: 0x%08x (UVSCC)\n", ICH9_REG_UVSCC, tmp);
Stefan Taunerf382e352011-11-08 11:55:24 +00001987 msg_pdbg("UVSCC: ");
Nico Huberc3b02dc2023-08-12 01:13:45 +02001988 prettyprint_ich_reg_vscc(tmp, FLASHPROG_MSG_DEBUG, false);
Stefan Taunerf382e352011-11-08 11:55:24 +00001989 }
Stefan Tauner1e146392011-09-15 23:52:55 +00001990
Nico Huberd2d39932019-01-18 16:49:37 +01001991 switch (ich_gen) {
1992 case CHIPSET_ICH8:
1993 case CHIPSET_100_SERIES_SUNRISE_POINT:
1994 case CHIPSET_C620_SERIES_LEWISBURG:
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001995 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +02001996 case CHIPSET_500_SERIES_TIGER_POINT:
Nico Huberd2d39932019-01-18 16:49:37 +01001997 case CHIPSET_APOLLO_LAKE:
Angel Pons4db0fdf2020-07-10 17:04:10 +02001998 case CHIPSET_GEMINI_LAKE:
Werner Zehe57d4e42022-01-03 09:44:29 +01001999 case CHIPSET_ELKHART_LAKE:
Nico Huberd2d39932019-01-18 16:49:37 +01002000 break;
2001 default:
2002 tmp = mmio_readl(ich_spibar + ICH9_REG_FPB);
2003 msg_pdbg("0x%x: 0x%08x (FPB)\n", ICH9_REG_FPB, tmp);
2004 break;
2005 }
2006
Nico Huberd54e4f42017-03-23 23:45:47 +01002007 if (read_ich_descriptors_via_fdo(ich_gen, ich_spibar, &desc) == ICH_RET_OK)
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +00002008 prettyprint_ich_descriptors(ich_gen, &desc);
2009
Stefan Tauner50e7c602011-11-08 10:55:54 +00002010 /* If the descriptor is valid and indicates multiple
2011 * flash devices we need to use hwseq to be able to
2012 * access the second flash device.
2013 */
2014 if (ich_spi_mode == ich_auto && desc.content.NC != 0) {
2015 msg_pinfo("Enabling hardware sequencing due to "
2016 "multiple flash chips detected.\n");
2017 ich_spi_mode = ich_hwseq;
2018 }
Stefan Tauner1e146392011-09-15 23:52:55 +00002019 }
Stefan Tauner50e7c602011-11-08 10:55:54 +00002020
2021 if (ich_spi_mode == ich_auto && ichspi_lock &&
2022 ich_missing_opcodes()) {
2023 msg_pinfo("Enabling hardware sequencing because "
2024 "some important opcode is locked.\n");
2025 ich_spi_mode = ich_hwseq;
2026 }
2027
Nico Huber2a5dfaf2019-07-04 16:01:51 +02002028 if (ich_spi_mode == ich_auto &&
2029 (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT ||
Michał Żygowski5c9f5422021-06-16 15:13:54 +02002030 ich_gen == CHIPSET_300_SERIES_CANNON_POINT ||
2031 ich_gen == CHIPSET_500_SERIES_TIGER_POINT)) {
Nico Huber2a5dfaf2019-07-04 16:01:51 +02002032 msg_pdbg("Enabling hardware sequencing by default for 100+ series PCH.\n");
Nico Huber22f2dc52017-08-31 16:14:22 +02002033 ich_spi_mode = ich_hwseq;
2034 }
2035
Angel Pons4db0fdf2020-07-10 17:04:10 +02002036 if (ich_spi_mode == ich_auto &&
2037 (ich_gen == CHIPSET_APOLLO_LAKE ||
Werner Zehe57d4e42022-01-03 09:44:29 +01002038 ich_gen == CHIPSET_GEMINI_LAKE ||
2039 ich_gen == CHIPSET_ELKHART_LAKE)) {
2040 msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini/Elkhart Lake.\n");
Nico Huberd2d39932019-01-18 16:49:37 +01002041 ich_spi_mode = ich_hwseq;
2042 }
2043
Stefan Tauner50e7c602011-11-08 10:55:54 +00002044 if (ich_spi_mode == ich_hwseq) {
2045 if (!desc_valid) {
2046 msg_perr("Hardware sequencing was requested "
2047 "but the flash descriptor is not "
2048 "valid. Aborting.\n");
2049 return ERROR_FATAL;
2050 }
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +00002051
2052 int tmpi = getFCBA_component_density(ich_generation, &desc, 0);
2053 if (tmpi < 0) {
2054 msg_perr("Could not determine density of flash component %d.\n", 0);
2055 return ERROR_FATAL;
2056 }
2057 hwseq_data.size_comp0 = tmpi;
2058
2059 tmpi = getFCBA_component_density(ich_generation, &desc, 1);
2060 if (tmpi < 0) {
2061 msg_perr("Could not determine density of flash component %d.\n", 1);
2062 return ERROR_FATAL;
2063 }
2064 hwseq_data.size_comp1 = tmpi;
2065
Anastasia Klimchuk21b20212021-05-13 12:28:47 +10002066 register_opaque_master(&opaque_master_ich_hwseq, NULL);
Stefan Tauner50e7c602011-11-08 10:55:54 +00002067 } else {
Nico Huber5e08e3e2021-05-11 17:38:14 +02002068 register_spi_master(&spi_master_ich9, NULL);
Stefan Tauner50e7c602011-11-08 10:55:54 +00002069 }
Michael Karchera4448d92010-07-22 18:04:15 +00002070 break;
Michael Karchera4448d92010-07-22 18:04:15 +00002071 }
2072
Michael Karchera4448d92010-07-22 18:04:15 +00002073 return 0;
2074}
2075
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00002076static const struct spi_master spi_master_via = {
Thomas Heijligen43040f22022-06-23 14:38:35 +02002077 .max_data_read = 16,
2078 .max_data_write = 16,
2079 .command = ich_spi_send_command,
2080 .multicommand = ich_spi_send_multicommand,
2081 .read = default_spi_read,
2082 .write_256 = default_spi_write_256,
Aarya Chaumal0cea7532022-07-04 18:21:50 +05302083 .probe_opcode = ich_spi_probe_opcode,
Michael Karcherb9dbe482011-05-11 17:07:07 +00002084};
2085
Nico Huber560111e2017-04-26 12:27:17 +02002086int via_init_spi(uint32_t mmio_base)
Michael Karchera4448d92010-07-22 18:04:15 +00002087{
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00002088 int i;
Michael Karchera4448d92010-07-22 18:04:15 +00002089
Stefan Tauner7fb5aa02013-08-14 15:48:44 +00002090 ich_spibar = rphysmap("VIA SPI MMIO registers", mmio_base, 0x70);
2091 if (ich_spibar == ERROR_PTR)
2092 return ERROR_FATAL;
Helge Wagnerdd73d832012-08-24 23:03:46 +00002093 /* Do we really need no write enable? Like the LPC one at D17F0 0x40 */
Michael Karchera4448d92010-07-22 18:04:15 +00002094
Michael Karchera4448d92010-07-22 18:04:15 +00002095 /* Not sure if it speaks all these bus protocols. */
Nico Huber2e50cdc2018-09-23 20:20:26 +02002096 internal_buses_supported &= BUS_LPC | BUS_FWH;
Stefan Taunera8d838d2011-11-06 23:51:09 +00002097 ich_generation = CHIPSET_ICH7;
Nico Huber5e08e3e2021-05-11 17:38:14 +02002098 register_spi_master(&spi_master_via, NULL);
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00002099
2100 msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0));
2101 msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2));
2102 msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(ich_spibar + 4));
2103 for (i = 0; i < 2; i++) {
2104 int offs;
2105 offs = 8 + (i * 8);
2106 msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs,
2107 mmio_readl(ich_spibar + offs), i);
2108 msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
2109 mmio_readl(ich_spibar + offs + 4), i);
2110 }
2111 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
2112 msg_pdbg("0x50: 0x%08x (BBAR)\n", ichspi_bbar);
2113 msg_pdbg("0x54: 0x%04x (PREOP)\n", mmio_readw(ich_spibar + 0x54));
2114 msg_pdbg("0x56: 0x%04x (OPTYPE)\n", mmio_readw(ich_spibar + 0x56));
2115 msg_pdbg("0x58: 0x%08x (OPMENU)\n", mmio_readl(ich_spibar + 0x58));
2116 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + 0x5c));
2117 for (i = 0; i < 3; i++) {
2118 int offs;
2119 offs = 0x60 + (i * 4);
2120 msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,
2121 mmio_readl(ich_spibar + offs), i);
2122 }
2123 msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n",
2124 mmio_readw(ich_spibar + 0x6c));
2125 if (mmio_readw(ich_spibar) & (1 << 15)) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00002126 msg_pwarn("Warning: SPI Configuration Lockdown activated.\n");
Felix Singer8cfc7372022-08-19 03:10:29 +02002127 ichspi_lock = true;
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00002128 }
2129
Stefan Taunera8d838d2011-11-06 23:51:09 +00002130 ich_set_bbar(0);
Michael Karchera4448d92010-07-22 18:04:15 +00002131 ich_init_opcodes();
2132
2133 return 0;
2134}