Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the flashrom project. |
| 3 | * |
| 4 | * Copyright (C) 2008 Stefan Wildemann <stefan.wildemann@kontron.com> |
| 5 | * Copyright (C) 2008 Claus Gindhart <claus.gindhart@kontron.com> |
| 6 | * Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com> |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 7 | * Copyright (C) 2008 coresystems GmbH <info@coresystems.de> |
Carl-Daniel Hailfinger | 5824fbf | 2010-05-21 23:09:42 +0000 | [diff] [blame] | 8 | * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger |
Stefan Tauner | 8b391b8 | 2011-08-09 01:49:34 +0000 | [diff] [blame] | 9 | * Copyright (C) 2011 Stefan Tauner |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2 of the License, or |
| 14 | * (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 24 | */ |
| 25 | |
Carl-Daniel Hailfinger | cceafa2 | 2010-05-26 01:45:41 +0000 | [diff] [blame] | 26 | #if defined(__i386__) || defined(__x86_64__) |
| 27 | |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 28 | #include <string.h> |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 29 | #include "flash.h" |
Carl-Daniel Hailfinger | 5b997c3 | 2010-07-27 22:41:39 +0000 | [diff] [blame] | 30 | #include "programmer.h" |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 31 | #include "spi.h" |
Stefan Tauner | 1e14639 | 2011-09-15 23:52:55 +0000 | [diff] [blame] | 32 | #include "ich_descriptors.h" |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 33 | |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 34 | /* ICH9 controller register definition */ |
Stefan Tauner | 5520694 | 2011-06-11 09:53:22 +0000 | [diff] [blame] | 35 | #define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ |
| 36 | #define HSFS_FDONE_OFF 0 /* 0: Flash Cycle Done */ |
| 37 | #define HSFS_FDONE (0x1 << HSFS_FDONE_OFF) |
| 38 | #define HSFS_FCERR_OFF 1 /* 1: Flash Cycle Error */ |
| 39 | #define HSFS_FCERR (0x1 << HSFS_FCERR_OFF) |
| 40 | #define HSFS_AEL_OFF 2 /* 2: Access Error Log */ |
| 41 | #define HSFS_AEL (0x1 << HSFS_AEL_OFF) |
| 42 | #define HSFS_BERASE_OFF 3 /* 3-4: Block/Sector Erase Size */ |
| 43 | #define HSFS_BERASE (0x3 << HSFS_BERASE_OFF) |
| 44 | #define HSFS_SCIP_OFF 5 /* 5: SPI Cycle In Progress */ |
| 45 | #define HSFS_SCIP (0x1 << HSFS_SCIP_OFF) |
| 46 | /* 6-12: reserved */ |
| 47 | #define HSFS_FDOPSS_OFF 13 /* 13: Flash Descriptor Override Pin-Strap Status */ |
| 48 | #define HSFS_FDOPSS (0x1 << HSFS_FDOPSS_OFF) |
| 49 | #define HSFS_FDV_OFF 14 /* 14: Flash Descriptor Valid */ |
| 50 | #define HSFS_FDV (0x1 << HSFS_FDV_OFF) |
| 51 | #define HSFS_FLOCKDN_OFF 15 /* 15: Flash Configuration Lock-Down */ |
| 52 | #define HSFS_FLOCKDN (0x1 << HSFS_FLOCKDN_OFF) |
| 53 | |
| 54 | #define ICH9_REG_HSFC 0x06 /* 16 Bits Hardware Sequencing Flash Control */ |
| 55 | #define HSFC_FGO_OFF 0 /* 0: Flash Cycle Go */ |
| 56 | #define HSFC_FGO (0x1 << HSFC_FGO_OFF) |
| 57 | #define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ |
| 58 | #define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) |
| 59 | /* 3-7: reserved */ |
| 60 | #define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ |
| 61 | #define HSFC_FDBC (0x3f << HSFC_FDBC_OFF) |
| 62 | /* 14: reserved */ |
| 63 | #define HSFC_SME_OFF 15 /* 15: SPI SMI# Enable */ |
| 64 | #define HSFC_SME (0x1 << HSFC_SME_OFF) |
| 65 | |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 66 | #define ICH9_REG_FADDR 0x08 /* 32 Bits */ |
| 67 | #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 68 | |
Stefan Tauner | 29c8083 | 2011-06-12 08:14:10 +0000 | [diff] [blame] | 69 | #define ICH9_REG_FRAP 0x50 /* 32 Bytes Flash Region Access Permissions */ |
| 70 | #define ICH9_REG_FREG0 0x54 /* 32 Bytes Flash Region 0 */ |
| 71 | |
| 72 | #define ICH9_REG_PR0 0x74 /* 32 Bytes Protected Range 0 */ |
| 73 | #define ICH9_REG_PR1 0x78 /* 32 Bytes Protected Range 1 */ |
| 74 | #define ICH9_REG_PR2 0x7c /* 32 Bytes Protected Range 2 */ |
| 75 | #define ICH9_REG_PR3 0x80 /* 32 Bytes Protected Range 3 */ |
| 76 | #define ICH9_REG_PR4 0x84 /* 32 Bytes Protected Range 4 */ |
| 77 | |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 78 | #define ICH9_REG_SSFS 0x90 /* 08 Bits */ |
Stefan Tauner | 0c1ec45 | 2011-06-11 09:53:09 +0000 | [diff] [blame] | 79 | #define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */ |
| 80 | #define SSFS_SCIP (0x1 << SSFS_SCIP_OFF) |
| 81 | #define SSFS_FDONE_OFF 2 /* Cycle Done Status */ |
| 82 | #define SSFS_FDONE (0x1 << SSFS_FDONE_OFF) |
| 83 | #define SSFS_FCERR_OFF 3 /* Flash Cycle Error */ |
| 84 | #define SSFS_FCERR (0x1 << SSFS_FCERR_OFF) |
| 85 | #define SSFS_AEL_OFF 4 /* Access Error Log */ |
| 86 | #define SSFS_AEL (0x1 << SSFS_AEL_OFF) |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 87 | /* The following bits are reserved in SSFS: 1,5-7. */ |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 88 | #define SSFS_RESERVED_MASK 0x000000e2 |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 89 | |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 90 | #define ICH9_REG_SSFC 0x91 /* 24 Bits */ |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 91 | /* We combine SSFS and SSFC to one 32-bit word, |
Stefan Tauner | 0c1ec45 | 2011-06-11 09:53:09 +0000 | [diff] [blame] | 92 | * therefore SSFC bits are off by 8. */ |
| 93 | /* 0: reserved */ |
| 94 | #define SSFC_SCGO_OFF (1 + 8) /* 1: SPI Cycle Go */ |
| 95 | #define SSFC_SCGO (0x1 << SSFC_SCGO_OFF) |
| 96 | #define SSFC_ACS_OFF (2 + 8) /* 2: Atomic Cycle Sequence */ |
| 97 | #define SSFC_ACS (0x1 << SSFC_ACS_OFF) |
| 98 | #define SSFC_SPOP_OFF (3 + 8) /* 3: Sequence Prefix Opcode Pointer */ |
| 99 | #define SSFC_SPOP (0x1 << SSFC_SPOP_OFF) |
| 100 | #define SSFC_COP_OFF (4 + 8) /* 4-6: Cycle Opcode Pointer */ |
| 101 | #define SSFC_COP (0x7 << SSFC_COP_OFF) |
| 102 | /* 7: reserved */ |
| 103 | #define SSFC_DBC_OFF (8 + 8) /* 8-13: Data Byte Count */ |
| 104 | #define SSFC_DBC (0x3f << SSFC_DBC_OFF) |
| 105 | #define SSFC_DS_OFF (14 + 8) /* 14: Data Cycle */ |
| 106 | #define SSFC_DS (0x1 << SSFC_DS_OFF) |
| 107 | #define SSFC_SME_OFF (15 + 8) /* 15: SPI SMI# Enable */ |
| 108 | #define SSFC_SME (0x1 << SSFC_SME_OFF) |
| 109 | #define SSFC_SCF_OFF (16 + 8) /* 16-18: SPI Cycle Frequency */ |
| 110 | #define SSFC_SCF (0x7 << SSFC_SCF_OFF) |
| 111 | #define SSFC_SCF_20MHZ 0x00000000 |
| 112 | #define SSFC_SCF_33MHZ 0x01000000 |
| 113 | /* 19-23: reserved */ |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 114 | #define SSFC_RESERVED_MASK 0xf8008100 |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 115 | |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 116 | #define ICH9_REG_PREOP 0x94 /* 16 Bits */ |
| 117 | #define ICH9_REG_OPTYPE 0x96 /* 16 Bits */ |
| 118 | #define ICH9_REG_OPMENU 0x98 /* 64 Bits */ |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 119 | |
Stefan Tauner | 29c8083 | 2011-06-12 08:14:10 +0000 | [diff] [blame] | 120 | #define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */ |
| 121 | #define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */ |
| 122 | |
Stefan Tauner | 1e14639 | 2011-09-15 23:52:55 +0000 | [diff] [blame] | 123 | #define ICH8_REG_VSCC 0xC1 /* 32 Bits Vendor Specific Component Capabilities */ |
| 124 | #define ICH9_REG_LVSCC 0xC4 /* 32 Bits Host Lower Vendor Specific Component Capabilities */ |
| 125 | #define ICH9_REG_UVSCC 0xC8 /* 32 Bits Host Upper Vendor Specific Component Capabilities */ |
| 126 | /* The individual fields of the VSCC registers are defined in the file |
| 127 | * ich_descriptors.h. The reason is that the same layout is also used in the |
| 128 | * flash descriptor to define the properties of the different flash chips |
| 129 | * supported. The BIOS (or the ME?) is responsible to populate the ICH registers |
| 130 | * with the information from the descriptor on startup depending on the actual |
| 131 | * chip(s) detected. */ |
| 132 | |
Stefan Tauner | bd649e4 | 2011-07-01 00:39:16 +0000 | [diff] [blame] | 133 | #define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */ |
| 134 | #define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */ |
| 135 | #define FPB_FPBA (0x1FFF << FPB_FPBA_OFF) |
| 136 | |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 137 | // ICH9R SPI commands |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 138 | #define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0 |
| 139 | #define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1 |
| 140 | #define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2 |
| 141 | #define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3 |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 142 | |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 143 | // ICH7 registers |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 144 | #define ICH7_REG_SPIS 0x00 /* 16 Bits */ |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 145 | #define SPIS_SCIP 0x0001 |
| 146 | #define SPIS_GRANT 0x0002 |
| 147 | #define SPIS_CDS 0x0004 |
| 148 | #define SPIS_FCERR 0x0008 |
| 149 | #define SPIS_RESERVED_MASK 0x7ff0 |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 150 | |
Rudolf Marek | 3fdbccf | 2008-06-30 21:38:30 +0000 | [diff] [blame] | 151 | /* VIA SPI is compatible with ICH7, but maxdata |
| 152 | to transfer is 16 bytes. |
| 153 | |
| 154 | DATA byte count on ICH7 is 8:13, on VIA 8:11 |
| 155 | |
| 156 | bit 12 is port select CS0 CS1 |
| 157 | bit 13 is FAST READ enable |
| 158 | bit 7 is used with fast read and one shot controls CS de-assert? |
| 159 | */ |
| 160 | |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 161 | #define ICH7_REG_SPIC 0x02 /* 16 Bits */ |
| 162 | #define SPIC_SCGO 0x0002 |
| 163 | #define SPIC_ACS 0x0004 |
| 164 | #define SPIC_SPOP 0x0008 |
| 165 | #define SPIC_DS 0x4000 |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 166 | |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 167 | #define ICH7_REG_SPIA 0x04 /* 32 Bits */ |
| 168 | #define ICH7_REG_SPID0 0x08 /* 64 Bytes */ |
| 169 | #define ICH7_REG_PREOP 0x54 /* 16 Bits */ |
| 170 | #define ICH7_REG_OPTYPE 0x56 /* 16 Bits */ |
| 171 | #define ICH7_REG_OPMENU 0x58 /* 64 Bits */ |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 172 | |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 173 | /* ICH SPI configuration lock-down. May be set during chipset enabling. */ |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 174 | static int ichspi_lock = 0; |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 175 | |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 176 | uint32_t ichspi_bbar = 0; |
| 177 | |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 178 | static void *ich_spibar = NULL; |
Carl-Daniel Hailfinger | ad3cc55 | 2010-07-03 11:02:10 +0000 | [diff] [blame] | 179 | |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 180 | typedef struct _OPCODE { |
| 181 | uint8_t opcode; //This commands spi opcode |
| 182 | uint8_t spi_type; //This commands spi type |
| 183 | uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1 |
| 184 | } OPCODE; |
| 185 | |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 186 | /* Suggested opcode definition: |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 187 | * Preop 1: Write Enable |
| 188 | * Preop 2: Write Status register enable |
| 189 | * |
| 190 | * OP 0: Write address |
| 191 | * OP 1: Read Address |
| 192 | * OP 2: ERASE block |
| 193 | * OP 3: Read Status register |
| 194 | * OP 4: Read ID |
| 195 | * OP 5: Write Status register |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 196 | * OP 6: chip private (read JEDEC id) |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 197 | * OP 7: Chip erase |
| 198 | */ |
| 199 | typedef struct _OPCODES { |
| 200 | uint8_t preop[2]; |
| 201 | OPCODE opcode[8]; |
| 202 | } OPCODES; |
| 203 | |
Stefan Reinauer | 325b5d4 | 2008-06-27 15:18:20 +0000 | [diff] [blame] | 204 | static OPCODES *curopcodes = NULL; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 205 | |
| 206 | /* HW access functions */ |
Uwe Hermann | 09e04f7 | 2009-05-16 22:36:00 +0000 | [diff] [blame] | 207 | static uint32_t REGREAD32(int X) |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 208 | { |
Carl-Daniel Hailfinger | ad3cc55 | 2010-07-03 11:02:10 +0000 | [diff] [blame] | 209 | return mmio_readl(ich_spibar + X); |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 210 | } |
| 211 | |
Uwe Hermann | 09e04f7 | 2009-05-16 22:36:00 +0000 | [diff] [blame] | 212 | static uint16_t REGREAD16(int X) |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 213 | { |
Carl-Daniel Hailfinger | ad3cc55 | 2010-07-03 11:02:10 +0000 | [diff] [blame] | 214 | return mmio_readw(ich_spibar + X); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 215 | } |
| 216 | |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 217 | static uint16_t REGREAD8(int X) |
| 218 | { |
| 219 | return mmio_readb(ich_spibar + X); |
| 220 | } |
| 221 | |
Stefan Tauner | ccd92a1 | 2011-07-01 00:39:01 +0000 | [diff] [blame] | 222 | #define REGWRITE32(off, val) mmio_writel(val, ich_spibar+(off)) |
| 223 | #define REGWRITE16(off, val) mmio_writew(val, ich_spibar+(off)) |
| 224 | #define REGWRITE8(off, val) mmio_writeb(val, ich_spibar+(off)) |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 225 | |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 226 | /* Common SPI functions */ |
Uwe Hermann | 09e04f7 | 2009-05-16 22:36:00 +0000 | [diff] [blame] | 227 | static int find_opcode(OPCODES *op, uint8_t opcode); |
| 228 | static int find_preop(OPCODES *op, uint8_t preop); |
FENG yu ning | f041e9b | 2008-12-15 02:32:11 +0000 | [diff] [blame] | 229 | static int generate_opcodes(OPCODES * op); |
Carl-Daniel Hailfinger | 54ce73a | 2011-05-03 21:49:41 +0000 | [diff] [blame] | 230 | static int program_opcodes(OPCODES *op, int enable_undo); |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 231 | static int run_opcode(OPCODE op, uint32_t offset, |
Stefan Reinauer | 325b5d4 | 2008-06-27 15:18:20 +0000 | [diff] [blame] | 232 | uint8_t datalength, uint8_t * data); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 233 | |
FENG yu ning | f041e9b | 2008-12-15 02:32:11 +0000 | [diff] [blame] | 234 | /* for pairing opcodes with their required preop */ |
| 235 | struct preop_opcode_pair { |
| 236 | uint8_t preop; |
| 237 | uint8_t opcode; |
| 238 | }; |
| 239 | |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 240 | /* List of opcodes which need preopcodes and matching preopcodes. Unused. */ |
Carl-Daniel Hailfinger | ad3cc55 | 2010-07-03 11:02:10 +0000 | [diff] [blame] | 241 | const struct preop_opcode_pair pops[] = { |
FENG yu ning | f041e9b | 2008-12-15 02:32:11 +0000 | [diff] [blame] | 242 | {JEDEC_WREN, JEDEC_BYTE_PROGRAM}, |
| 243 | {JEDEC_WREN, JEDEC_SE}, /* sector erase */ |
| 244 | {JEDEC_WREN, JEDEC_BE_52}, /* block erase */ |
| 245 | {JEDEC_WREN, JEDEC_BE_D8}, /* block erase */ |
| 246 | {JEDEC_WREN, JEDEC_CE_60}, /* chip erase */ |
| 247 | {JEDEC_WREN, JEDEC_CE_C7}, /* chip erase */ |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 248 | /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */ |
| 249 | {JEDEC_WREN, JEDEC_WRSR}, |
FENG yu ning | f041e9b | 2008-12-15 02:32:11 +0000 | [diff] [blame] | 250 | {JEDEC_EWSR, JEDEC_WRSR}, |
| 251 | {0,} |
| 252 | }; |
| 253 | |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 254 | /* Reasonable default configuration. Needs ad-hoc modifications if we |
| 255 | * encounter unlisted opcodes. Fun. |
| 256 | */ |
Carl-Daniel Hailfinger | ad3cc55 | 2010-07-03 11:02:10 +0000 | [diff] [blame] | 257 | static OPCODES O_ST_M25P = { |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 258 | { |
| 259 | JEDEC_WREN, |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 260 | JEDEC_EWSR, |
| 261 | }, |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 262 | { |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 263 | {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte |
Stefan Reinauer | 325b5d4 | 2008-06-27 15:18:20 +0000 | [diff] [blame] | 264 | {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 265 | {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector |
Stefan Reinauer | 325b5d4 | 2008-06-27 15:18:20 +0000 | [diff] [blame] | 266 | {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg |
Carl-Daniel Hailfinger | 15aa7c6 | 2009-05-26 21:25:08 +0000 | [diff] [blame] | 267 | {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 268 | {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register |
Stefan Reinauer | 325b5d4 | 2008-06-27 15:18:20 +0000 | [diff] [blame] | 269 | {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 270 | {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase |
| 271 | } |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 272 | }; |
| 273 | |
Helge Wagner | 738e252 | 2010-10-05 22:06:05 +0000 | [diff] [blame] | 274 | /* List of opcodes with their corresponding spi_type |
| 275 | * It is used to reprogram the chipset OPCODE table on-the-fly if an opcode |
| 276 | * is needed which is currently not in the chipset OPCODE table |
| 277 | */ |
| 278 | static OPCODE POSSIBLE_OPCODES[] = { |
| 279 | {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte |
| 280 | {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data |
| 281 | {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector |
| 282 | {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg |
| 283 | {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature |
| 284 | {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register |
| 285 | {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID |
| 286 | {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase |
| 287 | {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Sector erase |
| 288 | {JEDEC_BE_52, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Block erase |
| 289 | {JEDEC_AAI_WORD_PROGRAM, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Auto Address Increment |
| 290 | }; |
| 291 | |
Carl-Daniel Hailfinger | ad3cc55 | 2010-07-03 11:02:10 +0000 | [diff] [blame] | 292 | static OPCODES O_EXISTING = {}; |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 293 | |
Stefan Tauner | 2a8b262 | 2011-06-11 09:53:16 +0000 | [diff] [blame] | 294 | /* pretty printing functions */ |
Stefan Tauner | 8b391b8 | 2011-08-09 01:49:34 +0000 | [diff] [blame] | 295 | static void prettyprint_opcodes(OPCODES *ops) |
Stefan Tauner | 2a8b262 | 2011-06-11 09:53:16 +0000 | [diff] [blame] | 296 | { |
Stefan Tauner | 84e1dde | 2011-09-17 19:53:11 +0000 | [diff] [blame^] | 297 | OPCODE oc; |
| 298 | const char *t; |
| 299 | const char *a; |
| 300 | uint8_t i; |
| 301 | static const char *const spi_type[4] = { |
| 302 | "read w/o addr", |
| 303 | "write w/o addr", |
| 304 | "read w/ addr", |
| 305 | "write w/ addr" |
| 306 | }; |
| 307 | static const char *const atomic_type[3] = { |
| 308 | "none", |
| 309 | " 0 ", |
| 310 | " 1 " |
| 311 | }; |
| 312 | |
| 313 | if (ops == NULL) |
Stefan Tauner | 2a8b262 | 2011-06-11 09:53:16 +0000 | [diff] [blame] | 314 | return; |
| 315 | |
Stefan Tauner | 84e1dde | 2011-09-17 19:53:11 +0000 | [diff] [blame^] | 316 | msg_pdbg2(" OP Type Pre-OP\n"); |
Stefan Tauner | 2a8b262 | 2011-06-11 09:53:16 +0000 | [diff] [blame] | 317 | for (i = 0; i < 8; i++) { |
| 318 | oc = ops->opcode[i]; |
Stefan Tauner | 84e1dde | 2011-09-17 19:53:11 +0000 | [diff] [blame^] | 319 | t = (oc.spi_type > 3) ? "invalid" : spi_type[oc.spi_type]; |
| 320 | a = (oc.atomic > 2) ? "invalid" : atomic_type[oc.atomic]; |
| 321 | msg_pdbg2("op[%d]: 0x%02x, %s, %s\n", i, oc.opcode, t, a); |
Stefan Tauner | 2a8b262 | 2011-06-11 09:53:16 +0000 | [diff] [blame] | 322 | } |
Stefan Tauner | 84e1dde | 2011-09-17 19:53:11 +0000 | [diff] [blame^] | 323 | msg_pdbg2("Pre-OP 0: 0x%02x, Pre-OP 1: 0x%02x\n", ops->preop[0], |
| 324 | ops->preop[1]); |
Stefan Tauner | 2a8b262 | 2011-06-11 09:53:16 +0000 | [diff] [blame] | 325 | } |
| 326 | |
| 327 | #define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) |
| 328 | |
Stefan Tauner | 5520694 | 2011-06-11 09:53:22 +0000 | [diff] [blame] | 329 | static void prettyprint_ich9_reg_hsfs(uint16_t reg_val) |
| 330 | { |
| 331 | msg_pdbg("HSFS: "); |
| 332 | pprint_reg(HSFS, FDONE, reg_val, ", "); |
| 333 | pprint_reg(HSFS, FCERR, reg_val, ", "); |
| 334 | pprint_reg(HSFS, AEL, reg_val, ", "); |
| 335 | pprint_reg(HSFS, BERASE, reg_val, ", "); |
| 336 | pprint_reg(HSFS, SCIP, reg_val, ", "); |
| 337 | pprint_reg(HSFS, FDOPSS, reg_val, ", "); |
| 338 | pprint_reg(HSFS, FDV, reg_val, ", "); |
| 339 | pprint_reg(HSFS, FLOCKDN, reg_val, "\n"); |
| 340 | } |
| 341 | |
| 342 | static void prettyprint_ich9_reg_hsfc(uint16_t reg_val) |
| 343 | { |
| 344 | msg_pdbg("HSFC: "); |
| 345 | pprint_reg(HSFC, FGO, reg_val, ", "); |
| 346 | pprint_reg(HSFC, FCYCLE, reg_val, ", "); |
| 347 | pprint_reg(HSFC, FDBC, reg_val, ", "); |
| 348 | pprint_reg(HSFC, SME, reg_val, "\n"); |
| 349 | } |
| 350 | |
Stefan Tauner | 2a8b262 | 2011-06-11 09:53:16 +0000 | [diff] [blame] | 351 | static void prettyprint_ich9_reg_ssfs(uint32_t reg_val) |
| 352 | { |
| 353 | msg_pdbg("SSFS: "); |
| 354 | pprint_reg(SSFS, SCIP, reg_val, ", "); |
| 355 | pprint_reg(SSFS, FDONE, reg_val, ", "); |
| 356 | pprint_reg(SSFS, FCERR, reg_val, ", "); |
| 357 | pprint_reg(SSFS, AEL, reg_val, "\n"); |
| 358 | } |
| 359 | |
| 360 | static void prettyprint_ich9_reg_ssfc(uint32_t reg_val) |
| 361 | { |
| 362 | msg_pdbg("SSFC: "); |
| 363 | pprint_reg(SSFC, SCGO, reg_val, ", "); |
| 364 | pprint_reg(SSFC, ACS, reg_val, ", "); |
| 365 | pprint_reg(SSFC, SPOP, reg_val, ", "); |
| 366 | pprint_reg(SSFC, COP, reg_val, ", "); |
| 367 | pprint_reg(SSFC, DBC, reg_val, ", "); |
| 368 | pprint_reg(SSFC, SME, reg_val, ", "); |
| 369 | pprint_reg(SSFC, SCF, reg_val, "\n"); |
| 370 | } |
| 371 | |
Helge Wagner | 738e252 | 2010-10-05 22:06:05 +0000 | [diff] [blame] | 372 | static uint8_t lookup_spi_type(uint8_t opcode) |
| 373 | { |
| 374 | int a; |
| 375 | |
Uwe Hermann | 91f4afa | 2011-07-28 08:13:25 +0000 | [diff] [blame] | 376 | for (a = 0; a < ARRAY_SIZE(POSSIBLE_OPCODES); a++) { |
Helge Wagner | 738e252 | 2010-10-05 22:06:05 +0000 | [diff] [blame] | 377 | if (POSSIBLE_OPCODES[a].opcode == opcode) |
| 378 | return POSSIBLE_OPCODES[a].spi_type; |
| 379 | } |
| 380 | |
| 381 | return 0xFF; |
| 382 | } |
| 383 | |
| 384 | static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt) |
| 385 | { |
| 386 | uint8_t spi_type; |
| 387 | |
| 388 | spi_type = lookup_spi_type(opcode); |
| 389 | if (spi_type > 3) { |
| 390 | /* Try to guess spi type from read/write sizes. |
| 391 | * The following valid writecnt/readcnt combinations exist: |
| 392 | * writecnt = 4, readcnt >= 0 |
| 393 | * writecnt = 1, readcnt >= 0 |
| 394 | * writecnt >= 4, readcnt = 0 |
| 395 | * writecnt >= 1, readcnt = 0 |
| 396 | * writecnt >= 1 is guaranteed for all commands. |
| 397 | */ |
| 398 | if (readcnt == 0) |
| 399 | /* if readcnt=0 and writecount >= 4, we don't know if it is WRITE_NO_ADDRESS |
| 400 | * or WRITE_WITH_ADDRESS. But if we use WRITE_NO_ADDRESS and the first 3 data |
| 401 | * bytes are actual the address, they go to the bus anyhow |
| 402 | */ |
| 403 | spi_type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; |
| 404 | else if (writecnt == 1) // and readcnt is > 0 |
| 405 | spi_type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; |
| 406 | else if (writecnt == 4) // and readcnt is > 0 |
| 407 | spi_type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; |
| 408 | // else we have an invalid case, will be handled below |
| 409 | } |
| 410 | if (spi_type <= 3) { |
| 411 | int oppos=2; // use original JEDEC_BE_D8 offset |
| 412 | curopcodes->opcode[oppos].opcode = opcode; |
| 413 | curopcodes->opcode[oppos].spi_type = spi_type; |
Carl-Daniel Hailfinger | 54ce73a | 2011-05-03 21:49:41 +0000 | [diff] [blame] | 414 | program_opcodes(curopcodes, 0); |
Helge Wagner | 738e252 | 2010-10-05 22:06:05 +0000 | [diff] [blame] | 415 | oppos = find_opcode(curopcodes, opcode); |
| 416 | msg_pdbg ("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos); |
| 417 | return oppos; |
| 418 | } |
| 419 | return -1; |
| 420 | } |
| 421 | |
Uwe Hermann | 09e04f7 | 2009-05-16 22:36:00 +0000 | [diff] [blame] | 422 | static int find_opcode(OPCODES *op, uint8_t opcode) |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 423 | { |
| 424 | int a; |
| 425 | |
| 426 | for (a = 0; a < 8; a++) { |
| 427 | if (op->opcode[a].opcode == opcode) |
| 428 | return a; |
| 429 | } |
| 430 | |
| 431 | return -1; |
| 432 | } |
| 433 | |
Uwe Hermann | 09e04f7 | 2009-05-16 22:36:00 +0000 | [diff] [blame] | 434 | static int find_preop(OPCODES *op, uint8_t preop) |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 435 | { |
| 436 | int a; |
| 437 | |
| 438 | for (a = 0; a < 2; a++) { |
| 439 | if (op->preop[a] == preop) |
| 440 | return a; |
| 441 | } |
| 442 | |
| 443 | return -1; |
| 444 | } |
| 445 | |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 446 | /* Create a struct OPCODES based on what we find in the locked down chipset. */ |
FENG yu ning | f041e9b | 2008-12-15 02:32:11 +0000 | [diff] [blame] | 447 | static int generate_opcodes(OPCODES * op) |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 448 | { |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 449 | int a; |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 450 | uint16_t preop, optype; |
| 451 | uint32_t opmenu[2]; |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 452 | |
| 453 | if (op == NULL) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 454 | msg_perr("\n%s: null OPCODES pointer!\n", __func__); |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 455 | return -1; |
| 456 | } |
| 457 | |
Michael Karcher | b9dbe48 | 2011-05-11 17:07:07 +0000 | [diff] [blame] | 458 | switch (spi_programmer->type) { |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 459 | case SPI_CONTROLLER_ICH7: |
| 460 | case SPI_CONTROLLER_VIA: |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 461 | preop = REGREAD16(ICH7_REG_PREOP); |
| 462 | optype = REGREAD16(ICH7_REG_OPTYPE); |
| 463 | opmenu[0] = REGREAD32(ICH7_REG_OPMENU); |
| 464 | opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4); |
| 465 | break; |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 466 | case SPI_CONTROLLER_ICH9: |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 467 | preop = REGREAD16(ICH9_REG_PREOP); |
| 468 | optype = REGREAD16(ICH9_REG_OPTYPE); |
| 469 | opmenu[0] = REGREAD32(ICH9_REG_OPMENU); |
| 470 | opmenu[1] = REGREAD32(ICH9_REG_OPMENU + 4); |
| 471 | break; |
| 472 | default: |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 473 | msg_perr("%s: unsupported chipset\n", __func__); |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 474 | return -1; |
| 475 | } |
| 476 | |
| 477 | op->preop[0] = (uint8_t) preop; |
| 478 | op->preop[1] = (uint8_t) (preop >> 8); |
| 479 | |
| 480 | for (a = 0; a < 8; a++) { |
| 481 | op->opcode[a].spi_type = (uint8_t) (optype & 0x3); |
| 482 | optype >>= 2; |
| 483 | } |
| 484 | |
| 485 | for (a = 0; a < 4; a++) { |
| 486 | op->opcode[a].opcode = (uint8_t) (opmenu[0] & 0xff); |
| 487 | opmenu[0] >>= 8; |
| 488 | } |
| 489 | |
| 490 | for (a = 4; a < 8; a++) { |
| 491 | op->opcode[a].opcode = (uint8_t) (opmenu[1] & 0xff); |
| 492 | opmenu[1] >>= 8; |
| 493 | } |
| 494 | |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 495 | /* No preopcodes used by default. */ |
| 496 | for (a = 0; a < 8; a++) |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 497 | op->opcode[a].atomic = 0; |
| 498 | |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 499 | return 0; |
| 500 | } |
| 501 | |
Carl-Daniel Hailfinger | 54ce73a | 2011-05-03 21:49:41 +0000 | [diff] [blame] | 502 | static int program_opcodes(OPCODES *op, int enable_undo) |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 503 | { |
| 504 | uint8_t a; |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 505 | uint16_t preop, optype; |
| 506 | uint32_t opmenu[2]; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 507 | |
| 508 | /* Program Prefix Opcodes */ |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 509 | /* 0:7 Prefix Opcode 1 */ |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 510 | preop = (op->preop[0]); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 511 | /* 8:16 Prefix Opcode 2 */ |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 512 | preop |= ((uint16_t) op->preop[1]) << 8; |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 513 | |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 514 | /* Program Opcode Types 0 - 7 */ |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 515 | optype = 0; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 516 | for (a = 0; a < 8; a++) { |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 517 | optype |= ((uint16_t) op->opcode[a].spi_type) << (a * 2); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 518 | } |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 519 | |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 520 | /* Program Allowable Opcodes 0 - 3 */ |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 521 | opmenu[0] = 0; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 522 | for (a = 0; a < 4; a++) { |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 523 | opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 524 | } |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 525 | |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 526 | /*Program Allowable Opcodes 4 - 7 */ |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 527 | opmenu[1] = 0; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 528 | for (a = 4; a < 8; a++) { |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 529 | opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 530 | } |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 531 | |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 532 | msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); |
Michael Karcher | b9dbe48 | 2011-05-11 17:07:07 +0000 | [diff] [blame] | 533 | switch (spi_programmer->type) { |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 534 | case SPI_CONTROLLER_ICH7: |
| 535 | case SPI_CONTROLLER_VIA: |
Carl-Daniel Hailfinger | 54ce73a | 2011-05-03 21:49:41 +0000 | [diff] [blame] | 536 | /* Register undo only for enable_undo=1, i.e. first call. */ |
| 537 | if (enable_undo) { |
| 538 | rmmio_valw(ich_spibar + ICH7_REG_PREOP); |
| 539 | rmmio_valw(ich_spibar + ICH7_REG_OPTYPE); |
| 540 | rmmio_vall(ich_spibar + ICH7_REG_OPMENU); |
| 541 | rmmio_vall(ich_spibar + ICH7_REG_OPMENU + 4); |
| 542 | } |
| 543 | mmio_writew(preop, ich_spibar + ICH7_REG_PREOP); |
| 544 | mmio_writew(optype, ich_spibar + ICH7_REG_OPTYPE); |
| 545 | mmio_writel(opmenu[0], ich_spibar + ICH7_REG_OPMENU); |
| 546 | mmio_writel(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 547 | break; |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 548 | case SPI_CONTROLLER_ICH9: |
Carl-Daniel Hailfinger | 54ce73a | 2011-05-03 21:49:41 +0000 | [diff] [blame] | 549 | /* Register undo only for enable_undo=1, i.e. first call. */ |
| 550 | if (enable_undo) { |
| 551 | rmmio_valw(ich_spibar + ICH9_REG_PREOP); |
| 552 | rmmio_valw(ich_spibar + ICH9_REG_OPTYPE); |
| 553 | rmmio_vall(ich_spibar + ICH9_REG_OPMENU); |
| 554 | rmmio_vall(ich_spibar + ICH9_REG_OPMENU + 4); |
| 555 | } |
| 556 | mmio_writew(preop, ich_spibar + ICH9_REG_PREOP); |
| 557 | mmio_writew(optype, ich_spibar + ICH9_REG_OPTYPE); |
| 558 | mmio_writel(opmenu[0], ich_spibar + ICH9_REG_OPMENU); |
| 559 | mmio_writel(opmenu[1], ich_spibar + ICH9_REG_OPMENU + 4); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 560 | break; |
| 561 | default: |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 562 | msg_perr("%s: unsupported chipset\n", __func__); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 563 | return -1; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 564 | } |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 565 | |
| 566 | return 0; |
| 567 | } |
| 568 | |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 569 | /* |
| 570 | * Try to set BBAR (BIOS Base Address Register), but read back the value in case |
| 571 | * it didn't stick. |
| 572 | */ |
Stefan Tauner | e27b2d4 | 2011-07-01 00:39:09 +0000 | [diff] [blame] | 573 | static void ich_set_bbar(uint32_t min_addr) |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 574 | { |
Stefan Tauner | e27b2d4 | 2011-07-01 00:39:09 +0000 | [diff] [blame] | 575 | int bbar_off; |
Michael Karcher | b9dbe48 | 2011-05-11 17:07:07 +0000 | [diff] [blame] | 576 | switch (spi_programmer->type) { |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 577 | case SPI_CONTROLLER_ICH7: |
Carl-Daniel Hailfinger | 841d631 | 2010-11-24 23:37:22 +0000 | [diff] [blame] | 578 | case SPI_CONTROLLER_VIA: |
Stefan Tauner | e27b2d4 | 2011-07-01 00:39:09 +0000 | [diff] [blame] | 579 | bbar_off = 0x50; |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 580 | break; |
| 581 | case SPI_CONTROLLER_ICH9: |
Stefan Tauner | e27b2d4 | 2011-07-01 00:39:09 +0000 | [diff] [blame] | 582 | bbar_off = ICH9_REG_BBAR; |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 583 | break; |
| 584 | default: |
Carl-Daniel Hailfinger | 841d631 | 2010-11-24 23:37:22 +0000 | [diff] [blame] | 585 | msg_perr("Unknown chipset for BBAR setting!\n"); |
Stefan Tauner | e27b2d4 | 2011-07-01 00:39:09 +0000 | [diff] [blame] | 586 | return; |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 587 | } |
Stefan Tauner | e27b2d4 | 2011-07-01 00:39:09 +0000 | [diff] [blame] | 588 | |
| 589 | ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & ~BBAR_MASK; |
| 590 | if (ichspi_bbar) { |
| 591 | msg_pdbg("Reserved bits in BBAR not zero: 0x%08x\n", |
| 592 | ichspi_bbar); |
| 593 | } |
| 594 | min_addr &= BBAR_MASK; |
| 595 | ichspi_bbar |= min_addr; |
| 596 | rmmio_writel(ichspi_bbar, ich_spibar + bbar_off); |
| 597 | ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & BBAR_MASK; |
| 598 | |
| 599 | /* We don't have any option except complaining. And if the write |
| 600 | * failed, the restore will fail as well, so no problem there. |
| 601 | */ |
| 602 | if (ichspi_bbar != min_addr) |
| 603 | msg_perr("Setting BBAR failed!\n"); |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 604 | } |
| 605 | |
Stefan Tauner | 8b391b8 | 2011-08-09 01:49:34 +0000 | [diff] [blame] | 606 | /* Read len bytes from the fdata/spid register into the data array. |
| 607 | * |
| 608 | * Note that using len > spi_programmer->max_data_read will return garbage or |
| 609 | * may even crash. |
| 610 | */ |
| 611 | static void ich_read_data(uint8_t *data, int len, int reg0_off) |
| 612 | { |
| 613 | int i; |
| 614 | uint32_t temp32 = 0; |
| 615 | |
| 616 | for (i = 0; i < len; i++) { |
| 617 | if ((i % 4) == 0) |
| 618 | temp32 = REGREAD32(reg0_off + i); |
| 619 | |
| 620 | data[i] = (temp32 >> ((i % 4) * 8)) & 0xff; |
| 621 | } |
| 622 | } |
| 623 | |
| 624 | /* Fill len bytes from the data array into the fdata/spid registers. |
| 625 | * |
| 626 | * Note that using len > spi_programmer->max_data_write will trash the registers |
| 627 | * following the data registers. |
| 628 | */ |
| 629 | static void ich_fill_data(const uint8_t *data, int len, int reg0_off) |
| 630 | { |
| 631 | uint32_t temp32 = 0; |
| 632 | int i; |
| 633 | |
| 634 | if (len <= 0) |
| 635 | return; |
| 636 | |
| 637 | for (i = 0; i < len; i++) { |
| 638 | if ((i % 4) == 0) |
| 639 | temp32 = 0; |
| 640 | |
| 641 | temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8); |
| 642 | |
| 643 | if ((i % 4) == 3) /* 32 bits are full, write them to regs. */ |
| 644 | REGWRITE32(reg0_off + (i - (i % 4)), temp32); |
| 645 | } |
| 646 | i--; |
| 647 | if ((i % 4) != 3) /* Write remaining data to regs. */ |
| 648 | REGWRITE32(reg0_off + (i - (i % 4)), temp32); |
| 649 | } |
| 650 | |
FENG yu ning | f041e9b | 2008-12-15 02:32:11 +0000 | [diff] [blame] | 651 | /* This function generates OPCODES from or programs OPCODES to ICH according to |
| 652 | * the chipset's SPI configuration lock. |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 653 | * |
FENG yu ning | f041e9b | 2008-12-15 02:32:11 +0000 | [diff] [blame] | 654 | * It should be called before ICH sends any spi command. |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 655 | */ |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 656 | static int ich_init_opcodes(void) |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 657 | { |
| 658 | int rc = 0; |
| 659 | OPCODES *curopcodes_done; |
| 660 | |
| 661 | if (curopcodes) |
| 662 | return 0; |
| 663 | |
| 664 | if (ichspi_lock) { |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 665 | msg_pdbg("Reading OPCODES... "); |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 666 | curopcodes_done = &O_EXISTING; |
FENG yu ning | f041e9b | 2008-12-15 02:32:11 +0000 | [diff] [blame] | 667 | rc = generate_opcodes(curopcodes_done); |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 668 | } else { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 669 | msg_pdbg("Programming OPCODES... "); |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 670 | curopcodes_done = &O_ST_M25P; |
Carl-Daniel Hailfinger | 54ce73a | 2011-05-03 21:49:41 +0000 | [diff] [blame] | 671 | rc = program_opcodes(curopcodes_done, 1); |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 672 | /* Technically not part of opcode init, but it allows opcodes |
| 673 | * to run without transaction errors by setting the lowest |
| 674 | * allowed address to zero. |
| 675 | */ |
| 676 | ich_set_bbar(0); |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 677 | } |
| 678 | |
| 679 | if (rc) { |
| 680 | curopcodes = NULL; |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 681 | msg_perr("failed\n"); |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 682 | return 1; |
| 683 | } else { |
| 684 | curopcodes = curopcodes_done; |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 685 | msg_pdbg("done\n"); |
Stefan Tauner | 8b391b8 | 2011-08-09 01:49:34 +0000 | [diff] [blame] | 686 | prettyprint_opcodes(curopcodes); |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 687 | return 0; |
| 688 | } |
| 689 | } |
| 690 | |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 691 | static int ich7_run_opcode(OPCODE op, uint32_t offset, |
Rudolf Marek | 3fdbccf | 2008-06-30 21:38:30 +0000 | [diff] [blame] | 692 | uint8_t datalength, uint8_t * data, int maxdata) |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 693 | { |
| 694 | int write_cmd = 0; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 695 | int timeout; |
Stefan Tauner | 8b391b8 | 2011-08-09 01:49:34 +0000 | [diff] [blame] | 696 | uint32_t temp32; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 697 | uint16_t temp16; |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 698 | uint64_t opmenu; |
| 699 | int opcode_index; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 700 | |
| 701 | /* Is it a write command? */ |
| 702 | if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) |
| 703 | || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) { |
| 704 | write_cmd = 1; |
| 705 | } |
| 706 | |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 707 | timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ |
| 708 | while ((REGREAD16(ICH7_REG_SPIS) & SPIS_SCIP) && --timeout) { |
| 709 | programmer_delay(10); |
| 710 | } |
| 711 | if (!timeout) { |
| 712 | msg_perr("Error: SCIP never cleared!\n"); |
| 713 | return 1; |
| 714 | } |
| 715 | |
Stefan Tauner | 10b3e22 | 2011-07-01 00:39:23 +0000 | [diff] [blame] | 716 | /* Program offset in flash into SPIA while preserving reserved bits. */ |
| 717 | temp32 = REGREAD32(ICH7_REG_SPIA) & ~0x00FFFFFF; |
| 718 | REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF) | temp32); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 719 | |
Stefan Tauner | 10b3e22 | 2011-07-01 00:39:23 +0000 | [diff] [blame] | 720 | /* Program data into SPID0 to N */ |
Stefan Tauner | 8b391b8 | 2011-08-09 01:49:34 +0000 | [diff] [blame] | 721 | if (write_cmd && (datalength != 0)) |
| 722 | ich_fill_data(data, datalength, ICH7_REG_SPID0); |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 723 | |
| 724 | /* Assemble SPIS */ |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 725 | temp16 = REGREAD16(ICH7_REG_SPIS); |
| 726 | /* keep reserved bits */ |
| 727 | temp16 &= SPIS_RESERVED_MASK; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 728 | /* clear error status registers */ |
Stefan Tauner | 0c1ec45 | 2011-06-11 09:53:09 +0000 | [diff] [blame] | 729 | temp16 |= (SPIS_CDS | SPIS_FCERR); |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 730 | REGWRITE16(ICH7_REG_SPIS, temp16); |
| 731 | |
| 732 | /* Assemble SPIC */ |
| 733 | temp16 = 0; |
| 734 | |
| 735 | if (datalength != 0) { |
| 736 | temp16 |= SPIC_DS; |
Rudolf Marek | 3fdbccf | 2008-06-30 21:38:30 +0000 | [diff] [blame] | 737 | temp16 |= ((uint32_t) ((datalength - 1) & (maxdata - 1))) << 8; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 738 | } |
| 739 | |
| 740 | /* Select opcode */ |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 741 | opmenu = REGREAD32(ICH7_REG_OPMENU); |
| 742 | opmenu |= ((uint64_t)REGREAD32(ICH7_REG_OPMENU + 4)) << 32; |
| 743 | |
Uwe Hermann | 7b2969b | 2009-04-15 10:52:49 +0000 | [diff] [blame] | 744 | for (opcode_index = 0; opcode_index < 8; opcode_index++) { |
| 745 | if ((opmenu & 0xff) == op.opcode) { |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 746 | break; |
| 747 | } |
| 748 | opmenu >>= 8; |
| 749 | } |
| 750 | if (opcode_index == 8) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 751 | msg_pdbg("Opcode %x not found.\n", op.opcode); |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 752 | return 1; |
| 753 | } |
| 754 | temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 755 | |
Michael Karcher | 136125a | 2011-04-29 22:11:36 +0000 | [diff] [blame] | 756 | timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ |
| 757 | /* Handle Atomic. Atomic commands include three steps: |
| 758 | - sending the preop (mainly EWSR or WREN) |
| 759 | - sending the main command |
| 760 | - waiting for the busy bit (WIP) to be cleared |
| 761 | This means the timeout must be sufficient for chip erase |
| 762 | of slow high-capacity chips. |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 763 | */ |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 764 | switch (op.atomic) { |
| 765 | case 2: |
| 766 | /* Select second preop. */ |
| 767 | temp16 |= SPIC_SPOP; |
| 768 | /* And fall through. */ |
| 769 | case 1: |
| 770 | /* Atomic command (preop+op) */ |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 771 | temp16 |= SPIC_ACS; |
Michael Karcher | 136125a | 2011-04-29 22:11:36 +0000 | [diff] [blame] | 772 | timeout = 100 * 1000 * 60; /* 60 seconds */ |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 773 | break; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 774 | } |
| 775 | |
| 776 | /* Start */ |
| 777 | temp16 |= SPIC_SCGO; |
| 778 | |
| 779 | /* write it */ |
| 780 | REGWRITE16(ICH7_REG_SPIC, temp16); |
| 781 | |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 782 | /* Wait for Cycle Done Status or Flash Cycle Error. */ |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 783 | while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) && |
| 784 | --timeout) { |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 785 | programmer_delay(10); |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 786 | } |
| 787 | if (!timeout) { |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 788 | msg_perr("timeout, ICH7_REG_SPIS=0x%04x\n", |
| 789 | REGREAD16(ICH7_REG_SPIS)); |
| 790 | return 1; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 791 | } |
| 792 | |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 793 | /* FIXME: make sure we do not needlessly cause transaction errors. */ |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 794 | temp16 = REGREAD16(ICH7_REG_SPIS); |
| 795 | if (temp16 & SPIS_FCERR) { |
Stefan Tauner | 8ed2934 | 2011-04-29 23:53:09 +0000 | [diff] [blame] | 796 | msg_perr("Transaction error!\n"); |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 797 | /* keep reserved bits */ |
| 798 | temp16 &= SPIS_RESERVED_MASK; |
| 799 | REGWRITE16(ICH7_REG_SPIS, temp16 | SPIS_FCERR); |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 800 | return 1; |
| 801 | } |
| 802 | |
Stefan Tauner | 8b391b8 | 2011-08-09 01:49:34 +0000 | [diff] [blame] | 803 | if ((!write_cmd) && (datalength != 0)) |
| 804 | ich_read_data(data, datalength, ICH7_REG_SPID0); |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 805 | |
| 806 | return 0; |
| 807 | } |
| 808 | |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 809 | static int ich9_run_opcode(OPCODE op, uint32_t offset, |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 810 | uint8_t datalength, uint8_t * data) |
| 811 | { |
| 812 | int write_cmd = 0; |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 813 | int timeout; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 814 | uint32_t temp32; |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 815 | uint64_t opmenu; |
| 816 | int opcode_index; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 817 | |
| 818 | /* Is it a write command? */ |
| 819 | if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) |
| 820 | || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) { |
| 821 | write_cmd = 1; |
| 822 | } |
| 823 | |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 824 | timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ |
| 825 | while ((REGREAD8(ICH9_REG_SSFS) & SSFS_SCIP) && --timeout) { |
| 826 | programmer_delay(10); |
| 827 | } |
| 828 | if (!timeout) { |
| 829 | msg_perr("Error: SCIP never cleared!\n"); |
| 830 | return 1; |
| 831 | } |
| 832 | |
Stefan Tauner | 10b3e22 | 2011-07-01 00:39:23 +0000 | [diff] [blame] | 833 | /* Program offset in flash into FADDR while preserve the reserved bits |
| 834 | * and clearing the 25. address bit which is only useable in hwseq. */ |
| 835 | temp32 = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF; |
| 836 | REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF) | temp32); |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 837 | |
| 838 | /* Program data into FDATA0 to N */ |
Stefan Tauner | 8b391b8 | 2011-08-09 01:49:34 +0000 | [diff] [blame] | 839 | if (write_cmd && (datalength != 0)) |
| 840 | ich_fill_data(data, datalength, ICH9_REG_FDATA0); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 841 | |
| 842 | /* Assemble SSFS + SSFC */ |
Helge Wagner | a319be1 | 2010-08-11 21:06:10 +0000 | [diff] [blame] | 843 | temp32 = REGREAD32(ICH9_REG_SSFS); |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 844 | /* Keep reserved bits only */ |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 845 | temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; |
Stefan Tauner | 0c1ec45 | 2011-06-11 09:53:09 +0000 | [diff] [blame] | 846 | /* Clear cycle done and cycle error status registers */ |
| 847 | temp32 |= (SSFS_FDONE | SSFS_FCERR); |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 848 | REGWRITE32(ICH9_REG_SSFS, temp32); |
| 849 | |
Uwe Hermann | 4e3d0b3 | 2010-03-25 23:18:41 +0000 | [diff] [blame] | 850 | /* Use 20 MHz */ |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 851 | temp32 |= SSFC_SCF_20MHZ; |
| 852 | |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 853 | /* Set data byte count (DBC) and data cycle bit (DS) */ |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 854 | if (datalength != 0) { |
| 855 | uint32_t datatemp; |
| 856 | temp32 |= SSFC_DS; |
Stefan Tauner | 0c1ec45 | 2011-06-11 09:53:09 +0000 | [diff] [blame] | 857 | datatemp = ((((uint32_t)datalength - 1) << SSFC_DBC_OFF) & |
| 858 | SSFC_DBC); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 859 | temp32 |= datatemp; |
| 860 | } |
| 861 | |
| 862 | /* Select opcode */ |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 863 | opmenu = REGREAD32(ICH9_REG_OPMENU); |
| 864 | opmenu |= ((uint64_t)REGREAD32(ICH9_REG_OPMENU + 4)) << 32; |
| 865 | |
Uwe Hermann | 7b2969b | 2009-04-15 10:52:49 +0000 | [diff] [blame] | 866 | for (opcode_index = 0; opcode_index < 8; opcode_index++) { |
| 867 | if ((opmenu & 0xff) == op.opcode) { |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 868 | break; |
| 869 | } |
| 870 | opmenu >>= 8; |
| 871 | } |
| 872 | if (opcode_index == 8) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 873 | msg_pdbg("Opcode %x not found.\n", op.opcode); |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 874 | return 1; |
| 875 | } |
| 876 | temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 877 | |
Michael Karcher | 136125a | 2011-04-29 22:11:36 +0000 | [diff] [blame] | 878 | timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ |
| 879 | /* Handle Atomic. Atomic commands include three steps: |
| 880 | - sending the preop (mainly EWSR or WREN) |
| 881 | - sending the main command |
| 882 | - waiting for the busy bit (WIP) to be cleared |
| 883 | This means the timeout must be sufficient for chip erase |
| 884 | of slow high-capacity chips. |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 885 | */ |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 886 | switch (op.atomic) { |
| 887 | case 2: |
| 888 | /* Select second preop. */ |
| 889 | temp32 |= SSFC_SPOP; |
| 890 | /* And fall through. */ |
| 891 | case 1: |
| 892 | /* Atomic command (preop+op) */ |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 893 | temp32 |= SSFC_ACS; |
Michael Karcher | 136125a | 2011-04-29 22:11:36 +0000 | [diff] [blame] | 894 | timeout = 100 * 1000 * 60; /* 60 seconds */ |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 895 | break; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 896 | } |
| 897 | |
| 898 | /* Start */ |
| 899 | temp32 |= SSFC_SCGO; |
| 900 | |
| 901 | /* write it */ |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 902 | REGWRITE32(ICH9_REG_SSFS, temp32); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 903 | |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 904 | /* Wait for Cycle Done Status or Flash Cycle Error. */ |
Stefan Tauner | 0c1ec45 | 2011-06-11 09:53:09 +0000 | [diff] [blame] | 905 | while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_FDONE | SSFS_FCERR)) == 0) && |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 906 | --timeout) { |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 907 | programmer_delay(10); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 908 | } |
| 909 | if (!timeout) { |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 910 | msg_perr("timeout, ICH9_REG_SSFS=0x%08x\n", |
| 911 | REGREAD32(ICH9_REG_SSFS)); |
| 912 | return 1; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 913 | } |
| 914 | |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 915 | /* FIXME make sure we do not needlessly cause transaction errors. */ |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 916 | temp32 = REGREAD32(ICH9_REG_SSFS); |
| 917 | if (temp32 & SSFS_FCERR) { |
Stefan Tauner | 8ed2934 | 2011-04-29 23:53:09 +0000 | [diff] [blame] | 918 | msg_perr("Transaction error!\n"); |
Stefan Tauner | 2a8b262 | 2011-06-11 09:53:16 +0000 | [diff] [blame] | 919 | prettyprint_ich9_reg_ssfs(temp32); |
| 920 | prettyprint_ich9_reg_ssfc(temp32); |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 921 | /* keep reserved bits */ |
| 922 | temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; |
| 923 | /* Clear the transaction error. */ |
| 924 | REGWRITE32(ICH9_REG_SSFS, temp32 | SSFS_FCERR); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 925 | return 1; |
| 926 | } |
| 927 | |
Stefan Tauner | 8b391b8 | 2011-08-09 01:49:34 +0000 | [diff] [blame] | 928 | if ((!write_cmd) && (datalength != 0)) |
| 929 | ich_read_data(data, datalength, ICH9_REG_FDATA0); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 930 | |
| 931 | return 0; |
| 932 | } |
| 933 | |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 934 | static int run_opcode(OPCODE op, uint32_t offset, |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 935 | uint8_t datalength, uint8_t * data) |
| 936 | { |
Stefan Tauner | b2d5f6a | 2011-06-11 19:44:31 +0000 | [diff] [blame] | 937 | /* max_data_read == max_data_write for all Intel/VIA SPI masters */ |
| 938 | uint8_t maxlength = spi_programmer->max_data_read; |
| 939 | |
| 940 | if (spi_programmer->type == SPI_CONTROLLER_NONE) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 941 | msg_perr("%s: unsupported chipset\n", __func__); |
Stefan Tauner | b2d5f6a | 2011-06-11 19:44:31 +0000 | [diff] [blame] | 942 | return -1; |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 943 | } |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 944 | |
Stefan Tauner | b2d5f6a | 2011-06-11 19:44:31 +0000 | [diff] [blame] | 945 | if (datalength > maxlength) { |
| 946 | msg_perr("%s: Internal command size error for " |
| 947 | "opcode 0x%02x, got datalength=%i, want <=%i\n", |
| 948 | __func__, op.opcode, datalength, maxlength); |
| 949 | return SPI_INVALID_LENGTH; |
| 950 | } |
| 951 | |
| 952 | switch (spi_programmer->type) { |
| 953 | case SPI_CONTROLLER_VIA: |
| 954 | case SPI_CONTROLLER_ICH7: |
| 955 | return ich7_run_opcode(op, offset, datalength, data, maxlength); |
| 956 | case SPI_CONTROLLER_ICH9: |
| 957 | return ich9_run_opcode(op, offset, datalength, data); |
| 958 | default: |
| 959 | /* If we ever get here, something really weird happened */ |
| 960 | return -1; |
| 961 | } |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 962 | } |
| 963 | |
Michael Karcher | b9dbe48 | 2011-05-11 17:07:07 +0000 | [diff] [blame] | 964 | static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, |
Stefan Reinauer | 325b5d4 | 2008-06-27 15:18:20 +0000 | [diff] [blame] | 965 | const unsigned char *writearr, unsigned char *readarr) |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 966 | { |
Carl-Daniel Hailfinger | 142e30f | 2009-07-14 10:26:56 +0000 | [diff] [blame] | 967 | int result; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 968 | int opcode_index = -1; |
| 969 | const unsigned char cmd = *writearr; |
| 970 | OPCODE *opcode; |
| 971 | uint32_t addr = 0; |
| 972 | uint8_t *data; |
| 973 | int count; |
| 974 | |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 975 | /* find cmd in opcodes-table */ |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 976 | opcode_index = find_opcode(curopcodes, cmd); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 977 | if (opcode_index == -1) { |
Helge Wagner | 738e252 | 2010-10-05 22:06:05 +0000 | [diff] [blame] | 978 | if (!ichspi_lock) |
| 979 | opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt); |
| 980 | if (opcode_index == -1) { |
Stefan Tauner | 355cbfd | 2011-05-28 02:37:14 +0000 | [diff] [blame] | 981 | msg_pdbg("Invalid OPCODE 0x%02x, will not execute.\n", |
| 982 | cmd); |
Helge Wagner | 738e252 | 2010-10-05 22:06:05 +0000 | [diff] [blame] | 983 | return SPI_INVALID_OPCODE; |
| 984 | } |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 985 | } |
| 986 | |
| 987 | opcode = &(curopcodes->opcode[opcode_index]); |
| 988 | |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 989 | /* The following valid writecnt/readcnt combinations exist: |
| 990 | * writecnt = 4, readcnt >= 0 |
| 991 | * writecnt = 1, readcnt >= 0 |
| 992 | * writecnt >= 4, readcnt = 0 |
| 993 | * writecnt >= 1, readcnt = 0 |
| 994 | * writecnt >= 1 is guaranteed for all commands. |
| 995 | */ |
| 996 | if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) && |
| 997 | (writecnt != 4)) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 998 | msg_perr("%s: Internal command size error for opcode " |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 999 | "0x%02x, got writecnt=%i, want =4\n", __func__, cmd, |
| 1000 | writecnt); |
| 1001 | return SPI_INVALID_LENGTH; |
| 1002 | } |
| 1003 | if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_NO_ADDRESS) && |
| 1004 | (writecnt != 1)) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1005 | msg_perr("%s: Internal command size error for opcode " |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 1006 | "0x%02x, got writecnt=%i, want =1\n", __func__, cmd, |
| 1007 | writecnt); |
| 1008 | return SPI_INVALID_LENGTH; |
| 1009 | } |
| 1010 | if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) && |
| 1011 | (writecnt < 4)) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1012 | msg_perr("%s: Internal command size error for opcode " |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 1013 | "0x%02x, got writecnt=%i, want >=4\n", __func__, cmd, |
| 1014 | writecnt); |
| 1015 | return SPI_INVALID_LENGTH; |
| 1016 | } |
| 1017 | if (((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) || |
| 1018 | (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) && |
| 1019 | (readcnt)) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1020 | msg_perr("%s: Internal command size error for opcode " |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 1021 | "0x%02x, got readcnt=%i, want =0\n", __func__, cmd, |
| 1022 | readcnt); |
| 1023 | return SPI_INVALID_LENGTH; |
| 1024 | } |
| 1025 | |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 1026 | /* if opcode-type requires an address */ |
| 1027 | if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS || |
| 1028 | opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { |
Stefan Reinauer | 325b5d4 | 2008-06-27 15:18:20 +0000 | [diff] [blame] | 1029 | addr = (writearr[1] << 16) | |
| 1030 | (writearr[2] << 8) | (writearr[3] << 0); |
Michael Karcher | b9dbe48 | 2011-05-11 17:07:07 +0000 | [diff] [blame] | 1031 | switch (spi_programmer->type) { |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 1032 | case SPI_CONTROLLER_ICH7: |
Carl-Daniel Hailfinger | 841d631 | 2010-11-24 23:37:22 +0000 | [diff] [blame] | 1033 | case SPI_CONTROLLER_VIA: |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 1034 | case SPI_CONTROLLER_ICH9: |
| 1035 | if (addr < ichspi_bbar) { |
| 1036 | msg_perr("%s: Address 0x%06x below allowed " |
| 1037 | "range 0x%06x-0xffffff\n", __func__, |
| 1038 | addr, ichspi_bbar); |
| 1039 | return SPI_INVALID_ADDRESS; |
| 1040 | } |
| 1041 | break; |
| 1042 | default: |
| 1043 | break; |
| 1044 | } |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 1045 | } |
Stefan Reinauer | 325b5d4 | 2008-06-27 15:18:20 +0000 | [diff] [blame] | 1046 | |
Stefan Tauner | b2d5f6a | 2011-06-11 19:44:31 +0000 | [diff] [blame] | 1047 | /* Translate read/write array/count. |
| 1048 | * The maximum data length is identical for the maximum read length and |
| 1049 | * for the maximum write length excluding opcode and address. Opcode and |
| 1050 | * address are stored in separate registers, not in the data registers |
| 1051 | * and are thus not counted towards data length. The only exception |
| 1052 | * applies if the opcode definition (un)intentionally classifies said |
| 1053 | * opcode incorrectly as non-address opcode or vice versa. */ |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 1054 | if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) { |
Stefan Reinauer | 325b5d4 | 2008-06-27 15:18:20 +0000 | [diff] [blame] | 1055 | data = (uint8_t *) (writearr + 1); |
| 1056 | count = writecnt - 1; |
| 1057 | } else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { |
| 1058 | data = (uint8_t *) (writearr + 4); |
| 1059 | count = writecnt - 4; |
| 1060 | } else { |
| 1061 | data = (uint8_t *) readarr; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 1062 | count = readcnt; |
| 1063 | } |
Stefan Reinauer | 325b5d4 | 2008-06-27 15:18:20 +0000 | [diff] [blame] | 1064 | |
Carl-Daniel Hailfinger | 142e30f | 2009-07-14 10:26:56 +0000 | [diff] [blame] | 1065 | result = run_opcode(*opcode, addr, count, data); |
| 1066 | if (result) { |
Stefan Tauner | 8ed2934 | 2011-04-29 23:53:09 +0000 | [diff] [blame] | 1067 | msg_pdbg("Running OPCODE 0x%02x failed ", opcode->opcode); |
| 1068 | if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) || |
| 1069 | (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS)) { |
| 1070 | msg_pdbg("at address 0x%06x ", addr); |
| 1071 | } |
| 1072 | msg_pdbg("(payload length was %d).\n", count); |
| 1073 | |
| 1074 | /* Print out the data array if it contains data to write. |
| 1075 | * Errors are detected before the received data is read back into |
| 1076 | * the array so it won't make sense to print it then. */ |
| 1077 | if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) || |
| 1078 | (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) { |
| 1079 | int i; |
| 1080 | msg_pspew("The data was:\n"); |
| 1081 | for(i=0; i<count; i++){ |
| 1082 | msg_pspew("%3d: 0x%02x\n", i, data[i]); |
| 1083 | } |
| 1084 | } |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 1085 | } |
| 1086 | |
Carl-Daniel Hailfinger | 142e30f | 2009-07-14 10:26:56 +0000 | [diff] [blame] | 1087 | return result; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 1088 | } |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 1089 | |
Michael Karcher | b9dbe48 | 2011-05-11 17:07:07 +0000 | [diff] [blame] | 1090 | static int ich_spi_send_multicommand(struct spi_command *cmds) |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 1091 | { |
| 1092 | int ret = 0; |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 1093 | int i; |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 1094 | int oppos, preoppos; |
| 1095 | for (; (cmds->writecnt || cmds->readcnt) && !ret; cmds++) { |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 1096 | if ((cmds + 1)->writecnt || (cmds + 1)->readcnt) { |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 1097 | /* Next command is valid. */ |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 1098 | preoppos = find_preop(curopcodes, cmds->writearr[0]); |
| 1099 | oppos = find_opcode(curopcodes, (cmds + 1)->writearr[0]); |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 1100 | if ((oppos == -1) && (preoppos != -1)) { |
| 1101 | /* Current command is listed as preopcode in |
| 1102 | * ICH struct OPCODES, but next command is not |
| 1103 | * listed as opcode in that struct. |
| 1104 | * Check for command sanity, then |
| 1105 | * try to reprogram the ICH opcode list. |
| 1106 | */ |
| 1107 | if (find_preop(curopcodes, |
| 1108 | (cmds + 1)->writearr[0]) != -1) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1109 | msg_perr("%s: Two subsequent " |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 1110 | "preopcodes 0x%02x and 0x%02x, " |
| 1111 | "ignoring the first.\n", |
| 1112 | __func__, cmds->writearr[0], |
| 1113 | (cmds + 1)->writearr[0]); |
| 1114 | continue; |
| 1115 | } |
| 1116 | /* If the chipset is locked down, we'll fail |
| 1117 | * during execution of the next command anyway. |
| 1118 | * No need to bother with fixups. |
| 1119 | */ |
| 1120 | if (!ichspi_lock) { |
Helge Wagner | 738e252 | 2010-10-05 22:06:05 +0000 | [diff] [blame] | 1121 | oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt); |
| 1122 | if (oppos == -1) |
| 1123 | continue; |
| 1124 | curopcodes->opcode[oppos].atomic = preoppos + 1; |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 1125 | continue; |
| 1126 | } |
| 1127 | } |
| 1128 | if ((oppos != -1) && (preoppos != -1)) { |
| 1129 | /* Current command is listed as preopcode in |
| 1130 | * ICH struct OPCODES and next command is listed |
| 1131 | * as opcode in that struct. Match them up. |
| 1132 | */ |
| 1133 | curopcodes->opcode[oppos].atomic = preoppos + 1; |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 1134 | continue; |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 1135 | } |
| 1136 | /* If none of the above if-statements about oppos or |
| 1137 | * preoppos matched, this is a normal opcode. |
| 1138 | */ |
| 1139 | } |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 1140 | ret = ich_spi_send_command(cmds->writecnt, cmds->readcnt, |
| 1141 | cmds->writearr, cmds->readarr); |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 1142 | /* Reset the type of all opcodes to non-atomic. */ |
| 1143 | for (i = 0; i < 8; i++) |
| 1144 | curopcodes->opcode[i].atomic = 0; |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 1145 | } |
| 1146 | return ret; |
| 1147 | } |
Carl-Daniel Hailfinger | cceafa2 | 2010-05-26 01:45:41 +0000 | [diff] [blame] | 1148 | |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1149 | #define ICH_BMWAG(x) ((x >> 24) & 0xff) |
| 1150 | #define ICH_BMRAG(x) ((x >> 16) & 0xff) |
| 1151 | #define ICH_BRWA(x) ((x >> 8) & 0xff) |
| 1152 | #define ICH_BRRA(x) ((x >> 0) & 0xff) |
| 1153 | |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1154 | static void do_ich9_spi_frap(uint32_t frap, int i) |
| 1155 | { |
Mathias Krause | a60faab | 2011-01-17 07:50:42 +0000 | [diff] [blame] | 1156 | static const char *const access_names[4] = { |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1157 | "locked", "read-only", "write-only", "read-write" |
| 1158 | }; |
Mathias Krause | a60faab | 2011-01-17 07:50:42 +0000 | [diff] [blame] | 1159 | static const char *const region_names[5] = { |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1160 | "Flash Descriptor", "BIOS", "Management Engine", |
| 1161 | "Gigabit Ethernet", "Platform Data" |
| 1162 | }; |
| 1163 | uint32_t base, limit; |
| 1164 | int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) | |
| 1165 | (((ICH_BRRA(frap) >> i) & 1) << 0); |
Stefan Tauner | 29c8083 | 2011-06-12 08:14:10 +0000 | [diff] [blame] | 1166 | int offset = ICH9_REG_FREG0 + i * 4; |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1167 | uint32_t freg = mmio_readl(ich_spibar + offset); |
| 1168 | |
| 1169 | msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n", |
| 1170 | offset, freg, i, region_names[i]); |
| 1171 | |
| 1172 | base = ICH_FREG_BASE(freg); |
| 1173 | limit = ICH_FREG_LIMIT(freg); |
Joshua Roys | d172ecd | 2011-05-26 13:30:51 +0000 | [diff] [blame] | 1174 | if (base > limit) { |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1175 | /* this FREG is disabled */ |
| 1176 | msg_pdbg("%s region is unused.\n", region_names[i]); |
| 1177 | return; |
| 1178 | } |
| 1179 | |
Stefan Tauner | 1e14639 | 2011-09-15 23:52:55 +0000 | [diff] [blame] | 1180 | msg_pdbg("0x%08x-0x%08x is %s\n", base, (limit | 0x0fff), |
| 1181 | access_names[rwperms]); |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1182 | } |
| 1183 | |
Michael Karcher | b9dbe48 | 2011-05-11 17:07:07 +0000 | [diff] [blame] | 1184 | static const struct spi_programmer spi_programmer_ich7 = { |
| 1185 | .type = SPI_CONTROLLER_ICH7, |
| 1186 | .max_data_read = 64, |
| 1187 | .max_data_write = 64, |
| 1188 | .command = ich_spi_send_command, |
| 1189 | .multicommand = ich_spi_send_multicommand, |
| 1190 | .read = default_spi_read, |
| 1191 | .write_256 = default_spi_write_256, |
| 1192 | }; |
| 1193 | |
| 1194 | static const struct spi_programmer spi_programmer_ich9 = { |
| 1195 | .type = SPI_CONTROLLER_ICH9, |
| 1196 | .max_data_read = 64, |
| 1197 | .max_data_write = 64, |
| 1198 | .command = ich_spi_send_command, |
| 1199 | .multicommand = ich_spi_send_multicommand, |
| 1200 | .read = default_spi_read, |
| 1201 | .write_256 = default_spi_write_256, |
| 1202 | }; |
| 1203 | |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1204 | int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, |
| 1205 | int ich_generation) |
| 1206 | { |
| 1207 | int i; |
| 1208 | uint8_t old, new; |
| 1209 | uint16_t spibar_offset, tmp2; |
| 1210 | uint32_t tmp; |
Stefan Tauner | 1e14639 | 2011-09-15 23:52:55 +0000 | [diff] [blame] | 1211 | int ichspi_desc = 0; |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1212 | |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1213 | switch (ich_generation) { |
| 1214 | case 7: |
Michael Karcher | b9dbe48 | 2011-05-11 17:07:07 +0000 | [diff] [blame] | 1215 | register_spi_programmer(&spi_programmer_ich7); |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1216 | spibar_offset = 0x3020; |
| 1217 | break; |
| 1218 | case 8: |
Michael Karcher | b9dbe48 | 2011-05-11 17:07:07 +0000 | [diff] [blame] | 1219 | register_spi_programmer(&spi_programmer_ich9); |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1220 | spibar_offset = 0x3020; |
| 1221 | break; |
| 1222 | case 9: |
| 1223 | case 10: |
| 1224 | default: /* Future version might behave the same */ |
Michael Karcher | b9dbe48 | 2011-05-11 17:07:07 +0000 | [diff] [blame] | 1225 | register_spi_programmer(&spi_programmer_ich9); |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1226 | spibar_offset = 0x3800; |
| 1227 | break; |
| 1228 | } |
| 1229 | |
| 1230 | /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */ |
| 1231 | msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", base, spibar_offset); |
| 1232 | |
| 1233 | /* Assign Virtual Address */ |
| 1234 | ich_spibar = rcrb + spibar_offset; |
| 1235 | |
Michael Karcher | b9dbe48 | 2011-05-11 17:07:07 +0000 | [diff] [blame] | 1236 | switch (spi_programmer->type) { |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1237 | case SPI_CONTROLLER_ICH7: |
| 1238 | msg_pdbg("0x00: 0x%04x (SPIS)\n", |
| 1239 | mmio_readw(ich_spibar + 0)); |
| 1240 | msg_pdbg("0x02: 0x%04x (SPIC)\n", |
| 1241 | mmio_readw(ich_spibar + 2)); |
| 1242 | msg_pdbg("0x04: 0x%08x (SPIA)\n", |
| 1243 | mmio_readl(ich_spibar + 4)); |
| 1244 | for (i = 0; i < 8; i++) { |
| 1245 | int offs; |
| 1246 | offs = 8 + (i * 8); |
| 1247 | msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs, |
| 1248 | mmio_readl(ich_spibar + offs), i); |
| 1249 | msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, |
| 1250 | mmio_readl(ich_spibar + offs + 4), i); |
| 1251 | } |
| 1252 | ichspi_bbar = mmio_readl(ich_spibar + 0x50); |
| 1253 | msg_pdbg("0x50: 0x%08x (BBAR)\n", |
| 1254 | ichspi_bbar); |
| 1255 | msg_pdbg("0x54: 0x%04x (PREOP)\n", |
| 1256 | mmio_readw(ich_spibar + 0x54)); |
| 1257 | msg_pdbg("0x56: 0x%04x (OPTYPE)\n", |
| 1258 | mmio_readw(ich_spibar + 0x56)); |
| 1259 | msg_pdbg("0x58: 0x%08x (OPMENU)\n", |
| 1260 | mmio_readl(ich_spibar + 0x58)); |
| 1261 | msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", |
| 1262 | mmio_readl(ich_spibar + 0x5c)); |
Stefan Tauner | 122dd12 | 2011-07-24 15:34:56 +0000 | [diff] [blame] | 1263 | for (i = 0; i < 3; i++) { |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1264 | int offs; |
| 1265 | offs = 0x60 + (i * 4); |
| 1266 | msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, |
| 1267 | mmio_readl(ich_spibar + offs), i); |
| 1268 | } |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1269 | if (mmio_readw(ich_spibar) & (1 << 15)) { |
| 1270 | msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); |
| 1271 | ichspi_lock = 1; |
| 1272 | } |
| 1273 | ich_init_opcodes(); |
| 1274 | break; |
| 1275 | case SPI_CONTROLLER_ICH9: |
Stefan Tauner | 29c8083 | 2011-06-12 08:14:10 +0000 | [diff] [blame] | 1276 | tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1277 | msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); |
Stefan Tauner | 5520694 | 2011-06-11 09:53:22 +0000 | [diff] [blame] | 1278 | prettyprint_ich9_reg_hsfs(tmp2); |
Stefan Tauner | 29c8083 | 2011-06-12 08:14:10 +0000 | [diff] [blame] | 1279 | if (tmp2 & HSFS_FLOCKDN) { |
Stefan Tauner | 5520694 | 2011-06-11 09:53:22 +0000 | [diff] [blame] | 1280 | msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); |
| 1281 | ichspi_lock = 1; |
| 1282 | } |
Stefan Tauner | 1e14639 | 2011-09-15 23:52:55 +0000 | [diff] [blame] | 1283 | if (tmp2 & HSFS_FDV) |
| 1284 | ichspi_desc = 1; |
Stefan Tauner | 5520694 | 2011-06-11 09:53:22 +0000 | [diff] [blame] | 1285 | |
Stefan Tauner | 29c8083 | 2011-06-12 08:14:10 +0000 | [diff] [blame] | 1286 | tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); |
Stefan Tauner | 5520694 | 2011-06-11 09:53:22 +0000 | [diff] [blame] | 1287 | msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); |
| 1288 | prettyprint_ich9_reg_hsfc(tmp2); |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1289 | |
Stefan Tauner | 5ffe65b | 2011-07-07 04:10:57 +0000 | [diff] [blame] | 1290 | tmp = mmio_readl(ich_spibar + ICH9_REG_FADDR); |
| 1291 | msg_pdbg("0x08: 0x%08x (FADDR)\n", tmp); |
Stefan Tauner | 29c8083 | 2011-06-12 08:14:10 +0000 | [diff] [blame] | 1292 | tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP); |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1293 | msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); |
| 1294 | msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); |
| 1295 | msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); |
| 1296 | msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp)); |
| 1297 | msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp)); |
| 1298 | |
| 1299 | /* print out the FREGx registers along with FRAP access bits */ |
| 1300 | for(i = 0; i < 5; i++) |
| 1301 | do_ich9_spi_frap(tmp, i); |
| 1302 | |
| 1303 | msg_pdbg("0x74: 0x%08x (PR0)\n", |
Stefan Tauner | 29c8083 | 2011-06-12 08:14:10 +0000 | [diff] [blame] | 1304 | mmio_readl(ich_spibar + ICH9_REG_PR0)); |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1305 | msg_pdbg("0x78: 0x%08x (PR1)\n", |
Stefan Tauner | 29c8083 | 2011-06-12 08:14:10 +0000 | [diff] [blame] | 1306 | mmio_readl(ich_spibar + ICH9_REG_PR1)); |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1307 | msg_pdbg("0x7C: 0x%08x (PR2)\n", |
Stefan Tauner | 29c8083 | 2011-06-12 08:14:10 +0000 | [diff] [blame] | 1308 | mmio_readl(ich_spibar + ICH9_REG_PR2)); |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1309 | msg_pdbg("0x80: 0x%08x (PR3)\n", |
Stefan Tauner | 29c8083 | 2011-06-12 08:14:10 +0000 | [diff] [blame] | 1310 | mmio_readl(ich_spibar + ICH9_REG_PR3)); |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1311 | msg_pdbg("0x84: 0x%08x (PR4)\n", |
Stefan Tauner | 29c8083 | 2011-06-12 08:14:10 +0000 | [diff] [blame] | 1312 | mmio_readl(ich_spibar + ICH9_REG_PR4)); |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 1313 | |
Stefan Tauner | 29c8083 | 2011-06-12 08:14:10 +0000 | [diff] [blame] | 1314 | tmp = mmio_readl(ich_spibar + ICH9_REG_SSFS); |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 1315 | msg_pdbg("0x90: 0x%02x (SSFS)\n", tmp & 0xff); |
Stefan Tauner | 2a8b262 | 2011-06-11 09:53:16 +0000 | [diff] [blame] | 1316 | prettyprint_ich9_reg_ssfs(tmp); |
Stefan Tauner | 29c8083 | 2011-06-12 08:14:10 +0000 | [diff] [blame] | 1317 | if (tmp & SSFS_FCERR) { |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 1318 | msg_pdbg("Clearing SSFS.FCERR\n"); |
Stefan Tauner | 29c8083 | 2011-06-12 08:14:10 +0000 | [diff] [blame] | 1319 | mmio_writeb(SSFS_FCERR, ich_spibar + ICH9_REG_SSFS); |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 1320 | } |
Stefan Tauner | 2a8b262 | 2011-06-11 09:53:16 +0000 | [diff] [blame] | 1321 | msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp >> 8); |
| 1322 | prettyprint_ich9_reg_ssfc(tmp); |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 1323 | |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1324 | msg_pdbg("0x94: 0x%04x (PREOP)\n", |
Stefan Tauner | 29c8083 | 2011-06-12 08:14:10 +0000 | [diff] [blame] | 1325 | mmio_readw(ich_spibar + ICH9_REG_PREOP)); |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1326 | msg_pdbg("0x96: 0x%04x (OPTYPE)\n", |
Stefan Tauner | 29c8083 | 2011-06-12 08:14:10 +0000 | [diff] [blame] | 1327 | mmio_readw(ich_spibar + ICH9_REG_OPTYPE)); |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1328 | msg_pdbg("0x98: 0x%08x (OPMENU)\n", |
Stefan Tauner | 29c8083 | 2011-06-12 08:14:10 +0000 | [diff] [blame] | 1329 | mmio_readl(ich_spibar + ICH9_REG_OPMENU)); |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1330 | msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", |
Stefan Tauner | 29c8083 | 2011-06-12 08:14:10 +0000 | [diff] [blame] | 1331 | mmio_readl(ich_spibar + ICH9_REG_OPMENU + 4)); |
Stefan Tauner | 1e14639 | 2011-09-15 23:52:55 +0000 | [diff] [blame] | 1332 | if (ich_generation == 8) { |
| 1333 | tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC); |
| 1334 | msg_pdbg("0xC1: 0x%08x (VSCC)\n", tmp); |
| 1335 | msg_pdbg("VSCC: "); |
| 1336 | prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); |
| 1337 | } else { |
| 1338 | ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); |
| 1339 | msg_pdbg("0xA0: 0x%08x (BBAR)\n", |
| 1340 | ichspi_bbar); |
Stefan Tauner | bd649e4 | 2011-07-01 00:39:16 +0000 | [diff] [blame] | 1341 | |
Stefan Tauner | 1e14639 | 2011-09-15 23:52:55 +0000 | [diff] [blame] | 1342 | tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); |
| 1343 | msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp); |
| 1344 | msg_pdbg("LVSCC: "); |
| 1345 | prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); |
| 1346 | |
| 1347 | tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); |
| 1348 | msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp); |
| 1349 | msg_pdbg("UVSCC: "); |
| 1350 | prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); |
| 1351 | |
| 1352 | tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); |
| 1353 | msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); |
| 1354 | } |
| 1355 | |
| 1356 | msg_pdbg("\n"); |
| 1357 | if (ichspi_desc) { |
| 1358 | struct ich_descriptors desc = {{ 0 }}; |
| 1359 | if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == |
| 1360 | ICH_RET_OK) |
| 1361 | prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, |
| 1362 | &desc); |
| 1363 | } |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1364 | ich_init_opcodes(); |
| 1365 | break; |
| 1366 | default: |
| 1367 | /* Nothing */ |
| 1368 | break; |
| 1369 | } |
| 1370 | |
| 1371 | old = pci_read_byte(dev, 0xdc); |
| 1372 | msg_pdbg("SPI Read Configuration: "); |
| 1373 | new = (old >> 2) & 0x3; |
| 1374 | switch (new) { |
| 1375 | case 0: |
| 1376 | case 1: |
| 1377 | case 2: |
| 1378 | msg_pdbg("prefetching %sabled, caching %sabled, ", |
| 1379 | (new & 0x2) ? "en" : "dis", |
| 1380 | (new & 0x1) ? "dis" : "en"); |
| 1381 | break; |
| 1382 | default: |
| 1383 | msg_pdbg("invalid prefetching/caching settings, "); |
| 1384 | break; |
| 1385 | } |
| 1386 | return 0; |
| 1387 | } |
| 1388 | |
Michael Karcher | b9dbe48 | 2011-05-11 17:07:07 +0000 | [diff] [blame] | 1389 | static const struct spi_programmer spi_programmer_via = { |
| 1390 | .type = SPI_CONTROLLER_VIA, |
| 1391 | .max_data_read = 16, |
| 1392 | .max_data_write = 16, |
| 1393 | .command = ich_spi_send_command, |
| 1394 | .multicommand = ich_spi_send_multicommand, |
| 1395 | .read = default_spi_read, |
| 1396 | .write_256 = default_spi_write_256, |
| 1397 | }; |
| 1398 | |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1399 | int via_init_spi(struct pci_dev *dev) |
| 1400 | { |
| 1401 | uint32_t mmio_base; |
Carl-Daniel Hailfinger | 841d631 | 2010-11-24 23:37:22 +0000 | [diff] [blame] | 1402 | int i; |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1403 | |
| 1404 | mmio_base = (pci_read_long(dev, 0xbc)) << 8; |
| 1405 | msg_pdbg("MMIO base at = 0x%x\n", mmio_base); |
| 1406 | ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); |
| 1407 | |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1408 | /* Not sure if it speaks all these bus protocols. */ |
Carl-Daniel Hailfinger | 1a22795 | 2011-07-27 07:13:06 +0000 | [diff] [blame] | 1409 | buses_supported = BUS_LPC | BUS_FWH; |
Michael Karcher | b9dbe48 | 2011-05-11 17:07:07 +0000 | [diff] [blame] | 1410 | register_spi_programmer(&spi_programmer_via); |
Carl-Daniel Hailfinger | 841d631 | 2010-11-24 23:37:22 +0000 | [diff] [blame] | 1411 | |
| 1412 | msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); |
| 1413 | msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2)); |
| 1414 | msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(ich_spibar + 4)); |
| 1415 | for (i = 0; i < 2; i++) { |
| 1416 | int offs; |
| 1417 | offs = 8 + (i * 8); |
| 1418 | msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs, |
| 1419 | mmio_readl(ich_spibar + offs), i); |
| 1420 | msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, |
| 1421 | mmio_readl(ich_spibar + offs + 4), i); |
| 1422 | } |
| 1423 | ichspi_bbar = mmio_readl(ich_spibar + 0x50); |
| 1424 | msg_pdbg("0x50: 0x%08x (BBAR)\n", ichspi_bbar); |
| 1425 | msg_pdbg("0x54: 0x%04x (PREOP)\n", mmio_readw(ich_spibar + 0x54)); |
| 1426 | msg_pdbg("0x56: 0x%04x (OPTYPE)\n", mmio_readw(ich_spibar + 0x56)); |
| 1427 | msg_pdbg("0x58: 0x%08x (OPMENU)\n", mmio_readl(ich_spibar + 0x58)); |
| 1428 | msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + 0x5c)); |
| 1429 | for (i = 0; i < 3; i++) { |
| 1430 | int offs; |
| 1431 | offs = 0x60 + (i * 4); |
| 1432 | msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, |
| 1433 | mmio_readl(ich_spibar + offs), i); |
| 1434 | } |
| 1435 | msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n", |
| 1436 | mmio_readw(ich_spibar + 0x6c)); |
| 1437 | if (mmio_readw(ich_spibar) & (1 << 15)) { |
| 1438 | msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); |
| 1439 | ichspi_lock = 1; |
| 1440 | } |
| 1441 | |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1442 | ich_init_opcodes(); |
| 1443 | |
| 1444 | return 0; |
| 1445 | } |
| 1446 | |
Carl-Daniel Hailfinger | cceafa2 | 2010-05-26 01:45:41 +0000 | [diff] [blame] | 1447 | #endif |