blob: e1ede60d37fe9dae69dc5fd9a94abf3f1496def3 [file] [log] [blame]
Dominik Geyerb46acba2008-05-16 12:55:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2008 Stefan Wildemann <stefan.wildemann@kontron.com>
5 * Copyright (C) 2008 Claus Gindhart <claus.gindhart@kontron.com>
6 * Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com>
Stefan Reinauera9424d52008-06-27 16:28:34 +00007 * Copyright (C) 2008 coresystems GmbH <info@coresystems.de>
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +00008 * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
Stefan Tauner8b391b82011-08-09 01:49:34 +00009 * Copyright (C) 2011 Stefan Tauner
Dominik Geyerb46acba2008-05-16 12:55:55 +000010 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
Dominik Geyerb46acba2008-05-16 12:55:55 +000020 */
21
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000022#if defined(__i386__) || defined(__x86_64__)
23
Dominik Geyerb46acba2008-05-16 12:55:55 +000024#include <string.h>
Stefan Taunerd0c5dc22011-10-20 12:57:14 +000025#include <stdlib.h>
Dominik Geyerb46acba2008-05-16 12:55:55 +000026#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000027#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000028#include "hwaccess.h"
Dominik Geyerb46acba2008-05-16 12:55:55 +000029#include "spi.h"
Stefan Tauner1e146392011-09-15 23:52:55 +000030#include "ich_descriptors.h"
Dominik Geyerb46acba2008-05-16 12:55:55 +000031
Nico Huberd2d39932019-01-18 16:49:37 +010032/* Apollo Lake */
33#define APL_REG_FREG12 0xe0 /* 32 Bytes Flash Region 12 */
34
Nico Huberd54e4f42017-03-23 23:45:47 +010035/* Sunrise Point */
36
37/* Added HSFS Status bits */
38#define HSFS_WRSDIS_OFF 11 /* 11: Flash Configuration Lock-Down */
39#define HSFS_WRSDIS (0x1 << HSFS_WRSDIS_OFF)
40#define HSFS_PRR34_LOCKDN_OFF 12 /* 12: PRR3 PRR4 Lock-Down */
41#define HSFS_PRR34_LOCKDN (0x1 << HSFS_PRR34_LOCKDN_OFF)
42/* HSFS_BERASE vanished */
43
44/*
45 * HSFC and HSFS 16-bit registers are combined into the 32-bit
46 * BIOS_HSFSTS_CTL register in the Sunrise Point datasheet,
47 * however we still treat them separately in order to reuse code.
48 */
49
50/* Changed HSFC Control bits */
51#define PCH100_HSFC_FCYCLE_OFF (17 - 16) /* 1-4: FLASH Cycle */
52#define PCH100_HSFC_FCYCLE (0xf << PCH100_HSFC_FCYCLE_OFF)
53/* New HSFC Control bit */
54#define HSFC_WET_OFF (21 - 16) /* 5: Write Enable Type */
55#define HSFC_WET (0x1 << HSFC_WET_OFF)
56
57#define PCH100_FADDR_FLA 0x07ffffff
58
59#define PCH100_REG_DLOCK 0x0c /* 32 Bits Discrete Lock Bits */
60#define DLOCK_BMWAG_LOCKDN_OFF 0
61#define DLOCK_BMWAG_LOCKDN (0x1 << DLOCK_BMWAG_LOCKDN_OFF)
62#define DLOCK_BMRAG_LOCKDN_OFF 1
63#define DLOCK_BMRAG_LOCKDN (0x1 << DLOCK_BMRAG_LOCKDN_OFF)
64#define DLOCK_SBMWAG_LOCKDN_OFF 2
65#define DLOCK_SBMWAG_LOCKDN (0x1 << DLOCK_SBMWAG_LOCKDN_OFF)
66#define DLOCK_SBMRAG_LOCKDN_OFF 3
67#define DLOCK_SBMRAG_LOCKDN (0x1 << DLOCK_SBMRAG_LOCKDN_OFF)
68#define DLOCK_PR0_LOCKDN_OFF 8
69#define DLOCK_PR0_LOCKDN (0x1 << DLOCK_PR0_LOCKDN_OFF)
70#define DLOCK_PR1_LOCKDN_OFF 9
71#define DLOCK_PR1_LOCKDN (0x1 << DLOCK_PR1_LOCKDN_OFF)
72#define DLOCK_PR2_LOCKDN_OFF 10
73#define DLOCK_PR2_LOCKDN (0x1 << DLOCK_PR2_LOCKDN_OFF)
74#define DLOCK_PR3_LOCKDN_OFF 11
75#define DLOCK_PR3_LOCKDN (0x1 << DLOCK_PR3_LOCKDN_OFF)
76#define DLOCK_PR4_LOCKDN_OFF 12
77#define DLOCK_PR4_LOCKDN (0x1 << DLOCK_PR4_LOCKDN_OFF)
78#define DLOCK_SSEQ_LOCKDN_OFF 16
79#define DLOCK_SSEQ_LOCKDN (0x1 << DLOCK_SSEQ_LOCKDN_OFF)
80
81#define PCH100_REG_FPR0 0x84 /* 32 Bits Protected Range 0 */
82#define PCH100_REG_GPR0 0x98 /* 32 Bits Global Protected Range 0 */
83
84#define PCH100_REG_SSFSC 0xA0 /* 32 Bits Status (8) + Control (24) */
85#define PCH100_REG_PREOP 0xA4 /* 16 Bits */
86#define PCH100_REG_OPTYPE 0xA6 /* 16 Bits */
87#define PCH100_REG_OPMENU 0xA8 /* 64 Bits */
88
Stefan Reinauera9424d52008-06-27 16:28:34 +000089/* ICH9 controller register definition */
Stefan Tauner55206942011-06-11 09:53:22 +000090#define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */
91#define HSFS_FDONE_OFF 0 /* 0: Flash Cycle Done */
92#define HSFS_FDONE (0x1 << HSFS_FDONE_OFF)
93#define HSFS_FCERR_OFF 1 /* 1: Flash Cycle Error */
94#define HSFS_FCERR (0x1 << HSFS_FCERR_OFF)
95#define HSFS_AEL_OFF 2 /* 2: Access Error Log */
96#define HSFS_AEL (0x1 << HSFS_AEL_OFF)
97#define HSFS_BERASE_OFF 3 /* 3-4: Block/Sector Erase Size */
98#define HSFS_BERASE (0x3 << HSFS_BERASE_OFF)
99#define HSFS_SCIP_OFF 5 /* 5: SPI Cycle In Progress */
100#define HSFS_SCIP (0x1 << HSFS_SCIP_OFF)
101 /* 6-12: reserved */
102#define HSFS_FDOPSS_OFF 13 /* 13: Flash Descriptor Override Pin-Strap Status */
103#define HSFS_FDOPSS (0x1 << HSFS_FDOPSS_OFF)
104#define HSFS_FDV_OFF 14 /* 14: Flash Descriptor Valid */
105#define HSFS_FDV (0x1 << HSFS_FDV_OFF)
106#define HSFS_FLOCKDN_OFF 15 /* 15: Flash Configuration Lock-Down */
107#define HSFS_FLOCKDN (0x1 << HSFS_FLOCKDN_OFF)
108
109#define ICH9_REG_HSFC 0x06 /* 16 Bits Hardware Sequencing Flash Control */
110#define HSFC_FGO_OFF 0 /* 0: Flash Cycle Go */
111#define HSFC_FGO (0x1 << HSFC_FGO_OFF)
112#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */
113#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
114 /* 3-7: reserved */
115#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
116#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)
117 /* 14: reserved */
118#define HSFC_SME_OFF 15 /* 15: SPI SMI# Enable */
119#define HSFC_SME (0x1 << HSFC_SME_OFF)
120
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000121#define ICH9_REG_FADDR 0x08 /* 32 Bits */
Nico Huberd54e4f42017-03-23 23:45:47 +0100122#define ICH9_FADDR_FLA 0x01ffffff
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000123#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000124
Stefan Tauner29c80832011-06-12 08:14:10 +0000125#define ICH9_REG_FRAP 0x50 /* 32 Bytes Flash Region Access Permissions */
126#define ICH9_REG_FREG0 0x54 /* 32 Bytes Flash Region 0 */
127
128#define ICH9_REG_PR0 0x74 /* 32 Bytes Protected Range 0 */
Stefan Taunerbf69aaa2011-09-17 21:21:48 +0000129#define PR_WP_OFF 31 /* 31: write protection enable */
130#define PR_RP_OFF 15 /* 15: read protection enable */
Stefan Tauner29c80832011-06-12 08:14:10 +0000131
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000132#define ICH9_REG_SSFS 0x90 /* 08 Bits */
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000133#define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */
134#define SSFS_SCIP (0x1 << SSFS_SCIP_OFF)
135#define SSFS_FDONE_OFF 2 /* Cycle Done Status */
136#define SSFS_FDONE (0x1 << SSFS_FDONE_OFF)
137#define SSFS_FCERR_OFF 3 /* Flash Cycle Error */
138#define SSFS_FCERR (0x1 << SSFS_FCERR_OFF)
139#define SSFS_AEL_OFF 4 /* Access Error Log */
140#define SSFS_AEL (0x1 << SSFS_AEL_OFF)
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000141/* The following bits are reserved in SSFS: 1,5-7. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000142#define SSFS_RESERVED_MASK 0x000000e2
Stefan Reinauera9424d52008-06-27 16:28:34 +0000143
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000144#define ICH9_REG_SSFC 0x91 /* 24 Bits */
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000145/* We combine SSFS and SSFC to one 32-bit word,
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000146 * therefore SSFC bits are off by 8. */
147 /* 0: reserved */
148#define SSFC_SCGO_OFF (1 + 8) /* 1: SPI Cycle Go */
149#define SSFC_SCGO (0x1 << SSFC_SCGO_OFF)
150#define SSFC_ACS_OFF (2 + 8) /* 2: Atomic Cycle Sequence */
151#define SSFC_ACS (0x1 << SSFC_ACS_OFF)
152#define SSFC_SPOP_OFF (3 + 8) /* 3: Sequence Prefix Opcode Pointer */
153#define SSFC_SPOP (0x1 << SSFC_SPOP_OFF)
154#define SSFC_COP_OFF (4 + 8) /* 4-6: Cycle Opcode Pointer */
155#define SSFC_COP (0x7 << SSFC_COP_OFF)
156 /* 7: reserved */
157#define SSFC_DBC_OFF (8 + 8) /* 8-13: Data Byte Count */
158#define SSFC_DBC (0x3f << SSFC_DBC_OFF)
159#define SSFC_DS_OFF (14 + 8) /* 14: Data Cycle */
160#define SSFC_DS (0x1 << SSFC_DS_OFF)
161#define SSFC_SME_OFF (15 + 8) /* 15: SPI SMI# Enable */
162#define SSFC_SME (0x1 << SSFC_SME_OFF)
163#define SSFC_SCF_OFF (16 + 8) /* 16-18: SPI Cycle Frequency */
164#define SSFC_SCF (0x7 << SSFC_SCF_OFF)
165#define SSFC_SCF_20MHZ 0x00000000
166#define SSFC_SCF_33MHZ 0x01000000
167 /* 19-23: reserved */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000168#define SSFC_RESERVED_MASK 0xf8008100
Stefan Reinauera9424d52008-06-27 16:28:34 +0000169
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000170#define ICH9_REG_PREOP 0x94 /* 16 Bits */
171#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */
172#define ICH9_REG_OPMENU 0x98 /* 64 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000173
Stefan Tauner29c80832011-06-12 08:14:10 +0000174#define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */
175#define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */
176
Stefan Tauner1e146392011-09-15 23:52:55 +0000177#define ICH8_REG_VSCC 0xC1 /* 32 Bits Vendor Specific Component Capabilities */
178#define ICH9_REG_LVSCC 0xC4 /* 32 Bits Host Lower Vendor Specific Component Capabilities */
179#define ICH9_REG_UVSCC 0xC8 /* 32 Bits Host Upper Vendor Specific Component Capabilities */
180/* The individual fields of the VSCC registers are defined in the file
181 * ich_descriptors.h. The reason is that the same layout is also used in the
182 * flash descriptor to define the properties of the different flash chips
183 * supported. The BIOS (or the ME?) is responsible to populate the ICH registers
184 * with the information from the descriptor on startup depending on the actual
185 * chip(s) detected. */
186
Stefan Taunerbd649e42011-07-01 00:39:16 +0000187#define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */
188#define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */
189#define FPB_FPBA (0x1FFF << FPB_FPBA_OFF)
190
Dominik Geyerb46acba2008-05-16 12:55:55 +0000191// ICH9R SPI commands
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000192#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
193#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
194#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
195#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
Dominik Geyerb46acba2008-05-16 12:55:55 +0000196
Stefan Reinauera9424d52008-06-27 16:28:34 +0000197// ICH7 registers
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000198#define ICH7_REG_SPIS 0x00 /* 16 Bits */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000199#define SPIS_SCIP 0x0001
200#define SPIS_GRANT 0x0002
201#define SPIS_CDS 0x0004
202#define SPIS_FCERR 0x0008
203#define SPIS_RESERVED_MASK 0x7ff0
Stefan Reinauera9424d52008-06-27 16:28:34 +0000204
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000205/* VIA SPI is compatible with ICH7, but maxdata
206 to transfer is 16 bytes.
207
208 DATA byte count on ICH7 is 8:13, on VIA 8:11
209
210 bit 12 is port select CS0 CS1
211 bit 13 is FAST READ enable
212 bit 7 is used with fast read and one shot controls CS de-assert?
213*/
214
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000215#define ICH7_REG_SPIC 0x02 /* 16 Bits */
216#define SPIC_SCGO 0x0002
217#define SPIC_ACS 0x0004
218#define SPIC_SPOP 0x0008
219#define SPIC_DS 0x4000
Stefan Reinauera9424d52008-06-27 16:28:34 +0000220
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000221#define ICH7_REG_SPIA 0x04 /* 32 Bits */
222#define ICH7_REG_SPID0 0x08 /* 64 Bytes */
223#define ICH7_REG_PREOP 0x54 /* 16 Bits */
224#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */
225#define ICH7_REG_OPMENU 0x58 /* 64 Bits */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000226
Nico Huber7590d1a2016-05-03 13:38:28 +0200227enum ich_access_protection {
228 NO_PROT = 0,
229 READ_PROT = 1,
230 WRITE_PROT = 2,
231 LOCKED = 3,
232};
233
FENG yu ningc05a2952008-12-08 18:16:58 +0000234/* ICH SPI configuration lock-down. May be set during chipset enabling. */
Michael Karchera4448d92010-07-22 18:04:15 +0000235static int ichspi_lock = 0;
FENG yu ningc05a2952008-12-08 18:16:58 +0000236
Stefan Taunera8d838d2011-11-06 23:51:09 +0000237static enum ich_chipset ich_generation = CHIPSET_ICH_UNKNOWN;
Nico Hubered098d62017-04-21 23:47:08 +0200238static uint32_t ichspi_bbar;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000239
Michael Karchera4448d92010-07-22 18:04:15 +0000240static void *ich_spibar = NULL;
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000241
Dominik Geyerb46acba2008-05-16 12:55:55 +0000242typedef struct _OPCODE {
243 uint8_t opcode; //This commands spi opcode
244 uint8_t spi_type; //This commands spi type
245 uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1
246} OPCODE;
247
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000248/* Suggested opcode definition:
Dominik Geyerb46acba2008-05-16 12:55:55 +0000249 * Preop 1: Write Enable
250 * Preop 2: Write Status register enable
251 *
252 * OP 0: Write address
253 * OP 1: Read Address
254 * OP 2: ERASE block
255 * OP 3: Read Status register
256 * OP 4: Read ID
257 * OP 5: Write Status register
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000258 * OP 6: chip private (read JEDEC id)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000259 * OP 7: Chip erase
260 */
261typedef struct _OPCODES {
262 uint8_t preop[2];
263 OPCODE opcode[8];
264} OPCODES;
265
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000266static OPCODES *curopcodes = NULL;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000267
268/* HW access functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000269static uint32_t REGREAD32(int X)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000270{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000271 return mmio_readl(ich_spibar + X);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000272}
273
Uwe Hermann09e04f72009-05-16 22:36:00 +0000274static uint16_t REGREAD16(int X)
Stefan Reinauera9424d52008-06-27 16:28:34 +0000275{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000276 return mmio_readw(ich_spibar + X);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000277}
278
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000279static uint16_t REGREAD8(int X)
280{
281 return mmio_readb(ich_spibar + X);
282}
283
Stefan Taunerccd92a12011-07-01 00:39:01 +0000284#define REGWRITE32(off, val) mmio_writel(val, ich_spibar+(off))
285#define REGWRITE16(off, val) mmio_writew(val, ich_spibar+(off))
286#define REGWRITE8(off, val) mmio_writeb(val, ich_spibar+(off))
Dominik Geyerb46acba2008-05-16 12:55:55 +0000287
Dominik Geyerb46acba2008-05-16 12:55:55 +0000288/* Common SPI functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000289static int find_opcode(OPCODES *op, uint8_t opcode);
290static int find_preop(OPCODES *op, uint8_t preop);
FENG yu ningf041e9b2008-12-15 02:32:11 +0000291static int generate_opcodes(OPCODES * op);
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000292static int program_opcodes(OPCODES *op, int enable_undo);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000293static int run_opcode(const struct flashctx *flash, OPCODE op, uint32_t offset,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000294 uint8_t datalength, uint8_t * data);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000295
FENG yu ningf041e9b2008-12-15 02:32:11 +0000296/* for pairing opcodes with their required preop */
297struct preop_opcode_pair {
298 uint8_t preop;
299 uint8_t opcode;
300};
301
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000302/* List of opcodes which need preopcodes and matching preopcodes. Unused. */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000303const struct preop_opcode_pair pops[] = {
FENG yu ningf041e9b2008-12-15 02:32:11 +0000304 {JEDEC_WREN, JEDEC_BYTE_PROGRAM},
305 {JEDEC_WREN, JEDEC_SE}, /* sector erase */
306 {JEDEC_WREN, JEDEC_BE_52}, /* block erase */
307 {JEDEC_WREN, JEDEC_BE_D8}, /* block erase */
308 {JEDEC_WREN, JEDEC_CE_60}, /* chip erase */
309 {JEDEC_WREN, JEDEC_CE_C7}, /* chip erase */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000310 /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */
311 {JEDEC_WREN, JEDEC_WRSR},
FENG yu ningf041e9b2008-12-15 02:32:11 +0000312 {JEDEC_EWSR, JEDEC_WRSR},
313 {0,}
314};
315
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000316/* Reasonable default configuration. Needs ad-hoc modifications if we
317 * encounter unlisted opcodes. Fun.
318 */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000319static OPCODES O_ST_M25P = {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000320 {
321 JEDEC_WREN,
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000322 JEDEC_EWSR,
323 },
Dominik Geyerb46acba2008-05-16 12:55:55 +0000324 {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000325 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000326 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000327 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000328 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
Carl-Daniel Hailfinger15aa7c62009-05-26 21:25:08 +0000329 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000330 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000331 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000332 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
333 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000334};
335
Helge Wagner738e2522010-10-05 22:06:05 +0000336/* List of opcodes with their corresponding spi_type
337 * It is used to reprogram the chipset OPCODE table on-the-fly if an opcode
338 * is needed which is currently not in the chipset OPCODE table
339 */
340static OPCODE POSSIBLE_OPCODES[] = {
341 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
342 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
343 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
344 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
345 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
346 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
347 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
348 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
349 {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Sector erase
350 {JEDEC_BE_52, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Block erase
351 {JEDEC_AAI_WORD_PROGRAM, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Auto Address Increment
352};
353
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000354static OPCODES O_EXISTING = {};
FENG yu ningc05a2952008-12-08 18:16:58 +0000355
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000356/* pretty printing functions */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000357static void prettyprint_opcodes(OPCODES *ops)
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000358{
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000359 OPCODE oc;
360 const char *t;
361 const char *a;
362 uint8_t i;
363 static const char *const spi_type[4] = {
364 "read w/o addr",
365 "write w/o addr",
366 "read w/ addr",
367 "write w/ addr"
368 };
369 static const char *const atomic_type[3] = {
370 "none",
371 " 0 ",
372 " 1 "
373 };
374
375 if (ops == NULL)
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000376 return;
377
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000378 msg_pdbg2(" OP Type Pre-OP\n");
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000379 for (i = 0; i < 8; i++) {
380 oc = ops->opcode[i];
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000381 t = (oc.spi_type > 3) ? "invalid" : spi_type[oc.spi_type];
382 a = (oc.atomic > 2) ? "invalid" : atomic_type[oc.atomic];
383 msg_pdbg2("op[%d]: 0x%02x, %s, %s\n", i, oc.opcode, t, a);
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000384 }
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000385 msg_pdbg2("Pre-OP 0: 0x%02x, Pre-OP 1: 0x%02x\n", ops->preop[0],
386 ops->preop[1]);
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000387}
388
Nico Huberd54e4f42017-03-23 23:45:47 +0100389#define _pprint_reg(bit, mask, off, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & mask) >> off)
390#define pprint_reg(reg, bit, val, sep) _pprint_reg(bit, reg##_##bit, reg##_##bit##_OFF, val, sep)
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000391
Stefan Tauner55206942011-06-11 09:53:22 +0000392static void prettyprint_ich9_reg_hsfs(uint16_t reg_val)
393{
394 msg_pdbg("HSFS: ");
395 pprint_reg(HSFS, FDONE, reg_val, ", ");
396 pprint_reg(HSFS, FCERR, reg_val, ", ");
397 pprint_reg(HSFS, AEL, reg_val, ", ");
David Hendricksa5216362017-08-08 20:02:22 -0700398 if (ich_generation != CHIPSET_100_SERIES_SUNRISE_POINT &&
399 ich_generation != CHIPSET_C620_SERIES_LEWISBURG) {
Nico Huberd54e4f42017-03-23 23:45:47 +0100400 pprint_reg(HSFS, BERASE, reg_val, ", ");
401 }
Stefan Tauner55206942011-06-11 09:53:22 +0000402 pprint_reg(HSFS, SCIP, reg_val, ", ");
David Hendricksa5216362017-08-08 20:02:22 -0700403 if (ich_generation == CHIPSET_100_SERIES_SUNRISE_POINT ||
404 ich_generation == CHIPSET_C620_SERIES_LEWISBURG) {
Nico Huberd54e4f42017-03-23 23:45:47 +0100405 pprint_reg(HSFS, PRR34_LOCKDN, reg_val, ", ");
406 pprint_reg(HSFS, WRSDIS, reg_val, ", ");
407 }
Stefan Tauner55206942011-06-11 09:53:22 +0000408 pprint_reg(HSFS, FDOPSS, reg_val, ", ");
409 pprint_reg(HSFS, FDV, reg_val, ", ");
410 pprint_reg(HSFS, FLOCKDN, reg_val, "\n");
411}
412
413static void prettyprint_ich9_reg_hsfc(uint16_t reg_val)
414{
415 msg_pdbg("HSFC: ");
416 pprint_reg(HSFC, FGO, reg_val, ", ");
David Hendricksa5216362017-08-08 20:02:22 -0700417 if (ich_generation != CHIPSET_100_SERIES_SUNRISE_POINT &&
418 ich_generation != CHIPSET_C620_SERIES_LEWISBURG) {
Nico Huberd54e4f42017-03-23 23:45:47 +0100419 pprint_reg(HSFC, FCYCLE, reg_val, ", ");
420 } else {
421 _pprint_reg(HSFC, PCH100_HSFC_FCYCLE, PCH100_HSFC_FCYCLE_OFF, reg_val, ", ");
422 pprint_reg(HSFC, WET, reg_val, ", ");
423 }
Stefan Tauner55206942011-06-11 09:53:22 +0000424 pprint_reg(HSFC, FDBC, reg_val, ", ");
425 pprint_reg(HSFC, SME, reg_val, "\n");
426}
427
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000428static void prettyprint_ich9_reg_ssfs(uint32_t reg_val)
429{
430 msg_pdbg("SSFS: ");
431 pprint_reg(SSFS, SCIP, reg_val, ", ");
432 pprint_reg(SSFS, FDONE, reg_val, ", ");
433 pprint_reg(SSFS, FCERR, reg_val, ", ");
434 pprint_reg(SSFS, AEL, reg_val, "\n");
435}
436
437static void prettyprint_ich9_reg_ssfc(uint32_t reg_val)
438{
439 msg_pdbg("SSFC: ");
440 pprint_reg(SSFC, SCGO, reg_val, ", ");
441 pprint_reg(SSFC, ACS, reg_val, ", ");
442 pprint_reg(SSFC, SPOP, reg_val, ", ");
443 pprint_reg(SSFC, COP, reg_val, ", ");
444 pprint_reg(SSFC, DBC, reg_val, ", ");
445 pprint_reg(SSFC, SME, reg_val, ", ");
446 pprint_reg(SSFC, SCF, reg_val, "\n");
447}
448
Nico Huberd54e4f42017-03-23 23:45:47 +0100449static void prettyprint_pch100_reg_dlock(const uint32_t reg_val)
450{
451 msg_pdbg("DLOCK: ");
452 pprint_reg(DLOCK, BMWAG_LOCKDN, reg_val, ", ");
453 pprint_reg(DLOCK, BMRAG_LOCKDN, reg_val, ", ");
454 pprint_reg(DLOCK, SBMWAG_LOCKDN, reg_val, ", ");
455 pprint_reg(DLOCK, SBMRAG_LOCKDN, reg_val, ",\n ");
456 pprint_reg(DLOCK, PR0_LOCKDN, reg_val, ", ");
457 pprint_reg(DLOCK, PR1_LOCKDN, reg_val, ", ");
458 pprint_reg(DLOCK, PR2_LOCKDN, reg_val, ", ");
459 pprint_reg(DLOCK, PR3_LOCKDN, reg_val, ", ");
460 pprint_reg(DLOCK, PR4_LOCKDN, reg_val, ",\n ");
461 pprint_reg(DLOCK, SSEQ_LOCKDN, reg_val, "\n");
462}
463
464static struct {
465 size_t reg_ssfsc;
466 size_t reg_preop;
467 size_t reg_optype;
468 size_t reg_opmenu;
469} swseq_data;
470
Helge Wagner738e2522010-10-05 22:06:05 +0000471static uint8_t lookup_spi_type(uint8_t opcode)
472{
473 int a;
474
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000475 for (a = 0; a < ARRAY_SIZE(POSSIBLE_OPCODES); a++) {
Helge Wagner738e2522010-10-05 22:06:05 +0000476 if (POSSIBLE_OPCODES[a].opcode == opcode)
477 return POSSIBLE_OPCODES[a].spi_type;
478 }
479
480 return 0xFF;
481}
482
483static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt)
484{
485 uint8_t spi_type;
486
487 spi_type = lookup_spi_type(opcode);
488 if (spi_type > 3) {
489 /* Try to guess spi type from read/write sizes.
490 * The following valid writecnt/readcnt combinations exist:
491 * writecnt = 4, readcnt >= 0
492 * writecnt = 1, readcnt >= 0
493 * writecnt >= 4, readcnt = 0
494 * writecnt >= 1, readcnt = 0
495 * writecnt >= 1 is guaranteed for all commands.
496 */
497 if (readcnt == 0)
498 /* if readcnt=0 and writecount >= 4, we don't know if it is WRITE_NO_ADDRESS
499 * or WRITE_WITH_ADDRESS. But if we use WRITE_NO_ADDRESS and the first 3 data
500 * bytes are actual the address, they go to the bus anyhow
501 */
502 spi_type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
503 else if (writecnt == 1) // and readcnt is > 0
504 spi_type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
505 else if (writecnt == 4) // and readcnt is > 0
506 spi_type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
Stefan Taunerdc704ed2012-05-06 15:11:26 +0000507 else // we have an invalid case
508 return SPI_INVALID_LENGTH;
Helge Wagner738e2522010-10-05 22:06:05 +0000509 }
Stefan Taunerdc704ed2012-05-06 15:11:26 +0000510 int oppos = 2; // use original JEDEC_BE_D8 offset
511 curopcodes->opcode[oppos].opcode = opcode;
512 curopcodes->opcode[oppos].spi_type = spi_type;
513 program_opcodes(curopcodes, 0);
514 oppos = find_opcode(curopcodes, opcode);
Stefan Taunerd94d25d2012-07-28 03:17:15 +0000515 msg_pdbg2("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos);
Stefan Taunerdc704ed2012-05-06 15:11:26 +0000516 return oppos;
Helge Wagner738e2522010-10-05 22:06:05 +0000517}
518
Uwe Hermann09e04f72009-05-16 22:36:00 +0000519static int find_opcode(OPCODES *op, uint8_t opcode)
FENG yu ningc05a2952008-12-08 18:16:58 +0000520{
521 int a;
522
Stefan Tauner50e7c602011-11-08 10:55:54 +0000523 if (op == NULL) {
524 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
525 return -1;
526 }
527
FENG yu ningc05a2952008-12-08 18:16:58 +0000528 for (a = 0; a < 8; a++) {
529 if (op->opcode[a].opcode == opcode)
530 return a;
531 }
532
533 return -1;
534}
535
Uwe Hermann09e04f72009-05-16 22:36:00 +0000536static int find_preop(OPCODES *op, uint8_t preop)
FENG yu ningc05a2952008-12-08 18:16:58 +0000537{
538 int a;
539
Stefan Tauner50e7c602011-11-08 10:55:54 +0000540 if (op == NULL) {
541 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
542 return -1;
543 }
544
FENG yu ningc05a2952008-12-08 18:16:58 +0000545 for (a = 0; a < 2; a++) {
546 if (op->preop[a] == preop)
547 return a;
548 }
549
550 return -1;
551}
552
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000553/* Create a struct OPCODES based on what we find in the locked down chipset. */
FENG yu ningf041e9b2008-12-15 02:32:11 +0000554static int generate_opcodes(OPCODES * op)
FENG yu ningc05a2952008-12-08 18:16:58 +0000555{
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000556 int a;
FENG yu ningc05a2952008-12-08 18:16:58 +0000557 uint16_t preop, optype;
558 uint32_t opmenu[2];
FENG yu ningc05a2952008-12-08 18:16:58 +0000559
560 if (op == NULL) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000561 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
FENG yu ningc05a2952008-12-08 18:16:58 +0000562 return -1;
563 }
564
Stefan Taunera8d838d2011-11-06 23:51:09 +0000565 switch (ich_generation) {
566 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000567 case CHIPSET_TUNNEL_CREEK:
568 case CHIPSET_CENTERTON:
FENG yu ningc05a2952008-12-08 18:16:58 +0000569 preop = REGREAD16(ICH7_REG_PREOP);
570 optype = REGREAD16(ICH7_REG_OPTYPE);
571 opmenu[0] = REGREAD32(ICH7_REG_OPMENU);
572 opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4);
573 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000574 case CHIPSET_ICH8:
575 default: /* Future version might behave the same */
Nico Huberd54e4f42017-03-23 23:45:47 +0100576 preop = REGREAD16(swseq_data.reg_preop);
577 optype = REGREAD16(swseq_data.reg_optype);
578 opmenu[0] = REGREAD32(swseq_data.reg_opmenu);
579 opmenu[1] = REGREAD32(swseq_data.reg_opmenu + 4);
FENG yu ningc05a2952008-12-08 18:16:58 +0000580 break;
FENG yu ningc05a2952008-12-08 18:16:58 +0000581 }
582
583 op->preop[0] = (uint8_t) preop;
584 op->preop[1] = (uint8_t) (preop >> 8);
585
586 for (a = 0; a < 8; a++) {
587 op->opcode[a].spi_type = (uint8_t) (optype & 0x3);
588 optype >>= 2;
589 }
590
591 for (a = 0; a < 4; a++) {
592 op->opcode[a].opcode = (uint8_t) (opmenu[0] & 0xff);
593 opmenu[0] >>= 8;
594 }
595
596 for (a = 4; a < 8; a++) {
597 op->opcode[a].opcode = (uint8_t) (opmenu[1] & 0xff);
598 opmenu[1] >>= 8;
599 }
600
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000601 /* No preopcodes used by default. */
602 for (a = 0; a < 8; a++)
FENG yu ningc05a2952008-12-08 18:16:58 +0000603 op->opcode[a].atomic = 0;
604
FENG yu ningc05a2952008-12-08 18:16:58 +0000605 return 0;
606}
607
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000608static int program_opcodes(OPCODES *op, int enable_undo)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000609{
610 uint8_t a;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000611 uint16_t preop, optype;
612 uint32_t opmenu[2];
Dominik Geyerb46acba2008-05-16 12:55:55 +0000613
614 /* Program Prefix Opcodes */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000615 /* 0:7 Prefix Opcode 1 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000616 preop = (op->preop[0]);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000617 /* 8:16 Prefix Opcode 2 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000618 preop |= ((uint16_t) op->preop[1]) << 8;
Uwe Hermann394131e2008-10-18 21:14:13 +0000619
Stefan Reinauera9424d52008-06-27 16:28:34 +0000620 /* Program Opcode Types 0 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000621 optype = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000622 for (a = 0; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000623 optype |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000624 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000625
Stefan Reinauera9424d52008-06-27 16:28:34 +0000626 /* Program Allowable Opcodes 0 - 3 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000627 opmenu[0] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000628 for (a = 0; a < 4; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000629 opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000630 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000631
Stefan Tauner92d6a862013-10-25 00:33:37 +0000632 /* Program Allowable Opcodes 4 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000633 opmenu[1] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000634 for (a = 4; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000635 opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000636 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000637
Stefan Taunerd94d25d2012-07-28 03:17:15 +0000638 msg_pdbg2("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]);
Stefan Taunera8d838d2011-11-06 23:51:09 +0000639 switch (ich_generation) {
640 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000641 case CHIPSET_TUNNEL_CREEK:
642 case CHIPSET_CENTERTON:
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000643 /* Register undo only for enable_undo=1, i.e. first call. */
644 if (enable_undo) {
645 rmmio_valw(ich_spibar + ICH7_REG_PREOP);
646 rmmio_valw(ich_spibar + ICH7_REG_OPTYPE);
647 rmmio_vall(ich_spibar + ICH7_REG_OPMENU);
648 rmmio_vall(ich_spibar + ICH7_REG_OPMENU + 4);
649 }
650 mmio_writew(preop, ich_spibar + ICH7_REG_PREOP);
651 mmio_writew(optype, ich_spibar + ICH7_REG_OPTYPE);
652 mmio_writel(opmenu[0], ich_spibar + ICH7_REG_OPMENU);
653 mmio_writel(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000654 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000655 case CHIPSET_ICH8:
656 default: /* Future version might behave the same */
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000657 /* Register undo only for enable_undo=1, i.e. first call. */
658 if (enable_undo) {
Nico Huberd54e4f42017-03-23 23:45:47 +0100659 rmmio_valw(ich_spibar + swseq_data.reg_preop);
660 rmmio_valw(ich_spibar + swseq_data.reg_optype);
661 rmmio_vall(ich_spibar + swseq_data.reg_opmenu);
662 rmmio_vall(ich_spibar + swseq_data.reg_opmenu + 4);
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000663 }
Nico Huberd54e4f42017-03-23 23:45:47 +0100664 mmio_writew(preop, ich_spibar + swseq_data.reg_preop);
665 mmio_writew(optype, ich_spibar + swseq_data.reg_optype);
666 mmio_writel(opmenu[0], ich_spibar + swseq_data.reg_opmenu);
667 mmio_writel(opmenu[1], ich_spibar + swseq_data.reg_opmenu + 4);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000668 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000669 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000670
671 return 0;
672}
673
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000674/*
Stefan Tauner50e7c602011-11-08 10:55:54 +0000675 * Returns -1 if at least one mandatory opcode is inaccessible, 0 otherwise.
676 * FIXME: this should also check for
677 * - at least one probing opcode (RDID (incl. AT25F variants?), REMS, RES?)
678 * - at least one erasing opcode (lots.)
679 * - at least one program opcode (BYTE_PROGRAM, AAI_WORD_PROGRAM, ...?)
680 * - necessary preops? (EWSR, WREN, ...?)
681 */
Richard Hughes93e16252018-12-19 11:54:47 +0000682static int ich_missing_opcodes(void)
Stefan Tauner50e7c602011-11-08 10:55:54 +0000683{
684 uint8_t ops[] = {
685 JEDEC_READ,
686 JEDEC_RDSR,
687 0
688 };
689 int i = 0;
690 while (ops[i] != 0) {
691 msg_pspew("checking for opcode 0x%02x\n", ops[i]);
692 if (find_opcode(curopcodes, ops[i]) == -1)
693 return -1;
694 i++;
695 }
696 return 0;
697}
698
699/*
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000700 * Try to set BBAR (BIOS Base Address Register), but read back the value in case
701 * it didn't stick.
702 */
Stefan Taunera8d838d2011-11-06 23:51:09 +0000703static void ich_set_bbar(uint32_t min_addr)
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000704{
Stefan Taunere27b2d42011-07-01 00:39:09 +0000705 int bbar_off;
Stefan Tauner7783f312011-09-17 21:21:42 +0000706 switch (ich_generation) {
Stefan Taunera8d838d2011-11-06 23:51:09 +0000707 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000708 case CHIPSET_TUNNEL_CREEK:
709 case CHIPSET_CENTERTON:
Stefan Taunere27b2d42011-07-01 00:39:09 +0000710 bbar_off = 0x50;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000711 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000712 case CHIPSET_ICH8:
Duncan Laurie4095ed72014-08-20 15:39:32 +0000713 case CHIPSET_BAYTRAIL:
714 msg_pdbg("BBAR offset is unknown!\n");
Stefan Tauner7783f312011-09-17 21:21:42 +0000715 return;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000716 case CHIPSET_ICH9:
Stefan Tauner7783f312011-09-17 21:21:42 +0000717 default: /* Future version might behave the same */
Stefan Taunere27b2d42011-07-01 00:39:09 +0000718 bbar_off = ICH9_REG_BBAR;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000719 break;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000720 }
Elyes HAOUAS124ef382018-03-27 12:15:09 +0200721
Stefan Taunere27b2d42011-07-01 00:39:09 +0000722 ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & ~BBAR_MASK;
723 if (ichspi_bbar) {
724 msg_pdbg("Reserved bits in BBAR not zero: 0x%08x\n",
725 ichspi_bbar);
726 }
727 min_addr &= BBAR_MASK;
728 ichspi_bbar |= min_addr;
729 rmmio_writel(ichspi_bbar, ich_spibar + bbar_off);
730 ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & BBAR_MASK;
731
732 /* We don't have any option except complaining. And if the write
733 * failed, the restore will fail as well, so no problem there.
734 */
735 if (ichspi_bbar != min_addr)
Stefan Tauner7783f312011-09-17 21:21:42 +0000736 msg_perr("Setting BBAR to 0x%08x failed! New value: 0x%08x.\n",
737 min_addr, ichspi_bbar);
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000738}
739
Stefan Tauner8b391b82011-08-09 01:49:34 +0000740/* Read len bytes from the fdata/spid register into the data array.
741 *
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000742 * Note that using len > flash->mst->spi.max_data_read will return garbage or
Stefan Tauner8b391b82011-08-09 01:49:34 +0000743 * may even crash.
744 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000745static void ich_read_data(uint8_t *data, int len, int reg0_off)
Elyes HAOUAS124ef382018-03-27 12:15:09 +0200746{
Stefan Tauner8b391b82011-08-09 01:49:34 +0000747 int i;
748 uint32_t temp32 = 0;
749
750 for (i = 0; i < len; i++) {
751 if ((i % 4) == 0)
752 temp32 = REGREAD32(reg0_off + i);
753
754 data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
755 }
756}
757
758/* Fill len bytes from the data array into the fdata/spid registers.
759 *
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000760 * Note that using len > flash->mst->spi.max_data_write will trash the registers
Stefan Tauner8b391b82011-08-09 01:49:34 +0000761 * following the data registers.
762 */
763static void ich_fill_data(const uint8_t *data, int len, int reg0_off)
764{
765 uint32_t temp32 = 0;
766 int i;
767
768 if (len <= 0)
769 return;
770
771 for (i = 0; i < len; i++) {
772 if ((i % 4) == 0)
773 temp32 = 0;
774
775 temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
776
777 if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
778 REGWRITE32(reg0_off + (i - (i % 4)), temp32);
779 }
780 i--;
781 if ((i % 4) != 3) /* Write remaining data to regs. */
782 REGWRITE32(reg0_off + (i - (i % 4)), temp32);
783}
784
FENG yu ningf041e9b2008-12-15 02:32:11 +0000785/* This function generates OPCODES from or programs OPCODES to ICH according to
786 * the chipset's SPI configuration lock.
FENG yu ningc05a2952008-12-08 18:16:58 +0000787 *
FENG yu ningf041e9b2008-12-15 02:32:11 +0000788 * It should be called before ICH sends any spi command.
FENG yu ningc05a2952008-12-08 18:16:58 +0000789 */
Michael Karchera4448d92010-07-22 18:04:15 +0000790static int ich_init_opcodes(void)
FENG yu ningc05a2952008-12-08 18:16:58 +0000791{
792 int rc = 0;
793 OPCODES *curopcodes_done;
794
795 if (curopcodes)
796 return 0;
797
798 if (ichspi_lock) {
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000799 msg_pdbg("Reading OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000800 curopcodes_done = &O_EXISTING;
FENG yu ningf041e9b2008-12-15 02:32:11 +0000801 rc = generate_opcodes(curopcodes_done);
FENG yu ningc05a2952008-12-08 18:16:58 +0000802 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000803 msg_pdbg("Programming OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000804 curopcodes_done = &O_ST_M25P;
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000805 rc = program_opcodes(curopcodes_done, 1);
FENG yu ningc05a2952008-12-08 18:16:58 +0000806 }
807
808 if (rc) {
809 curopcodes = NULL;
Sean Nelson316a29f2010-05-07 20:09:04 +0000810 msg_perr("failed\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000811 return 1;
812 } else {
813 curopcodes = curopcodes_done;
Sean Nelson316a29f2010-05-07 20:09:04 +0000814 msg_pdbg("done\n");
Stefan Tauner8b391b82011-08-09 01:49:34 +0000815 prettyprint_opcodes(curopcodes);
FENG yu ningc05a2952008-12-08 18:16:58 +0000816 return 0;
817 }
818}
819
Stefan Reinauer43119562008-11-02 19:51:50 +0000820static int ich7_run_opcode(OPCODE op, uint32_t offset,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000821 uint8_t datalength, uint8_t * data, int maxdata)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000822{
823 int write_cmd = 0;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000824 int timeout;
Stefan Tauner8b391b82011-08-09 01:49:34 +0000825 uint32_t temp32;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000826 uint16_t temp16;
Stefan Reinauer43119562008-11-02 19:51:50 +0000827 uint64_t opmenu;
828 int opcode_index;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000829
830 /* Is it a write command? */
831 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
832 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
833 write_cmd = 1;
834 }
835
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000836 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
837 while ((REGREAD16(ICH7_REG_SPIS) & SPIS_SCIP) && --timeout) {
838 programmer_delay(10);
839 }
840 if (!timeout) {
841 msg_perr("Error: SCIP never cleared!\n");
842 return 1;
843 }
844
Stefan Tauner10b3e222011-07-01 00:39:23 +0000845 /* Program offset in flash into SPIA while preserving reserved bits. */
846 temp32 = REGREAD32(ICH7_REG_SPIA) & ~0x00FFFFFF;
847 REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF) | temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000848
Stefan Tauner10b3e222011-07-01 00:39:23 +0000849 /* Program data into SPID0 to N */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000850 if (write_cmd && (datalength != 0))
851 ich_fill_data(data, datalength, ICH7_REG_SPID0);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000852
853 /* Assemble SPIS */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000854 temp16 = REGREAD16(ICH7_REG_SPIS);
855 /* keep reserved bits */
856 temp16 &= SPIS_RESERVED_MASK;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000857 /* clear error status registers */
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000858 temp16 |= (SPIS_CDS | SPIS_FCERR);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000859 REGWRITE16(ICH7_REG_SPIS, temp16);
860
861 /* Assemble SPIC */
862 temp16 = 0;
863
864 if (datalength != 0) {
865 temp16 |= SPIC_DS;
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000866 temp16 |= ((uint32_t) ((datalength - 1) & (maxdata - 1))) << 8;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000867 }
868
869 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000870 opmenu = REGREAD32(ICH7_REG_OPMENU);
871 opmenu |= ((uint64_t)REGREAD32(ICH7_REG_OPMENU + 4)) << 32;
872
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000873 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
874 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000875 break;
876 }
877 opmenu >>= 8;
878 }
879 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000880 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +0000881 return 1;
882 }
883 temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000884
Michael Karcher136125a2011-04-29 22:11:36 +0000885 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
886 /* Handle Atomic. Atomic commands include three steps:
887 - sending the preop (mainly EWSR or WREN)
888 - sending the main command
889 - waiting for the busy bit (WIP) to be cleared
890 This means the timeout must be sufficient for chip erase
891 of slow high-capacity chips.
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000892 */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000893 switch (op.atomic) {
894 case 2:
895 /* Select second preop. */
896 temp16 |= SPIC_SPOP;
Richard Hughesdb7482b2018-12-19 12:04:30 +0000897 /* Fall through. */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000898 case 1:
899 /* Atomic command (preop+op) */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000900 temp16 |= SPIC_ACS;
Michael Karcher136125a2011-04-29 22:11:36 +0000901 timeout = 100 * 1000 * 60; /* 60 seconds */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000902 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000903 }
904
905 /* Start */
906 temp16 |= SPIC_SCGO;
907
908 /* write it */
909 REGWRITE16(ICH7_REG_SPIC, temp16);
910
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000911 /* Wait for Cycle Done Status or Flash Cycle Error. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000912 while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) &&
913 --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000914 programmer_delay(10);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000915 }
916 if (!timeout) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000917 msg_perr("timeout, ICH7_REG_SPIS=0x%04x\n",
918 REGREAD16(ICH7_REG_SPIS));
919 return 1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000920 }
921
Sean Nelson316a29f2010-05-07 20:09:04 +0000922 /* FIXME: make sure we do not needlessly cause transaction errors. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000923 temp16 = REGREAD16(ICH7_REG_SPIS);
924 if (temp16 & SPIS_FCERR) {
Stefan Tauner8ed29342011-04-29 23:53:09 +0000925 msg_perr("Transaction error!\n");
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000926 /* keep reserved bits */
927 temp16 &= SPIS_RESERVED_MASK;
928 REGWRITE16(ICH7_REG_SPIS, temp16 | SPIS_FCERR);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000929 return 1;
930 }
931
Stefan Tauner8b391b82011-08-09 01:49:34 +0000932 if ((!write_cmd) && (datalength != 0))
933 ich_read_data(data, datalength, ICH7_REG_SPID0);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000934
935 return 0;
936}
937
Stefan Reinauer43119562008-11-02 19:51:50 +0000938static int ich9_run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000939 uint8_t datalength, uint8_t * data)
940{
941 int write_cmd = 0;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000942 int timeout;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000943 uint32_t temp32;
Stefan Reinauer43119562008-11-02 19:51:50 +0000944 uint64_t opmenu;
945 int opcode_index;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000946
947 /* Is it a write command? */
948 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
949 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
950 write_cmd = 1;
951 }
952
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000953 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
Nico Huberd54e4f42017-03-23 23:45:47 +0100954 while ((REGREAD8(swseq_data.reg_ssfsc) & SSFS_SCIP) && --timeout) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000955 programmer_delay(10);
956 }
957 if (!timeout) {
958 msg_perr("Error: SCIP never cleared!\n");
959 return 1;
960 }
961
Stefan Tauner10b3e222011-07-01 00:39:23 +0000962 /* Program offset in flash into FADDR while preserve the reserved bits
963 * and clearing the 25. address bit which is only useable in hwseq. */
964 temp32 = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF;
965 REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF) | temp32);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000966
967 /* Program data into FDATA0 to N */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000968 if (write_cmd && (datalength != 0))
969 ich_fill_data(data, datalength, ICH9_REG_FDATA0);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000970
971 /* Assemble SSFS + SSFC */
Nico Huberd54e4f42017-03-23 23:45:47 +0100972 temp32 = REGREAD32(swseq_data.reg_ssfsc);
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000973 /* Keep reserved bits only */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000974 temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000975 /* Clear cycle done and cycle error status registers */
976 temp32 |= (SSFS_FDONE | SSFS_FCERR);
Nico Huberd54e4f42017-03-23 23:45:47 +0100977 REGWRITE32(swseq_data.reg_ssfsc, temp32);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000978
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000979 /* Use 20 MHz */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000980 temp32 |= SSFC_SCF_20MHZ;
981
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000982 /* Set data byte count (DBC) and data cycle bit (DS) */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000983 if (datalength != 0) {
984 uint32_t datatemp;
985 temp32 |= SSFC_DS;
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000986 datatemp = ((((uint32_t)datalength - 1) << SSFC_DBC_OFF) &
987 SSFC_DBC);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000988 temp32 |= datatemp;
989 }
990
991 /* Select opcode */
Nico Huber8b2152d2017-08-31 13:18:49 +0200992 opmenu = REGREAD32(swseq_data.reg_opmenu);
993 opmenu |= ((uint64_t)REGREAD32(swseq_data.reg_opmenu + 4)) << 32;
Stefan Reinauer43119562008-11-02 19:51:50 +0000994
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000995 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
996 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000997 break;
998 }
999 opmenu >>= 8;
1000 }
1001 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001002 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +00001003 return 1;
1004 }
1005 temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001006
Michael Karcher136125a2011-04-29 22:11:36 +00001007 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
1008 /* Handle Atomic. Atomic commands include three steps:
1009 - sending the preop (mainly EWSR or WREN)
1010 - sending the main command
1011 - waiting for the busy bit (WIP) to be cleared
1012 This means the timeout must be sufficient for chip erase
1013 of slow high-capacity chips.
Stefan Taunerc0aaf952011-05-19 02:58:17 +00001014 */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001015 switch (op.atomic) {
1016 case 2:
1017 /* Select second preop. */
1018 temp32 |= SSFC_SPOP;
Richard Hughesdb7482b2018-12-19 12:04:30 +00001019 /* Fall through. */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001020 case 1:
1021 /* Atomic command (preop+op) */
Dominik Geyerb46acba2008-05-16 12:55:55 +00001022 temp32 |= SSFC_ACS;
Michael Karcher136125a2011-04-29 22:11:36 +00001023 timeout = 100 * 1000 * 60; /* 60 seconds */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001024 break;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001025 }
1026
1027 /* Start */
1028 temp32 |= SSFC_SCGO;
1029
1030 /* write it */
Nico Huberd54e4f42017-03-23 23:45:47 +01001031 REGWRITE32(swseq_data.reg_ssfsc, temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001032
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001033 /* Wait for Cycle Done Status or Flash Cycle Error. */
Nico Huberd54e4f42017-03-23 23:45:47 +01001034 while (((REGREAD32(swseq_data.reg_ssfsc) & (SSFS_FDONE | SSFS_FCERR)) == 0) &&
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001035 --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +00001036 programmer_delay(10);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +00001037 }
1038 if (!timeout) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001039 msg_perr("timeout, REG_SSFS=0x%08x\n",
1040 REGREAD32(swseq_data.reg_ssfsc));
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001041 return 1;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001042 }
1043
Sean Nelson316a29f2010-05-07 20:09:04 +00001044 /* FIXME make sure we do not needlessly cause transaction errors. */
Nico Huberd54e4f42017-03-23 23:45:47 +01001045 temp32 = REGREAD32(swseq_data.reg_ssfsc);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001046 if (temp32 & SSFS_FCERR) {
Stefan Tauner8ed29342011-04-29 23:53:09 +00001047 msg_perr("Transaction error!\n");
Stefan Tauner2a8b2622011-06-11 09:53:16 +00001048 prettyprint_ich9_reg_ssfs(temp32);
1049 prettyprint_ich9_reg_ssfc(temp32);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001050 /* keep reserved bits */
1051 temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
1052 /* Clear the transaction error. */
Nico Huberd54e4f42017-03-23 23:45:47 +01001053 REGWRITE32(swseq_data.reg_ssfsc, temp32 | SSFS_FCERR);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001054 return 1;
1055 }
1056
Stefan Tauner8b391b82011-08-09 01:49:34 +00001057 if ((!write_cmd) && (datalength != 0))
1058 ich_read_data(data, datalength, ICH9_REG_FDATA0);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001059
1060 return 0;
1061}
1062
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001063static int run_opcode(const struct flashctx *flash, OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +00001064 uint8_t datalength, uint8_t * data)
1065{
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001066 /* max_data_read == max_data_write for all Intel/VIA SPI masters */
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001067 uint8_t maxlength = flash->mst->spi.max_data_read;
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001068
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +00001069 if (ich_generation == CHIPSET_ICH_UNKNOWN) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001070 msg_perr("%s: unsupported chipset\n", __func__);
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001071 return -1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +00001072 }
Stefan Reinauera9424d52008-06-27 16:28:34 +00001073
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001074 if (datalength > maxlength) {
1075 msg_perr("%s: Internal command size error for "
1076 "opcode 0x%02x, got datalength=%i, want <=%i\n",
1077 __func__, op.opcode, datalength, maxlength);
1078 return SPI_INVALID_LENGTH;
1079 }
1080
Stefan Taunera8d838d2011-11-06 23:51:09 +00001081 switch (ich_generation) {
1082 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +00001083 case CHIPSET_TUNNEL_CREEK:
1084 case CHIPSET_CENTERTON:
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001085 return ich7_run_opcode(op, offset, datalength, data, maxlength);
Stefan Taunera8d838d2011-11-06 23:51:09 +00001086 case CHIPSET_ICH8:
1087 default: /* Future version might behave the same */
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001088 return ich9_run_opcode(op, offset, datalength, data);
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001089 }
Stefan Reinauera9424d52008-06-27 16:28:34 +00001090}
1091
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001092static int ich_spi_send_command(struct flashctx *flash, unsigned int writecnt,
1093 unsigned int readcnt,
1094 const unsigned char *writearr,
1095 unsigned char *readarr)
Dominik Geyerb46acba2008-05-16 12:55:55 +00001096{
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001097 int result;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001098 int opcode_index = -1;
1099 const unsigned char cmd = *writearr;
1100 OPCODE *opcode;
1101 uint32_t addr = 0;
1102 uint8_t *data;
1103 int count;
1104
Dominik Geyerb46acba2008-05-16 12:55:55 +00001105 /* find cmd in opcodes-table */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001106 opcode_index = find_opcode(curopcodes, cmd);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001107 if (opcode_index == -1) {
Helge Wagner738e2522010-10-05 22:06:05 +00001108 if (!ichspi_lock)
1109 opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt);
Stefan Taunerdc704ed2012-05-06 15:11:26 +00001110 if (opcode_index == SPI_INVALID_LENGTH) {
1111 msg_pdbg("OPCODE 0x%02x has unsupported length, will not execute.\n", cmd);
1112 return SPI_INVALID_LENGTH;
1113 } else if (opcode_index == -1) {
Stefan Tauner355cbfd2011-05-28 02:37:14 +00001114 msg_pdbg("Invalid OPCODE 0x%02x, will not execute.\n",
1115 cmd);
Helge Wagner738e2522010-10-05 22:06:05 +00001116 return SPI_INVALID_OPCODE;
1117 }
Dominik Geyerb46acba2008-05-16 12:55:55 +00001118 }
1119
1120 opcode = &(curopcodes->opcode[opcode_index]);
1121
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001122 /* The following valid writecnt/readcnt combinations exist:
1123 * writecnt = 4, readcnt >= 0
1124 * writecnt = 1, readcnt >= 0
1125 * writecnt >= 4, readcnt = 0
1126 * writecnt >= 1, readcnt = 0
1127 * writecnt >= 1 is guaranteed for all commands.
1128 */
1129 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) &&
1130 (writecnt != 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001131 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001132 "0x%02x, got writecnt=%i, want =4\n", __func__, cmd,
1133 writecnt);
1134 return SPI_INVALID_LENGTH;
1135 }
1136 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_NO_ADDRESS) &&
1137 (writecnt != 1)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001138 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001139 "0x%02x, got writecnt=%i, want =1\n", __func__, cmd,
1140 writecnt);
1141 return SPI_INVALID_LENGTH;
1142 }
1143 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) &&
1144 (writecnt < 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001145 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001146 "0x%02x, got writecnt=%i, want >=4\n", __func__, cmd,
1147 writecnt);
1148 return SPI_INVALID_LENGTH;
1149 }
1150 if (((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1151 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) &&
1152 (readcnt)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001153 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001154 "0x%02x, got readcnt=%i, want =0\n", __func__, cmd,
1155 readcnt);
1156 return SPI_INVALID_LENGTH;
1157 }
1158
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001159 /* Translate read/write array/count.
1160 * The maximum data length is identical for the maximum read length and
1161 * for the maximum write length excluding opcode and address. Opcode and
1162 * address are stored in separate registers, not in the data registers
1163 * and are thus not counted towards data length. The only exception
1164 * applies if the opcode definition (un)intentionally classifies said
1165 * opcode incorrectly as non-address opcode or vice versa. */
Dominik Geyerb46acba2008-05-16 12:55:55 +00001166 if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001167 data = (uint8_t *) (writearr + 1);
1168 count = writecnt - 1;
1169 } else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
1170 data = (uint8_t *) (writearr + 4);
1171 count = writecnt - 4;
1172 } else {
1173 data = (uint8_t *) readarr;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001174 count = readcnt;
1175 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001176
Nico Hubered098d62017-04-21 23:47:08 +02001177 /* if opcode-type requires an address */
1178 if (cmd == JEDEC_REMS || cmd == JEDEC_RES) {
1179 addr = ichspi_bbar;
1180 } else if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS ||
1181 opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
1182 /* BBAR may cut part of the chip off at the lower end. */
1183 const uint32_t valid_base = ichspi_bbar & ((flash->chip->total_size * 1024) - 1);
1184 const uint32_t addr_offset = ichspi_bbar - valid_base;
1185 /* Highest address we can program is (2^24 - 1). */
1186 const uint32_t valid_end = (1 << 24) - addr_offset;
1187
1188 addr = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
1189 const uint32_t addr_end = addr + count;
1190
1191 if (addr < valid_base ||
1192 addr_end < addr || /* integer overflow check */
1193 addr_end > valid_end) {
1194 msg_perr("%s: Addressed region 0x%06x-0x%06x not in allowed range 0x%06x-0x%06x\n",
1195 __func__, addr, addr_end - 1, valid_base, valid_end - 1);
1196 return SPI_INVALID_ADDRESS;
1197 }
1198 addr += addr_offset;
1199 }
1200
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001201 result = run_opcode(flash, *opcode, addr, count, data);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001202 if (result) {
Stefan Tauner8ed29342011-04-29 23:53:09 +00001203 msg_pdbg("Running OPCODE 0x%02x failed ", opcode->opcode);
1204 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1205 (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS)) {
1206 msg_pdbg("at address 0x%06x ", addr);
1207 }
1208 msg_pdbg("(payload length was %d).\n", count);
1209
1210 /* Print out the data array if it contains data to write.
1211 * Errors are detected before the received data is read back into
1212 * the array so it won't make sense to print it then. */
1213 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1214 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) {
1215 int i;
1216 msg_pspew("The data was:\n");
Stefan Taunerf382e352011-11-08 11:55:24 +00001217 for (i = 0; i < count; i++){
Stefan Tauner8ed29342011-04-29 23:53:09 +00001218 msg_pspew("%3d: 0x%02x\n", i, data[i]);
1219 }
1220 }
Dominik Geyerb46acba2008-05-16 12:55:55 +00001221 }
1222
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001223 return result;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001224}
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001225
Stefan Tauner50e7c602011-11-08 10:55:54 +00001226static struct hwseq_data {
1227 uint32_t size_comp0;
1228 uint32_t size_comp1;
Nico Huberd54e4f42017-03-23 23:45:47 +01001229 uint32_t addr_mask;
1230 bool only_4k;
1231 uint32_t hsfc_fcycle;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001232} hwseq_data;
1233
Nico Huberd54e4f42017-03-23 23:45:47 +01001234/* Sets FLA in FADDR to (addr & hwseq_data.addr_mask) without touching other bits. */
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001235static void ich_hwseq_set_addr(uint32_t addr)
1236{
Nico Huberd54e4f42017-03-23 23:45:47 +01001237 uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~hwseq_data.addr_mask;
1238 REGWRITE32(ICH9_REG_FADDR, (addr & hwseq_data.addr_mask) | addr_old);
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001239}
1240
1241/* Sets FADDR.FLA to 'addr' and returns the erase block size in bytes
1242 * of the block containing this address. May return nonsense if the address is
1243 * not valid. The erase block size for a specific address depends on the flash
1244 * partition layout as specified by FPB and the partition properties as defined
1245 * by UVSCC and LVSCC respectively. An alternative to implement this method
1246 * would be by querying FPB and the respective VSCC register directly.
1247 */
1248static uint32_t ich_hwseq_get_erase_block_size(unsigned int addr)
1249{
Elyes HAOUAS29e46d02019-06-09 17:38:25 +02001250 uint8_t enc_berase;
1251 static const uint32_t dec_berase[4] = {
1252 256,
1253 4 * 1024,
1254 8 * 1024,
1255 64 * 1024
1256 };
1257
Nico Huberd54e4f42017-03-23 23:45:47 +01001258 if (hwseq_data.only_4k) {
1259 return 4 * 1024;
Nico Huberd54e4f42017-03-23 23:45:47 +01001260 }
Elyes HAOUAS29e46d02019-06-09 17:38:25 +02001261
1262 ich_hwseq_set_addr(addr);
1263 enc_berase = (REGREAD16(ICH9_REG_HSFS) & HSFS_BERASE) >> HSFS_BERASE_OFF;
1264 return dec_berase[enc_berase];
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001265}
1266
1267/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.
1268 Resets all error flags in HSFS.
1269 Returns 0 if the cycle completes successfully without errors within
1270 timeout us, 1 on errors. */
1271static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
1272 unsigned int len)
1273{
1274 uint16_t hsfs;
1275 uint32_t addr;
1276
1277 timeout /= 8; /* scale timeout duration to counter */
1278 while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) &
1279 (HSFS_FDONE | HSFS_FCERR)) == 0) &&
1280 --timeout) {
1281 programmer_delay(8);
1282 }
1283 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1284 if (!timeout) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001285 addr = REGREAD32(ICH9_REG_FADDR) & hwseq_data.addr_mask;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001286 msg_perr("Timeout error between offset 0x%08x and "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001287 "0x%08x (= 0x%08x + %d)!\n",
1288 addr, addr + len - 1, addr, len - 1);
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001289 prettyprint_ich9_reg_hsfs(hsfs);
1290 prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC));
1291 return 1;
1292 }
1293
1294 if (hsfs & HSFS_FCERR) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001295 addr = REGREAD32(ICH9_REG_FADDR) & hwseq_data.addr_mask;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001296 msg_perr("Transaction error between offset 0x%08x and "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001297 "0x%08x (= 0x%08x + %d)!\n",
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001298 addr, addr + len - 1, addr, len - 1);
1299 prettyprint_ich9_reg_hsfs(hsfs);
1300 prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC));
1301 return 1;
1302 }
1303 return 0;
1304}
Stefan Tauner50e7c602011-11-08 10:55:54 +00001305
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001306static int ich_hwseq_probe(struct flashctx *flash)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001307{
1308 uint32_t total_size, boundary;
1309 uint32_t erase_size_low, size_low, erase_size_high, size_high;
1310 struct block_eraser *eraser;
1311
1312 total_size = hwseq_data.size_comp0 + hwseq_data.size_comp1;
Stefan Tauner5c316f92015-02-08 21:57:52 +00001313 msg_cdbg("Hardware sequencing reports %d attached SPI flash chip",
Stefan Tauner50e7c602011-11-08 10:55:54 +00001314 (hwseq_data.size_comp1 != 0) ? 2 : 1);
1315 if (hwseq_data.size_comp1 != 0)
1316 msg_cdbg("s with a combined");
1317 else
1318 msg_cdbg(" with a");
1319 msg_cdbg(" density of %d kB.\n", total_size / 1024);
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001320 flash->chip->total_size = total_size / 1024;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001321
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001322 eraser = &(flash->chip->block_erasers[0]);
Nico Huberd54e4f42017-03-23 23:45:47 +01001323 if (!hwseq_data.only_4k)
1324 boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12;
1325 else
1326 boundary = 0;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001327 size_high = total_size - boundary;
1328 erase_size_high = ich_hwseq_get_erase_block_size(boundary);
1329
1330 if (boundary == 0) {
Stefan Tauner5c316f92015-02-08 21:57:52 +00001331 msg_cdbg2("There is only one partition containing the whole "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001332 "address space (0x%06x - 0x%06x).\n", 0, size_high-1);
1333 eraser->eraseblocks[0].size = erase_size_high;
1334 eraser->eraseblocks[0].count = size_high / erase_size_high;
Stefan Tauner5c316f92015-02-08 21:57:52 +00001335 msg_cdbg2("There are %d erase blocks with %d B each.\n",
Stefan Tauner50e7c602011-11-08 10:55:54 +00001336 size_high / erase_size_high, erase_size_high);
1337 } else {
Stefan Tauner5c316f92015-02-08 21:57:52 +00001338 msg_cdbg2("The flash address space (0x%06x - 0x%06x) is divided "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001339 "at address 0x%06x in two partitions.\n",
Stefan Taunerdbac46c2013-08-13 22:10:41 +00001340 0, total_size-1, boundary);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001341 size_low = total_size - size_high;
1342 erase_size_low = ich_hwseq_get_erase_block_size(0);
1343
1344 eraser->eraseblocks[0].size = erase_size_low;
1345 eraser->eraseblocks[0].count = size_low / erase_size_low;
1346 msg_cdbg("The first partition ranges from 0x%06x to 0x%06x.\n",
1347 0, size_low-1);
1348 msg_cdbg("In that range are %d erase blocks with %d B each.\n",
1349 size_low / erase_size_low, erase_size_low);
1350
1351 eraser->eraseblocks[1].size = erase_size_high;
1352 eraser->eraseblocks[1].count = size_high / erase_size_high;
1353 msg_cdbg("The second partition ranges from 0x%06x to 0x%06x.\n",
Stefan Taunerdbac46c2013-08-13 22:10:41 +00001354 boundary, total_size-1);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001355 msg_cdbg("In that range are %d erase blocks with %d B each.\n",
1356 size_high / erase_size_high, erase_size_high);
1357 }
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001358 flash->chip->tested = TEST_OK_PREW;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001359 return 1;
1360}
1361
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001362static int ich_hwseq_block_erase(struct flashctx *flash, unsigned int addr,
1363 unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001364{
1365 uint32_t erase_block;
1366 uint16_t hsfc;
1367 uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */
1368
1369 erase_block = ich_hwseq_get_erase_block_size(addr);
1370 if (len != erase_block) {
1371 msg_cerr("Erase block size for address 0x%06x is %d B, "
1372 "but requested erase block size is %d B. "
1373 "Not erasing anything.\n", addr, erase_block, len);
1374 return -1;
1375 }
1376
1377 /* Although the hardware supports this (it would erase the whole block
1378 * containing the address) we play safe here. */
1379 if (addr % erase_block != 0) {
1380 msg_cerr("Erase address 0x%06x is not aligned to the erase "
1381 "block boundary (any multiple of %d). "
1382 "Not erasing anything.\n", addr, erase_block);
1383 return -1;
1384 }
1385
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001386 if (addr + len > flash->chip->total_size * 1024) {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001387 msg_perr("Request to erase some inaccessible memory address(es)"
1388 " (addr=0x%x, len=%d). "
1389 "Not erasing anything.\n", addr, len);
1390 return -1;
1391 }
1392
1393 msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr);
Stefan Tauner7608d362014-08-05 23:28:47 +00001394 ich_hwseq_set_addr(addr);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001395
1396 /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */
1397 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1398
1399 hsfc = REGREAD16(ICH9_REG_HSFC);
Nico Huberd54e4f42017-03-23 23:45:47 +01001400 hsfc &= ~hwseq_data.hsfc_fcycle; /* clear operation */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001401 hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */
1402 hsfc |= HSFC_FGO; /* start */
1403 msg_pdbg("HSFC used for block erasing: ");
1404 prettyprint_ich9_reg_hsfc(hsfc);
1405 REGWRITE16(ICH9_REG_HSFC, hsfc);
1406
1407 if (ich_hwseq_wait_for_cycle_complete(timeout, len))
1408 return -1;
1409 return 0;
1410}
1411
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001412static int ich_hwseq_read(struct flashctx *flash, uint8_t *buf,
1413 unsigned int addr, unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001414{
1415 uint16_t hsfc;
1416 uint16_t timeout = 100 * 60;
1417 uint8_t block_len;
1418
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001419 if (addr + len > flash->chip->total_size * 1024) {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001420 msg_perr("Request to read from an inaccessible memory address "
1421 "(addr=0x%x, len=%d).\n", addr, len);
1422 return -1;
1423 }
1424
1425 msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr);
1426 /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
1427 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1428
1429 while (len > 0) {
Stefan Tauner7608d362014-08-05 23:28:47 +00001430 /* Obey programmer limit... */
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001431 block_len = min(len, flash->mst->opaque.max_data_read);
Stefan Tauner7608d362014-08-05 23:28:47 +00001432 /* as well as flash chip page borders as demanded in the Intel datasheets. */
1433 block_len = min(block_len, 256 - (addr & 0xFF));
1434
Stefan Tauner50e7c602011-11-08 10:55:54 +00001435 ich_hwseq_set_addr(addr);
1436 hsfc = REGREAD16(ICH9_REG_HSFC);
Nico Huberd54e4f42017-03-23 23:45:47 +01001437 hsfc &= ~hwseq_data.hsfc_fcycle; /* set read operation */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001438 hsfc &= ~HSFC_FDBC; /* clear byte count */
1439 /* set byte count */
1440 hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
1441 hsfc |= HSFC_FGO; /* start */
1442 REGWRITE16(ICH9_REG_HSFC, hsfc);
1443
1444 if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
1445 return 1;
1446 ich_read_data(buf, block_len, ICH9_REG_FDATA0);
1447 addr += block_len;
1448 buf += block_len;
1449 len -= block_len;
1450 }
1451 return 0;
1452}
1453
Mark Marshallf20b7be2014-05-09 21:16:21 +00001454static int ich_hwseq_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001455{
1456 uint16_t hsfc;
1457 uint16_t timeout = 100 * 60;
1458 uint8_t block_len;
1459
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001460 if (addr + len > flash->chip->total_size * 1024) {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001461 msg_perr("Request to write to an inaccessible memory address "
1462 "(addr=0x%x, len=%d).\n", addr, len);
1463 return -1;
1464 }
1465
1466 msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr);
1467 /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
1468 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1469
1470 while (len > 0) {
1471 ich_hwseq_set_addr(addr);
Stefan Tauner7608d362014-08-05 23:28:47 +00001472 /* Obey programmer limit... */
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001473 block_len = min(len, flash->mst->opaque.max_data_write);
Stefan Tauner7608d362014-08-05 23:28:47 +00001474 /* as well as flash chip page borders as demanded in the Intel datasheets. */
1475 block_len = min(block_len, 256 - (addr & 0xFF));
Stefan Tauner50e7c602011-11-08 10:55:54 +00001476 ich_fill_data(buf, block_len, ICH9_REG_FDATA0);
1477 hsfc = REGREAD16(ICH9_REG_HSFC);
Nico Huberd54e4f42017-03-23 23:45:47 +01001478 hsfc &= ~hwseq_data.hsfc_fcycle; /* clear operation */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001479 hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */
1480 hsfc &= ~HSFC_FDBC; /* clear byte count */
1481 /* set byte count */
1482 hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
1483 hsfc |= HSFC_FGO; /* start */
1484 REGWRITE16(ICH9_REG_HSFC, hsfc);
1485
1486 if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
1487 return -1;
1488 addr += block_len;
1489 buf += block_len;
1490 len -= block_len;
1491 }
1492 return 0;
1493}
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001494
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001495static int ich_spi_send_multicommand(struct flashctx *flash,
1496 struct spi_command *cmds)
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001497{
1498 int ret = 0;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001499 int i;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001500 int oppos, preoppos;
1501 for (; (cmds->writecnt || cmds->readcnt) && !ret; cmds++) {
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001502 if ((cmds + 1)->writecnt || (cmds + 1)->readcnt) {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001503 /* Next command is valid. */
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001504 preoppos = find_preop(curopcodes, cmds->writearr[0]);
1505 oppos = find_opcode(curopcodes, (cmds + 1)->writearr[0]);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001506 if ((oppos == -1) && (preoppos != -1)) {
1507 /* Current command is listed as preopcode in
1508 * ICH struct OPCODES, but next command is not
1509 * listed as opcode in that struct.
1510 * Check for command sanity, then
1511 * try to reprogram the ICH opcode list.
1512 */
1513 if (find_preop(curopcodes,
1514 (cmds + 1)->writearr[0]) != -1) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001515 msg_perr("%s: Two subsequent "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001516 "preopcodes 0x%02x and 0x%02x, "
1517 "ignoring the first.\n",
1518 __func__, cmds->writearr[0],
1519 (cmds + 1)->writearr[0]);
1520 continue;
1521 }
1522 /* If the chipset is locked down, we'll fail
1523 * during execution of the next command anyway.
1524 * No need to bother with fixups.
1525 */
1526 if (!ichspi_lock) {
Helge Wagner738e2522010-10-05 22:06:05 +00001527 oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt);
1528 if (oppos == -1)
1529 continue;
1530 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001531 continue;
1532 }
1533 }
1534 if ((oppos != -1) && (preoppos != -1)) {
1535 /* Current command is listed as preopcode in
1536 * ICH struct OPCODES and next command is listed
1537 * as opcode in that struct. Match them up.
1538 */
1539 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001540 continue;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001541 }
1542 /* If none of the above if-statements about oppos or
1543 * preoppos matched, this is a normal opcode.
1544 */
1545 }
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001546 ret = ich_spi_send_command(flash, cmds->writecnt, cmds->readcnt,
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001547 cmds->writearr, cmds->readarr);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001548 /* Reset the type of all opcodes to non-atomic. */
1549 for (i = 0; i < 8; i++)
1550 curopcodes->opcode[i].atomic = 0;
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001551 }
1552 return ret;
1553}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001554
Michael Karchera4448d92010-07-22 18:04:15 +00001555#define ICH_BMWAG(x) ((x >> 24) & 0xff)
1556#define ICH_BMRAG(x) ((x >> 16) & 0xff)
1557#define ICH_BRWA(x) ((x >> 8) & 0xff)
1558#define ICH_BRRA(x) ((x >> 0) & 0xff)
1559
Nico Huber7590d1a2016-05-03 13:38:28 +02001560static const enum ich_access_protection access_perms_to_protection[] = {
1561 LOCKED, WRITE_PROT, READ_PROT, NO_PROT
1562};
1563static const char *const access_names[] = {
1564 "locked", "read-only", "write-only", "read-write"
1565};
1566
1567static enum ich_access_protection ich9_handle_frap(uint32_t frap, int i)
Michael Karchera4448d92010-07-22 18:04:15 +00001568{
Nico Huberaa91d5c2017-08-19 17:04:21 +02001569 const int rwperms_unknown = ARRAY_SIZE(access_names);
Nico Huberd2d39932019-01-18 16:49:37 +01001570 static const char *const region_names[6] = {
Michael Karchera4448d92010-07-22 18:04:15 +00001571 "Flash Descriptor", "BIOS", "Management Engine",
Nico Huberd2d39932019-01-18 16:49:37 +01001572 "Gigabit Ethernet", "Platform Data", "Device Expansion",
Michael Karchera4448d92010-07-22 18:04:15 +00001573 };
Nico Huberd54e4f42017-03-23 23:45:47 +01001574 const char *const region_name = i < ARRAY_SIZE(region_names) ? region_names[i] : "unknown";
1575
Michael Karchera4448d92010-07-22 18:04:15 +00001576 uint32_t base, limit;
Nico Huberaa91d5c2017-08-19 17:04:21 +02001577 int rwperms;
Nico Huberd2d39932019-01-18 16:49:37 +01001578 const int offset = i < 12
1579 ? ICH9_REG_FREG0 + i * 4
1580 : APL_REG_FREG12 + (i - 12) * 4;
Michael Karchera4448d92010-07-22 18:04:15 +00001581 uint32_t freg = mmio_readl(ich_spibar + offset);
1582
Nico Huberaa91d5c2017-08-19 17:04:21 +02001583 if (i < 8) {
1584 rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) |
1585 (((ICH_BRRA(frap) >> i) & 1) << 0);
1586 } else {
1587 /* Datasheets don't define any access bits for regions > 7. We
1588 can't rely on the actual descriptor settings either as there
1589 are several overrides for them (those by other masters are
1590 not even readable by us, *shrug*). */
1591 rwperms = rwperms_unknown;
1592 }
1593
Michael Karchera4448d92010-07-22 18:04:15 +00001594 base = ICH_FREG_BASE(freg);
1595 limit = ICH_FREG_LIMIT(freg);
Stefan Taunere3adea02012-08-27 15:12:36 +00001596 if (base > limit || (freg == 0 && i > 0)) {
Michael Karchera4448d92010-07-22 18:04:15 +00001597 /* this FREG is disabled */
Stefan Tauner5210e722012-02-16 01:13:00 +00001598 msg_pdbg2("0x%02X: 0x%08x FREG%i: %s region is unused.\n",
Nico Huberd54e4f42017-03-23 23:45:47 +01001599 offset, freg, i, region_name);
Nico Huber7590d1a2016-05-03 13:38:28 +02001600 return NO_PROT;
Stefan Tauner5210e722012-02-16 01:13:00 +00001601 }
1602 msg_pdbg("0x%02X: 0x%08x ", offset, freg);
1603 if (rwperms == 0x3) {
1604 msg_pdbg("FREG%i: %s region (0x%08x-0x%08x) is %s.\n", i,
Nico Huber0bb3f712017-03-29 16:44:33 +02001605 region_name, base, limit, access_names[rwperms]);
Nico Huber7590d1a2016-05-03 13:38:28 +02001606 return NO_PROT;
Michael Karchera4448d92010-07-22 18:04:15 +00001607 }
Nico Huberaa91d5c2017-08-19 17:04:21 +02001608 if (rwperms == rwperms_unknown) {
1609 msg_pdbg("FREG%i: %s region (0x%08x-0x%08x) has unknown permissions.\n",
1610 i, region_name, base, limit);
Nico Huber7590d1a2016-05-03 13:38:28 +02001611 return NO_PROT;
Nico Huberaa91d5c2017-08-19 17:04:21 +02001612 }
Michael Karchera4448d92010-07-22 18:04:15 +00001613
Nico Huber7590d1a2016-05-03 13:38:28 +02001614 msg_pinfo("FREG%i: %s region (0x%08x-0x%08x) is %s.\n", i,
Nico Huber0bb3f712017-03-29 16:44:33 +02001615 region_name, base, limit, access_names[rwperms]);
Nico Huber7590d1a2016-05-03 13:38:28 +02001616 return access_perms_to_protection[rwperms];
Michael Karchera4448d92010-07-22 18:04:15 +00001617}
1618
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001619 /* In contrast to FRAP and the master section of the descriptor the bits
1620 * in the PR registers have an inverted meaning. The bits in FRAP
1621 * indicate read and write access _grant_. Here they indicate read
1622 * and write _protection_ respectively. If both bits are 0 the address
1623 * bits are ignored.
1624 */
1625#define ICH_PR_PERMS(pr) (((~((pr) >> PR_RP_OFF) & 1) << 0) | \
1626 ((~((pr) >> PR_WP_OFF) & 1) << 1))
1627
Nico Huber7590d1a2016-05-03 13:38:28 +02001628static enum ich_access_protection ich9_handle_pr(const size_t reg_pr0, int i)
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001629{
Nico Huberd54e4f42017-03-23 23:45:47 +01001630 uint8_t off = reg_pr0 + (i * 4);
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001631 uint32_t pr = mmio_readl(ich_spibar + off);
Stefan Tauner5210e722012-02-16 01:13:00 +00001632 unsigned int rwperms = ICH_PR_PERMS(pr);
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001633
Nico Huberd54e4f42017-03-23 23:45:47 +01001634 /* From 5 on we have GPR registers and start from 0 again. */
1635 const char *const prefix = i >= 5 ? "G" : "";
1636 if (i >= 5)
1637 i -= 5;
1638
Stefan Tauner5210e722012-02-16 01:13:00 +00001639 if (rwperms == 0x3) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001640 msg_pdbg2("0x%02X: 0x%08x (%sPR%u is unused)\n", off, pr, prefix, i);
Nico Huber7590d1a2016-05-03 13:38:28 +02001641 return NO_PROT;
Stefan Tauner5210e722012-02-16 01:13:00 +00001642 }
1643
1644 msg_pdbg("0x%02X: 0x%08x ", off, pr);
Nico Huberd54e4f42017-03-23 23:45:47 +01001645 msg_pwarn("%sPR%u: Warning: 0x%08x-0x%08x is %s.\n", prefix, i, ICH_FREG_BASE(pr),
Nico Huber0bb3f712017-03-29 16:44:33 +02001646 ICH_FREG_LIMIT(pr), access_names[rwperms]);
Nico Huber7590d1a2016-05-03 13:38:28 +02001647 return access_perms_to_protection[rwperms];
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001648}
1649
Stefan Tauner75da80c2011-09-17 22:21:55 +00001650/* Set/Clear the read and write protection enable bits of PR register @i
1651 * according to @read_prot and @write_prot. */
Nico Huberd54e4f42017-03-23 23:45:47 +01001652static void ich9_set_pr(const size_t reg_pr0, int i, int read_prot, int write_prot)
Stefan Tauner75da80c2011-09-17 22:21:55 +00001653{
Nico Huberd54e4f42017-03-23 23:45:47 +01001654 void *addr = ich_spibar + reg_pr0 + (i * 4);
Stefan Tauner75da80c2011-09-17 22:21:55 +00001655 uint32_t old = mmio_readl(addr);
1656 uint32_t new;
1657
1658 msg_gspew("PR%u is 0x%08x", i, old);
1659 new = old & ~((1 << PR_RP_OFF) | (1 << PR_WP_OFF));
1660 if (read_prot)
1661 new |= (1 << PR_RP_OFF);
1662 if (write_prot)
1663 new |= (1 << PR_WP_OFF);
1664 if (old == new) {
1665 msg_gspew(" already.\n");
1666 return;
1667 }
1668 msg_gspew(", trying to set it to 0x%08x ", new);
1669 rmmio_writel(new, addr);
1670 msg_gspew("resulted in 0x%08x.\n", mmio_readl(addr));
1671}
1672
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001673static const struct spi_master spi_master_ich7 = {
Michael Karcherb9dbe482011-05-11 17:07:07 +00001674 .max_data_read = 64,
1675 .max_data_write = 64,
1676 .command = ich_spi_send_command,
1677 .multicommand = ich_spi_send_multicommand,
1678 .read = default_spi_read,
1679 .write_256 = default_spi_write_256,
Nico Huber7bca1262012-06-15 22:28:12 +00001680 .write_aai = default_spi_write_aai,
Michael Karcherb9dbe482011-05-11 17:07:07 +00001681};
1682
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001683static const struct spi_master spi_master_ich9 = {
Michael Karcherb9dbe482011-05-11 17:07:07 +00001684 .max_data_read = 64,
1685 .max_data_write = 64,
1686 .command = ich_spi_send_command,
1687 .multicommand = ich_spi_send_multicommand,
1688 .read = default_spi_read,
1689 .write_256 = default_spi_write_256,
Nico Huber7bca1262012-06-15 22:28:12 +00001690 .write_aai = default_spi_write_aai,
Michael Karcherb9dbe482011-05-11 17:07:07 +00001691};
1692
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001693static const struct opaque_master opaque_master_ich_hwseq = {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001694 .max_data_read = 64,
1695 .max_data_write = 64,
1696 .probe = ich_hwseq_probe,
1697 .read = ich_hwseq_read,
1698 .write = ich_hwseq_write,
1699 .erase = ich_hwseq_block_erase,
1700};
1701
Nico Huber560111e2017-04-26 12:27:17 +02001702int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
Michael Karchera4448d92010-07-22 18:04:15 +00001703{
1704 int i;
Stefan Tauner92d6a862013-10-25 00:33:37 +00001705 uint16_t tmp2;
Michael Karchera4448d92010-07-22 18:04:15 +00001706 uint32_t tmp;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001707 char *arg;
Stefan Tauner5210e722012-02-16 01:13:00 +00001708 int ich_spi_rw_restricted = 0;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001709 int desc_valid = 0;
Richard Hughese2cbb122019-01-02 21:11:08 +00001710 struct ich_descriptors desc;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001711 enum ich_spi_mode {
1712 ich_auto,
1713 ich_hwseq,
1714 ich_swseq
1715 } ich_spi_mode = ich_auto;
Nico Huberd54e4f42017-03-23 23:45:47 +01001716 size_t num_freg, num_pr, reg_pr0;
Michael Karchera4448d92010-07-22 18:04:15 +00001717
Stefan Taunera8d838d2011-11-06 23:51:09 +00001718 ich_generation = ich_gen;
Stefan Tauner92d6a862013-10-25 00:33:37 +00001719 ich_spibar = spibar;
Michael Karchera4448d92010-07-22 18:04:15 +00001720
Richard Hughese2cbb122019-01-02 21:11:08 +00001721 memset(&desc, 0x00, sizeof(struct ich_descriptors));
1722
Nico Huberd54e4f42017-03-23 23:45:47 +01001723 /* Moving registers / bits */
Nico Huberd2d39932019-01-18 16:49:37 +01001724 switch (ich_generation) {
1725 case CHIPSET_100_SERIES_SUNRISE_POINT:
1726 case CHIPSET_C620_SERIES_LEWISBURG:
1727 case CHIPSET_APOLLO_LAKE:
David Hendricksa5216362017-08-08 20:02:22 -07001728 num_pr = 6; /* Includes GPR0 */
1729 reg_pr0 = PCH100_REG_FPR0;
1730 swseq_data.reg_ssfsc = PCH100_REG_SSFSC;
1731 swseq_data.reg_preop = PCH100_REG_PREOP;
1732 swseq_data.reg_optype = PCH100_REG_OPTYPE;
1733 swseq_data.reg_opmenu = PCH100_REG_OPMENU;
1734 hwseq_data.addr_mask = PCH100_FADDR_FLA;
1735 hwseq_data.only_4k = true;
1736 hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE;
Nico Huberd2d39932019-01-18 16:49:37 +01001737 break;
1738 default:
Nico Huberd54e4f42017-03-23 23:45:47 +01001739 num_pr = 5;
1740 reg_pr0 = ICH9_REG_PR0;
1741 swseq_data.reg_ssfsc = ICH9_REG_SSFS;
1742 swseq_data.reg_preop = ICH9_REG_PREOP;
1743 swseq_data.reg_optype = ICH9_REG_OPTYPE;
1744 swseq_data.reg_opmenu = ICH9_REG_OPMENU;
1745 hwseq_data.addr_mask = ICH9_FADDR_FLA;
1746 hwseq_data.only_4k = false;
1747 hwseq_data.hsfc_fcycle = HSFC_FCYCLE;
Nico Huberd2d39932019-01-18 16:49:37 +01001748 break;
1749 }
1750 switch (ich_generation) {
1751 case CHIPSET_100_SERIES_SUNRISE_POINT:
1752 num_freg = 10;
1753 break;
1754 case CHIPSET_C620_SERIES_LEWISBURG:
1755 num_freg = 12; /* 12 MMIO regs, but 16 regions in FD spec */
1756 break;
1757 case CHIPSET_APOLLO_LAKE:
1758 num_freg = 16;
1759 break;
1760 default:
1761 num_freg = 5;
1762 break;
Nico Huberd54e4f42017-03-23 23:45:47 +01001763 }
1764
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001765 switch (ich_generation) {
Stefan Taunera8d838d2011-11-06 23:51:09 +00001766 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +00001767 case CHIPSET_TUNNEL_CREEK:
1768 case CHIPSET_CENTERTON:
Michael Karchera4448d92010-07-22 18:04:15 +00001769 msg_pdbg("0x00: 0x%04x (SPIS)\n",
1770 mmio_readw(ich_spibar + 0));
1771 msg_pdbg("0x02: 0x%04x (SPIC)\n",
1772 mmio_readw(ich_spibar + 2));
1773 msg_pdbg("0x04: 0x%08x (SPIA)\n",
1774 mmio_readl(ich_spibar + 4));
Michael Karchera4448d92010-07-22 18:04:15 +00001775 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
1776 msg_pdbg("0x50: 0x%08x (BBAR)\n",
1777 ichspi_bbar);
1778 msg_pdbg("0x54: 0x%04x (PREOP)\n",
1779 mmio_readw(ich_spibar + 0x54));
1780 msg_pdbg("0x56: 0x%04x (OPTYPE)\n",
1781 mmio_readw(ich_spibar + 0x56));
1782 msg_pdbg("0x58: 0x%08x (OPMENU)\n",
1783 mmio_readl(ich_spibar + 0x58));
1784 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n",
1785 mmio_readl(ich_spibar + 0x5c));
Stefan Tauner122dd122011-07-24 15:34:56 +00001786 for (i = 0; i < 3; i++) {
Michael Karchera4448d92010-07-22 18:04:15 +00001787 int offs;
1788 offs = 0x60 + (i * 4);
1789 msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,
1790 mmio_readl(ich_spibar + offs), i);
1791 }
Michael Karchera4448d92010-07-22 18:04:15 +00001792 if (mmio_readw(ich_spibar) & (1 << 15)) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00001793 msg_pwarn("WARNING: SPI Configuration Lockdown activated.\n");
Michael Karchera4448d92010-07-22 18:04:15 +00001794 ichspi_lock = 1;
1795 }
Stefan Tauner745f6bb2011-11-13 15:17:10 +00001796 ich_init_opcodes();
Stefan Taunera8d838d2011-11-06 23:51:09 +00001797 ich_set_bbar(0);
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001798 register_spi_master(&spi_master_ich7);
Michael Karchera4448d92010-07-22 18:04:15 +00001799 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +00001800 case CHIPSET_ICH8:
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001801 default: /* Future version might behave the same */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001802 arg = extract_programmer_param("ich_spi_mode");
1803 if (arg && !strcmp(arg, "hwseq")) {
1804 ich_spi_mode = ich_hwseq;
1805 msg_pspew("user selected hwseq\n");
1806 } else if (arg && !strcmp(arg, "swseq")) {
1807 ich_spi_mode = ich_swseq;
1808 msg_pspew("user selected swseq\n");
1809 } else if (arg && !strcmp(arg, "auto")) {
1810 msg_pspew("user selected auto\n");
1811 ich_spi_mode = ich_auto;
1812 } else if (arg && !strlen(arg)) {
1813 msg_perr("Missing argument for ich_spi_mode.\n");
1814 free(arg);
1815 return ERROR_FATAL;
1816 } else if (arg) {
1817 msg_perr("Unknown argument for ich_spi_mode: %s\n",
1818 arg);
1819 free(arg);
1820 return ERROR_FATAL;
1821 }
1822 free(arg);
1823
Stefan Tauner29c80832011-06-12 08:14:10 +00001824 tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS);
Michael Karchera4448d92010-07-22 18:04:15 +00001825 msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2);
Stefan Tauner55206942011-06-11 09:53:22 +00001826 prettyprint_ich9_reg_hsfs(tmp2);
Stefan Tauner29c80832011-06-12 08:14:10 +00001827 if (tmp2 & HSFS_FLOCKDN) {
Nico Huber7590d1a2016-05-03 13:38:28 +02001828 msg_pinfo("SPI Configuration is locked down.\n");
Stefan Tauner55206942011-06-11 09:53:22 +00001829 ichspi_lock = 1;
1830 }
Stefan Tauner1e146392011-09-15 23:52:55 +00001831 if (tmp2 & HSFS_FDV)
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001832 desc_valid = 1;
1833 if (!(tmp2 & HSFS_FDOPSS) && desc_valid)
Stefan Taunerd7d423b2012-10-20 09:13:16 +00001834 msg_pinfo("The Flash Descriptor Override Strap-Pin is set. Restrictions implied by\n"
1835 "the Master Section of the flash descriptor are NOT in effect. Please note\n"
1836 "that Protected Range (PR) restrictions still apply.\n");
Stefan Tauner745f6bb2011-11-13 15:17:10 +00001837 ich_init_opcodes();
Stefan Tauner55206942011-06-11 09:53:22 +00001838
Stefan Taunerf382e352011-11-08 11:55:24 +00001839 if (desc_valid) {
1840 tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC);
1841 msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2);
1842 prettyprint_ich9_reg_hsfc(tmp2);
1843 }
Michael Karchera4448d92010-07-22 18:04:15 +00001844
Stefan Tauner5ffe65b2011-07-07 04:10:57 +00001845 tmp = mmio_readl(ich_spibar + ICH9_REG_FADDR);
Stefan Taunereb582572012-09-21 12:52:50 +00001846 msg_pdbg2("0x08: 0x%08x (FADDR)\n", tmp);
Michael Karchera4448d92010-07-22 18:04:15 +00001847
Nico Huberd2d39932019-01-18 16:49:37 +01001848 switch (ich_gen) {
1849 case CHIPSET_100_SERIES_SUNRISE_POINT:
1850 case CHIPSET_C620_SERIES_LEWISBURG:
1851 case CHIPSET_APOLLO_LAKE:
1852 tmp = mmio_readl(ich_spibar + PCH100_REG_DLOCK);
1853 msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp);
1854 prettyprint_pch100_reg_dlock(tmp);
1855 break;
1856 default:
1857 break;
Nico Huberd54e4f42017-03-23 23:45:47 +01001858 }
1859
Stefan Taunerf382e352011-11-08 11:55:24 +00001860 if (desc_valid) {
1861 tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP);
1862 msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp);
1863 msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp));
1864 msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp));
1865 msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp));
1866 msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp));
1867
Stefan Tauner5210e722012-02-16 01:13:00 +00001868 /* Handle FREGx and FRAP registers */
Nico Huberd54e4f42017-03-23 23:45:47 +01001869 for (i = 0; i < num_freg; i++)
Stefan Tauner5210e722012-02-16 01:13:00 +00001870 ich_spi_rw_restricted |= ich9_handle_frap(tmp, i);
Stefan Tauner27cb34b2013-06-01 00:06:12 +00001871 if (ich_spi_rw_restricted)
Nico Huber7590d1a2016-05-03 13:38:28 +02001872 msg_pinfo("Not all flash regions are freely accessible by flashrom. This is "
Stefan Tauner4c723152016-01-14 22:47:55 +00001873 "most likely\ndue to an active ME. Please see "
1874 "https://flashrom.org/ME for details.\n");
Stefan Taunerf382e352011-11-08 11:55:24 +00001875 }
Michael Karchera4448d92010-07-22 18:04:15 +00001876
Stefan Taunereb582572012-09-21 12:52:50 +00001877 /* Handle PR registers */
Nico Huberd54e4f42017-03-23 23:45:47 +01001878 for (i = 0; i < num_pr; i++) {
Stefan Tauner5210e722012-02-16 01:13:00 +00001879 /* if not locked down try to disable PR locks first */
1880 if (!ichspi_lock)
Nico Huberd54e4f42017-03-23 23:45:47 +01001881 ich9_set_pr(reg_pr0, i, 0, 0);
1882 ich_spi_rw_restricted |= ich9_handle_pr(reg_pr0, i);
Stefan Tauner5210e722012-02-16 01:13:00 +00001883 }
1884
Nico Huber7590d1a2016-05-03 13:38:28 +02001885 switch (ich_spi_rw_restricted) {
1886 case WRITE_PROT:
1887 msg_pwarn("At least some flash regions are write protected. For write operations,\n"
1888 "you should use a flash layout and include only writable regions. See\n"
1889 "manpage for more details.\n");
1890 break;
1891 case READ_PROT:
1892 case LOCKED:
1893 msg_pwarn("At least some flash regions are read protected. You have to use a flash\n"
1894 "layout and include only accessible regions. For write operations, you'll\n"
1895 "additionally need the --noverify-all switch. See manpage for more details.\n"
1896 );
1897 break;
Stefan Tauner5210e722012-02-16 01:13:00 +00001898 }
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001899
Nico Huberd54e4f42017-03-23 23:45:47 +01001900 tmp = mmio_readl(ich_spibar + swseq_data.reg_ssfsc);
1901 msg_pdbg("0x%zx: 0x%02x (SSFS)\n", swseq_data.reg_ssfsc, tmp & 0xff);
Stefan Tauner2a8b2622011-06-11 09:53:16 +00001902 prettyprint_ich9_reg_ssfs(tmp);
Stefan Tauner29c80832011-06-12 08:14:10 +00001903 if (tmp & SSFS_FCERR) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001904 msg_pdbg("Clearing SSFS.FCERR\n");
Nico Huberd54e4f42017-03-23 23:45:47 +01001905 mmio_writeb(SSFS_FCERR, ich_spibar + swseq_data.reg_ssfsc);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001906 }
Nico Huberd54e4f42017-03-23 23:45:47 +01001907 msg_pdbg("0x%zx: 0x%06x (SSFC)\n", swseq_data.reg_ssfsc + 1, tmp >> 8);
Stefan Tauner2a8b2622011-06-11 09:53:16 +00001908 prettyprint_ich9_reg_ssfc(tmp);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001909
Nico Huberd54e4f42017-03-23 23:45:47 +01001910 msg_pdbg("0x%zx: 0x%04x (PREOP)\n",
1911 swseq_data.reg_preop, mmio_readw(ich_spibar + swseq_data.reg_preop));
1912 msg_pdbg("0x%zx: 0x%04x (OPTYPE)\n",
1913 swseq_data.reg_optype, mmio_readw(ich_spibar + swseq_data.reg_optype));
1914 msg_pdbg("0x%zx: 0x%08x (OPMENU)\n",
1915 swseq_data.reg_opmenu, mmio_readl(ich_spibar + swseq_data.reg_opmenu));
1916 msg_pdbg("0x%zx: 0x%08x (OPMENU+4)\n",
1917 swseq_data.reg_opmenu + 4, mmio_readl(ich_spibar + swseq_data.reg_opmenu + 4));
Nico Huberd2d39932019-01-18 16:49:37 +01001918
1919 if (desc_valid) {
1920 switch (ich_gen) {
1921 case CHIPSET_ICH8:
1922 case CHIPSET_100_SERIES_SUNRISE_POINT:
1923 case CHIPSET_C620_SERIES_LEWISBURG:
1924 case CHIPSET_APOLLO_LAKE:
1925 case CHIPSET_BAYTRAIL:
1926 break;
1927 default:
Duncan Laurie4095ed72014-08-20 15:39:32 +00001928 ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR);
Nico Huberd2d39932019-01-18 16:49:37 +01001929 msg_pdbg("0x%x: 0x%08x (BBAR)\n", ICH9_REG_BBAR, ichspi_bbar);
Duncan Laurie4095ed72014-08-20 15:39:32 +00001930 ich_set_bbar(0);
Nico Huberd2d39932019-01-18 16:49:37 +01001931 break;
Duncan Laurie4095ed72014-08-20 15:39:32 +00001932 }
Stefan Taunerbd649e42011-07-01 00:39:16 +00001933
Nico Huberd2d39932019-01-18 16:49:37 +01001934 if (ich_gen == CHIPSET_ICH8) {
1935 tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC);
1936 msg_pdbg("0x%x: 0x%08x (VSCC)\n", ICH8_REG_VSCC, tmp);
1937 msg_pdbg("VSCC: ");
1938 prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true);
1939 } else {
Stefan Taunerf382e352011-11-08 11:55:24 +00001940 tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC);
Nico Huberd2d39932019-01-18 16:49:37 +01001941 msg_pdbg("0x%x: 0x%08x (LVSCC)\n", ICH9_REG_LVSCC, tmp);
Stefan Taunerf382e352011-11-08 11:55:24 +00001942 msg_pdbg("LVSCC: ");
Nico Huberd152fb92017-06-19 12:57:10 +02001943 prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true);
Stefan Tauner1e146392011-09-15 23:52:55 +00001944
Stefan Taunerf382e352011-11-08 11:55:24 +00001945 tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC);
Nico Huberd2d39932019-01-18 16:49:37 +01001946 msg_pdbg("0x%x: 0x%08x (UVSCC)\n", ICH9_REG_UVSCC, tmp);
Stefan Taunerf382e352011-11-08 11:55:24 +00001947 msg_pdbg("UVSCC: ");
Nico Huberd152fb92017-06-19 12:57:10 +02001948 prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, false);
Stefan Taunerf382e352011-11-08 11:55:24 +00001949 }
Stefan Tauner1e146392011-09-15 23:52:55 +00001950
Nico Huberd2d39932019-01-18 16:49:37 +01001951 switch (ich_gen) {
1952 case CHIPSET_ICH8:
1953 case CHIPSET_100_SERIES_SUNRISE_POINT:
1954 case CHIPSET_C620_SERIES_LEWISBURG:
1955 case CHIPSET_APOLLO_LAKE:
1956 break;
1957 default:
1958 tmp = mmio_readl(ich_spibar + ICH9_REG_FPB);
1959 msg_pdbg("0x%x: 0x%08x (FPB)\n", ICH9_REG_FPB, tmp);
1960 break;
1961 }
1962
Nico Huberd54e4f42017-03-23 23:45:47 +01001963 if (read_ich_descriptors_via_fdo(ich_gen, ich_spibar, &desc) == ICH_RET_OK)
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +00001964 prettyprint_ich_descriptors(ich_gen, &desc);
1965
Stefan Tauner50e7c602011-11-08 10:55:54 +00001966 /* If the descriptor is valid and indicates multiple
1967 * flash devices we need to use hwseq to be able to
1968 * access the second flash device.
1969 */
1970 if (ich_spi_mode == ich_auto && desc.content.NC != 0) {
1971 msg_pinfo("Enabling hardware sequencing due to "
1972 "multiple flash chips detected.\n");
1973 ich_spi_mode = ich_hwseq;
1974 }
Stefan Tauner1e146392011-09-15 23:52:55 +00001975 }
Stefan Tauner50e7c602011-11-08 10:55:54 +00001976
1977 if (ich_spi_mode == ich_auto && ichspi_lock &&
1978 ich_missing_opcodes()) {
1979 msg_pinfo("Enabling hardware sequencing because "
1980 "some important opcode is locked.\n");
1981 ich_spi_mode = ich_hwseq;
1982 }
1983
Nico Huber22f2dc52017-08-31 16:14:22 +02001984 if (ich_spi_mode == ich_auto && ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT) {
1985 msg_pdbg("Enabling hardware sequencing by default for 100 series PCH.\n");
1986 ich_spi_mode = ich_hwseq;
1987 }
1988
Nico Huberd2d39932019-01-18 16:49:37 +01001989 if (ich_spi_mode == ich_auto && ich_gen == CHIPSET_APOLLO_LAKE) {
1990 msg_pdbg("Enabling hardware sequencing by default for Apollo Lake.\n");
1991 ich_spi_mode = ich_hwseq;
1992 }
1993
Stefan Tauner50e7c602011-11-08 10:55:54 +00001994 if (ich_spi_mode == ich_hwseq) {
1995 if (!desc_valid) {
1996 msg_perr("Hardware sequencing was requested "
1997 "but the flash descriptor is not "
1998 "valid. Aborting.\n");
1999 return ERROR_FATAL;
2000 }
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +00002001
2002 int tmpi = getFCBA_component_density(ich_generation, &desc, 0);
2003 if (tmpi < 0) {
2004 msg_perr("Could not determine density of flash component %d.\n", 0);
2005 return ERROR_FATAL;
2006 }
2007 hwseq_data.size_comp0 = tmpi;
2008
2009 tmpi = getFCBA_component_density(ich_generation, &desc, 1);
2010 if (tmpi < 0) {
2011 msg_perr("Could not determine density of flash component %d.\n", 1);
2012 return ERROR_FATAL;
2013 }
2014 hwseq_data.size_comp1 = tmpi;
2015
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00002016 register_opaque_master(&opaque_master_ich_hwseq);
Stefan Tauner50e7c602011-11-08 10:55:54 +00002017 } else {
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00002018 register_spi_master(&spi_master_ich9);
Stefan Tauner50e7c602011-11-08 10:55:54 +00002019 }
Michael Karchera4448d92010-07-22 18:04:15 +00002020 break;
Michael Karchera4448d92010-07-22 18:04:15 +00002021 }
2022
Michael Karchera4448d92010-07-22 18:04:15 +00002023 return 0;
2024}
2025
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00002026static const struct spi_master spi_master_via = {
Michael Karcherb9dbe482011-05-11 17:07:07 +00002027 .max_data_read = 16,
2028 .max_data_write = 16,
2029 .command = ich_spi_send_command,
2030 .multicommand = ich_spi_send_multicommand,
2031 .read = default_spi_read,
2032 .write_256 = default_spi_write_256,
Nico Huber7bca1262012-06-15 22:28:12 +00002033 .write_aai = default_spi_write_aai,
Michael Karcherb9dbe482011-05-11 17:07:07 +00002034};
2035
Nico Huber560111e2017-04-26 12:27:17 +02002036int via_init_spi(uint32_t mmio_base)
Michael Karchera4448d92010-07-22 18:04:15 +00002037{
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00002038 int i;
Michael Karchera4448d92010-07-22 18:04:15 +00002039
Stefan Tauner7fb5aa02013-08-14 15:48:44 +00002040 ich_spibar = rphysmap("VIA SPI MMIO registers", mmio_base, 0x70);
2041 if (ich_spibar == ERROR_PTR)
2042 return ERROR_FATAL;
Helge Wagnerdd73d832012-08-24 23:03:46 +00002043 /* Do we really need no write enable? Like the LPC one at D17F0 0x40 */
Michael Karchera4448d92010-07-22 18:04:15 +00002044
Michael Karchera4448d92010-07-22 18:04:15 +00002045 /* Not sure if it speaks all these bus protocols. */
Nico Huber2e50cdc2018-09-23 20:20:26 +02002046 internal_buses_supported &= BUS_LPC | BUS_FWH;
Stefan Taunera8d838d2011-11-06 23:51:09 +00002047 ich_generation = CHIPSET_ICH7;
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00002048 register_spi_master(&spi_master_via);
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00002049
2050 msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0));
2051 msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2));
2052 msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(ich_spibar + 4));
2053 for (i = 0; i < 2; i++) {
2054 int offs;
2055 offs = 8 + (i * 8);
2056 msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs,
2057 mmio_readl(ich_spibar + offs), i);
2058 msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
2059 mmio_readl(ich_spibar + offs + 4), i);
2060 }
2061 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
2062 msg_pdbg("0x50: 0x%08x (BBAR)\n", ichspi_bbar);
2063 msg_pdbg("0x54: 0x%04x (PREOP)\n", mmio_readw(ich_spibar + 0x54));
2064 msg_pdbg("0x56: 0x%04x (OPTYPE)\n", mmio_readw(ich_spibar + 0x56));
2065 msg_pdbg("0x58: 0x%08x (OPMENU)\n", mmio_readl(ich_spibar + 0x58));
2066 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + 0x5c));
2067 for (i = 0; i < 3; i++) {
2068 int offs;
2069 offs = 0x60 + (i * 4);
2070 msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,
2071 mmio_readl(ich_spibar + offs), i);
2072 }
2073 msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n",
2074 mmio_readw(ich_spibar + 0x6c));
2075 if (mmio_readw(ich_spibar) & (1 << 15)) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00002076 msg_pwarn("Warning: SPI Configuration Lockdown activated.\n");
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00002077 ichspi_lock = 1;
2078 }
2079
Stefan Taunera8d838d2011-11-06 23:51:09 +00002080 ich_set_bbar(0);
Michael Karchera4448d92010-07-22 18:04:15 +00002081 ich_init_opcodes();
2082
2083 return 0;
2084}
2085
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00002086#endif