blob: cbc81b02f8db8a506c572646bff30a21da24ea06 [file] [log] [blame]
Dominik Geyerb46acba2008-05-16 12:55:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2008 Stefan Wildemann <stefan.wildemann@kontron.com>
5 * Copyright (C) 2008 Claus Gindhart <claus.gindhart@kontron.com>
6 * Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com>
Stefan Reinauera9424d52008-06-27 16:28:34 +00007 * Copyright (C) 2008 coresystems GmbH <info@coresystems.de>
Dominik Geyerb46acba2008-05-16 12:55:55 +00008 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 *
23 */
24
25/*
26 * This module is designed for supporting the devices
27 * ST M25P40
28 * ST M25P80
29 * ST M25P16
30 * ST M25P32 already tested
31 * ST M25P64
32 * AT 25DF321 already tested
33 *
34 */
35
36#include <stdio.h>
37#include <string.h>
38#include <stdint.h>
39#include <sys/mman.h>
40#include <pci/pci.h>
41#include "flash.h"
42#include "spi.h"
43
Stefan Reinauera9424d52008-06-27 16:28:34 +000044/* ICH9 controller register definition */
45#define ICH9_REG_FADDR 0x08 /* 32 Bits */
46#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */
47
48#define ICH9_REG_SSFS 0x90 /* 08 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +000049#define SSFS_SCIP 0x00000001
50#define SSFS_CDS 0x00000004
51#define SSFS_FCERR 0x00000008
52#define SSFS_AEL 0x00000010
Stefan Reinauera9424d52008-06-27 16:28:34 +000053
54#define ICH9_REG_SSFC 0x91 /* 24 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +000055#define SSFC_SCGO 0x00000200
56#define SSFC_ACS 0x00000400
57#define SSFC_SPOP 0x00000800
58#define SSFC_COP 0x00001000
59#define SSFC_DBC 0x00010000
60#define SSFC_DS 0x00400000
61#define SSFC_SME 0x00800000
62#define SSFC_SCF 0x01000000
63#define SSFC_SCF_20MHZ 0x00000000
64#define SSFC_SCF_33MHZ 0x01000000
Stefan Reinauera9424d52008-06-27 16:28:34 +000065
66#define ICH9_REG_PREOP 0x94 /* 16 Bits */
67#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */
68#define ICH9_REG_OPMENU 0x98 /* 64 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +000069
70// ICH9R SPI commands
71#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
72#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
73#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
74#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
75
Stefan Reinauera9424d52008-06-27 16:28:34 +000076// ICH7 registers
77#define ICH7_REG_SPIS 0x00 /* 16 Bits */
78#define SPIS_SCIP 0x00000001
79#define SPIS_CDS 0x00000004
80#define SPIS_FCERR 0x00000008
81
Rudolf Marek3fdbccf2008-06-30 21:38:30 +000082/* VIA SPI is compatible with ICH7, but maxdata
83 to transfer is 16 bytes.
84
85 DATA byte count on ICH7 is 8:13, on VIA 8:11
86
87 bit 12 is port select CS0 CS1
88 bit 13 is FAST READ enable
89 bit 7 is used with fast read and one shot controls CS de-assert?
90*/
91
Stefan Reinauera9424d52008-06-27 16:28:34 +000092#define ICH7_REG_SPIC 0x02 /* 16 Bits */
93#define SPIC_SCGO 0x0002
94#define SPIC_ACS 0x0004
95#define SPIC_SPOP 0x0008
Rudolf Marek3fdbccf2008-06-30 21:38:30 +000096#define SPIC_DS 0x4000
Stefan Reinauera9424d52008-06-27 16:28:34 +000097
98#define ICH7_REG_SPIA 0x04 /* 32 Bits */
99#define ICH7_REG_SPID0 0x08 /* 64 Bytes */
100#define ICH7_REG_PREOP 0x54 /* 16 Bits */
101#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */
102#define ICH7_REG_OPMENU 0x58 /* 64 Bits */
103
FENG yu ningc05a2952008-12-08 18:16:58 +0000104/* ICH SPI configuration lock-down. May be set during chipset enabling. */
105int ichspi_lock = 0;
106
Dominik Geyerb46acba2008-05-16 12:55:55 +0000107typedef struct _OPCODE {
108 uint8_t opcode; //This commands spi opcode
109 uint8_t spi_type; //This commands spi type
110 uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1
111} OPCODE;
112
113/* Opcode definition:
114 * Preop 1: Write Enable
115 * Preop 2: Write Status register enable
116 *
117 * OP 0: Write address
118 * OP 1: Read Address
119 * OP 2: ERASE block
120 * OP 3: Read Status register
121 * OP 4: Read ID
122 * OP 5: Write Status register
123 * OP 6: chip private (read JDEC id)
124 * OP 7: Chip erase
125 */
126typedef struct _OPCODES {
127 uint8_t preop[2];
128 OPCODE opcode[8];
129} OPCODES;
130
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000131static OPCODES *curopcodes = NULL;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000132
133/* HW access functions */
134static inline uint32_t REGREAD32(int X)
135{
136 volatile uint32_t regval;
Uwe Hermann394131e2008-10-18 21:14:13 +0000137 regval = *(volatile uint32_t *)((uint8_t *) spibar + X);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000138 return regval;
139}
140
141static inline uint16_t REGREAD16(int X)
142{
143 volatile uint16_t regval;
Uwe Hermann394131e2008-10-18 21:14:13 +0000144 regval = *(volatile uint16_t *)((uint8_t *) spibar + X);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000145 return regval;
146}
147
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000148#define REGWRITE32(X,Y) (*(uint32_t *)((uint8_t *)spibar+X)=Y)
149#define REGWRITE16(X,Y) (*(uint16_t *)((uint8_t *)spibar+X)=Y)
150#define REGWRITE8(X,Y) (*(uint8_t *)((uint8_t *)spibar+X)=Y)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000151
Dominik Geyerb46acba2008-05-16 12:55:55 +0000152/* Common SPI functions */
FENG yu ningc05a2952008-12-08 18:16:58 +0000153static inline int find_opcode(OPCODES *op, uint8_t opcode);
154static inline int find_preop(OPCODES *op, uint8_t preop);
155static int generate_opcodes(struct flashchip * flash, OPCODES * op);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000156static int program_opcodes(OPCODES * op);
FENG yu ningc05a2952008-12-08 18:16:58 +0000157int ich_check_opcodes(struct flashchip * flash);
Stefan Reinauer43119562008-11-02 19:51:50 +0000158static int run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000159 uint8_t datalength, uint8_t * data);
160static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000161 int offset, int maxdata);
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000162static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000163 int offset, int maxdata);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000164
Dominik Geyerb46acba2008-05-16 12:55:55 +0000165OPCODES O_ST_M25P = {
166 {
167 JEDEC_WREN,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000168 0},
Dominik Geyerb46acba2008-05-16 12:55:55 +0000169 {
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000170 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 1}, // Write Byte
171 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
172 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 1}, // Erase Sector
173 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
174 {JEDEC_RES, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Resume Deep Power-Down
175 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 1}, // Write Status Register
176 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
177 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 1}, // Bulk erase
178 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000179};
180
FENG yu ningc05a2952008-12-08 18:16:58 +0000181OPCODES O_EXISTING = {};
182
183static inline int find_opcode(OPCODES *op, uint8_t opcode)
184{
185 int a;
186
187 for (a = 0; a < 8; a++) {
188 if (op->opcode[a].opcode == opcode)
189 return a;
190 }
191
192 return -1;
193}
194
195static inline int find_preop(OPCODES *op, uint8_t preop)
196{
197 int a;
198
199 for (a = 0; a < 2; a++) {
200 if (op->preop[a] == preop)
201 return a;
202 }
203
204 return -1;
205}
206
207static int generate_opcodes(struct flashchip * flash, OPCODES * op)
208{
209 int a, b, i;
210 uint16_t preop, optype;
211 uint32_t opmenu[2];
212 struct preop_opcode_pair *pair;
213
214 if (op == NULL) {
215 printf_debug("\n%s: null OPCODES pointer!\n", __FUNCTION__);
216 return -1;
217 }
218
219 switch (flashbus) {
220 case BUS_TYPE_ICH7_SPI:
221 case BUS_TYPE_VIA_SPI:
222 preop = REGREAD16(ICH7_REG_PREOP);
223 optype = REGREAD16(ICH7_REG_OPTYPE);
224 opmenu[0] = REGREAD32(ICH7_REG_OPMENU);
225 opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4);
226 break;
227 case BUS_TYPE_ICH9_SPI:
228 preop = REGREAD16(ICH9_REG_PREOP);
229 optype = REGREAD16(ICH9_REG_OPTYPE);
230 opmenu[0] = REGREAD32(ICH9_REG_OPMENU);
231 opmenu[1] = REGREAD32(ICH9_REG_OPMENU + 4);
232 break;
233 default:
234 printf_debug("%s: unsupported chipset\n", __FUNCTION__);
235 return -1;
236 }
237
238 op->preop[0] = (uint8_t) preop;
239 op->preop[1] = (uint8_t) (preop >> 8);
240
241 for (a = 0; a < 8; a++) {
242 op->opcode[a].spi_type = (uint8_t) (optype & 0x3);
243 optype >>= 2;
244 }
245
246 for (a = 0; a < 4; a++) {
247 op->opcode[a].opcode = (uint8_t) (opmenu[0] & 0xff);
248 opmenu[0] >>= 8;
249 }
250
251 for (a = 4; a < 8; a++) {
252 op->opcode[a].opcode = (uint8_t) (opmenu[1] & 0xff);
253 opmenu[1] >>= 8;
254 }
255
256 /* atomic (link opcode with required pre-op) */
257 for (a = 4; a < 8; a++)
258 op->opcode[a].atomic = 0;
259
260 pair = flash->preop_opcode_pairs;
261 if (pair) {
262 for (i = 0; pair[i].opcode; i++) {
263 a = find_opcode(op, pair[i].opcode);
264 b = find_preop(op, pair[i].preop);
265 if ((a != -1) && (b != -1))
266 op->opcode[a].atomic = (uint8_t) ++b;
267 }
268 }
269
270 return 0;
271}
272
Dominik Geyerb46acba2008-05-16 12:55:55 +0000273int program_opcodes(OPCODES * op)
274{
275 uint8_t a;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000276 uint16_t preop, optype;
277 uint32_t opmenu[2];
Dominik Geyerb46acba2008-05-16 12:55:55 +0000278
279 /* Program Prefix Opcodes */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000280 preop = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000281 /* 0:7 Prefix Opcode 1 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000282 preop = (op->preop[0]);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000283 /* 8:16 Prefix Opcode 2 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000284 preop |= ((uint16_t) op->preop[1]) << 8;
Uwe Hermann394131e2008-10-18 21:14:13 +0000285
Stefan Reinauera9424d52008-06-27 16:28:34 +0000286 /* Program Opcode Types 0 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000287 optype = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000288 for (a = 0; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000289 optype |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000290 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000291
Stefan Reinauera9424d52008-06-27 16:28:34 +0000292 /* Program Allowable Opcodes 0 - 3 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000293 opmenu[0] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000294 for (a = 0; a < 4; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000295 opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000296 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000297
Dominik Geyerb46acba2008-05-16 12:55:55 +0000298 /*Program Allowable Opcodes 4 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000299 opmenu[1] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000300 for (a = 4; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000301 opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000302 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000303
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000304 switch (flashbus) {
Uwe Hermann394131e2008-10-18 21:14:13 +0000305 case BUS_TYPE_ICH7_SPI:
306 case BUS_TYPE_VIA_SPI:
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000307 REGWRITE16(ICH7_REG_PREOP, preop);
308 REGWRITE16(ICH7_REG_OPTYPE, optype);
309 REGWRITE32(ICH7_REG_OPMENU, opmenu[0]);
310 REGWRITE32(ICH7_REG_OPMENU + 4, opmenu[1]);
311 break;
312 case BUS_TYPE_ICH9_SPI:
313 REGWRITE16(ICH9_REG_PREOP, preop);
314 REGWRITE16(ICH9_REG_OPTYPE, optype);
315 REGWRITE32(ICH9_REG_OPMENU, opmenu[0]);
316 REGWRITE32(ICH9_REG_OPMENU + 4, opmenu[1]);
317 break;
318 default:
319 printf_debug("%s: unsupported chipset\n", __FUNCTION__);
320 return -1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000321 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000322
323 return 0;
324}
325
FENG yu ningc05a2952008-12-08 18:16:58 +0000326/* This function generates OPCODES from or programs OPCODES to the chipset
327 * according to its SPI configuration lock.
328 *
329 * It should be called in the ICH7/ICH9/VIA part of each operation driver(i.e.
330 * probe, read, erase, write, etc.) before any command is sent.
331 */
332int ich_check_opcodes(struct flashchip * flash)
333{
334 int rc = 0;
335 OPCODES *curopcodes_done;
336
337 if (curopcodes)
338 return 0;
339
340 if (ichspi_lock) {
341 printf_debug("Generating OPCODES... ");
342 curopcodes_done = &O_EXISTING;
343 rc = generate_opcodes(flash, curopcodes_done);
344 } else {
345 printf_debug("Programming OPCODES... ");
346 curopcodes_done = &O_ST_M25P;
347 rc = program_opcodes(curopcodes_done);
348 }
349
350 if (rc) {
351 curopcodes = NULL;
352 printf_debug("failed\n");
353 return 1;
354 } else {
355 curopcodes = curopcodes_done;
356 printf_debug("done\n");
357 return 0;
358 }
359}
360
Stefan Reinauer43119562008-11-02 19:51:50 +0000361static int ich7_run_opcode(OPCODE op, uint32_t offset,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000362 uint8_t datalength, uint8_t * data, int maxdata)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000363{
364 int write_cmd = 0;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000365 int timeout;
Peter Stuge7e2c0792008-06-29 01:30:41 +0000366 uint32_t temp32 = 0;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000367 uint16_t temp16;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000368 uint32_t a;
Stefan Reinauer43119562008-11-02 19:51:50 +0000369 uint64_t opmenu;
370 int opcode_index;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000371
372 /* Is it a write command? */
373 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
374 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
375 write_cmd = 1;
376 }
377
378 /* Programm Offset in Flash into FADDR */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000379 REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000380
381 /* Program data into FDATA0 to N */
382 if (write_cmd && (datalength != 0)) {
383 temp32 = 0;
384 for (a = 0; a < datalength; a++) {
385 if ((a % 4) == 0) {
386 temp32 = 0;
387 }
388
389 temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8);
390
391 if ((a % 4) == 3) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000392 REGWRITE32(ICH7_REG_SPID0 + (a - (a % 4)),
393 temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000394 }
395 }
396 if (((a - 1) % 4) != 3) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000397 REGWRITE32(ICH7_REG_SPID0 +
398 ((a - 1) - ((a - 1) % 4)), temp32);
399 }
400
401 }
402
403 /* Assemble SPIS */
404 temp16 = 0;
405 /* clear error status registers */
406 temp16 |= (SPIS_CDS + SPIS_FCERR);
407 REGWRITE16(ICH7_REG_SPIS, temp16);
408
409 /* Assemble SPIC */
410 temp16 = 0;
411
412 if (datalength != 0) {
413 temp16 |= SPIC_DS;
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000414 temp16 |= ((uint32_t) ((datalength - 1) & (maxdata - 1))) << 8;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000415 }
416
417 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000418 opmenu = REGREAD32(ICH7_REG_OPMENU);
419 opmenu |= ((uint64_t)REGREAD32(ICH7_REG_OPMENU + 4)) << 32;
420
421 for (opcode_index=0; opcode_index<8; opcode_index++) {
422 if((opmenu & 0xff) == op.opcode) {
423 break;
424 }
425 opmenu >>= 8;
426 }
427 if (opcode_index == 8) {
428 printf_debug("Opcode %x not found.\n", op.opcode);
429 return 1;
430 }
431 temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000432
433 /* Handle Atomic */
434 if (op.atomic != 0) {
435 /* Select atomic command */
436 temp16 |= SPIC_ACS;
Carl-Daniel Hailfinger738fdff2008-11-18 00:43:14 +0000437 /* Select prefix opcode */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000438 if ((op.atomic - 1) == 1) {
439 /*Select prefix opcode 2 */
440 temp16 |= SPIC_SPOP;
441 }
442 }
443
444 /* Start */
445 temp16 |= SPIC_SCGO;
446
447 /* write it */
448 REGWRITE16(ICH7_REG_SPIC, temp16);
449
450 /* wait for cycle complete */
451 timeout = 1000 * 60; // 60s is a looong timeout.
452 while (((REGREAD16(ICH7_REG_SPIS) & SPIS_CDS) == 0) && --timeout) {
453 myusec_delay(1000);
454 }
455 if (!timeout) {
456 printf_debug("timeout\n");
457 }
458
459 if ((REGREAD16(ICH7_REG_SPIS) & SPIS_FCERR) != 0) {
460 printf_debug("Transaction error!\n");
461 return 1;
462 }
463
464 if ((!write_cmd) && (datalength != 0)) {
465 for (a = 0; a < datalength; a++) {
466 if ((a % 4) == 0) {
467 temp32 = REGREAD32(ICH7_REG_SPID0 + (a));
468 }
469
470 data[a] =
471 (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8)))
472 >> ((a % 4) * 8);
473 }
474 }
475
476 return 0;
477}
478
Stefan Reinauer43119562008-11-02 19:51:50 +0000479static int ich9_run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000480 uint8_t datalength, uint8_t * data)
481{
482 int write_cmd = 0;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000483 int timeout;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000484 uint32_t temp32;
485 uint32_t a;
Stefan Reinauer43119562008-11-02 19:51:50 +0000486 uint64_t opmenu;
487 int opcode_index;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000488
489 /* Is it a write command? */
490 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
491 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
492 write_cmd = 1;
493 }
494
495 /* Programm Offset in Flash into FADDR */
496 REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */
497
498 /* Program data into FDATA0 to N */
499 if (write_cmd && (datalength != 0)) {
500 temp32 = 0;
501 for (a = 0; a < datalength; a++) {
502 if ((a % 4) == 0) {
503 temp32 = 0;
504 }
505
506 temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8);
507
508 if ((a % 4) == 3) {
509 REGWRITE32(ICH9_REG_FDATA0 + (a - (a % 4)),
510 temp32);
511 }
512 }
513 if (((a - 1) % 4) != 3) {
514 REGWRITE32(ICH9_REG_FDATA0 +
515 ((a - 1) - ((a - 1) % 4)), temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000516 }
517
518 }
519
520 /* Assemble SSFS + SSFC */
521 temp32 = 0;
522
523 /* clear error status registers */
524 temp32 |= (SSFS_CDS + SSFS_FCERR);
525 /* USE 20 MhZ */
526 temp32 |= SSFC_SCF_20MHZ;
527
528 if (datalength != 0) {
529 uint32_t datatemp;
530 temp32 |= SSFC_DS;
531 datatemp = ((uint32_t) ((datalength - 1) & 0x3f)) << (8 + 8);
532 temp32 |= datatemp;
533 }
534
535 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000536 opmenu = REGREAD32(ICH9_REG_OPMENU);
537 opmenu |= ((uint64_t)REGREAD32(ICH9_REG_OPMENU + 4)) << 32;
538
539 for (opcode_index=0; opcode_index<8; opcode_index++) {
540 if((opmenu & 0xff) == op.opcode) {
541 break;
542 }
543 opmenu >>= 8;
544 }
545 if (opcode_index == 8) {
546 printf_debug("Opcode %x not found.\n", op.opcode);
547 return 1;
548 }
549 temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000550
551 /* Handle Atomic */
552 if (op.atomic != 0) {
553 /* Select atomic command */
554 temp32 |= SSFC_ACS;
555 /* Selct prefix opcode */
556 if ((op.atomic - 1) == 1) {
557 /*Select prefix opcode 2 */
558 temp32 |= SSFC_SPOP;
559 }
560 }
561
562 /* Start */
563 temp32 |= SSFC_SCGO;
564
565 /* write it */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000566 REGWRITE32(ICH9_REG_SSFS, temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000567
568 /*wait for cycle complete */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000569 timeout = 1000 * 60; // 60s is a looong timeout.
570 while (((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) && --timeout) {
571 myusec_delay(1000);
572 }
573 if (!timeout) {
574 printf_debug("timeout\n");
Dominik Geyerb46acba2008-05-16 12:55:55 +0000575 }
576
Stefan Reinauera9424d52008-06-27 16:28:34 +0000577 if ((REGREAD32(ICH9_REG_SSFS) & SSFS_FCERR) != 0) {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000578 printf_debug("Transaction error!\n");
579 return 1;
580 }
581
582 if ((!write_cmd) && (datalength != 0)) {
583 for (a = 0; a < datalength; a++) {
584 if ((a % 4) == 0) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000585 temp32 = REGREAD32(ICH9_REG_FDATA0 + (a));
Dominik Geyerb46acba2008-05-16 12:55:55 +0000586 }
587
588 data[a] =
Stefan Reinauera9424d52008-06-27 16:28:34 +0000589 (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8)))
590 >> ((a % 4) * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000591 }
592 }
593
594 return 0;
595}
596
Stefan Reinauer43119562008-11-02 19:51:50 +0000597static int run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000598 uint8_t datalength, uint8_t * data)
599{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000600 switch (flashbus) {
601 case BUS_TYPE_VIA_SPI:
Stefan Reinauer43119562008-11-02 19:51:50 +0000602 return ich7_run_opcode(op, offset, datalength, data, 16);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000603 case BUS_TYPE_ICH7_SPI:
Stefan Reinauer43119562008-11-02 19:51:50 +0000604 return ich7_run_opcode(op, offset, datalength, data, 64);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000605 case BUS_TYPE_ICH9_SPI:
Stefan Reinauer43119562008-11-02 19:51:50 +0000606 return ich9_run_opcode(op, offset, datalength, data);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000607 default:
608 printf_debug("%s: unsupported chipset\n", __FUNCTION__);
609 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000610
611 /* If we ever get here, something really weird happened */
612 return -1;
613}
614
Uwe Hermann394131e2008-10-18 21:14:13 +0000615static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int offset,
616 int maxdata)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000617{
618 int page_size = flash->page_size;
619 uint32_t remaining = flash->page_size;
620 int a;
621
Stefan Reinauera9424d52008-06-27 16:28:34 +0000622 printf_debug("ich_spi_read_page: offset=%d, number=%d, buf=%p\n",
623 offset, page_size, buf);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000624
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000625 for (a = 0; a < page_size; a += maxdata) {
626 if (remaining < maxdata) {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000627
Carl-Daniel Hailfinger738fdff2008-11-18 00:43:14 +0000628 if (spi_nbyte_read(offset + (page_size - remaining),
629 &buf[page_size - remaining], remaining)) {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000630 printf_debug("Error reading");
631 return 1;
632 }
633 remaining = 0;
634 } else {
Carl-Daniel Hailfinger738fdff2008-11-18 00:43:14 +0000635 if (spi_nbyte_read(offset + (page_size - remaining),
636 &buf[page_size - remaining], maxdata)) {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000637 printf_debug("Error reading");
638 return 1;
639 }
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000640 remaining -= maxdata;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000641 }
642 }
643
644 return 0;
645}
646
647static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000648 int offset, int maxdata)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000649{
650 int page_size = flash->page_size;
651 uint32_t remaining = page_size;
652 int a;
653
Stefan Reinauera9424d52008-06-27 16:28:34 +0000654 printf_debug("ich_spi_write_page: offset=%d, number=%d, buf=%p\n",
655 offset, page_size, bytes);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000656
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000657 for (a = 0; a < page_size; a += maxdata) {
658 if (remaining < maxdata) {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000659 if (run_opcode
Stefan Reinauer43119562008-11-02 19:51:50 +0000660 (curopcodes->opcode[0],
Stefan Reinauera9424d52008-06-27 16:28:34 +0000661 offset + (page_size - remaining), remaining,
Dominik Geyerb46acba2008-05-16 12:55:55 +0000662 &bytes[page_size - remaining]) != 0) {
663 printf_debug("Error writing");
664 return 1;
665 }
666 remaining = 0;
667 } else {
668 if (run_opcode
Stefan Reinauer43119562008-11-02 19:51:50 +0000669 (curopcodes->opcode[0],
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000670 offset + (page_size - remaining), maxdata,
Dominik Geyerb46acba2008-05-16 12:55:55 +0000671 &bytes[page_size - remaining]) != 0) {
672 printf_debug("Error writing");
673 return 1;
674 }
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000675 remaining -= maxdata;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000676 }
677 }
678
679 return 0;
680}
681
Dominik Geyerb46acba2008-05-16 12:55:55 +0000682int ich_spi_read(struct flashchip *flash, uint8_t * buf)
683{
684 int i, rc = 0;
685 int total_size = flash->total_size * 1024;
686 int page_size = flash->page_size;
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000687 int maxdata = 64;
688
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000689 if (flashbus == BUS_TYPE_VIA_SPI) {
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000690 maxdata = 16;
691 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000692
693 for (i = 0; (i < total_size / page_size) && (rc == 0); i++) {
694 rc = ich_spi_read_page(flash, (void *)(buf + i * page_size),
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000695 i * page_size, maxdata);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000696 }
697
698 return rc;
699}
700
Dominik Geyerb46acba2008-05-16 12:55:55 +0000701int ich_spi_write(struct flashchip *flash, uint8_t * buf)
702{
703 int i, j, rc = 0;
704 int total_size = flash->total_size * 1024;
705 int page_size = flash->page_size;
706 int erase_size = 64 * 1024;
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000707 int maxdata = 64;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000708
709 spi_disable_blockprotect();
710
711 printf("Programming page: \n");
712
713 for (i = 0; i < total_size / erase_size; i++) {
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000714 /* FIMXE: call the chip-specific spi_block_erase_XX instead.
715 * For this, we need to add a block erase function to
716 * struct flashchip.
717 */
718 rc = spi_block_erase_d8(flash, i * erase_size);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000719 if (rc) {
720 printf("Error erasing block at 0x%x\n", i);
721 break;
722 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000723
Peter Stuge6a214162008-07-07 05:14:06 +0000724 if (flashbus == BUS_TYPE_VIA_SPI)
725 maxdata = 16;
726
Dominik Geyerb46acba2008-05-16 12:55:55 +0000727 for (j = 0; j < erase_size / page_size; j++) {
Uwe Hermann394131e2008-10-18 21:14:13 +0000728 ich_spi_write_page(flash,
729 (void *)(buf + (i * erase_size) + (j * page_size)),
730 (i * erase_size) + (j * page_size), maxdata);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000731 }
732 }
733
734 printf("\n");
735
736 return rc;
737}
738
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000739int ich_spi_command(unsigned int writecnt, unsigned int readcnt,
740 const unsigned char *writearr, unsigned char *readarr)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000741{
742 int a;
743 int opcode_index = -1;
744 const unsigned char cmd = *writearr;
745 OPCODE *opcode;
746 uint32_t addr = 0;
747 uint8_t *data;
748 int count;
749
750 /* program opcodes if not already done */
751 if (curopcodes == NULL) {
Carl-Daniel Hailfinger10693352008-06-29 10:57:13 +0000752 printf_debug("Programming OPCODES... ");
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000753 curopcodes = &O_ST_M25P;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000754 program_opcodes(curopcodes);
Carl-Daniel Hailfinger10693352008-06-29 10:57:13 +0000755 printf_debug("done\n");
Dominik Geyerb46acba2008-05-16 12:55:55 +0000756 }
757
758 /* find cmd in opcodes-table */
759 for (a = 0; a < 8; a++) {
760 if ((curopcodes->opcode[a]).opcode == cmd) {
761 opcode_index = a;
762 break;
763 }
764 }
765
766 /* unknown / not programmed command */
767 if (opcode_index == -1) {
768 printf_debug("Invalid OPCODE 0x%02x\n", cmd);
769 return 1;
770 }
771
772 opcode = &(curopcodes->opcode[opcode_index]);
773
774 /* if opcode-type requires an address */
775 if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS ||
776 opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000777 addr = (writearr[1] << 16) |
778 (writearr[2] << 8) | (writearr[3] << 0);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000779 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000780
Dominik Geyerb46acba2008-05-16 12:55:55 +0000781 /* translate read/write array/count */
782 if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000783 data = (uint8_t *) (writearr + 1);
784 count = writecnt - 1;
785 } else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
786 data = (uint8_t *) (writearr + 4);
787 count = writecnt - 4;
788 } else {
789 data = (uint8_t *) readarr;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000790 count = readcnt;
791 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000792
Stefan Reinauer43119562008-11-02 19:51:50 +0000793 if (run_opcode(*opcode, addr, count, data) != 0) {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000794 printf_debug("run OPCODE 0x%02x failed\n", opcode->opcode);
795 return 1;
796 }
797
798 return 0;
799}