Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the flashrom project. |
| 3 | * |
| 4 | * Copyright (C) 2008 Stefan Wildemann <stefan.wildemann@kontron.com> |
| 5 | * Copyright (C) 2008 Claus Gindhart <claus.gindhart@kontron.com> |
| 6 | * Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com> |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 7 | * Copyright (C) 2008 coresystems GmbH <info@coresystems.de> |
Carl-Daniel Hailfinger | 5824fbf | 2010-05-21 23:09:42 +0000 | [diff] [blame] | 8 | * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; either version 2 of the License, or |
| 13 | * (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 23 | */ |
| 24 | |
| 25 | /* |
| 26 | * This module is designed for supporting the devices |
| 27 | * ST M25P40 |
| 28 | * ST M25P80 |
| 29 | * ST M25P16 |
| 30 | * ST M25P32 already tested |
| 31 | * ST M25P64 |
| 32 | * AT 25DF321 already tested |
Helge Wagner | 738e252 | 2010-10-05 22:06:05 +0000 | [diff] [blame] | 33 | * ... and many more SPI flash devices |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 34 | * |
| 35 | */ |
| 36 | |
Carl-Daniel Hailfinger | cceafa2 | 2010-05-26 01:45:41 +0000 | [diff] [blame] | 37 | #if defined(__i386__) || defined(__x86_64__) |
| 38 | |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 39 | #include <string.h> |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 40 | #include "flash.h" |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 41 | #include "chipdrivers.h" |
Carl-Daniel Hailfinger | 5b997c3 | 2010-07-27 22:41:39 +0000 | [diff] [blame] | 42 | #include "programmer.h" |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 43 | #include "spi.h" |
| 44 | |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 45 | /* ICH9 controller register definition */ |
| 46 | #define ICH9_REG_FADDR 0x08 /* 32 Bits */ |
| 47 | #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ |
| 48 | |
| 49 | #define ICH9_REG_SSFS 0x90 /* 08 Bits */ |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 50 | #define SSFS_SCIP 0x00000001 |
| 51 | #define SSFS_CDS 0x00000004 |
| 52 | #define SSFS_FCERR 0x00000008 |
| 53 | #define SSFS_AEL 0x00000010 |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 54 | #define SSFS_RESERVED_MASK 0x000000e2 |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 55 | |
| 56 | #define ICH9_REG_SSFC 0x91 /* 24 Bits */ |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 57 | #define SSFC_SCGO 0x00000200 |
| 58 | #define SSFC_ACS 0x00000400 |
| 59 | #define SSFC_SPOP 0x00000800 |
| 60 | #define SSFC_COP 0x00001000 |
| 61 | #define SSFC_DBC 0x00010000 |
| 62 | #define SSFC_DS 0x00400000 |
| 63 | #define SSFC_SME 0x00800000 |
| 64 | #define SSFC_SCF 0x01000000 |
| 65 | #define SSFC_SCF_20MHZ 0x00000000 |
| 66 | #define SSFC_SCF_33MHZ 0x01000000 |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 67 | #define SSFC_RESERVED_MASK 0xf8008100 |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 68 | |
| 69 | #define ICH9_REG_PREOP 0x94 /* 16 Bits */ |
| 70 | #define ICH9_REG_OPTYPE 0x96 /* 16 Bits */ |
| 71 | #define ICH9_REG_OPMENU 0x98 /* 64 Bits */ |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 72 | |
| 73 | // ICH9R SPI commands |
| 74 | #define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0 |
| 75 | #define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1 |
| 76 | #define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2 |
| 77 | #define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3 |
| 78 | |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 79 | // ICH7 registers |
| 80 | #define ICH7_REG_SPIS 0x00 /* 16 Bits */ |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 81 | #define SPIS_SCIP 0x0001 |
| 82 | #define SPIS_GRANT 0x0002 |
| 83 | #define SPIS_CDS 0x0004 |
| 84 | #define SPIS_FCERR 0x0008 |
| 85 | #define SPIS_RESERVED_MASK 0x7ff0 |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 86 | |
Rudolf Marek | 3fdbccf | 2008-06-30 21:38:30 +0000 | [diff] [blame] | 87 | /* VIA SPI is compatible with ICH7, but maxdata |
| 88 | to transfer is 16 bytes. |
| 89 | |
| 90 | DATA byte count on ICH7 is 8:13, on VIA 8:11 |
| 91 | |
| 92 | bit 12 is port select CS0 CS1 |
| 93 | bit 13 is FAST READ enable |
| 94 | bit 7 is used with fast read and one shot controls CS de-assert? |
| 95 | */ |
| 96 | |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 97 | #define ICH7_REG_SPIC 0x02 /* 16 Bits */ |
| 98 | #define SPIC_SCGO 0x0002 |
| 99 | #define SPIC_ACS 0x0004 |
| 100 | #define SPIC_SPOP 0x0008 |
Rudolf Marek | 3fdbccf | 2008-06-30 21:38:30 +0000 | [diff] [blame] | 101 | #define SPIC_DS 0x4000 |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 102 | |
| 103 | #define ICH7_REG_SPIA 0x04 /* 32 Bits */ |
| 104 | #define ICH7_REG_SPID0 0x08 /* 64 Bytes */ |
| 105 | #define ICH7_REG_PREOP 0x54 /* 16 Bits */ |
| 106 | #define ICH7_REG_OPTYPE 0x56 /* 16 Bits */ |
| 107 | #define ICH7_REG_OPMENU 0x58 /* 64 Bits */ |
| 108 | |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 109 | /* ICH SPI configuration lock-down. May be set during chipset enabling. */ |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 110 | static int ichspi_lock = 0; |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 111 | |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 112 | uint32_t ichspi_bbar = 0; |
| 113 | |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 114 | static void *ich_spibar = NULL; |
Carl-Daniel Hailfinger | ad3cc55 | 2010-07-03 11:02:10 +0000 | [diff] [blame] | 115 | |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 116 | typedef struct _OPCODE { |
| 117 | uint8_t opcode; //This commands spi opcode |
| 118 | uint8_t spi_type; //This commands spi type |
| 119 | uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1 |
| 120 | } OPCODE; |
| 121 | |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 122 | /* Suggested opcode definition: |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 123 | * Preop 1: Write Enable |
| 124 | * Preop 2: Write Status register enable |
| 125 | * |
| 126 | * OP 0: Write address |
| 127 | * OP 1: Read Address |
| 128 | * OP 2: ERASE block |
| 129 | * OP 3: Read Status register |
| 130 | * OP 4: Read ID |
| 131 | * OP 5: Write Status register |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 132 | * OP 6: chip private (read JEDEC id) |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 133 | * OP 7: Chip erase |
| 134 | */ |
| 135 | typedef struct _OPCODES { |
| 136 | uint8_t preop[2]; |
| 137 | OPCODE opcode[8]; |
| 138 | } OPCODES; |
| 139 | |
Stefan Reinauer | 325b5d4 | 2008-06-27 15:18:20 +0000 | [diff] [blame] | 140 | static OPCODES *curopcodes = NULL; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 141 | |
| 142 | /* HW access functions */ |
Uwe Hermann | 09e04f7 | 2009-05-16 22:36:00 +0000 | [diff] [blame] | 143 | static uint32_t REGREAD32(int X) |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 144 | { |
Carl-Daniel Hailfinger | ad3cc55 | 2010-07-03 11:02:10 +0000 | [diff] [blame] | 145 | return mmio_readl(ich_spibar + X); |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 146 | } |
| 147 | |
Uwe Hermann | 09e04f7 | 2009-05-16 22:36:00 +0000 | [diff] [blame] | 148 | static uint16_t REGREAD16(int X) |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 149 | { |
Carl-Daniel Hailfinger | ad3cc55 | 2010-07-03 11:02:10 +0000 | [diff] [blame] | 150 | return mmio_readw(ich_spibar + X); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 151 | } |
| 152 | |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 153 | static uint16_t REGREAD8(int X) |
| 154 | { |
| 155 | return mmio_readb(ich_spibar + X); |
| 156 | } |
| 157 | |
Carl-Daniel Hailfinger | ad3cc55 | 2010-07-03 11:02:10 +0000 | [diff] [blame] | 158 | #define REGWRITE32(X,Y) mmio_writel(Y, ich_spibar+X) |
| 159 | #define REGWRITE16(X,Y) mmio_writew(Y, ich_spibar+X) |
| 160 | #define REGWRITE8(X,Y) mmio_writeb(Y, ich_spibar+X) |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 161 | |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 162 | /* Common SPI functions */ |
Uwe Hermann | 09e04f7 | 2009-05-16 22:36:00 +0000 | [diff] [blame] | 163 | static int find_opcode(OPCODES *op, uint8_t opcode); |
| 164 | static int find_preop(OPCODES *op, uint8_t preop); |
FENG yu ning | f041e9b | 2008-12-15 02:32:11 +0000 | [diff] [blame] | 165 | static int generate_opcodes(OPCODES * op); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 166 | static int program_opcodes(OPCODES * op); |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 167 | static int run_opcode(OPCODE op, uint32_t offset, |
Stefan Reinauer | 325b5d4 | 2008-06-27 15:18:20 +0000 | [diff] [blame] | 168 | uint8_t datalength, uint8_t * data); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 169 | |
FENG yu ning | f041e9b | 2008-12-15 02:32:11 +0000 | [diff] [blame] | 170 | /* for pairing opcodes with their required preop */ |
| 171 | struct preop_opcode_pair { |
| 172 | uint8_t preop; |
| 173 | uint8_t opcode; |
| 174 | }; |
| 175 | |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 176 | /* List of opcodes which need preopcodes and matching preopcodes. Unused. */ |
Carl-Daniel Hailfinger | ad3cc55 | 2010-07-03 11:02:10 +0000 | [diff] [blame] | 177 | const struct preop_opcode_pair pops[] = { |
FENG yu ning | f041e9b | 2008-12-15 02:32:11 +0000 | [diff] [blame] | 178 | {JEDEC_WREN, JEDEC_BYTE_PROGRAM}, |
| 179 | {JEDEC_WREN, JEDEC_SE}, /* sector erase */ |
| 180 | {JEDEC_WREN, JEDEC_BE_52}, /* block erase */ |
| 181 | {JEDEC_WREN, JEDEC_BE_D8}, /* block erase */ |
| 182 | {JEDEC_WREN, JEDEC_CE_60}, /* chip erase */ |
| 183 | {JEDEC_WREN, JEDEC_CE_C7}, /* chip erase */ |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 184 | /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */ |
| 185 | {JEDEC_WREN, JEDEC_WRSR}, |
FENG yu ning | f041e9b | 2008-12-15 02:32:11 +0000 | [diff] [blame] | 186 | {JEDEC_EWSR, JEDEC_WRSR}, |
| 187 | {0,} |
| 188 | }; |
| 189 | |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 190 | /* Reasonable default configuration. Needs ad-hoc modifications if we |
| 191 | * encounter unlisted opcodes. Fun. |
| 192 | */ |
Carl-Daniel Hailfinger | ad3cc55 | 2010-07-03 11:02:10 +0000 | [diff] [blame] | 193 | static OPCODES O_ST_M25P = { |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 194 | { |
| 195 | JEDEC_WREN, |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 196 | JEDEC_EWSR, |
| 197 | }, |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 198 | { |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 199 | {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte |
Stefan Reinauer | 325b5d4 | 2008-06-27 15:18:20 +0000 | [diff] [blame] | 200 | {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 201 | {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector |
Stefan Reinauer | 325b5d4 | 2008-06-27 15:18:20 +0000 | [diff] [blame] | 202 | {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg |
Carl-Daniel Hailfinger | 15aa7c6 | 2009-05-26 21:25:08 +0000 | [diff] [blame] | 203 | {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 204 | {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register |
Stefan Reinauer | 325b5d4 | 2008-06-27 15:18:20 +0000 | [diff] [blame] | 205 | {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 206 | {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase |
| 207 | } |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 208 | }; |
| 209 | |
Helge Wagner | 738e252 | 2010-10-05 22:06:05 +0000 | [diff] [blame] | 210 | /* List of opcodes with their corresponding spi_type |
| 211 | * It is used to reprogram the chipset OPCODE table on-the-fly if an opcode |
| 212 | * is needed which is currently not in the chipset OPCODE table |
| 213 | */ |
| 214 | static OPCODE POSSIBLE_OPCODES[] = { |
| 215 | {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte |
| 216 | {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data |
| 217 | {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector |
| 218 | {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg |
| 219 | {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature |
| 220 | {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register |
| 221 | {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID |
| 222 | {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase |
| 223 | {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Sector erase |
| 224 | {JEDEC_BE_52, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Block erase |
| 225 | {JEDEC_AAI_WORD_PROGRAM, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Auto Address Increment |
| 226 | }; |
| 227 | |
Carl-Daniel Hailfinger | ad3cc55 | 2010-07-03 11:02:10 +0000 | [diff] [blame] | 228 | static OPCODES O_EXISTING = {}; |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 229 | |
Helge Wagner | 738e252 | 2010-10-05 22:06:05 +0000 | [diff] [blame] | 230 | static uint8_t lookup_spi_type(uint8_t opcode) |
| 231 | { |
| 232 | int a; |
| 233 | |
| 234 | for (a = 0; a < sizeof(POSSIBLE_OPCODES)/sizeof(POSSIBLE_OPCODES[0]); a++) { |
| 235 | if (POSSIBLE_OPCODES[a].opcode == opcode) |
| 236 | return POSSIBLE_OPCODES[a].spi_type; |
| 237 | } |
| 238 | |
| 239 | return 0xFF; |
| 240 | } |
| 241 | |
| 242 | static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt) |
| 243 | { |
| 244 | uint8_t spi_type; |
| 245 | |
| 246 | spi_type = lookup_spi_type(opcode); |
| 247 | if (spi_type > 3) { |
| 248 | /* Try to guess spi type from read/write sizes. |
| 249 | * The following valid writecnt/readcnt combinations exist: |
| 250 | * writecnt = 4, readcnt >= 0 |
| 251 | * writecnt = 1, readcnt >= 0 |
| 252 | * writecnt >= 4, readcnt = 0 |
| 253 | * writecnt >= 1, readcnt = 0 |
| 254 | * writecnt >= 1 is guaranteed for all commands. |
| 255 | */ |
| 256 | if (readcnt == 0) |
| 257 | /* if readcnt=0 and writecount >= 4, we don't know if it is WRITE_NO_ADDRESS |
| 258 | * or WRITE_WITH_ADDRESS. But if we use WRITE_NO_ADDRESS and the first 3 data |
| 259 | * bytes are actual the address, they go to the bus anyhow |
| 260 | */ |
| 261 | spi_type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; |
| 262 | else if (writecnt == 1) // and readcnt is > 0 |
| 263 | spi_type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; |
| 264 | else if (writecnt == 4) // and readcnt is > 0 |
| 265 | spi_type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; |
| 266 | // else we have an invalid case, will be handled below |
| 267 | } |
| 268 | if (spi_type <= 3) { |
| 269 | int oppos=2; // use original JEDEC_BE_D8 offset |
| 270 | curopcodes->opcode[oppos].opcode = opcode; |
| 271 | curopcodes->opcode[oppos].spi_type = spi_type; |
| 272 | program_opcodes(curopcodes); |
| 273 | oppos = find_opcode(curopcodes, opcode); |
| 274 | msg_pdbg ("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos); |
| 275 | return oppos; |
| 276 | } |
| 277 | return -1; |
| 278 | } |
| 279 | |
Uwe Hermann | 09e04f7 | 2009-05-16 22:36:00 +0000 | [diff] [blame] | 280 | static int find_opcode(OPCODES *op, uint8_t opcode) |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 281 | { |
| 282 | int a; |
| 283 | |
| 284 | for (a = 0; a < 8; a++) { |
| 285 | if (op->opcode[a].opcode == opcode) |
| 286 | return a; |
| 287 | } |
| 288 | |
| 289 | return -1; |
| 290 | } |
| 291 | |
Uwe Hermann | 09e04f7 | 2009-05-16 22:36:00 +0000 | [diff] [blame] | 292 | static int find_preop(OPCODES *op, uint8_t preop) |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 293 | { |
| 294 | int a; |
| 295 | |
| 296 | for (a = 0; a < 2; a++) { |
| 297 | if (op->preop[a] == preop) |
| 298 | return a; |
| 299 | } |
| 300 | |
| 301 | return -1; |
| 302 | } |
| 303 | |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 304 | /* Create a struct OPCODES based on what we find in the locked down chipset. */ |
FENG yu ning | f041e9b | 2008-12-15 02:32:11 +0000 | [diff] [blame] | 305 | static int generate_opcodes(OPCODES * op) |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 306 | { |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 307 | int a; |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 308 | uint16_t preop, optype; |
| 309 | uint32_t opmenu[2]; |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 310 | |
| 311 | if (op == NULL) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 312 | msg_perr("\n%s: null OPCODES pointer!\n", __func__); |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 313 | return -1; |
| 314 | } |
| 315 | |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 316 | switch (spi_controller) { |
| 317 | case SPI_CONTROLLER_ICH7: |
| 318 | case SPI_CONTROLLER_VIA: |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 319 | preop = REGREAD16(ICH7_REG_PREOP); |
| 320 | optype = REGREAD16(ICH7_REG_OPTYPE); |
| 321 | opmenu[0] = REGREAD32(ICH7_REG_OPMENU); |
| 322 | opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4); |
| 323 | break; |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 324 | case SPI_CONTROLLER_ICH9: |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 325 | preop = REGREAD16(ICH9_REG_PREOP); |
| 326 | optype = REGREAD16(ICH9_REG_OPTYPE); |
| 327 | opmenu[0] = REGREAD32(ICH9_REG_OPMENU); |
| 328 | opmenu[1] = REGREAD32(ICH9_REG_OPMENU + 4); |
| 329 | break; |
| 330 | default: |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 331 | msg_perr("%s: unsupported chipset\n", __func__); |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 332 | return -1; |
| 333 | } |
| 334 | |
| 335 | op->preop[0] = (uint8_t) preop; |
| 336 | op->preop[1] = (uint8_t) (preop >> 8); |
| 337 | |
| 338 | for (a = 0; a < 8; a++) { |
| 339 | op->opcode[a].spi_type = (uint8_t) (optype & 0x3); |
| 340 | optype >>= 2; |
| 341 | } |
| 342 | |
| 343 | for (a = 0; a < 4; a++) { |
| 344 | op->opcode[a].opcode = (uint8_t) (opmenu[0] & 0xff); |
| 345 | opmenu[0] >>= 8; |
| 346 | } |
| 347 | |
| 348 | for (a = 4; a < 8; a++) { |
| 349 | op->opcode[a].opcode = (uint8_t) (opmenu[1] & 0xff); |
| 350 | opmenu[1] >>= 8; |
| 351 | } |
| 352 | |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 353 | /* No preopcodes used by default. */ |
| 354 | for (a = 0; a < 8; a++) |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 355 | op->opcode[a].atomic = 0; |
| 356 | |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 357 | return 0; |
| 358 | } |
| 359 | |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 360 | int program_opcodes(OPCODES * op) |
| 361 | { |
| 362 | uint8_t a; |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 363 | uint16_t preop, optype; |
| 364 | uint32_t opmenu[2]; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 365 | |
| 366 | /* Program Prefix Opcodes */ |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 367 | /* 0:7 Prefix Opcode 1 */ |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 368 | preop = (op->preop[0]); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 369 | /* 8:16 Prefix Opcode 2 */ |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 370 | preop |= ((uint16_t) op->preop[1]) << 8; |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 371 | |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 372 | /* Program Opcode Types 0 - 7 */ |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 373 | optype = 0; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 374 | for (a = 0; a < 8; a++) { |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 375 | optype |= ((uint16_t) op->opcode[a].spi_type) << (a * 2); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 376 | } |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 377 | |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 378 | /* Program Allowable Opcodes 0 - 3 */ |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 379 | opmenu[0] = 0; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 380 | for (a = 0; a < 4; a++) { |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 381 | opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 382 | } |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 383 | |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 384 | /*Program Allowable Opcodes 4 - 7 */ |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 385 | opmenu[1] = 0; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 386 | for (a = 4; a < 8; a++) { |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 387 | opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 388 | } |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 389 | |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 390 | msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 391 | switch (spi_controller) { |
| 392 | case SPI_CONTROLLER_ICH7: |
| 393 | case SPI_CONTROLLER_VIA: |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 394 | REGWRITE16(ICH7_REG_PREOP, preop); |
| 395 | REGWRITE16(ICH7_REG_OPTYPE, optype); |
| 396 | REGWRITE32(ICH7_REG_OPMENU, opmenu[0]); |
| 397 | REGWRITE32(ICH7_REG_OPMENU + 4, opmenu[1]); |
| 398 | break; |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 399 | case SPI_CONTROLLER_ICH9: |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 400 | REGWRITE16(ICH9_REG_PREOP, preop); |
| 401 | REGWRITE16(ICH9_REG_OPTYPE, optype); |
| 402 | REGWRITE32(ICH9_REG_OPMENU, opmenu[0]); |
| 403 | REGWRITE32(ICH9_REG_OPMENU + 4, opmenu[1]); |
| 404 | break; |
| 405 | default: |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 406 | msg_perr("%s: unsupported chipset\n", __func__); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 407 | return -1; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 408 | } |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 409 | |
| 410 | return 0; |
| 411 | } |
| 412 | |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 413 | /* |
| 414 | * Try to set BBAR (BIOS Base Address Register), but read back the value in case |
| 415 | * it didn't stick. |
| 416 | */ |
| 417 | void ich_set_bbar(uint32_t minaddr) |
| 418 | { |
Carl-Daniel Hailfinger | 841d631 | 2010-11-24 23:37:22 +0000 | [diff] [blame] | 419 | #define BBAR_MASK 0x00ffff00 |
| 420 | minaddr &= BBAR_MASK; |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 421 | switch (spi_controller) { |
| 422 | case SPI_CONTROLLER_ICH7: |
Carl-Daniel Hailfinger | 841d631 | 2010-11-24 23:37:22 +0000 | [diff] [blame] | 423 | case SPI_CONTROLLER_VIA: |
| 424 | ichspi_bbar = mmio_readl(ich_spibar + 0x50) & ~BBAR_MASK; |
| 425 | if (ichspi_bbar) |
| 426 | msg_pdbg("Reserved bits in BBAR not zero: 0x%04x", |
| 427 | ichspi_bbar); |
| 428 | ichspi_bbar |= minaddr; |
| 429 | mmio_writel(ichspi_bbar, ich_spibar + 0x50); |
Carl-Daniel Hailfinger | ad3cc55 | 2010-07-03 11:02:10 +0000 | [diff] [blame] | 430 | ichspi_bbar = mmio_readl(ich_spibar + 0x50); |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 431 | /* We don't have any option except complaining. */ |
| 432 | if (ichspi_bbar != minaddr) |
| 433 | msg_perr("Setting BBAR failed!\n"); |
| 434 | break; |
| 435 | case SPI_CONTROLLER_ICH9: |
Carl-Daniel Hailfinger | 841d631 | 2010-11-24 23:37:22 +0000 | [diff] [blame] | 436 | ichspi_bbar = mmio_readl(ich_spibar + 0xA0) & ~BBAR_MASK; |
| 437 | if (ichspi_bbar) |
| 438 | msg_pdbg("Reserved bits in BBAR not zero: 0x%04x", |
| 439 | ichspi_bbar); |
| 440 | ichspi_bbar |= minaddr; |
| 441 | mmio_writel(ichspi_bbar, ich_spibar + 0xA0); |
Carl-Daniel Hailfinger | ad3cc55 | 2010-07-03 11:02:10 +0000 | [diff] [blame] | 442 | ichspi_bbar = mmio_readl(ich_spibar + 0xA0); |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 443 | /* We don't have any option except complaining. */ |
| 444 | if (ichspi_bbar != minaddr) |
| 445 | msg_perr("Setting BBAR failed!\n"); |
| 446 | break; |
| 447 | default: |
Carl-Daniel Hailfinger | 841d631 | 2010-11-24 23:37:22 +0000 | [diff] [blame] | 448 | msg_perr("Unknown chipset for BBAR setting!\n"); |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 449 | break; |
| 450 | } |
| 451 | } |
| 452 | |
FENG yu ning | f041e9b | 2008-12-15 02:32:11 +0000 | [diff] [blame] | 453 | /* This function generates OPCODES from or programs OPCODES to ICH according to |
| 454 | * the chipset's SPI configuration lock. |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 455 | * |
FENG yu ning | f041e9b | 2008-12-15 02:32:11 +0000 | [diff] [blame] | 456 | * It should be called before ICH sends any spi command. |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 457 | */ |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 458 | static int ich_init_opcodes(void) |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 459 | { |
| 460 | int rc = 0; |
| 461 | OPCODES *curopcodes_done; |
| 462 | |
| 463 | if (curopcodes) |
| 464 | return 0; |
| 465 | |
| 466 | if (ichspi_lock) { |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 467 | msg_pdbg("Reading OPCODES... "); |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 468 | curopcodes_done = &O_EXISTING; |
FENG yu ning | f041e9b | 2008-12-15 02:32:11 +0000 | [diff] [blame] | 469 | rc = generate_opcodes(curopcodes_done); |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 470 | } else { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 471 | msg_pdbg("Programming OPCODES... "); |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 472 | curopcodes_done = &O_ST_M25P; |
| 473 | rc = program_opcodes(curopcodes_done); |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 474 | /* Technically not part of opcode init, but it allows opcodes |
| 475 | * to run without transaction errors by setting the lowest |
| 476 | * allowed address to zero. |
| 477 | */ |
| 478 | ich_set_bbar(0); |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 479 | } |
| 480 | |
| 481 | if (rc) { |
| 482 | curopcodes = NULL; |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 483 | msg_perr("failed\n"); |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 484 | return 1; |
| 485 | } else { |
| 486 | curopcodes = curopcodes_done; |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 487 | msg_pdbg("done\n"); |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 488 | return 0; |
| 489 | } |
| 490 | } |
| 491 | |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 492 | static int ich7_run_opcode(OPCODE op, uint32_t offset, |
Rudolf Marek | 3fdbccf | 2008-06-30 21:38:30 +0000 | [diff] [blame] | 493 | uint8_t datalength, uint8_t * data, int maxdata) |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 494 | { |
| 495 | int write_cmd = 0; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 496 | int timeout; |
Peter Stuge | 7e2c079 | 2008-06-29 01:30:41 +0000 | [diff] [blame] | 497 | uint32_t temp32 = 0; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 498 | uint16_t temp16; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 499 | uint32_t a; |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 500 | uint64_t opmenu; |
| 501 | int opcode_index; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 502 | |
| 503 | /* Is it a write command? */ |
| 504 | if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) |
| 505 | || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) { |
| 506 | write_cmd = 1; |
| 507 | } |
| 508 | |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 509 | timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ |
| 510 | while ((REGREAD16(ICH7_REG_SPIS) & SPIS_SCIP) && --timeout) { |
| 511 | programmer_delay(10); |
| 512 | } |
| 513 | if (!timeout) { |
| 514 | msg_perr("Error: SCIP never cleared!\n"); |
| 515 | return 1; |
| 516 | } |
| 517 | |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 518 | /* Programm Offset in Flash into FADDR */ |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 519 | REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */ |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 520 | |
| 521 | /* Program data into FDATA0 to N */ |
| 522 | if (write_cmd && (datalength != 0)) { |
| 523 | temp32 = 0; |
| 524 | for (a = 0; a < datalength; a++) { |
| 525 | if ((a % 4) == 0) { |
| 526 | temp32 = 0; |
| 527 | } |
| 528 | |
| 529 | temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8); |
| 530 | |
| 531 | if ((a % 4) == 3) { |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 532 | REGWRITE32(ICH7_REG_SPID0 + (a - (a % 4)), |
| 533 | temp32); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 534 | } |
| 535 | } |
| 536 | if (((a - 1) % 4) != 3) { |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 537 | REGWRITE32(ICH7_REG_SPID0 + |
| 538 | ((a - 1) - ((a - 1) % 4)), temp32); |
| 539 | } |
| 540 | |
| 541 | } |
| 542 | |
| 543 | /* Assemble SPIS */ |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 544 | temp16 = REGREAD16(ICH7_REG_SPIS); |
| 545 | /* keep reserved bits */ |
| 546 | temp16 &= SPIS_RESERVED_MASK; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 547 | /* clear error status registers */ |
| 548 | temp16 |= (SPIS_CDS + SPIS_FCERR); |
| 549 | REGWRITE16(ICH7_REG_SPIS, temp16); |
| 550 | |
| 551 | /* Assemble SPIC */ |
| 552 | temp16 = 0; |
| 553 | |
| 554 | if (datalength != 0) { |
| 555 | temp16 |= SPIC_DS; |
Rudolf Marek | 3fdbccf | 2008-06-30 21:38:30 +0000 | [diff] [blame] | 556 | temp16 |= ((uint32_t) ((datalength - 1) & (maxdata - 1))) << 8; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 557 | } |
| 558 | |
| 559 | /* Select opcode */ |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 560 | opmenu = REGREAD32(ICH7_REG_OPMENU); |
| 561 | opmenu |= ((uint64_t)REGREAD32(ICH7_REG_OPMENU + 4)) << 32; |
| 562 | |
Uwe Hermann | 7b2969b | 2009-04-15 10:52:49 +0000 | [diff] [blame] | 563 | for (opcode_index = 0; opcode_index < 8; opcode_index++) { |
| 564 | if ((opmenu & 0xff) == op.opcode) { |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 565 | break; |
| 566 | } |
| 567 | opmenu >>= 8; |
| 568 | } |
| 569 | if (opcode_index == 8) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 570 | msg_pdbg("Opcode %x not found.\n", op.opcode); |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 571 | return 1; |
| 572 | } |
| 573 | temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 574 | |
Michael Karcher | 136125a | 2011-04-29 22:11:36 +0000 | [diff] [blame] | 575 | timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ |
| 576 | /* Handle Atomic. Atomic commands include three steps: |
| 577 | - sending the preop (mainly EWSR or WREN) |
| 578 | - sending the main command |
| 579 | - waiting for the busy bit (WIP) to be cleared |
| 580 | This means the timeout must be sufficient for chip erase |
| 581 | of slow high-capacity chips. |
| 582 | */ |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 583 | switch (op.atomic) { |
| 584 | case 2: |
| 585 | /* Select second preop. */ |
| 586 | temp16 |= SPIC_SPOP; |
| 587 | /* And fall through. */ |
| 588 | case 1: |
| 589 | /* Atomic command (preop+op) */ |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 590 | temp16 |= SPIC_ACS; |
Michael Karcher | 136125a | 2011-04-29 22:11:36 +0000 | [diff] [blame] | 591 | timeout = 100 * 1000 * 60; /* 60 seconds */ |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 592 | break; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 593 | } |
| 594 | |
| 595 | /* Start */ |
| 596 | temp16 |= SPIC_SCGO; |
| 597 | |
| 598 | /* write it */ |
| 599 | REGWRITE16(ICH7_REG_SPIC, temp16); |
| 600 | |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 601 | /* Wait for Cycle Done Status or Flash Cycle Error. */ |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 602 | while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) && |
| 603 | --timeout) { |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 604 | programmer_delay(10); |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 605 | } |
| 606 | if (!timeout) { |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 607 | msg_perr("timeout, ICH7_REG_SPIS=0x%04x\n", |
| 608 | REGREAD16(ICH7_REG_SPIS)); |
| 609 | return 1; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 610 | } |
| 611 | |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 612 | /* FIXME: make sure we do not needlessly cause transaction errors. */ |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 613 | temp16 = REGREAD16(ICH7_REG_SPIS); |
| 614 | if (temp16 & SPIS_FCERR) { |
Stefan Tauner | 8ed2934 | 2011-04-29 23:53:09 +0000 | [diff] [blame^] | 615 | msg_perr("Transaction error!\n"); |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 616 | /* keep reserved bits */ |
| 617 | temp16 &= SPIS_RESERVED_MASK; |
| 618 | REGWRITE16(ICH7_REG_SPIS, temp16 | SPIS_FCERR); |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 619 | return 1; |
| 620 | } |
| 621 | |
| 622 | if ((!write_cmd) && (datalength != 0)) { |
| 623 | for (a = 0; a < datalength; a++) { |
| 624 | if ((a % 4) == 0) { |
| 625 | temp32 = REGREAD32(ICH7_REG_SPID0 + (a)); |
| 626 | } |
| 627 | |
| 628 | data[a] = |
| 629 | (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) |
| 630 | >> ((a % 4) * 8); |
| 631 | } |
| 632 | } |
| 633 | |
| 634 | return 0; |
| 635 | } |
| 636 | |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 637 | static int ich9_run_opcode(OPCODE op, uint32_t offset, |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 638 | uint8_t datalength, uint8_t * data) |
| 639 | { |
| 640 | int write_cmd = 0; |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 641 | int timeout; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 642 | uint32_t temp32; |
| 643 | uint32_t a; |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 644 | uint64_t opmenu; |
| 645 | int opcode_index; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 646 | |
| 647 | /* Is it a write command? */ |
| 648 | if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) |
| 649 | || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) { |
| 650 | write_cmd = 1; |
| 651 | } |
| 652 | |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 653 | timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ |
| 654 | while ((REGREAD8(ICH9_REG_SSFS) & SSFS_SCIP) && --timeout) { |
| 655 | programmer_delay(10); |
| 656 | } |
| 657 | if (!timeout) { |
| 658 | msg_perr("Error: SCIP never cleared!\n"); |
| 659 | return 1; |
| 660 | } |
| 661 | |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 662 | /* Programm Offset in Flash into FADDR */ |
| 663 | REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */ |
| 664 | |
| 665 | /* Program data into FDATA0 to N */ |
| 666 | if (write_cmd && (datalength != 0)) { |
| 667 | temp32 = 0; |
| 668 | for (a = 0; a < datalength; a++) { |
| 669 | if ((a % 4) == 0) { |
| 670 | temp32 = 0; |
| 671 | } |
| 672 | |
| 673 | temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8); |
| 674 | |
| 675 | if ((a % 4) == 3) { |
| 676 | REGWRITE32(ICH9_REG_FDATA0 + (a - (a % 4)), |
| 677 | temp32); |
| 678 | } |
| 679 | } |
| 680 | if (((a - 1) % 4) != 3) { |
| 681 | REGWRITE32(ICH9_REG_FDATA0 + |
| 682 | ((a - 1) - ((a - 1) % 4)), temp32); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 683 | } |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 684 | } |
| 685 | |
| 686 | /* Assemble SSFS + SSFC */ |
Helge Wagner | a319be1 | 2010-08-11 21:06:10 +0000 | [diff] [blame] | 687 | temp32 = REGREAD32(ICH9_REG_SSFS); |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 688 | /* keep reserved bits */ |
| 689 | temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 690 | /* clear error status registers */ |
| 691 | temp32 |= (SSFS_CDS + SSFS_FCERR); |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 692 | REGWRITE32(ICH9_REG_SSFS, temp32); |
| 693 | |
Uwe Hermann | 4e3d0b3 | 2010-03-25 23:18:41 +0000 | [diff] [blame] | 694 | /* Use 20 MHz */ |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 695 | temp32 |= SSFC_SCF_20MHZ; |
| 696 | |
| 697 | if (datalength != 0) { |
| 698 | uint32_t datatemp; |
| 699 | temp32 |= SSFC_DS; |
| 700 | datatemp = ((uint32_t) ((datalength - 1) & 0x3f)) << (8 + 8); |
| 701 | temp32 |= datatemp; |
| 702 | } |
| 703 | |
| 704 | /* Select opcode */ |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 705 | opmenu = REGREAD32(ICH9_REG_OPMENU); |
| 706 | opmenu |= ((uint64_t)REGREAD32(ICH9_REG_OPMENU + 4)) << 32; |
| 707 | |
Uwe Hermann | 7b2969b | 2009-04-15 10:52:49 +0000 | [diff] [blame] | 708 | for (opcode_index = 0; opcode_index < 8; opcode_index++) { |
| 709 | if ((opmenu & 0xff) == op.opcode) { |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 710 | break; |
| 711 | } |
| 712 | opmenu >>= 8; |
| 713 | } |
| 714 | if (opcode_index == 8) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 715 | msg_pdbg("Opcode %x not found.\n", op.opcode); |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 716 | return 1; |
| 717 | } |
| 718 | temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 719 | |
Michael Karcher | 136125a | 2011-04-29 22:11:36 +0000 | [diff] [blame] | 720 | timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ |
| 721 | /* Handle Atomic. Atomic commands include three steps: |
| 722 | - sending the preop (mainly EWSR or WREN) |
| 723 | - sending the main command |
| 724 | - waiting for the busy bit (WIP) to be cleared |
| 725 | This means the timeout must be sufficient for chip erase |
| 726 | of slow high-capacity chips. |
| 727 | */ |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 728 | switch (op.atomic) { |
| 729 | case 2: |
| 730 | /* Select second preop. */ |
| 731 | temp32 |= SSFC_SPOP; |
| 732 | /* And fall through. */ |
| 733 | case 1: |
| 734 | /* Atomic command (preop+op) */ |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 735 | temp32 |= SSFC_ACS; |
Michael Karcher | 136125a | 2011-04-29 22:11:36 +0000 | [diff] [blame] | 736 | timeout = 100 * 1000 * 60; /* 60 seconds */ |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 737 | break; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 738 | } |
| 739 | |
| 740 | /* Start */ |
| 741 | temp32 |= SSFC_SCGO; |
| 742 | |
| 743 | /* write it */ |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 744 | REGWRITE32(ICH9_REG_SSFS, temp32); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 745 | |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 746 | /* Wait for Cycle Done Status or Flash Cycle Error. */ |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 747 | while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_CDS | SSFS_FCERR)) == 0) && |
| 748 | --timeout) { |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 749 | programmer_delay(10); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 750 | } |
| 751 | if (!timeout) { |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 752 | msg_perr("timeout, ICH9_REG_SSFS=0x%08x\n", |
| 753 | REGREAD32(ICH9_REG_SSFS)); |
| 754 | return 1; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 755 | } |
| 756 | |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 757 | /* FIXME make sure we do not needlessly cause transaction errors. */ |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 758 | temp32 = REGREAD32(ICH9_REG_SSFS); |
| 759 | if (temp32 & SSFS_FCERR) { |
Stefan Tauner | 8ed2934 | 2011-04-29 23:53:09 +0000 | [diff] [blame^] | 760 | msg_perr("Transaction error!\n"); |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 761 | /* keep reserved bits */ |
| 762 | temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; |
| 763 | /* Clear the transaction error. */ |
| 764 | REGWRITE32(ICH9_REG_SSFS, temp32 | SSFS_FCERR); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 765 | return 1; |
| 766 | } |
| 767 | |
| 768 | if ((!write_cmd) && (datalength != 0)) { |
| 769 | for (a = 0; a < datalength; a++) { |
| 770 | if ((a % 4) == 0) { |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 771 | temp32 = REGREAD32(ICH9_REG_FDATA0 + (a)); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 772 | } |
| 773 | |
| 774 | data[a] = |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 775 | (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) |
| 776 | >> ((a % 4) * 8); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 777 | } |
| 778 | } |
| 779 | |
| 780 | return 0; |
| 781 | } |
| 782 | |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 783 | static int run_opcode(OPCODE op, uint32_t offset, |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 784 | uint8_t datalength, uint8_t * data) |
| 785 | { |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 786 | switch (spi_controller) { |
| 787 | case SPI_CONTROLLER_VIA: |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 788 | if (datalength > 16) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 789 | msg_perr("%s: Internal command size error for " |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 790 | "opcode 0x%02x, got datalength=%i, want <=16\n", |
| 791 | __func__, op.opcode, datalength); |
Carl-Daniel Hailfinger | 142e30f | 2009-07-14 10:26:56 +0000 | [diff] [blame] | 792 | return SPI_INVALID_LENGTH; |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 793 | } |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 794 | return ich7_run_opcode(op, offset, datalength, data, 16); |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 795 | case SPI_CONTROLLER_ICH7: |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 796 | if (datalength > 64) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 797 | msg_perr("%s: Internal command size error for " |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 798 | "opcode 0x%02x, got datalength=%i, want <=16\n", |
| 799 | __func__, op.opcode, datalength); |
Carl-Daniel Hailfinger | 142e30f | 2009-07-14 10:26:56 +0000 | [diff] [blame] | 800 | return SPI_INVALID_LENGTH; |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 801 | } |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 802 | return ich7_run_opcode(op, offset, datalength, data, 64); |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 803 | case SPI_CONTROLLER_ICH9: |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 804 | if (datalength > 64) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 805 | msg_perr("%s: Internal command size error for " |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 806 | "opcode 0x%02x, got datalength=%i, want <=16\n", |
| 807 | __func__, op.opcode, datalength); |
Carl-Daniel Hailfinger | 142e30f | 2009-07-14 10:26:56 +0000 | [diff] [blame] | 808 | return SPI_INVALID_LENGTH; |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 809 | } |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 810 | return ich9_run_opcode(op, offset, datalength, data); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 811 | default: |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 812 | msg_perr("%s: unsupported chipset\n", __func__); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 813 | } |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 814 | |
| 815 | /* If we ever get here, something really weird happened */ |
| 816 | return -1; |
| 817 | } |
| 818 | |
Carl-Daniel Hailfinger | cbf563c | 2009-06-16 08:55:44 +0000 | [diff] [blame] | 819 | int ich_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len) |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 820 | { |
Rudolf Marek | 3fdbccf | 2008-06-30 21:38:30 +0000 | [diff] [blame] | 821 | int maxdata = 64; |
| 822 | |
Carl-Daniel Hailfinger | 38a059d | 2009-06-13 12:04:03 +0000 | [diff] [blame] | 823 | if (spi_controller == SPI_CONTROLLER_VIA) |
Rudolf Marek | 3fdbccf | 2008-06-30 21:38:30 +0000 | [diff] [blame] | 824 | maxdata = 16; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 825 | |
Carl-Daniel Hailfinger | cbf563c | 2009-06-16 08:55:44 +0000 | [diff] [blame] | 826 | return spi_read_chunked(flash, buf, start, len, maxdata); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 827 | } |
| 828 | |
Carl-Daniel Hailfinger | 9a795d8 | 2010-07-14 16:19:05 +0000 | [diff] [blame] | 829 | int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len) |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 830 | { |
Rudolf Marek | 3fdbccf | 2008-06-30 21:38:30 +0000 | [diff] [blame] | 831 | int maxdata = 64; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 832 | |
Carl-Daniel Hailfinger | 5824fbf | 2010-05-21 23:09:42 +0000 | [diff] [blame] | 833 | if (spi_controller == SPI_CONTROLLER_VIA) |
| 834 | maxdata = 16; |
| 835 | |
Carl-Daniel Hailfinger | 9a795d8 | 2010-07-14 16:19:05 +0000 | [diff] [blame] | 836 | return spi_write_chunked(flash, buf, start, len, maxdata); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 837 | } |
| 838 | |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 839 | int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, |
Stefan Reinauer | 325b5d4 | 2008-06-27 15:18:20 +0000 | [diff] [blame] | 840 | const unsigned char *writearr, unsigned char *readarr) |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 841 | { |
Carl-Daniel Hailfinger | 142e30f | 2009-07-14 10:26:56 +0000 | [diff] [blame] | 842 | int result; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 843 | int opcode_index = -1; |
| 844 | const unsigned char cmd = *writearr; |
| 845 | OPCODE *opcode; |
| 846 | uint32_t addr = 0; |
| 847 | uint8_t *data; |
| 848 | int count; |
| 849 | |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 850 | /* find cmd in opcodes-table */ |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 851 | opcode_index = find_opcode(curopcodes, cmd); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 852 | if (opcode_index == -1) { |
Helge Wagner | 738e252 | 2010-10-05 22:06:05 +0000 | [diff] [blame] | 853 | if (!ichspi_lock) |
| 854 | opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt); |
| 855 | if (opcode_index == -1) { |
| 856 | msg_pdbg("Invalid OPCODE 0x%02x\n", cmd); |
| 857 | return SPI_INVALID_OPCODE; |
| 858 | } |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 859 | } |
| 860 | |
| 861 | opcode = &(curopcodes->opcode[opcode_index]); |
| 862 | |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 863 | /* The following valid writecnt/readcnt combinations exist: |
| 864 | * writecnt = 4, readcnt >= 0 |
| 865 | * writecnt = 1, readcnt >= 0 |
| 866 | * writecnt >= 4, readcnt = 0 |
| 867 | * writecnt >= 1, readcnt = 0 |
| 868 | * writecnt >= 1 is guaranteed for all commands. |
| 869 | */ |
| 870 | if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) && |
| 871 | (writecnt != 4)) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 872 | msg_perr("%s: Internal command size error for opcode " |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 873 | "0x%02x, got writecnt=%i, want =4\n", __func__, cmd, |
| 874 | writecnt); |
| 875 | return SPI_INVALID_LENGTH; |
| 876 | } |
| 877 | if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_NO_ADDRESS) && |
| 878 | (writecnt != 1)) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 879 | msg_perr("%s: Internal command size error for opcode " |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 880 | "0x%02x, got writecnt=%i, want =1\n", __func__, cmd, |
| 881 | writecnt); |
| 882 | return SPI_INVALID_LENGTH; |
| 883 | } |
| 884 | if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) && |
| 885 | (writecnt < 4)) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 886 | msg_perr("%s: Internal command size error for opcode " |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 887 | "0x%02x, got writecnt=%i, want >=4\n", __func__, cmd, |
| 888 | writecnt); |
| 889 | return SPI_INVALID_LENGTH; |
| 890 | } |
| 891 | if (((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) || |
| 892 | (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) && |
| 893 | (readcnt)) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 894 | msg_perr("%s: Internal command size error for opcode " |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 895 | "0x%02x, got readcnt=%i, want =0\n", __func__, cmd, |
| 896 | readcnt); |
| 897 | return SPI_INVALID_LENGTH; |
| 898 | } |
| 899 | |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 900 | /* if opcode-type requires an address */ |
| 901 | if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS || |
| 902 | opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { |
Stefan Reinauer | 325b5d4 | 2008-06-27 15:18:20 +0000 | [diff] [blame] | 903 | addr = (writearr[1] << 16) | |
| 904 | (writearr[2] << 8) | (writearr[3] << 0); |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 905 | switch (spi_controller) { |
| 906 | case SPI_CONTROLLER_ICH7: |
Carl-Daniel Hailfinger | 841d631 | 2010-11-24 23:37:22 +0000 | [diff] [blame] | 907 | case SPI_CONTROLLER_VIA: |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 908 | case SPI_CONTROLLER_ICH9: |
| 909 | if (addr < ichspi_bbar) { |
| 910 | msg_perr("%s: Address 0x%06x below allowed " |
| 911 | "range 0x%06x-0xffffff\n", __func__, |
| 912 | addr, ichspi_bbar); |
| 913 | return SPI_INVALID_ADDRESS; |
| 914 | } |
| 915 | break; |
| 916 | default: |
| 917 | break; |
| 918 | } |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 919 | } |
Stefan Reinauer | 325b5d4 | 2008-06-27 15:18:20 +0000 | [diff] [blame] | 920 | |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 921 | /* translate read/write array/count */ |
| 922 | if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) { |
Stefan Reinauer | 325b5d4 | 2008-06-27 15:18:20 +0000 | [diff] [blame] | 923 | data = (uint8_t *) (writearr + 1); |
| 924 | count = writecnt - 1; |
| 925 | } else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { |
| 926 | data = (uint8_t *) (writearr + 4); |
| 927 | count = writecnt - 4; |
| 928 | } else { |
| 929 | data = (uint8_t *) readarr; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 930 | count = readcnt; |
| 931 | } |
Stefan Reinauer | 325b5d4 | 2008-06-27 15:18:20 +0000 | [diff] [blame] | 932 | |
Carl-Daniel Hailfinger | 142e30f | 2009-07-14 10:26:56 +0000 | [diff] [blame] | 933 | result = run_opcode(*opcode, addr, count, data); |
| 934 | if (result) { |
Stefan Tauner | 8ed2934 | 2011-04-29 23:53:09 +0000 | [diff] [blame^] | 935 | msg_pdbg("Running OPCODE 0x%02x failed ", opcode->opcode); |
| 936 | if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) || |
| 937 | (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS)) { |
| 938 | msg_pdbg("at address 0x%06x ", addr); |
| 939 | } |
| 940 | msg_pdbg("(payload length was %d).\n", count); |
| 941 | |
| 942 | /* Print out the data array if it contains data to write. |
| 943 | * Errors are detected before the received data is read back into |
| 944 | * the array so it won't make sense to print it then. */ |
| 945 | if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) || |
| 946 | (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) { |
| 947 | int i; |
| 948 | msg_pspew("The data was:\n"); |
| 949 | for(i=0; i<count; i++){ |
| 950 | msg_pspew("%3d: 0x%02x\n", i, data[i]); |
| 951 | } |
| 952 | } |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 953 | } |
| 954 | |
Carl-Daniel Hailfinger | 142e30f | 2009-07-14 10:26:56 +0000 | [diff] [blame] | 955 | return result; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 956 | } |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 957 | |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 958 | int ich_spi_send_multicommand(struct spi_command *cmds) |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 959 | { |
| 960 | int ret = 0; |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 961 | int i; |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 962 | int oppos, preoppos; |
| 963 | for (; (cmds->writecnt || cmds->readcnt) && !ret; cmds++) { |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 964 | if ((cmds + 1)->writecnt || (cmds + 1)->readcnt) { |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 965 | /* Next command is valid. */ |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 966 | preoppos = find_preop(curopcodes, cmds->writearr[0]); |
| 967 | oppos = find_opcode(curopcodes, (cmds + 1)->writearr[0]); |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 968 | if ((oppos == -1) && (preoppos != -1)) { |
| 969 | /* Current command is listed as preopcode in |
| 970 | * ICH struct OPCODES, but next command is not |
| 971 | * listed as opcode in that struct. |
| 972 | * Check for command sanity, then |
| 973 | * try to reprogram the ICH opcode list. |
| 974 | */ |
| 975 | if (find_preop(curopcodes, |
| 976 | (cmds + 1)->writearr[0]) != -1) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 977 | msg_perr("%s: Two subsequent " |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 978 | "preopcodes 0x%02x and 0x%02x, " |
| 979 | "ignoring the first.\n", |
| 980 | __func__, cmds->writearr[0], |
| 981 | (cmds + 1)->writearr[0]); |
| 982 | continue; |
| 983 | } |
| 984 | /* If the chipset is locked down, we'll fail |
| 985 | * during execution of the next command anyway. |
| 986 | * No need to bother with fixups. |
| 987 | */ |
| 988 | if (!ichspi_lock) { |
Helge Wagner | 738e252 | 2010-10-05 22:06:05 +0000 | [diff] [blame] | 989 | oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt); |
| 990 | if (oppos == -1) |
| 991 | continue; |
| 992 | curopcodes->opcode[oppos].atomic = preoppos + 1; |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 993 | continue; |
| 994 | } |
| 995 | } |
| 996 | if ((oppos != -1) && (preoppos != -1)) { |
| 997 | /* Current command is listed as preopcode in |
| 998 | * ICH struct OPCODES and next command is listed |
| 999 | * as opcode in that struct. Match them up. |
| 1000 | */ |
| 1001 | curopcodes->opcode[oppos].atomic = preoppos + 1; |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 1002 | continue; |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 1003 | } |
| 1004 | /* If none of the above if-statements about oppos or |
| 1005 | * preoppos matched, this is a normal opcode. |
| 1006 | */ |
| 1007 | } |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 1008 | ret = ich_spi_send_command(cmds->writecnt, cmds->readcnt, |
| 1009 | cmds->writearr, cmds->readarr); |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 1010 | /* Reset the type of all opcodes to non-atomic. */ |
| 1011 | for (i = 0; i < 8; i++) |
| 1012 | curopcodes->opcode[i].atomic = 0; |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 1013 | } |
| 1014 | return ret; |
| 1015 | } |
Carl-Daniel Hailfinger | cceafa2 | 2010-05-26 01:45:41 +0000 | [diff] [blame] | 1016 | |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1017 | #define ICH_BMWAG(x) ((x >> 24) & 0xff) |
| 1018 | #define ICH_BMRAG(x) ((x >> 16) & 0xff) |
| 1019 | #define ICH_BRWA(x) ((x >> 8) & 0xff) |
| 1020 | #define ICH_BRRA(x) ((x >> 0) & 0xff) |
| 1021 | |
| 1022 | #define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff) |
| 1023 | #define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff) |
| 1024 | |
| 1025 | static void do_ich9_spi_frap(uint32_t frap, int i) |
| 1026 | { |
Mathias Krause | a60faab | 2011-01-17 07:50:42 +0000 | [diff] [blame] | 1027 | static const char *const access_names[4] = { |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1028 | "locked", "read-only", "write-only", "read-write" |
| 1029 | }; |
Mathias Krause | a60faab | 2011-01-17 07:50:42 +0000 | [diff] [blame] | 1030 | static const char *const region_names[5] = { |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1031 | "Flash Descriptor", "BIOS", "Management Engine", |
| 1032 | "Gigabit Ethernet", "Platform Data" |
| 1033 | }; |
| 1034 | uint32_t base, limit; |
| 1035 | int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) | |
| 1036 | (((ICH_BRRA(frap) >> i) & 1) << 0); |
| 1037 | int offset = 0x54 + i * 4; |
| 1038 | uint32_t freg = mmio_readl(ich_spibar + offset); |
| 1039 | |
| 1040 | msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n", |
| 1041 | offset, freg, i, region_names[i]); |
| 1042 | |
| 1043 | base = ICH_FREG_BASE(freg); |
| 1044 | limit = ICH_FREG_LIMIT(freg); |
| 1045 | if (base == 0x1fff && limit == 0) { |
| 1046 | /* this FREG is disabled */ |
| 1047 | msg_pdbg("%s region is unused.\n", region_names[i]); |
| 1048 | return; |
| 1049 | } |
| 1050 | |
| 1051 | msg_pdbg("0x%08x-0x%08x is %s\n", |
| 1052 | (base << 12), (limit << 12) | 0x0fff, |
| 1053 | access_names[rwperms]); |
| 1054 | } |
| 1055 | |
| 1056 | int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, |
| 1057 | int ich_generation) |
| 1058 | { |
| 1059 | int i; |
| 1060 | uint8_t old, new; |
| 1061 | uint16_t spibar_offset, tmp2; |
| 1062 | uint32_t tmp; |
| 1063 | |
| 1064 | buses_supported |= CHIP_BUSTYPE_SPI; |
| 1065 | switch (ich_generation) { |
| 1066 | case 7: |
| 1067 | spi_controller = SPI_CONTROLLER_ICH7; |
| 1068 | spibar_offset = 0x3020; |
| 1069 | break; |
| 1070 | case 8: |
| 1071 | spi_controller = SPI_CONTROLLER_ICH9; |
| 1072 | spibar_offset = 0x3020; |
| 1073 | break; |
| 1074 | case 9: |
| 1075 | case 10: |
| 1076 | default: /* Future version might behave the same */ |
| 1077 | spi_controller = SPI_CONTROLLER_ICH9; |
| 1078 | spibar_offset = 0x3800; |
| 1079 | break; |
| 1080 | } |
| 1081 | |
| 1082 | /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */ |
| 1083 | msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", base, spibar_offset); |
| 1084 | |
| 1085 | /* Assign Virtual Address */ |
| 1086 | ich_spibar = rcrb + spibar_offset; |
| 1087 | |
| 1088 | switch (spi_controller) { |
| 1089 | case SPI_CONTROLLER_ICH7: |
| 1090 | msg_pdbg("0x00: 0x%04x (SPIS)\n", |
| 1091 | mmio_readw(ich_spibar + 0)); |
| 1092 | msg_pdbg("0x02: 0x%04x (SPIC)\n", |
| 1093 | mmio_readw(ich_spibar + 2)); |
| 1094 | msg_pdbg("0x04: 0x%08x (SPIA)\n", |
| 1095 | mmio_readl(ich_spibar + 4)); |
| 1096 | for (i = 0; i < 8; i++) { |
| 1097 | int offs; |
| 1098 | offs = 8 + (i * 8); |
| 1099 | msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs, |
| 1100 | mmio_readl(ich_spibar + offs), i); |
| 1101 | msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, |
| 1102 | mmio_readl(ich_spibar + offs + 4), i); |
| 1103 | } |
| 1104 | ichspi_bbar = mmio_readl(ich_spibar + 0x50); |
| 1105 | msg_pdbg("0x50: 0x%08x (BBAR)\n", |
| 1106 | ichspi_bbar); |
| 1107 | msg_pdbg("0x54: 0x%04x (PREOP)\n", |
| 1108 | mmio_readw(ich_spibar + 0x54)); |
| 1109 | msg_pdbg("0x56: 0x%04x (OPTYPE)\n", |
| 1110 | mmio_readw(ich_spibar + 0x56)); |
| 1111 | msg_pdbg("0x58: 0x%08x (OPMENU)\n", |
| 1112 | mmio_readl(ich_spibar + 0x58)); |
| 1113 | msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", |
| 1114 | mmio_readl(ich_spibar + 0x5c)); |
| 1115 | for (i = 0; i < 4; i++) { |
| 1116 | int offs; |
| 1117 | offs = 0x60 + (i * 4); |
| 1118 | msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, |
| 1119 | mmio_readl(ich_spibar + offs), i); |
| 1120 | } |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1121 | if (mmio_readw(ich_spibar) & (1 << 15)) { |
| 1122 | msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); |
| 1123 | ichspi_lock = 1; |
| 1124 | } |
| 1125 | ich_init_opcodes(); |
| 1126 | break; |
| 1127 | case SPI_CONTROLLER_ICH9: |
| 1128 | tmp2 = mmio_readw(ich_spibar + 4); |
| 1129 | msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); |
| 1130 | msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1)); |
| 1131 | msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1); |
| 1132 | msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1); |
| 1133 | msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1); |
| 1134 | msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3); |
| 1135 | msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1); |
| 1136 | msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1); |
| 1137 | msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1); |
| 1138 | |
| 1139 | tmp = mmio_readl(ich_spibar + 0x50); |
| 1140 | msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); |
| 1141 | msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); |
| 1142 | msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); |
| 1143 | msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp)); |
| 1144 | msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp)); |
| 1145 | |
| 1146 | /* print out the FREGx registers along with FRAP access bits */ |
| 1147 | for(i = 0; i < 5; i++) |
| 1148 | do_ich9_spi_frap(tmp, i); |
| 1149 | |
| 1150 | msg_pdbg("0x74: 0x%08x (PR0)\n", |
| 1151 | mmio_readl(ich_spibar + 0x74)); |
| 1152 | msg_pdbg("0x78: 0x%08x (PR1)\n", |
| 1153 | mmio_readl(ich_spibar + 0x78)); |
| 1154 | msg_pdbg("0x7C: 0x%08x (PR2)\n", |
| 1155 | mmio_readl(ich_spibar + 0x7C)); |
| 1156 | msg_pdbg("0x80: 0x%08x (PR3)\n", |
| 1157 | mmio_readl(ich_spibar + 0x80)); |
| 1158 | msg_pdbg("0x84: 0x%08x (PR4)\n", |
| 1159 | mmio_readl(ich_spibar + 0x84)); |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 1160 | |
| 1161 | tmp = mmio_readl(ich_spibar + 0x90); |
| 1162 | msg_pdbg("0x90: 0x%02x (SSFS)\n", tmp & 0xff); |
| 1163 | msg_pdbg("AEL %i, ", (tmp >> 4) & 1); |
| 1164 | msg_pdbg("FCERR %i, ", (tmp >> 3) & 1); |
| 1165 | msg_pdbg("FDONE %i, ", (tmp >> 2) & 1); |
| 1166 | msg_pdbg("SCIP %i\n", (tmp >> 0) & 1); |
| 1167 | if (tmp & (1 << 3)) { |
| 1168 | msg_pdbg("Clearing SSFS.FCERR\n"); |
| 1169 | mmio_writeb(1 << 3, ich_spibar + 0x90); |
| 1170 | } |
| 1171 | tmp >>= 8; |
| 1172 | msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp); |
| 1173 | |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1174 | msg_pdbg("0x94: 0x%04x (PREOP)\n", |
| 1175 | mmio_readw(ich_spibar + 0x94)); |
| 1176 | msg_pdbg("0x96: 0x%04x (OPTYPE)\n", |
| 1177 | mmio_readw(ich_spibar + 0x96)); |
| 1178 | msg_pdbg("0x98: 0x%08x (OPMENU)\n", |
| 1179 | mmio_readl(ich_spibar + 0x98)); |
| 1180 | msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", |
| 1181 | mmio_readl(ich_spibar + 0x9C)); |
| 1182 | ichspi_bbar = mmio_readl(ich_spibar + 0xA0); |
| 1183 | msg_pdbg("0xA0: 0x%08x (BBAR)\n", |
| 1184 | ichspi_bbar); |
| 1185 | msg_pdbg("0xB0: 0x%08x (FDOC)\n", |
| 1186 | mmio_readl(ich_spibar + 0xB0)); |
| 1187 | if (tmp2 & (1 << 15)) { |
| 1188 | msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); |
| 1189 | ichspi_lock = 1; |
| 1190 | } |
| 1191 | ich_init_opcodes(); |
| 1192 | break; |
| 1193 | default: |
| 1194 | /* Nothing */ |
| 1195 | break; |
| 1196 | } |
| 1197 | |
| 1198 | old = pci_read_byte(dev, 0xdc); |
| 1199 | msg_pdbg("SPI Read Configuration: "); |
| 1200 | new = (old >> 2) & 0x3; |
| 1201 | switch (new) { |
| 1202 | case 0: |
| 1203 | case 1: |
| 1204 | case 2: |
| 1205 | msg_pdbg("prefetching %sabled, caching %sabled, ", |
| 1206 | (new & 0x2) ? "en" : "dis", |
| 1207 | (new & 0x1) ? "dis" : "en"); |
| 1208 | break; |
| 1209 | default: |
| 1210 | msg_pdbg("invalid prefetching/caching settings, "); |
| 1211 | break; |
| 1212 | } |
| 1213 | return 0; |
| 1214 | } |
| 1215 | |
| 1216 | int via_init_spi(struct pci_dev *dev) |
| 1217 | { |
| 1218 | uint32_t mmio_base; |
Carl-Daniel Hailfinger | 841d631 | 2010-11-24 23:37:22 +0000 | [diff] [blame] | 1219 | int i; |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1220 | |
| 1221 | mmio_base = (pci_read_long(dev, 0xbc)) << 8; |
| 1222 | msg_pdbg("MMIO base at = 0x%x\n", mmio_base); |
| 1223 | ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); |
| 1224 | |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1225 | /* Not sure if it speaks all these bus protocols. */ |
| 1226 | buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; |
| 1227 | spi_controller = SPI_CONTROLLER_VIA; |
Carl-Daniel Hailfinger | 841d631 | 2010-11-24 23:37:22 +0000 | [diff] [blame] | 1228 | |
| 1229 | msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); |
| 1230 | msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2)); |
| 1231 | msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(ich_spibar + 4)); |
| 1232 | for (i = 0; i < 2; i++) { |
| 1233 | int offs; |
| 1234 | offs = 8 + (i * 8); |
| 1235 | msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs, |
| 1236 | mmio_readl(ich_spibar + offs), i); |
| 1237 | msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, |
| 1238 | mmio_readl(ich_spibar + offs + 4), i); |
| 1239 | } |
| 1240 | ichspi_bbar = mmio_readl(ich_spibar + 0x50); |
| 1241 | msg_pdbg("0x50: 0x%08x (BBAR)\n", ichspi_bbar); |
| 1242 | msg_pdbg("0x54: 0x%04x (PREOP)\n", mmio_readw(ich_spibar + 0x54)); |
| 1243 | msg_pdbg("0x56: 0x%04x (OPTYPE)\n", mmio_readw(ich_spibar + 0x56)); |
| 1244 | msg_pdbg("0x58: 0x%08x (OPMENU)\n", mmio_readl(ich_spibar + 0x58)); |
| 1245 | msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + 0x5c)); |
| 1246 | for (i = 0; i < 3; i++) { |
| 1247 | int offs; |
| 1248 | offs = 0x60 + (i * 4); |
| 1249 | msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, |
| 1250 | mmio_readl(ich_spibar + offs), i); |
| 1251 | } |
| 1252 | msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n", |
| 1253 | mmio_readw(ich_spibar + 0x6c)); |
| 1254 | if (mmio_readw(ich_spibar) & (1 << 15)) { |
| 1255 | msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); |
| 1256 | ichspi_lock = 1; |
| 1257 | } |
| 1258 | |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1259 | ich_init_opcodes(); |
| 1260 | |
| 1261 | return 0; |
| 1262 | } |
| 1263 | |
Carl-Daniel Hailfinger | cceafa2 | 2010-05-26 01:45:41 +0000 | [diff] [blame] | 1264 | #endif |