blob: a30ca021f2faac8cf781dc9fcbbd1197693cc846 [file] [log] [blame]
Dominik Geyerb46acba2008-05-16 12:55:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2008 Stefan Wildemann <stefan.wildemann@kontron.com>
5 * Copyright (C) 2008 Claus Gindhart <claus.gindhart@kontron.com>
6 * Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com>
Stefan Reinauera9424d52008-06-27 16:28:34 +00007 * Copyright (C) 2008 coresystems GmbH <info@coresystems.de>
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +00008 * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
Stefan Tauner8b391b82011-08-09 01:49:34 +00009 * Copyright (C) 2011 Stefan Tauner
Dominik Geyerb46acba2008-05-16 12:55:55 +000010 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
Dominik Geyerb46acba2008-05-16 12:55:55 +000020 */
21
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000022#if defined(__i386__) || defined(__x86_64__)
23
Dominik Geyerb46acba2008-05-16 12:55:55 +000024#include <string.h>
Stefan Taunerd0c5dc22011-10-20 12:57:14 +000025#include <stdlib.h>
Dominik Geyerb46acba2008-05-16 12:55:55 +000026#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000027#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000028#include "hwaccess.h"
Dominik Geyerb46acba2008-05-16 12:55:55 +000029#include "spi.h"
Stefan Tauner1e146392011-09-15 23:52:55 +000030#include "ich_descriptors.h"
Dominik Geyerb46acba2008-05-16 12:55:55 +000031
Nico Huberd54e4f42017-03-23 23:45:47 +010032/* Sunrise Point */
33
34/* Added HSFS Status bits */
35#define HSFS_WRSDIS_OFF 11 /* 11: Flash Configuration Lock-Down */
36#define HSFS_WRSDIS (0x1 << HSFS_WRSDIS_OFF)
37#define HSFS_PRR34_LOCKDN_OFF 12 /* 12: PRR3 PRR4 Lock-Down */
38#define HSFS_PRR34_LOCKDN (0x1 << HSFS_PRR34_LOCKDN_OFF)
39/* HSFS_BERASE vanished */
40
41/*
42 * HSFC and HSFS 16-bit registers are combined into the 32-bit
43 * BIOS_HSFSTS_CTL register in the Sunrise Point datasheet,
44 * however we still treat them separately in order to reuse code.
45 */
46
47/* Changed HSFC Control bits */
48#define PCH100_HSFC_FCYCLE_OFF (17 - 16) /* 1-4: FLASH Cycle */
49#define PCH100_HSFC_FCYCLE (0xf << PCH100_HSFC_FCYCLE_OFF)
50/* New HSFC Control bit */
51#define HSFC_WET_OFF (21 - 16) /* 5: Write Enable Type */
52#define HSFC_WET (0x1 << HSFC_WET_OFF)
53
54#define PCH100_FADDR_FLA 0x07ffffff
55
56#define PCH100_REG_DLOCK 0x0c /* 32 Bits Discrete Lock Bits */
57#define DLOCK_BMWAG_LOCKDN_OFF 0
58#define DLOCK_BMWAG_LOCKDN (0x1 << DLOCK_BMWAG_LOCKDN_OFF)
59#define DLOCK_BMRAG_LOCKDN_OFF 1
60#define DLOCK_BMRAG_LOCKDN (0x1 << DLOCK_BMRAG_LOCKDN_OFF)
61#define DLOCK_SBMWAG_LOCKDN_OFF 2
62#define DLOCK_SBMWAG_LOCKDN (0x1 << DLOCK_SBMWAG_LOCKDN_OFF)
63#define DLOCK_SBMRAG_LOCKDN_OFF 3
64#define DLOCK_SBMRAG_LOCKDN (0x1 << DLOCK_SBMRAG_LOCKDN_OFF)
65#define DLOCK_PR0_LOCKDN_OFF 8
66#define DLOCK_PR0_LOCKDN (0x1 << DLOCK_PR0_LOCKDN_OFF)
67#define DLOCK_PR1_LOCKDN_OFF 9
68#define DLOCK_PR1_LOCKDN (0x1 << DLOCK_PR1_LOCKDN_OFF)
69#define DLOCK_PR2_LOCKDN_OFF 10
70#define DLOCK_PR2_LOCKDN (0x1 << DLOCK_PR2_LOCKDN_OFF)
71#define DLOCK_PR3_LOCKDN_OFF 11
72#define DLOCK_PR3_LOCKDN (0x1 << DLOCK_PR3_LOCKDN_OFF)
73#define DLOCK_PR4_LOCKDN_OFF 12
74#define DLOCK_PR4_LOCKDN (0x1 << DLOCK_PR4_LOCKDN_OFF)
75#define DLOCK_SSEQ_LOCKDN_OFF 16
76#define DLOCK_SSEQ_LOCKDN (0x1 << DLOCK_SSEQ_LOCKDN_OFF)
77
78#define PCH100_REG_FPR0 0x84 /* 32 Bits Protected Range 0 */
79#define PCH100_REG_GPR0 0x98 /* 32 Bits Global Protected Range 0 */
80
81#define PCH100_REG_SSFSC 0xA0 /* 32 Bits Status (8) + Control (24) */
82#define PCH100_REG_PREOP 0xA4 /* 16 Bits */
83#define PCH100_REG_OPTYPE 0xA6 /* 16 Bits */
84#define PCH100_REG_OPMENU 0xA8 /* 64 Bits */
85
Stefan Reinauera9424d52008-06-27 16:28:34 +000086/* ICH9 controller register definition */
Stefan Tauner55206942011-06-11 09:53:22 +000087#define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */
88#define HSFS_FDONE_OFF 0 /* 0: Flash Cycle Done */
89#define HSFS_FDONE (0x1 << HSFS_FDONE_OFF)
90#define HSFS_FCERR_OFF 1 /* 1: Flash Cycle Error */
91#define HSFS_FCERR (0x1 << HSFS_FCERR_OFF)
92#define HSFS_AEL_OFF 2 /* 2: Access Error Log */
93#define HSFS_AEL (0x1 << HSFS_AEL_OFF)
94#define HSFS_BERASE_OFF 3 /* 3-4: Block/Sector Erase Size */
95#define HSFS_BERASE (0x3 << HSFS_BERASE_OFF)
96#define HSFS_SCIP_OFF 5 /* 5: SPI Cycle In Progress */
97#define HSFS_SCIP (0x1 << HSFS_SCIP_OFF)
98 /* 6-12: reserved */
99#define HSFS_FDOPSS_OFF 13 /* 13: Flash Descriptor Override Pin-Strap Status */
100#define HSFS_FDOPSS (0x1 << HSFS_FDOPSS_OFF)
101#define HSFS_FDV_OFF 14 /* 14: Flash Descriptor Valid */
102#define HSFS_FDV (0x1 << HSFS_FDV_OFF)
103#define HSFS_FLOCKDN_OFF 15 /* 15: Flash Configuration Lock-Down */
104#define HSFS_FLOCKDN (0x1 << HSFS_FLOCKDN_OFF)
105
106#define ICH9_REG_HSFC 0x06 /* 16 Bits Hardware Sequencing Flash Control */
107#define HSFC_FGO_OFF 0 /* 0: Flash Cycle Go */
108#define HSFC_FGO (0x1 << HSFC_FGO_OFF)
109#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */
110#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
111 /* 3-7: reserved */
112#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
113#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)
114 /* 14: reserved */
115#define HSFC_SME_OFF 15 /* 15: SPI SMI# Enable */
116#define HSFC_SME (0x1 << HSFC_SME_OFF)
117
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000118#define ICH9_REG_FADDR 0x08 /* 32 Bits */
Nico Huberd54e4f42017-03-23 23:45:47 +0100119#define ICH9_FADDR_FLA 0x01ffffff
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000120#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000121
Stefan Tauner29c80832011-06-12 08:14:10 +0000122#define ICH9_REG_FRAP 0x50 /* 32 Bytes Flash Region Access Permissions */
123#define ICH9_REG_FREG0 0x54 /* 32 Bytes Flash Region 0 */
124
125#define ICH9_REG_PR0 0x74 /* 32 Bytes Protected Range 0 */
Stefan Taunerbf69aaa2011-09-17 21:21:48 +0000126#define PR_WP_OFF 31 /* 31: write protection enable */
127#define PR_RP_OFF 15 /* 15: read protection enable */
Stefan Tauner29c80832011-06-12 08:14:10 +0000128
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000129#define ICH9_REG_SSFS 0x90 /* 08 Bits */
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000130#define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */
131#define SSFS_SCIP (0x1 << SSFS_SCIP_OFF)
132#define SSFS_FDONE_OFF 2 /* Cycle Done Status */
133#define SSFS_FDONE (0x1 << SSFS_FDONE_OFF)
134#define SSFS_FCERR_OFF 3 /* Flash Cycle Error */
135#define SSFS_FCERR (0x1 << SSFS_FCERR_OFF)
136#define SSFS_AEL_OFF 4 /* Access Error Log */
137#define SSFS_AEL (0x1 << SSFS_AEL_OFF)
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000138/* The following bits are reserved in SSFS: 1,5-7. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000139#define SSFS_RESERVED_MASK 0x000000e2
Stefan Reinauera9424d52008-06-27 16:28:34 +0000140
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000141#define ICH9_REG_SSFC 0x91 /* 24 Bits */
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000142/* We combine SSFS and SSFC to one 32-bit word,
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000143 * therefore SSFC bits are off by 8. */
144 /* 0: reserved */
145#define SSFC_SCGO_OFF (1 + 8) /* 1: SPI Cycle Go */
146#define SSFC_SCGO (0x1 << SSFC_SCGO_OFF)
147#define SSFC_ACS_OFF (2 + 8) /* 2: Atomic Cycle Sequence */
148#define SSFC_ACS (0x1 << SSFC_ACS_OFF)
149#define SSFC_SPOP_OFF (3 + 8) /* 3: Sequence Prefix Opcode Pointer */
150#define SSFC_SPOP (0x1 << SSFC_SPOP_OFF)
151#define SSFC_COP_OFF (4 + 8) /* 4-6: Cycle Opcode Pointer */
152#define SSFC_COP (0x7 << SSFC_COP_OFF)
153 /* 7: reserved */
154#define SSFC_DBC_OFF (8 + 8) /* 8-13: Data Byte Count */
155#define SSFC_DBC (0x3f << SSFC_DBC_OFF)
156#define SSFC_DS_OFF (14 + 8) /* 14: Data Cycle */
157#define SSFC_DS (0x1 << SSFC_DS_OFF)
158#define SSFC_SME_OFF (15 + 8) /* 15: SPI SMI# Enable */
159#define SSFC_SME (0x1 << SSFC_SME_OFF)
160#define SSFC_SCF_OFF (16 + 8) /* 16-18: SPI Cycle Frequency */
161#define SSFC_SCF (0x7 << SSFC_SCF_OFF)
162#define SSFC_SCF_20MHZ 0x00000000
163#define SSFC_SCF_33MHZ 0x01000000
164 /* 19-23: reserved */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000165#define SSFC_RESERVED_MASK 0xf8008100
Stefan Reinauera9424d52008-06-27 16:28:34 +0000166
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000167#define ICH9_REG_PREOP 0x94 /* 16 Bits */
168#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */
169#define ICH9_REG_OPMENU 0x98 /* 64 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000170
Stefan Tauner29c80832011-06-12 08:14:10 +0000171#define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */
172#define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */
173
Stefan Tauner1e146392011-09-15 23:52:55 +0000174#define ICH8_REG_VSCC 0xC1 /* 32 Bits Vendor Specific Component Capabilities */
175#define ICH9_REG_LVSCC 0xC4 /* 32 Bits Host Lower Vendor Specific Component Capabilities */
176#define ICH9_REG_UVSCC 0xC8 /* 32 Bits Host Upper Vendor Specific Component Capabilities */
177/* The individual fields of the VSCC registers are defined in the file
178 * ich_descriptors.h. The reason is that the same layout is also used in the
179 * flash descriptor to define the properties of the different flash chips
180 * supported. The BIOS (or the ME?) is responsible to populate the ICH registers
181 * with the information from the descriptor on startup depending on the actual
182 * chip(s) detected. */
183
Stefan Taunerbd649e42011-07-01 00:39:16 +0000184#define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */
185#define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */
186#define FPB_FPBA (0x1FFF << FPB_FPBA_OFF)
187
Dominik Geyerb46acba2008-05-16 12:55:55 +0000188// ICH9R SPI commands
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000189#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
190#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
191#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
192#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
Dominik Geyerb46acba2008-05-16 12:55:55 +0000193
Stefan Reinauera9424d52008-06-27 16:28:34 +0000194// ICH7 registers
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000195#define ICH7_REG_SPIS 0x00 /* 16 Bits */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000196#define SPIS_SCIP 0x0001
197#define SPIS_GRANT 0x0002
198#define SPIS_CDS 0x0004
199#define SPIS_FCERR 0x0008
200#define SPIS_RESERVED_MASK 0x7ff0
Stefan Reinauera9424d52008-06-27 16:28:34 +0000201
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000202/* VIA SPI is compatible with ICH7, but maxdata
203 to transfer is 16 bytes.
204
205 DATA byte count on ICH7 is 8:13, on VIA 8:11
206
207 bit 12 is port select CS0 CS1
208 bit 13 is FAST READ enable
209 bit 7 is used with fast read and one shot controls CS de-assert?
210*/
211
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000212#define ICH7_REG_SPIC 0x02 /* 16 Bits */
213#define SPIC_SCGO 0x0002
214#define SPIC_ACS 0x0004
215#define SPIC_SPOP 0x0008
216#define SPIC_DS 0x4000
Stefan Reinauera9424d52008-06-27 16:28:34 +0000217
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000218#define ICH7_REG_SPIA 0x04 /* 32 Bits */
219#define ICH7_REG_SPID0 0x08 /* 64 Bytes */
220#define ICH7_REG_PREOP 0x54 /* 16 Bits */
221#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */
222#define ICH7_REG_OPMENU 0x58 /* 64 Bits */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000223
Nico Huber7590d1a2016-05-03 13:38:28 +0200224enum ich_access_protection {
225 NO_PROT = 0,
226 READ_PROT = 1,
227 WRITE_PROT = 2,
228 LOCKED = 3,
229};
230
FENG yu ningc05a2952008-12-08 18:16:58 +0000231/* ICH SPI configuration lock-down. May be set during chipset enabling. */
Michael Karchera4448d92010-07-22 18:04:15 +0000232static int ichspi_lock = 0;
FENG yu ningc05a2952008-12-08 18:16:58 +0000233
Stefan Taunera8d838d2011-11-06 23:51:09 +0000234static enum ich_chipset ich_generation = CHIPSET_ICH_UNKNOWN;
Nico Hubered098d62017-04-21 23:47:08 +0200235static uint32_t ichspi_bbar;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000236
Michael Karchera4448d92010-07-22 18:04:15 +0000237static void *ich_spibar = NULL;
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000238
Dominik Geyerb46acba2008-05-16 12:55:55 +0000239typedef struct _OPCODE {
240 uint8_t opcode; //This commands spi opcode
241 uint8_t spi_type; //This commands spi type
242 uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1
243} OPCODE;
244
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000245/* Suggested opcode definition:
Dominik Geyerb46acba2008-05-16 12:55:55 +0000246 * Preop 1: Write Enable
247 * Preop 2: Write Status register enable
248 *
249 * OP 0: Write address
250 * OP 1: Read Address
251 * OP 2: ERASE block
252 * OP 3: Read Status register
253 * OP 4: Read ID
254 * OP 5: Write Status register
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000255 * OP 6: chip private (read JEDEC id)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000256 * OP 7: Chip erase
257 */
258typedef struct _OPCODES {
259 uint8_t preop[2];
260 OPCODE opcode[8];
261} OPCODES;
262
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000263static OPCODES *curopcodes = NULL;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000264
265/* HW access functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000266static uint32_t REGREAD32(int X)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000267{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000268 return mmio_readl(ich_spibar + X);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000269}
270
Uwe Hermann09e04f72009-05-16 22:36:00 +0000271static uint16_t REGREAD16(int X)
Stefan Reinauera9424d52008-06-27 16:28:34 +0000272{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000273 return mmio_readw(ich_spibar + X);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000274}
275
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000276static uint16_t REGREAD8(int X)
277{
278 return mmio_readb(ich_spibar + X);
279}
280
Stefan Taunerccd92a12011-07-01 00:39:01 +0000281#define REGWRITE32(off, val) mmio_writel(val, ich_spibar+(off))
282#define REGWRITE16(off, val) mmio_writew(val, ich_spibar+(off))
283#define REGWRITE8(off, val) mmio_writeb(val, ich_spibar+(off))
Dominik Geyerb46acba2008-05-16 12:55:55 +0000284
Dominik Geyerb46acba2008-05-16 12:55:55 +0000285/* Common SPI functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000286static int find_opcode(OPCODES *op, uint8_t opcode);
287static int find_preop(OPCODES *op, uint8_t preop);
FENG yu ningf041e9b2008-12-15 02:32:11 +0000288static int generate_opcodes(OPCODES * op);
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000289static int program_opcodes(OPCODES *op, int enable_undo);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000290static int run_opcode(const struct flashctx *flash, OPCODE op, uint32_t offset,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000291 uint8_t datalength, uint8_t * data);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000292
FENG yu ningf041e9b2008-12-15 02:32:11 +0000293/* for pairing opcodes with their required preop */
294struct preop_opcode_pair {
295 uint8_t preop;
296 uint8_t opcode;
297};
298
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000299/* List of opcodes which need preopcodes and matching preopcodes. Unused. */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000300const struct preop_opcode_pair pops[] = {
FENG yu ningf041e9b2008-12-15 02:32:11 +0000301 {JEDEC_WREN, JEDEC_BYTE_PROGRAM},
302 {JEDEC_WREN, JEDEC_SE}, /* sector erase */
303 {JEDEC_WREN, JEDEC_BE_52}, /* block erase */
304 {JEDEC_WREN, JEDEC_BE_D8}, /* block erase */
305 {JEDEC_WREN, JEDEC_CE_60}, /* chip erase */
306 {JEDEC_WREN, JEDEC_CE_C7}, /* chip erase */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000307 /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */
308 {JEDEC_WREN, JEDEC_WRSR},
FENG yu ningf041e9b2008-12-15 02:32:11 +0000309 {JEDEC_EWSR, JEDEC_WRSR},
310 {0,}
311};
312
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000313/* Reasonable default configuration. Needs ad-hoc modifications if we
314 * encounter unlisted opcodes. Fun.
315 */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000316static OPCODES O_ST_M25P = {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000317 {
318 JEDEC_WREN,
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000319 JEDEC_EWSR,
320 },
Dominik Geyerb46acba2008-05-16 12:55:55 +0000321 {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000322 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000323 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000324 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000325 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
Carl-Daniel Hailfinger15aa7c62009-05-26 21:25:08 +0000326 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000327 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000328 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000329 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
330 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000331};
332
Helge Wagner738e2522010-10-05 22:06:05 +0000333/* List of opcodes with their corresponding spi_type
334 * It is used to reprogram the chipset OPCODE table on-the-fly if an opcode
335 * is needed which is currently not in the chipset OPCODE table
336 */
337static OPCODE POSSIBLE_OPCODES[] = {
338 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
339 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
340 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
341 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
342 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
343 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
344 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
345 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
346 {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Sector erase
347 {JEDEC_BE_52, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Block erase
348 {JEDEC_AAI_WORD_PROGRAM, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Auto Address Increment
349};
350
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000351static OPCODES O_EXISTING = {};
FENG yu ningc05a2952008-12-08 18:16:58 +0000352
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000353/* pretty printing functions */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000354static void prettyprint_opcodes(OPCODES *ops)
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000355{
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000356 OPCODE oc;
357 const char *t;
358 const char *a;
359 uint8_t i;
360 static const char *const spi_type[4] = {
361 "read w/o addr",
362 "write w/o addr",
363 "read w/ addr",
364 "write w/ addr"
365 };
366 static const char *const atomic_type[3] = {
367 "none",
368 " 0 ",
369 " 1 "
370 };
371
372 if (ops == NULL)
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000373 return;
374
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000375 msg_pdbg2(" OP Type Pre-OP\n");
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000376 for (i = 0; i < 8; i++) {
377 oc = ops->opcode[i];
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000378 t = (oc.spi_type > 3) ? "invalid" : spi_type[oc.spi_type];
379 a = (oc.atomic > 2) ? "invalid" : atomic_type[oc.atomic];
380 msg_pdbg2("op[%d]: 0x%02x, %s, %s\n", i, oc.opcode, t, a);
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000381 }
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000382 msg_pdbg2("Pre-OP 0: 0x%02x, Pre-OP 1: 0x%02x\n", ops->preop[0],
383 ops->preop[1]);
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000384}
385
Nico Huberd54e4f42017-03-23 23:45:47 +0100386#define _pprint_reg(bit, mask, off, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & mask) >> off)
387#define pprint_reg(reg, bit, val, sep) _pprint_reg(bit, reg##_##bit, reg##_##bit##_OFF, val, sep)
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000388
Stefan Tauner55206942011-06-11 09:53:22 +0000389static void prettyprint_ich9_reg_hsfs(uint16_t reg_val)
390{
391 msg_pdbg("HSFS: ");
392 pprint_reg(HSFS, FDONE, reg_val, ", ");
393 pprint_reg(HSFS, FCERR, reg_val, ", ");
394 pprint_reg(HSFS, AEL, reg_val, ", ");
David Hendricksa5216362017-08-08 20:02:22 -0700395 if (ich_generation != CHIPSET_100_SERIES_SUNRISE_POINT &&
396 ich_generation != CHIPSET_C620_SERIES_LEWISBURG) {
Nico Huberd54e4f42017-03-23 23:45:47 +0100397 pprint_reg(HSFS, BERASE, reg_val, ", ");
398 }
Stefan Tauner55206942011-06-11 09:53:22 +0000399 pprint_reg(HSFS, SCIP, reg_val, ", ");
David Hendricksa5216362017-08-08 20:02:22 -0700400 if (ich_generation == CHIPSET_100_SERIES_SUNRISE_POINT ||
401 ich_generation == CHIPSET_C620_SERIES_LEWISBURG) {
Nico Huberd54e4f42017-03-23 23:45:47 +0100402 pprint_reg(HSFS, PRR34_LOCKDN, reg_val, ", ");
403 pprint_reg(HSFS, WRSDIS, reg_val, ", ");
404 }
Stefan Tauner55206942011-06-11 09:53:22 +0000405 pprint_reg(HSFS, FDOPSS, reg_val, ", ");
406 pprint_reg(HSFS, FDV, reg_val, ", ");
407 pprint_reg(HSFS, FLOCKDN, reg_val, "\n");
408}
409
410static void prettyprint_ich9_reg_hsfc(uint16_t reg_val)
411{
412 msg_pdbg("HSFC: ");
413 pprint_reg(HSFC, FGO, reg_val, ", ");
David Hendricksa5216362017-08-08 20:02:22 -0700414 if (ich_generation != CHIPSET_100_SERIES_SUNRISE_POINT &&
415 ich_generation != CHIPSET_C620_SERIES_LEWISBURG) {
Nico Huberd54e4f42017-03-23 23:45:47 +0100416 pprint_reg(HSFC, FCYCLE, reg_val, ", ");
417 } else {
418 _pprint_reg(HSFC, PCH100_HSFC_FCYCLE, PCH100_HSFC_FCYCLE_OFF, reg_val, ", ");
419 pprint_reg(HSFC, WET, reg_val, ", ");
420 }
Stefan Tauner55206942011-06-11 09:53:22 +0000421 pprint_reg(HSFC, FDBC, reg_val, ", ");
422 pprint_reg(HSFC, SME, reg_val, "\n");
423}
424
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000425static void prettyprint_ich9_reg_ssfs(uint32_t reg_val)
426{
427 msg_pdbg("SSFS: ");
428 pprint_reg(SSFS, SCIP, reg_val, ", ");
429 pprint_reg(SSFS, FDONE, reg_val, ", ");
430 pprint_reg(SSFS, FCERR, reg_val, ", ");
431 pprint_reg(SSFS, AEL, reg_val, "\n");
432}
433
434static void prettyprint_ich9_reg_ssfc(uint32_t reg_val)
435{
436 msg_pdbg("SSFC: ");
437 pprint_reg(SSFC, SCGO, reg_val, ", ");
438 pprint_reg(SSFC, ACS, reg_val, ", ");
439 pprint_reg(SSFC, SPOP, reg_val, ", ");
440 pprint_reg(SSFC, COP, reg_val, ", ");
441 pprint_reg(SSFC, DBC, reg_val, ", ");
442 pprint_reg(SSFC, SME, reg_val, ", ");
443 pprint_reg(SSFC, SCF, reg_val, "\n");
444}
445
Nico Huberd54e4f42017-03-23 23:45:47 +0100446static void prettyprint_pch100_reg_dlock(const uint32_t reg_val)
447{
448 msg_pdbg("DLOCK: ");
449 pprint_reg(DLOCK, BMWAG_LOCKDN, reg_val, ", ");
450 pprint_reg(DLOCK, BMRAG_LOCKDN, reg_val, ", ");
451 pprint_reg(DLOCK, SBMWAG_LOCKDN, reg_val, ", ");
452 pprint_reg(DLOCK, SBMRAG_LOCKDN, reg_val, ",\n ");
453 pprint_reg(DLOCK, PR0_LOCKDN, reg_val, ", ");
454 pprint_reg(DLOCK, PR1_LOCKDN, reg_val, ", ");
455 pprint_reg(DLOCK, PR2_LOCKDN, reg_val, ", ");
456 pprint_reg(DLOCK, PR3_LOCKDN, reg_val, ", ");
457 pprint_reg(DLOCK, PR4_LOCKDN, reg_val, ",\n ");
458 pprint_reg(DLOCK, SSEQ_LOCKDN, reg_val, "\n");
459}
460
461static struct {
462 size_t reg_ssfsc;
463 size_t reg_preop;
464 size_t reg_optype;
465 size_t reg_opmenu;
466} swseq_data;
467
Helge Wagner738e2522010-10-05 22:06:05 +0000468static uint8_t lookup_spi_type(uint8_t opcode)
469{
470 int a;
471
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000472 for (a = 0; a < ARRAY_SIZE(POSSIBLE_OPCODES); a++) {
Helge Wagner738e2522010-10-05 22:06:05 +0000473 if (POSSIBLE_OPCODES[a].opcode == opcode)
474 return POSSIBLE_OPCODES[a].spi_type;
475 }
476
477 return 0xFF;
478}
479
480static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt)
481{
482 uint8_t spi_type;
483
484 spi_type = lookup_spi_type(opcode);
485 if (spi_type > 3) {
486 /* Try to guess spi type from read/write sizes.
487 * The following valid writecnt/readcnt combinations exist:
488 * writecnt = 4, readcnt >= 0
489 * writecnt = 1, readcnt >= 0
490 * writecnt >= 4, readcnt = 0
491 * writecnt >= 1, readcnt = 0
492 * writecnt >= 1 is guaranteed for all commands.
493 */
494 if (readcnt == 0)
495 /* if readcnt=0 and writecount >= 4, we don't know if it is WRITE_NO_ADDRESS
496 * or WRITE_WITH_ADDRESS. But if we use WRITE_NO_ADDRESS and the first 3 data
497 * bytes are actual the address, they go to the bus anyhow
498 */
499 spi_type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
500 else if (writecnt == 1) // and readcnt is > 0
501 spi_type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
502 else if (writecnt == 4) // and readcnt is > 0
503 spi_type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
Stefan Taunerdc704ed2012-05-06 15:11:26 +0000504 else // we have an invalid case
505 return SPI_INVALID_LENGTH;
Helge Wagner738e2522010-10-05 22:06:05 +0000506 }
Stefan Taunerdc704ed2012-05-06 15:11:26 +0000507 int oppos = 2; // use original JEDEC_BE_D8 offset
508 curopcodes->opcode[oppos].opcode = opcode;
509 curopcodes->opcode[oppos].spi_type = spi_type;
510 program_opcodes(curopcodes, 0);
511 oppos = find_opcode(curopcodes, opcode);
Stefan Taunerd94d25d2012-07-28 03:17:15 +0000512 msg_pdbg2("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos);
Stefan Taunerdc704ed2012-05-06 15:11:26 +0000513 return oppos;
Helge Wagner738e2522010-10-05 22:06:05 +0000514}
515
Uwe Hermann09e04f72009-05-16 22:36:00 +0000516static int find_opcode(OPCODES *op, uint8_t opcode)
FENG yu ningc05a2952008-12-08 18:16:58 +0000517{
518 int a;
519
Stefan Tauner50e7c602011-11-08 10:55:54 +0000520 if (op == NULL) {
521 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
522 return -1;
523 }
524
FENG yu ningc05a2952008-12-08 18:16:58 +0000525 for (a = 0; a < 8; a++) {
526 if (op->opcode[a].opcode == opcode)
527 return a;
528 }
529
530 return -1;
531}
532
Uwe Hermann09e04f72009-05-16 22:36:00 +0000533static int find_preop(OPCODES *op, uint8_t preop)
FENG yu ningc05a2952008-12-08 18:16:58 +0000534{
535 int a;
536
Stefan Tauner50e7c602011-11-08 10:55:54 +0000537 if (op == NULL) {
538 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
539 return -1;
540 }
541
FENG yu ningc05a2952008-12-08 18:16:58 +0000542 for (a = 0; a < 2; a++) {
543 if (op->preop[a] == preop)
544 return a;
545 }
546
547 return -1;
548}
549
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000550/* Create a struct OPCODES based on what we find in the locked down chipset. */
FENG yu ningf041e9b2008-12-15 02:32:11 +0000551static int generate_opcodes(OPCODES * op)
FENG yu ningc05a2952008-12-08 18:16:58 +0000552{
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000553 int a;
FENG yu ningc05a2952008-12-08 18:16:58 +0000554 uint16_t preop, optype;
555 uint32_t opmenu[2];
FENG yu ningc05a2952008-12-08 18:16:58 +0000556
557 if (op == NULL) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000558 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
FENG yu ningc05a2952008-12-08 18:16:58 +0000559 return -1;
560 }
561
Stefan Taunera8d838d2011-11-06 23:51:09 +0000562 switch (ich_generation) {
563 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000564 case CHIPSET_TUNNEL_CREEK:
565 case CHIPSET_CENTERTON:
FENG yu ningc05a2952008-12-08 18:16:58 +0000566 preop = REGREAD16(ICH7_REG_PREOP);
567 optype = REGREAD16(ICH7_REG_OPTYPE);
568 opmenu[0] = REGREAD32(ICH7_REG_OPMENU);
569 opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4);
570 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000571 case CHIPSET_ICH8:
572 default: /* Future version might behave the same */
Nico Huberd54e4f42017-03-23 23:45:47 +0100573 preop = REGREAD16(swseq_data.reg_preop);
574 optype = REGREAD16(swseq_data.reg_optype);
575 opmenu[0] = REGREAD32(swseq_data.reg_opmenu);
576 opmenu[1] = REGREAD32(swseq_data.reg_opmenu + 4);
FENG yu ningc05a2952008-12-08 18:16:58 +0000577 break;
FENG yu ningc05a2952008-12-08 18:16:58 +0000578 }
579
580 op->preop[0] = (uint8_t) preop;
581 op->preop[1] = (uint8_t) (preop >> 8);
582
583 for (a = 0; a < 8; a++) {
584 op->opcode[a].spi_type = (uint8_t) (optype & 0x3);
585 optype >>= 2;
586 }
587
588 for (a = 0; a < 4; a++) {
589 op->opcode[a].opcode = (uint8_t) (opmenu[0] & 0xff);
590 opmenu[0] >>= 8;
591 }
592
593 for (a = 4; a < 8; a++) {
594 op->opcode[a].opcode = (uint8_t) (opmenu[1] & 0xff);
595 opmenu[1] >>= 8;
596 }
597
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000598 /* No preopcodes used by default. */
599 for (a = 0; a < 8; a++)
FENG yu ningc05a2952008-12-08 18:16:58 +0000600 op->opcode[a].atomic = 0;
601
FENG yu ningc05a2952008-12-08 18:16:58 +0000602 return 0;
603}
604
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000605static int program_opcodes(OPCODES *op, int enable_undo)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000606{
607 uint8_t a;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000608 uint16_t preop, optype;
609 uint32_t opmenu[2];
Dominik Geyerb46acba2008-05-16 12:55:55 +0000610
611 /* Program Prefix Opcodes */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000612 /* 0:7 Prefix Opcode 1 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000613 preop = (op->preop[0]);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000614 /* 8:16 Prefix Opcode 2 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000615 preop |= ((uint16_t) op->preop[1]) << 8;
Uwe Hermann394131e2008-10-18 21:14:13 +0000616
Stefan Reinauera9424d52008-06-27 16:28:34 +0000617 /* Program Opcode Types 0 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000618 optype = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000619 for (a = 0; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000620 optype |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000621 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000622
Stefan Reinauera9424d52008-06-27 16:28:34 +0000623 /* Program Allowable Opcodes 0 - 3 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000624 opmenu[0] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000625 for (a = 0; a < 4; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000626 opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000627 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000628
Stefan Tauner92d6a862013-10-25 00:33:37 +0000629 /* Program Allowable Opcodes 4 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000630 opmenu[1] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000631 for (a = 4; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000632 opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000633 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000634
Stefan Taunerd94d25d2012-07-28 03:17:15 +0000635 msg_pdbg2("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]);
Stefan Taunera8d838d2011-11-06 23:51:09 +0000636 switch (ich_generation) {
637 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000638 case CHIPSET_TUNNEL_CREEK:
639 case CHIPSET_CENTERTON:
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000640 /* Register undo only for enable_undo=1, i.e. first call. */
641 if (enable_undo) {
642 rmmio_valw(ich_spibar + ICH7_REG_PREOP);
643 rmmio_valw(ich_spibar + ICH7_REG_OPTYPE);
644 rmmio_vall(ich_spibar + ICH7_REG_OPMENU);
645 rmmio_vall(ich_spibar + ICH7_REG_OPMENU + 4);
646 }
647 mmio_writew(preop, ich_spibar + ICH7_REG_PREOP);
648 mmio_writew(optype, ich_spibar + ICH7_REG_OPTYPE);
649 mmio_writel(opmenu[0], ich_spibar + ICH7_REG_OPMENU);
650 mmio_writel(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000651 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000652 case CHIPSET_ICH8:
653 default: /* Future version might behave the same */
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000654 /* Register undo only for enable_undo=1, i.e. first call. */
655 if (enable_undo) {
Nico Huberd54e4f42017-03-23 23:45:47 +0100656 rmmio_valw(ich_spibar + swseq_data.reg_preop);
657 rmmio_valw(ich_spibar + swseq_data.reg_optype);
658 rmmio_vall(ich_spibar + swseq_data.reg_opmenu);
659 rmmio_vall(ich_spibar + swseq_data.reg_opmenu + 4);
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000660 }
Nico Huberd54e4f42017-03-23 23:45:47 +0100661 mmio_writew(preop, ich_spibar + swseq_data.reg_preop);
662 mmio_writew(optype, ich_spibar + swseq_data.reg_optype);
663 mmio_writel(opmenu[0], ich_spibar + swseq_data.reg_opmenu);
664 mmio_writel(opmenu[1], ich_spibar + swseq_data.reg_opmenu + 4);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000665 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000666 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000667
668 return 0;
669}
670
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000671/*
Stefan Tauner50e7c602011-11-08 10:55:54 +0000672 * Returns -1 if at least one mandatory opcode is inaccessible, 0 otherwise.
673 * FIXME: this should also check for
674 * - at least one probing opcode (RDID (incl. AT25F variants?), REMS, RES?)
675 * - at least one erasing opcode (lots.)
676 * - at least one program opcode (BYTE_PROGRAM, AAI_WORD_PROGRAM, ...?)
677 * - necessary preops? (EWSR, WREN, ...?)
678 */
Richard Hughes93e16252018-12-19 11:54:47 +0000679static int ich_missing_opcodes(void)
Stefan Tauner50e7c602011-11-08 10:55:54 +0000680{
681 uint8_t ops[] = {
682 JEDEC_READ,
683 JEDEC_RDSR,
684 0
685 };
686 int i = 0;
687 while (ops[i] != 0) {
688 msg_pspew("checking for opcode 0x%02x\n", ops[i]);
689 if (find_opcode(curopcodes, ops[i]) == -1)
690 return -1;
691 i++;
692 }
693 return 0;
694}
695
696/*
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000697 * Try to set BBAR (BIOS Base Address Register), but read back the value in case
698 * it didn't stick.
699 */
Stefan Taunera8d838d2011-11-06 23:51:09 +0000700static void ich_set_bbar(uint32_t min_addr)
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000701{
Stefan Taunere27b2d42011-07-01 00:39:09 +0000702 int bbar_off;
Stefan Tauner7783f312011-09-17 21:21:42 +0000703 switch (ich_generation) {
Stefan Taunera8d838d2011-11-06 23:51:09 +0000704 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000705 case CHIPSET_TUNNEL_CREEK:
706 case CHIPSET_CENTERTON:
Stefan Taunere27b2d42011-07-01 00:39:09 +0000707 bbar_off = 0x50;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000708 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000709 case CHIPSET_ICH8:
Duncan Laurie4095ed72014-08-20 15:39:32 +0000710 case CHIPSET_BAYTRAIL:
711 msg_pdbg("BBAR offset is unknown!\n");
Stefan Tauner7783f312011-09-17 21:21:42 +0000712 return;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000713 case CHIPSET_ICH9:
Stefan Tauner7783f312011-09-17 21:21:42 +0000714 default: /* Future version might behave the same */
Stefan Taunere27b2d42011-07-01 00:39:09 +0000715 bbar_off = ICH9_REG_BBAR;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000716 break;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000717 }
Elyes HAOUAS124ef382018-03-27 12:15:09 +0200718
Stefan Taunere27b2d42011-07-01 00:39:09 +0000719 ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & ~BBAR_MASK;
720 if (ichspi_bbar) {
721 msg_pdbg("Reserved bits in BBAR not zero: 0x%08x\n",
722 ichspi_bbar);
723 }
724 min_addr &= BBAR_MASK;
725 ichspi_bbar |= min_addr;
726 rmmio_writel(ichspi_bbar, ich_spibar + bbar_off);
727 ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & BBAR_MASK;
728
729 /* We don't have any option except complaining. And if the write
730 * failed, the restore will fail as well, so no problem there.
731 */
732 if (ichspi_bbar != min_addr)
Stefan Tauner7783f312011-09-17 21:21:42 +0000733 msg_perr("Setting BBAR to 0x%08x failed! New value: 0x%08x.\n",
734 min_addr, ichspi_bbar);
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000735}
736
Stefan Tauner8b391b82011-08-09 01:49:34 +0000737/* Read len bytes from the fdata/spid register into the data array.
738 *
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000739 * Note that using len > flash->mst->spi.max_data_read will return garbage or
Stefan Tauner8b391b82011-08-09 01:49:34 +0000740 * may even crash.
741 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000742static void ich_read_data(uint8_t *data, int len, int reg0_off)
Elyes HAOUAS124ef382018-03-27 12:15:09 +0200743{
Stefan Tauner8b391b82011-08-09 01:49:34 +0000744 int i;
745 uint32_t temp32 = 0;
746
747 for (i = 0; i < len; i++) {
748 if ((i % 4) == 0)
749 temp32 = REGREAD32(reg0_off + i);
750
751 data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
752 }
753}
754
755/* Fill len bytes from the data array into the fdata/spid registers.
756 *
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000757 * Note that using len > flash->mst->spi.max_data_write will trash the registers
Stefan Tauner8b391b82011-08-09 01:49:34 +0000758 * following the data registers.
759 */
760static void ich_fill_data(const uint8_t *data, int len, int reg0_off)
761{
762 uint32_t temp32 = 0;
763 int i;
764
765 if (len <= 0)
766 return;
767
768 for (i = 0; i < len; i++) {
769 if ((i % 4) == 0)
770 temp32 = 0;
771
772 temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
773
774 if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
775 REGWRITE32(reg0_off + (i - (i % 4)), temp32);
776 }
777 i--;
778 if ((i % 4) != 3) /* Write remaining data to regs. */
779 REGWRITE32(reg0_off + (i - (i % 4)), temp32);
780}
781
FENG yu ningf041e9b2008-12-15 02:32:11 +0000782/* This function generates OPCODES from or programs OPCODES to ICH according to
783 * the chipset's SPI configuration lock.
FENG yu ningc05a2952008-12-08 18:16:58 +0000784 *
FENG yu ningf041e9b2008-12-15 02:32:11 +0000785 * It should be called before ICH sends any spi command.
FENG yu ningc05a2952008-12-08 18:16:58 +0000786 */
Michael Karchera4448d92010-07-22 18:04:15 +0000787static int ich_init_opcodes(void)
FENG yu ningc05a2952008-12-08 18:16:58 +0000788{
789 int rc = 0;
790 OPCODES *curopcodes_done;
791
792 if (curopcodes)
793 return 0;
794
795 if (ichspi_lock) {
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000796 msg_pdbg("Reading OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000797 curopcodes_done = &O_EXISTING;
FENG yu ningf041e9b2008-12-15 02:32:11 +0000798 rc = generate_opcodes(curopcodes_done);
FENG yu ningc05a2952008-12-08 18:16:58 +0000799 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000800 msg_pdbg("Programming OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000801 curopcodes_done = &O_ST_M25P;
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000802 rc = program_opcodes(curopcodes_done, 1);
FENG yu ningc05a2952008-12-08 18:16:58 +0000803 }
804
805 if (rc) {
806 curopcodes = NULL;
Sean Nelson316a29f2010-05-07 20:09:04 +0000807 msg_perr("failed\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000808 return 1;
809 } else {
810 curopcodes = curopcodes_done;
Sean Nelson316a29f2010-05-07 20:09:04 +0000811 msg_pdbg("done\n");
Stefan Tauner8b391b82011-08-09 01:49:34 +0000812 prettyprint_opcodes(curopcodes);
FENG yu ningc05a2952008-12-08 18:16:58 +0000813 return 0;
814 }
815}
816
Stefan Reinauer43119562008-11-02 19:51:50 +0000817static int ich7_run_opcode(OPCODE op, uint32_t offset,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000818 uint8_t datalength, uint8_t * data, int maxdata)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000819{
820 int write_cmd = 0;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000821 int timeout;
Stefan Tauner8b391b82011-08-09 01:49:34 +0000822 uint32_t temp32;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000823 uint16_t temp16;
Stefan Reinauer43119562008-11-02 19:51:50 +0000824 uint64_t opmenu;
825 int opcode_index;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000826
827 /* Is it a write command? */
828 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
829 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
830 write_cmd = 1;
831 }
832
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000833 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
834 while ((REGREAD16(ICH7_REG_SPIS) & SPIS_SCIP) && --timeout) {
835 programmer_delay(10);
836 }
837 if (!timeout) {
838 msg_perr("Error: SCIP never cleared!\n");
839 return 1;
840 }
841
Stefan Tauner10b3e222011-07-01 00:39:23 +0000842 /* Program offset in flash into SPIA while preserving reserved bits. */
843 temp32 = REGREAD32(ICH7_REG_SPIA) & ~0x00FFFFFF;
844 REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF) | temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000845
Stefan Tauner10b3e222011-07-01 00:39:23 +0000846 /* Program data into SPID0 to N */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000847 if (write_cmd && (datalength != 0))
848 ich_fill_data(data, datalength, ICH7_REG_SPID0);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000849
850 /* Assemble SPIS */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000851 temp16 = REGREAD16(ICH7_REG_SPIS);
852 /* keep reserved bits */
853 temp16 &= SPIS_RESERVED_MASK;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000854 /* clear error status registers */
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000855 temp16 |= (SPIS_CDS | SPIS_FCERR);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000856 REGWRITE16(ICH7_REG_SPIS, temp16);
857
858 /* Assemble SPIC */
859 temp16 = 0;
860
861 if (datalength != 0) {
862 temp16 |= SPIC_DS;
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000863 temp16 |= ((uint32_t) ((datalength - 1) & (maxdata - 1))) << 8;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000864 }
865
866 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000867 opmenu = REGREAD32(ICH7_REG_OPMENU);
868 opmenu |= ((uint64_t)REGREAD32(ICH7_REG_OPMENU + 4)) << 32;
869
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000870 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
871 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000872 break;
873 }
874 opmenu >>= 8;
875 }
876 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000877 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +0000878 return 1;
879 }
880 temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000881
Michael Karcher136125a2011-04-29 22:11:36 +0000882 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
883 /* Handle Atomic. Atomic commands include three steps:
884 - sending the preop (mainly EWSR or WREN)
885 - sending the main command
886 - waiting for the busy bit (WIP) to be cleared
887 This means the timeout must be sufficient for chip erase
888 of slow high-capacity chips.
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000889 */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000890 switch (op.atomic) {
891 case 2:
892 /* Select second preop. */
893 temp16 |= SPIC_SPOP;
Richard Hughesdb7482b2018-12-19 12:04:30 +0000894 /* Fall through. */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000895 case 1:
896 /* Atomic command (preop+op) */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000897 temp16 |= SPIC_ACS;
Michael Karcher136125a2011-04-29 22:11:36 +0000898 timeout = 100 * 1000 * 60; /* 60 seconds */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000899 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000900 }
901
902 /* Start */
903 temp16 |= SPIC_SCGO;
904
905 /* write it */
906 REGWRITE16(ICH7_REG_SPIC, temp16);
907
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000908 /* Wait for Cycle Done Status or Flash Cycle Error. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000909 while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) &&
910 --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000911 programmer_delay(10);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000912 }
913 if (!timeout) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000914 msg_perr("timeout, ICH7_REG_SPIS=0x%04x\n",
915 REGREAD16(ICH7_REG_SPIS));
916 return 1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000917 }
918
Sean Nelson316a29f2010-05-07 20:09:04 +0000919 /* FIXME: make sure we do not needlessly cause transaction errors. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000920 temp16 = REGREAD16(ICH7_REG_SPIS);
921 if (temp16 & SPIS_FCERR) {
Stefan Tauner8ed29342011-04-29 23:53:09 +0000922 msg_perr("Transaction error!\n");
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000923 /* keep reserved bits */
924 temp16 &= SPIS_RESERVED_MASK;
925 REGWRITE16(ICH7_REG_SPIS, temp16 | SPIS_FCERR);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000926 return 1;
927 }
928
Stefan Tauner8b391b82011-08-09 01:49:34 +0000929 if ((!write_cmd) && (datalength != 0))
930 ich_read_data(data, datalength, ICH7_REG_SPID0);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000931
932 return 0;
933}
934
Stefan Reinauer43119562008-11-02 19:51:50 +0000935static int ich9_run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000936 uint8_t datalength, uint8_t * data)
937{
938 int write_cmd = 0;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000939 int timeout;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000940 uint32_t temp32;
Stefan Reinauer43119562008-11-02 19:51:50 +0000941 uint64_t opmenu;
942 int opcode_index;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000943
944 /* Is it a write command? */
945 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
946 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
947 write_cmd = 1;
948 }
949
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000950 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
Nico Huberd54e4f42017-03-23 23:45:47 +0100951 while ((REGREAD8(swseq_data.reg_ssfsc) & SSFS_SCIP) && --timeout) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000952 programmer_delay(10);
953 }
954 if (!timeout) {
955 msg_perr("Error: SCIP never cleared!\n");
956 return 1;
957 }
958
Stefan Tauner10b3e222011-07-01 00:39:23 +0000959 /* Program offset in flash into FADDR while preserve the reserved bits
960 * and clearing the 25. address bit which is only useable in hwseq. */
961 temp32 = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF;
962 REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF) | temp32);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000963
964 /* Program data into FDATA0 to N */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000965 if (write_cmd && (datalength != 0))
966 ich_fill_data(data, datalength, ICH9_REG_FDATA0);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000967
968 /* Assemble SSFS + SSFC */
Nico Huberd54e4f42017-03-23 23:45:47 +0100969 temp32 = REGREAD32(swseq_data.reg_ssfsc);
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000970 /* Keep reserved bits only */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000971 temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000972 /* Clear cycle done and cycle error status registers */
973 temp32 |= (SSFS_FDONE | SSFS_FCERR);
Nico Huberd54e4f42017-03-23 23:45:47 +0100974 REGWRITE32(swseq_data.reg_ssfsc, temp32);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000975
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000976 /* Use 20 MHz */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000977 temp32 |= SSFC_SCF_20MHZ;
978
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000979 /* Set data byte count (DBC) and data cycle bit (DS) */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000980 if (datalength != 0) {
981 uint32_t datatemp;
982 temp32 |= SSFC_DS;
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000983 datatemp = ((((uint32_t)datalength - 1) << SSFC_DBC_OFF) &
984 SSFC_DBC);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000985 temp32 |= datatemp;
986 }
987
988 /* Select opcode */
Nico Huber8b2152d2017-08-31 13:18:49 +0200989 opmenu = REGREAD32(swseq_data.reg_opmenu);
990 opmenu |= ((uint64_t)REGREAD32(swseq_data.reg_opmenu + 4)) << 32;
Stefan Reinauer43119562008-11-02 19:51:50 +0000991
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000992 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
993 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000994 break;
995 }
996 opmenu >>= 8;
997 }
998 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000999 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +00001000 return 1;
1001 }
1002 temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001003
Michael Karcher136125a2011-04-29 22:11:36 +00001004 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
1005 /* Handle Atomic. Atomic commands include three steps:
1006 - sending the preop (mainly EWSR or WREN)
1007 - sending the main command
1008 - waiting for the busy bit (WIP) to be cleared
1009 This means the timeout must be sufficient for chip erase
1010 of slow high-capacity chips.
Stefan Taunerc0aaf952011-05-19 02:58:17 +00001011 */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001012 switch (op.atomic) {
1013 case 2:
1014 /* Select second preop. */
1015 temp32 |= SSFC_SPOP;
Richard Hughesdb7482b2018-12-19 12:04:30 +00001016 /* Fall through. */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001017 case 1:
1018 /* Atomic command (preop+op) */
Dominik Geyerb46acba2008-05-16 12:55:55 +00001019 temp32 |= SSFC_ACS;
Michael Karcher136125a2011-04-29 22:11:36 +00001020 timeout = 100 * 1000 * 60; /* 60 seconds */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001021 break;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001022 }
1023
1024 /* Start */
1025 temp32 |= SSFC_SCGO;
1026
1027 /* write it */
Nico Huberd54e4f42017-03-23 23:45:47 +01001028 REGWRITE32(swseq_data.reg_ssfsc, temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001029
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001030 /* Wait for Cycle Done Status or Flash Cycle Error. */
Nico Huberd54e4f42017-03-23 23:45:47 +01001031 while (((REGREAD32(swseq_data.reg_ssfsc) & (SSFS_FDONE | SSFS_FCERR)) == 0) &&
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001032 --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +00001033 programmer_delay(10);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +00001034 }
1035 if (!timeout) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001036 msg_perr("timeout, REG_SSFS=0x%08x\n",
1037 REGREAD32(swseq_data.reg_ssfsc));
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001038 return 1;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001039 }
1040
Sean Nelson316a29f2010-05-07 20:09:04 +00001041 /* FIXME make sure we do not needlessly cause transaction errors. */
Nico Huberd54e4f42017-03-23 23:45:47 +01001042 temp32 = REGREAD32(swseq_data.reg_ssfsc);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001043 if (temp32 & SSFS_FCERR) {
Stefan Tauner8ed29342011-04-29 23:53:09 +00001044 msg_perr("Transaction error!\n");
Stefan Tauner2a8b2622011-06-11 09:53:16 +00001045 prettyprint_ich9_reg_ssfs(temp32);
1046 prettyprint_ich9_reg_ssfc(temp32);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001047 /* keep reserved bits */
1048 temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
1049 /* Clear the transaction error. */
Nico Huberd54e4f42017-03-23 23:45:47 +01001050 REGWRITE32(swseq_data.reg_ssfsc, temp32 | SSFS_FCERR);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001051 return 1;
1052 }
1053
Stefan Tauner8b391b82011-08-09 01:49:34 +00001054 if ((!write_cmd) && (datalength != 0))
1055 ich_read_data(data, datalength, ICH9_REG_FDATA0);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001056
1057 return 0;
1058}
1059
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001060static int run_opcode(const struct flashctx *flash, OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +00001061 uint8_t datalength, uint8_t * data)
1062{
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001063 /* max_data_read == max_data_write for all Intel/VIA SPI masters */
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001064 uint8_t maxlength = flash->mst->spi.max_data_read;
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001065
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +00001066 if (ich_generation == CHIPSET_ICH_UNKNOWN) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001067 msg_perr("%s: unsupported chipset\n", __func__);
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001068 return -1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +00001069 }
Stefan Reinauera9424d52008-06-27 16:28:34 +00001070
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001071 if (datalength > maxlength) {
1072 msg_perr("%s: Internal command size error for "
1073 "opcode 0x%02x, got datalength=%i, want <=%i\n",
1074 __func__, op.opcode, datalength, maxlength);
1075 return SPI_INVALID_LENGTH;
1076 }
1077
Stefan Taunera8d838d2011-11-06 23:51:09 +00001078 switch (ich_generation) {
1079 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +00001080 case CHIPSET_TUNNEL_CREEK:
1081 case CHIPSET_CENTERTON:
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001082 return ich7_run_opcode(op, offset, datalength, data, maxlength);
Stefan Taunera8d838d2011-11-06 23:51:09 +00001083 case CHIPSET_ICH8:
1084 default: /* Future version might behave the same */
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001085 return ich9_run_opcode(op, offset, datalength, data);
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001086 }
Stefan Reinauera9424d52008-06-27 16:28:34 +00001087}
1088
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001089static int ich_spi_send_command(struct flashctx *flash, unsigned int writecnt,
1090 unsigned int readcnt,
1091 const unsigned char *writearr,
1092 unsigned char *readarr)
Dominik Geyerb46acba2008-05-16 12:55:55 +00001093{
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001094 int result;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001095 int opcode_index = -1;
1096 const unsigned char cmd = *writearr;
1097 OPCODE *opcode;
1098 uint32_t addr = 0;
1099 uint8_t *data;
1100 int count;
1101
Dominik Geyerb46acba2008-05-16 12:55:55 +00001102 /* find cmd in opcodes-table */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001103 opcode_index = find_opcode(curopcodes, cmd);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001104 if (opcode_index == -1) {
Helge Wagner738e2522010-10-05 22:06:05 +00001105 if (!ichspi_lock)
1106 opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt);
Stefan Taunerdc704ed2012-05-06 15:11:26 +00001107 if (opcode_index == SPI_INVALID_LENGTH) {
1108 msg_pdbg("OPCODE 0x%02x has unsupported length, will not execute.\n", cmd);
1109 return SPI_INVALID_LENGTH;
1110 } else if (opcode_index == -1) {
Stefan Tauner355cbfd2011-05-28 02:37:14 +00001111 msg_pdbg("Invalid OPCODE 0x%02x, will not execute.\n",
1112 cmd);
Helge Wagner738e2522010-10-05 22:06:05 +00001113 return SPI_INVALID_OPCODE;
1114 }
Dominik Geyerb46acba2008-05-16 12:55:55 +00001115 }
1116
1117 opcode = &(curopcodes->opcode[opcode_index]);
1118
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001119 /* The following valid writecnt/readcnt combinations exist:
1120 * writecnt = 4, readcnt >= 0
1121 * writecnt = 1, readcnt >= 0
1122 * writecnt >= 4, readcnt = 0
1123 * writecnt >= 1, readcnt = 0
1124 * writecnt >= 1 is guaranteed for all commands.
1125 */
1126 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) &&
1127 (writecnt != 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001128 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001129 "0x%02x, got writecnt=%i, want =4\n", __func__, cmd,
1130 writecnt);
1131 return SPI_INVALID_LENGTH;
1132 }
1133 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_NO_ADDRESS) &&
1134 (writecnt != 1)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001135 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001136 "0x%02x, got writecnt=%i, want =1\n", __func__, cmd,
1137 writecnt);
1138 return SPI_INVALID_LENGTH;
1139 }
1140 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) &&
1141 (writecnt < 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001142 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001143 "0x%02x, got writecnt=%i, want >=4\n", __func__, cmd,
1144 writecnt);
1145 return SPI_INVALID_LENGTH;
1146 }
1147 if (((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1148 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) &&
1149 (readcnt)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001150 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001151 "0x%02x, got readcnt=%i, want =0\n", __func__, cmd,
1152 readcnt);
1153 return SPI_INVALID_LENGTH;
1154 }
1155
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001156 /* Translate read/write array/count.
1157 * The maximum data length is identical for the maximum read length and
1158 * for the maximum write length excluding opcode and address. Opcode and
1159 * address are stored in separate registers, not in the data registers
1160 * and are thus not counted towards data length. The only exception
1161 * applies if the opcode definition (un)intentionally classifies said
1162 * opcode incorrectly as non-address opcode or vice versa. */
Dominik Geyerb46acba2008-05-16 12:55:55 +00001163 if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001164 data = (uint8_t *) (writearr + 1);
1165 count = writecnt - 1;
1166 } else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
1167 data = (uint8_t *) (writearr + 4);
1168 count = writecnt - 4;
1169 } else {
1170 data = (uint8_t *) readarr;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001171 count = readcnt;
1172 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001173
Nico Hubered098d62017-04-21 23:47:08 +02001174 /* if opcode-type requires an address */
1175 if (cmd == JEDEC_REMS || cmd == JEDEC_RES) {
1176 addr = ichspi_bbar;
1177 } else if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS ||
1178 opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
1179 /* BBAR may cut part of the chip off at the lower end. */
1180 const uint32_t valid_base = ichspi_bbar & ((flash->chip->total_size * 1024) - 1);
1181 const uint32_t addr_offset = ichspi_bbar - valid_base;
1182 /* Highest address we can program is (2^24 - 1). */
1183 const uint32_t valid_end = (1 << 24) - addr_offset;
1184
1185 addr = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
1186 const uint32_t addr_end = addr + count;
1187
1188 if (addr < valid_base ||
1189 addr_end < addr || /* integer overflow check */
1190 addr_end > valid_end) {
1191 msg_perr("%s: Addressed region 0x%06x-0x%06x not in allowed range 0x%06x-0x%06x\n",
1192 __func__, addr, addr_end - 1, valid_base, valid_end - 1);
1193 return SPI_INVALID_ADDRESS;
1194 }
1195 addr += addr_offset;
1196 }
1197
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001198 result = run_opcode(flash, *opcode, addr, count, data);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001199 if (result) {
Stefan Tauner8ed29342011-04-29 23:53:09 +00001200 msg_pdbg("Running OPCODE 0x%02x failed ", opcode->opcode);
1201 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1202 (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS)) {
1203 msg_pdbg("at address 0x%06x ", addr);
1204 }
1205 msg_pdbg("(payload length was %d).\n", count);
1206
1207 /* Print out the data array if it contains data to write.
1208 * Errors are detected before the received data is read back into
1209 * the array so it won't make sense to print it then. */
1210 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1211 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) {
1212 int i;
1213 msg_pspew("The data was:\n");
Stefan Taunerf382e352011-11-08 11:55:24 +00001214 for (i = 0; i < count; i++){
Stefan Tauner8ed29342011-04-29 23:53:09 +00001215 msg_pspew("%3d: 0x%02x\n", i, data[i]);
1216 }
1217 }
Dominik Geyerb46acba2008-05-16 12:55:55 +00001218 }
1219
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001220 return result;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001221}
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001222
Stefan Tauner50e7c602011-11-08 10:55:54 +00001223static struct hwseq_data {
1224 uint32_t size_comp0;
1225 uint32_t size_comp1;
Nico Huberd54e4f42017-03-23 23:45:47 +01001226 uint32_t addr_mask;
1227 bool only_4k;
1228 uint32_t hsfc_fcycle;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001229} hwseq_data;
1230
Nico Huberd54e4f42017-03-23 23:45:47 +01001231/* Sets FLA in FADDR to (addr & hwseq_data.addr_mask) without touching other bits. */
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001232static void ich_hwseq_set_addr(uint32_t addr)
1233{
Nico Huberd54e4f42017-03-23 23:45:47 +01001234 uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~hwseq_data.addr_mask;
1235 REGWRITE32(ICH9_REG_FADDR, (addr & hwseq_data.addr_mask) | addr_old);
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001236}
1237
1238/* Sets FADDR.FLA to 'addr' and returns the erase block size in bytes
1239 * of the block containing this address. May return nonsense if the address is
1240 * not valid. The erase block size for a specific address depends on the flash
1241 * partition layout as specified by FPB and the partition properties as defined
1242 * by UVSCC and LVSCC respectively. An alternative to implement this method
1243 * would be by querying FPB and the respective VSCC register directly.
1244 */
1245static uint32_t ich_hwseq_get_erase_block_size(unsigned int addr)
1246{
Nico Huberd54e4f42017-03-23 23:45:47 +01001247 if (hwseq_data.only_4k) {
1248 return 4 * 1024;
1249 } else {
1250 uint8_t enc_berase;
1251 static const uint32_t dec_berase[4] = {
1252 256,
1253 4 * 1024,
1254 8 * 1024,
1255 64 * 1024
1256 };
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001257
Nico Huberd54e4f42017-03-23 23:45:47 +01001258 ich_hwseq_set_addr(addr);
1259 enc_berase = (REGREAD16(ICH9_REG_HSFS) & HSFS_BERASE) >> HSFS_BERASE_OFF;
1260 return dec_berase[enc_berase];
1261 }
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001262}
1263
1264/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.
1265 Resets all error flags in HSFS.
1266 Returns 0 if the cycle completes successfully without errors within
1267 timeout us, 1 on errors. */
1268static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
1269 unsigned int len)
1270{
1271 uint16_t hsfs;
1272 uint32_t addr;
1273
1274 timeout /= 8; /* scale timeout duration to counter */
1275 while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) &
1276 (HSFS_FDONE | HSFS_FCERR)) == 0) &&
1277 --timeout) {
1278 programmer_delay(8);
1279 }
1280 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1281 if (!timeout) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001282 addr = REGREAD32(ICH9_REG_FADDR) & hwseq_data.addr_mask;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001283 msg_perr("Timeout error between offset 0x%08x and "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001284 "0x%08x (= 0x%08x + %d)!\n",
1285 addr, addr + len - 1, addr, len - 1);
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001286 prettyprint_ich9_reg_hsfs(hsfs);
1287 prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC));
1288 return 1;
1289 }
1290
1291 if (hsfs & HSFS_FCERR) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001292 addr = REGREAD32(ICH9_REG_FADDR) & hwseq_data.addr_mask;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001293 msg_perr("Transaction error between offset 0x%08x and "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001294 "0x%08x (= 0x%08x + %d)!\n",
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001295 addr, addr + len - 1, addr, len - 1);
1296 prettyprint_ich9_reg_hsfs(hsfs);
1297 prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC));
1298 return 1;
1299 }
1300 return 0;
1301}
Stefan Tauner50e7c602011-11-08 10:55:54 +00001302
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001303static int ich_hwseq_probe(struct flashctx *flash)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001304{
1305 uint32_t total_size, boundary;
1306 uint32_t erase_size_low, size_low, erase_size_high, size_high;
1307 struct block_eraser *eraser;
1308
1309 total_size = hwseq_data.size_comp0 + hwseq_data.size_comp1;
Stefan Tauner5c316f92015-02-08 21:57:52 +00001310 msg_cdbg("Hardware sequencing reports %d attached SPI flash chip",
Stefan Tauner50e7c602011-11-08 10:55:54 +00001311 (hwseq_data.size_comp1 != 0) ? 2 : 1);
1312 if (hwseq_data.size_comp1 != 0)
1313 msg_cdbg("s with a combined");
1314 else
1315 msg_cdbg(" with a");
1316 msg_cdbg(" density of %d kB.\n", total_size / 1024);
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001317 flash->chip->total_size = total_size / 1024;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001318
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001319 eraser = &(flash->chip->block_erasers[0]);
Nico Huberd54e4f42017-03-23 23:45:47 +01001320 if (!hwseq_data.only_4k)
1321 boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12;
1322 else
1323 boundary = 0;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001324 size_high = total_size - boundary;
1325 erase_size_high = ich_hwseq_get_erase_block_size(boundary);
1326
1327 if (boundary == 0) {
Stefan Tauner5c316f92015-02-08 21:57:52 +00001328 msg_cdbg2("There is only one partition containing the whole "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001329 "address space (0x%06x - 0x%06x).\n", 0, size_high-1);
1330 eraser->eraseblocks[0].size = erase_size_high;
1331 eraser->eraseblocks[0].count = size_high / erase_size_high;
Stefan Tauner5c316f92015-02-08 21:57:52 +00001332 msg_cdbg2("There are %d erase blocks with %d B each.\n",
Stefan Tauner50e7c602011-11-08 10:55:54 +00001333 size_high / erase_size_high, erase_size_high);
1334 } else {
Stefan Tauner5c316f92015-02-08 21:57:52 +00001335 msg_cdbg2("The flash address space (0x%06x - 0x%06x) is divided "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001336 "at address 0x%06x in two partitions.\n",
Stefan Taunerdbac46c2013-08-13 22:10:41 +00001337 0, total_size-1, boundary);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001338 size_low = total_size - size_high;
1339 erase_size_low = ich_hwseq_get_erase_block_size(0);
1340
1341 eraser->eraseblocks[0].size = erase_size_low;
1342 eraser->eraseblocks[0].count = size_low / erase_size_low;
1343 msg_cdbg("The first partition ranges from 0x%06x to 0x%06x.\n",
1344 0, size_low-1);
1345 msg_cdbg("In that range are %d erase blocks with %d B each.\n",
1346 size_low / erase_size_low, erase_size_low);
1347
1348 eraser->eraseblocks[1].size = erase_size_high;
1349 eraser->eraseblocks[1].count = size_high / erase_size_high;
1350 msg_cdbg("The second partition ranges from 0x%06x to 0x%06x.\n",
Stefan Taunerdbac46c2013-08-13 22:10:41 +00001351 boundary, total_size-1);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001352 msg_cdbg("In that range are %d erase blocks with %d B each.\n",
1353 size_high / erase_size_high, erase_size_high);
1354 }
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001355 flash->chip->tested = TEST_OK_PREW;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001356 return 1;
1357}
1358
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001359static int ich_hwseq_block_erase(struct flashctx *flash, unsigned int addr,
1360 unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001361{
1362 uint32_t erase_block;
1363 uint16_t hsfc;
1364 uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */
1365
1366 erase_block = ich_hwseq_get_erase_block_size(addr);
1367 if (len != erase_block) {
1368 msg_cerr("Erase block size for address 0x%06x is %d B, "
1369 "but requested erase block size is %d B. "
1370 "Not erasing anything.\n", addr, erase_block, len);
1371 return -1;
1372 }
1373
1374 /* Although the hardware supports this (it would erase the whole block
1375 * containing the address) we play safe here. */
1376 if (addr % erase_block != 0) {
1377 msg_cerr("Erase address 0x%06x is not aligned to the erase "
1378 "block boundary (any multiple of %d). "
1379 "Not erasing anything.\n", addr, erase_block);
1380 return -1;
1381 }
1382
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001383 if (addr + len > flash->chip->total_size * 1024) {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001384 msg_perr("Request to erase some inaccessible memory address(es)"
1385 " (addr=0x%x, len=%d). "
1386 "Not erasing anything.\n", addr, len);
1387 return -1;
1388 }
1389
1390 msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr);
Stefan Tauner7608d362014-08-05 23:28:47 +00001391 ich_hwseq_set_addr(addr);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001392
1393 /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */
1394 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1395
1396 hsfc = REGREAD16(ICH9_REG_HSFC);
Nico Huberd54e4f42017-03-23 23:45:47 +01001397 hsfc &= ~hwseq_data.hsfc_fcycle; /* clear operation */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001398 hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */
1399 hsfc |= HSFC_FGO; /* start */
1400 msg_pdbg("HSFC used for block erasing: ");
1401 prettyprint_ich9_reg_hsfc(hsfc);
1402 REGWRITE16(ICH9_REG_HSFC, hsfc);
1403
1404 if (ich_hwseq_wait_for_cycle_complete(timeout, len))
1405 return -1;
1406 return 0;
1407}
1408
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001409static int ich_hwseq_read(struct flashctx *flash, uint8_t *buf,
1410 unsigned int addr, unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001411{
1412 uint16_t hsfc;
1413 uint16_t timeout = 100 * 60;
1414 uint8_t block_len;
1415
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001416 if (addr + len > flash->chip->total_size * 1024) {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001417 msg_perr("Request to read from an inaccessible memory address "
1418 "(addr=0x%x, len=%d).\n", addr, len);
1419 return -1;
1420 }
1421
1422 msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr);
1423 /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
1424 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1425
1426 while (len > 0) {
Stefan Tauner7608d362014-08-05 23:28:47 +00001427 /* Obey programmer limit... */
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001428 block_len = min(len, flash->mst->opaque.max_data_read);
Stefan Tauner7608d362014-08-05 23:28:47 +00001429 /* as well as flash chip page borders as demanded in the Intel datasheets. */
1430 block_len = min(block_len, 256 - (addr & 0xFF));
1431
Stefan Tauner50e7c602011-11-08 10:55:54 +00001432 ich_hwseq_set_addr(addr);
1433 hsfc = REGREAD16(ICH9_REG_HSFC);
Nico Huberd54e4f42017-03-23 23:45:47 +01001434 hsfc &= ~hwseq_data.hsfc_fcycle; /* set read operation */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001435 hsfc &= ~HSFC_FDBC; /* clear byte count */
1436 /* set byte count */
1437 hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
1438 hsfc |= HSFC_FGO; /* start */
1439 REGWRITE16(ICH9_REG_HSFC, hsfc);
1440
1441 if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
1442 return 1;
1443 ich_read_data(buf, block_len, ICH9_REG_FDATA0);
1444 addr += block_len;
1445 buf += block_len;
1446 len -= block_len;
1447 }
1448 return 0;
1449}
1450
Mark Marshallf20b7be2014-05-09 21:16:21 +00001451static int ich_hwseq_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001452{
1453 uint16_t hsfc;
1454 uint16_t timeout = 100 * 60;
1455 uint8_t block_len;
1456
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001457 if (addr + len > flash->chip->total_size * 1024) {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001458 msg_perr("Request to write to an inaccessible memory address "
1459 "(addr=0x%x, len=%d).\n", addr, len);
1460 return -1;
1461 }
1462
1463 msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr);
1464 /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
1465 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1466
1467 while (len > 0) {
1468 ich_hwseq_set_addr(addr);
Stefan Tauner7608d362014-08-05 23:28:47 +00001469 /* Obey programmer limit... */
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001470 block_len = min(len, flash->mst->opaque.max_data_write);
Stefan Tauner7608d362014-08-05 23:28:47 +00001471 /* as well as flash chip page borders as demanded in the Intel datasheets. */
1472 block_len = min(block_len, 256 - (addr & 0xFF));
Stefan Tauner50e7c602011-11-08 10:55:54 +00001473 ich_fill_data(buf, block_len, ICH9_REG_FDATA0);
1474 hsfc = REGREAD16(ICH9_REG_HSFC);
Nico Huberd54e4f42017-03-23 23:45:47 +01001475 hsfc &= ~hwseq_data.hsfc_fcycle; /* clear operation */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001476 hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */
1477 hsfc &= ~HSFC_FDBC; /* clear byte count */
1478 /* set byte count */
1479 hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
1480 hsfc |= HSFC_FGO; /* start */
1481 REGWRITE16(ICH9_REG_HSFC, hsfc);
1482
1483 if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
1484 return -1;
1485 addr += block_len;
1486 buf += block_len;
1487 len -= block_len;
1488 }
1489 return 0;
1490}
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001491
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001492static int ich_spi_send_multicommand(struct flashctx *flash,
1493 struct spi_command *cmds)
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001494{
1495 int ret = 0;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001496 int i;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001497 int oppos, preoppos;
1498 for (; (cmds->writecnt || cmds->readcnt) && !ret; cmds++) {
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001499 if ((cmds + 1)->writecnt || (cmds + 1)->readcnt) {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001500 /* Next command is valid. */
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001501 preoppos = find_preop(curopcodes, cmds->writearr[0]);
1502 oppos = find_opcode(curopcodes, (cmds + 1)->writearr[0]);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001503 if ((oppos == -1) && (preoppos != -1)) {
1504 /* Current command is listed as preopcode in
1505 * ICH struct OPCODES, but next command is not
1506 * listed as opcode in that struct.
1507 * Check for command sanity, then
1508 * try to reprogram the ICH opcode list.
1509 */
1510 if (find_preop(curopcodes,
1511 (cmds + 1)->writearr[0]) != -1) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001512 msg_perr("%s: Two subsequent "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001513 "preopcodes 0x%02x and 0x%02x, "
1514 "ignoring the first.\n",
1515 __func__, cmds->writearr[0],
1516 (cmds + 1)->writearr[0]);
1517 continue;
1518 }
1519 /* If the chipset is locked down, we'll fail
1520 * during execution of the next command anyway.
1521 * No need to bother with fixups.
1522 */
1523 if (!ichspi_lock) {
Helge Wagner738e2522010-10-05 22:06:05 +00001524 oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt);
1525 if (oppos == -1)
1526 continue;
1527 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001528 continue;
1529 }
1530 }
1531 if ((oppos != -1) && (preoppos != -1)) {
1532 /* Current command is listed as preopcode in
1533 * ICH struct OPCODES and next command is listed
1534 * as opcode in that struct. Match them up.
1535 */
1536 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001537 continue;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001538 }
1539 /* If none of the above if-statements about oppos or
1540 * preoppos matched, this is a normal opcode.
1541 */
1542 }
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001543 ret = ich_spi_send_command(flash, cmds->writecnt, cmds->readcnt,
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001544 cmds->writearr, cmds->readarr);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001545 /* Reset the type of all opcodes to non-atomic. */
1546 for (i = 0; i < 8; i++)
1547 curopcodes->opcode[i].atomic = 0;
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001548 }
1549 return ret;
1550}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001551
Michael Karchera4448d92010-07-22 18:04:15 +00001552#define ICH_BMWAG(x) ((x >> 24) & 0xff)
1553#define ICH_BMRAG(x) ((x >> 16) & 0xff)
1554#define ICH_BRWA(x) ((x >> 8) & 0xff)
1555#define ICH_BRRA(x) ((x >> 0) & 0xff)
1556
Nico Huber7590d1a2016-05-03 13:38:28 +02001557static const enum ich_access_protection access_perms_to_protection[] = {
1558 LOCKED, WRITE_PROT, READ_PROT, NO_PROT
1559};
1560static const char *const access_names[] = {
1561 "locked", "read-only", "write-only", "read-write"
1562};
1563
1564static enum ich_access_protection ich9_handle_frap(uint32_t frap, int i)
Michael Karchera4448d92010-07-22 18:04:15 +00001565{
Nico Huberaa91d5c2017-08-19 17:04:21 +02001566 const int rwperms_unknown = ARRAY_SIZE(access_names);
Mathias Krausea60faab2011-01-17 07:50:42 +00001567 static const char *const region_names[5] = {
Michael Karchera4448d92010-07-22 18:04:15 +00001568 "Flash Descriptor", "BIOS", "Management Engine",
1569 "Gigabit Ethernet", "Platform Data"
1570 };
Nico Huberd54e4f42017-03-23 23:45:47 +01001571 const char *const region_name = i < ARRAY_SIZE(region_names) ? region_names[i] : "unknown";
1572
Michael Karchera4448d92010-07-22 18:04:15 +00001573 uint32_t base, limit;
Nico Huberaa91d5c2017-08-19 17:04:21 +02001574 int rwperms;
Stefan Tauner29c80832011-06-12 08:14:10 +00001575 int offset = ICH9_REG_FREG0 + i * 4;
Michael Karchera4448d92010-07-22 18:04:15 +00001576 uint32_t freg = mmio_readl(ich_spibar + offset);
1577
Nico Huberaa91d5c2017-08-19 17:04:21 +02001578 if (i < 8) {
1579 rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) |
1580 (((ICH_BRRA(frap) >> i) & 1) << 0);
1581 } else {
1582 /* Datasheets don't define any access bits for regions > 7. We
1583 can't rely on the actual descriptor settings either as there
1584 are several overrides for them (those by other masters are
1585 not even readable by us, *shrug*). */
1586 rwperms = rwperms_unknown;
1587 }
1588
Michael Karchera4448d92010-07-22 18:04:15 +00001589 base = ICH_FREG_BASE(freg);
1590 limit = ICH_FREG_LIMIT(freg);
Stefan Taunere3adea02012-08-27 15:12:36 +00001591 if (base > limit || (freg == 0 && i > 0)) {
Michael Karchera4448d92010-07-22 18:04:15 +00001592 /* this FREG is disabled */
Stefan Tauner5210e722012-02-16 01:13:00 +00001593 msg_pdbg2("0x%02X: 0x%08x FREG%i: %s region is unused.\n",
Nico Huberd54e4f42017-03-23 23:45:47 +01001594 offset, freg, i, region_name);
Nico Huber7590d1a2016-05-03 13:38:28 +02001595 return NO_PROT;
Stefan Tauner5210e722012-02-16 01:13:00 +00001596 }
1597 msg_pdbg("0x%02X: 0x%08x ", offset, freg);
1598 if (rwperms == 0x3) {
1599 msg_pdbg("FREG%i: %s region (0x%08x-0x%08x) is %s.\n", i,
Nico Huber0bb3f712017-03-29 16:44:33 +02001600 region_name, base, limit, access_names[rwperms]);
Nico Huber7590d1a2016-05-03 13:38:28 +02001601 return NO_PROT;
Michael Karchera4448d92010-07-22 18:04:15 +00001602 }
Nico Huberaa91d5c2017-08-19 17:04:21 +02001603 if (rwperms == rwperms_unknown) {
1604 msg_pdbg("FREG%i: %s region (0x%08x-0x%08x) has unknown permissions.\n",
1605 i, region_name, base, limit);
Nico Huber7590d1a2016-05-03 13:38:28 +02001606 return NO_PROT;
Nico Huberaa91d5c2017-08-19 17:04:21 +02001607 }
Michael Karchera4448d92010-07-22 18:04:15 +00001608
Nico Huber7590d1a2016-05-03 13:38:28 +02001609 msg_pinfo("FREG%i: %s region (0x%08x-0x%08x) is %s.\n", i,
Nico Huber0bb3f712017-03-29 16:44:33 +02001610 region_name, base, limit, access_names[rwperms]);
Nico Huber7590d1a2016-05-03 13:38:28 +02001611 return access_perms_to_protection[rwperms];
Michael Karchera4448d92010-07-22 18:04:15 +00001612}
1613
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001614 /* In contrast to FRAP and the master section of the descriptor the bits
1615 * in the PR registers have an inverted meaning. The bits in FRAP
1616 * indicate read and write access _grant_. Here they indicate read
1617 * and write _protection_ respectively. If both bits are 0 the address
1618 * bits are ignored.
1619 */
1620#define ICH_PR_PERMS(pr) (((~((pr) >> PR_RP_OFF) & 1) << 0) | \
1621 ((~((pr) >> PR_WP_OFF) & 1) << 1))
1622
Nico Huber7590d1a2016-05-03 13:38:28 +02001623static enum ich_access_protection ich9_handle_pr(const size_t reg_pr0, int i)
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001624{
Nico Huberd54e4f42017-03-23 23:45:47 +01001625 uint8_t off = reg_pr0 + (i * 4);
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001626 uint32_t pr = mmio_readl(ich_spibar + off);
Stefan Tauner5210e722012-02-16 01:13:00 +00001627 unsigned int rwperms = ICH_PR_PERMS(pr);
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001628
Nico Huberd54e4f42017-03-23 23:45:47 +01001629 /* From 5 on we have GPR registers and start from 0 again. */
1630 const char *const prefix = i >= 5 ? "G" : "";
1631 if (i >= 5)
1632 i -= 5;
1633
Stefan Tauner5210e722012-02-16 01:13:00 +00001634 if (rwperms == 0x3) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001635 msg_pdbg2("0x%02X: 0x%08x (%sPR%u is unused)\n", off, pr, prefix, i);
Nico Huber7590d1a2016-05-03 13:38:28 +02001636 return NO_PROT;
Stefan Tauner5210e722012-02-16 01:13:00 +00001637 }
1638
1639 msg_pdbg("0x%02X: 0x%08x ", off, pr);
Nico Huberd54e4f42017-03-23 23:45:47 +01001640 msg_pwarn("%sPR%u: Warning: 0x%08x-0x%08x is %s.\n", prefix, i, ICH_FREG_BASE(pr),
Nico Huber0bb3f712017-03-29 16:44:33 +02001641 ICH_FREG_LIMIT(pr), access_names[rwperms]);
Nico Huber7590d1a2016-05-03 13:38:28 +02001642 return access_perms_to_protection[rwperms];
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001643}
1644
Stefan Tauner75da80c2011-09-17 22:21:55 +00001645/* Set/Clear the read and write protection enable bits of PR register @i
1646 * according to @read_prot and @write_prot. */
Nico Huberd54e4f42017-03-23 23:45:47 +01001647static void ich9_set_pr(const size_t reg_pr0, int i, int read_prot, int write_prot)
Stefan Tauner75da80c2011-09-17 22:21:55 +00001648{
Nico Huberd54e4f42017-03-23 23:45:47 +01001649 void *addr = ich_spibar + reg_pr0 + (i * 4);
Stefan Tauner75da80c2011-09-17 22:21:55 +00001650 uint32_t old = mmio_readl(addr);
1651 uint32_t new;
1652
1653 msg_gspew("PR%u is 0x%08x", i, old);
1654 new = old & ~((1 << PR_RP_OFF) | (1 << PR_WP_OFF));
1655 if (read_prot)
1656 new |= (1 << PR_RP_OFF);
1657 if (write_prot)
1658 new |= (1 << PR_WP_OFF);
1659 if (old == new) {
1660 msg_gspew(" already.\n");
1661 return;
1662 }
1663 msg_gspew(", trying to set it to 0x%08x ", new);
1664 rmmio_writel(new, addr);
1665 msg_gspew("resulted in 0x%08x.\n", mmio_readl(addr));
1666}
1667
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001668static const struct spi_master spi_master_ich7 = {
Michael Karcherb9dbe482011-05-11 17:07:07 +00001669 .type = SPI_CONTROLLER_ICH7,
1670 .max_data_read = 64,
1671 .max_data_write = 64,
1672 .command = ich_spi_send_command,
1673 .multicommand = ich_spi_send_multicommand,
1674 .read = default_spi_read,
1675 .write_256 = default_spi_write_256,
Nico Huber7bca1262012-06-15 22:28:12 +00001676 .write_aai = default_spi_write_aai,
Michael Karcherb9dbe482011-05-11 17:07:07 +00001677};
1678
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001679static const struct spi_master spi_master_ich9 = {
Michael Karcherb9dbe482011-05-11 17:07:07 +00001680 .type = SPI_CONTROLLER_ICH9,
1681 .max_data_read = 64,
1682 .max_data_write = 64,
1683 .command = ich_spi_send_command,
1684 .multicommand = ich_spi_send_multicommand,
1685 .read = default_spi_read,
1686 .write_256 = default_spi_write_256,
Nico Huber7bca1262012-06-15 22:28:12 +00001687 .write_aai = default_spi_write_aai,
Michael Karcherb9dbe482011-05-11 17:07:07 +00001688};
1689
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001690static const struct opaque_master opaque_master_ich_hwseq = {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001691 .max_data_read = 64,
1692 .max_data_write = 64,
1693 .probe = ich_hwseq_probe,
1694 .read = ich_hwseq_read,
1695 .write = ich_hwseq_write,
1696 .erase = ich_hwseq_block_erase,
1697};
1698
Nico Huber560111e2017-04-26 12:27:17 +02001699int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
Michael Karchera4448d92010-07-22 18:04:15 +00001700{
1701 int i;
Stefan Tauner92d6a862013-10-25 00:33:37 +00001702 uint16_t tmp2;
Michael Karchera4448d92010-07-22 18:04:15 +00001703 uint32_t tmp;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001704 char *arg;
Stefan Tauner5210e722012-02-16 01:13:00 +00001705 int ich_spi_rw_restricted = 0;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001706 int desc_valid = 0;
Richard Hughese2cbb122019-01-02 21:11:08 +00001707 struct ich_descriptors desc;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001708 enum ich_spi_mode {
1709 ich_auto,
1710 ich_hwseq,
1711 ich_swseq
1712 } ich_spi_mode = ich_auto;
Nico Huberd54e4f42017-03-23 23:45:47 +01001713 size_t num_freg, num_pr, reg_pr0;
Michael Karchera4448d92010-07-22 18:04:15 +00001714
Stefan Taunera8d838d2011-11-06 23:51:09 +00001715 ich_generation = ich_gen;
Stefan Tauner92d6a862013-10-25 00:33:37 +00001716 ich_spibar = spibar;
Michael Karchera4448d92010-07-22 18:04:15 +00001717
Richard Hughese2cbb122019-01-02 21:11:08 +00001718 memset(&desc, 0x00, sizeof(struct ich_descriptors));
1719
Nico Huberd54e4f42017-03-23 23:45:47 +01001720 /* Moving registers / bits */
1721 if (ich_generation == CHIPSET_100_SERIES_SUNRISE_POINT) {
1722 num_freg = 10;
David Hendricksa5216362017-08-08 20:02:22 -07001723 num_pr = 6; /* Includes GPR0 */
1724 reg_pr0 = PCH100_REG_FPR0;
1725 swseq_data.reg_ssfsc = PCH100_REG_SSFSC;
1726 swseq_data.reg_preop = PCH100_REG_PREOP;
1727 swseq_data.reg_optype = PCH100_REG_OPTYPE;
1728 swseq_data.reg_opmenu = PCH100_REG_OPMENU;
1729 hwseq_data.addr_mask = PCH100_FADDR_FLA;
1730 hwseq_data.only_4k = true;
1731 hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE;
Nico Huber19eb0792017-12-13 00:44:45 +01001732 } else if (ich_generation == CHIPSET_C620_SERIES_LEWISBURG) {
David Hendricksa5216362017-08-08 20:02:22 -07001733 num_freg = 12; /* 12 MMIO regs, but 16 regions in FD spec */
1734 num_pr = 6; /* Includes GPR0 */
Nico Huberd54e4f42017-03-23 23:45:47 +01001735 reg_pr0 = PCH100_REG_FPR0;
1736 swseq_data.reg_ssfsc = PCH100_REG_SSFSC;
1737 swseq_data.reg_preop = PCH100_REG_PREOP;
1738 swseq_data.reg_optype = PCH100_REG_OPTYPE;
1739 swseq_data.reg_opmenu = PCH100_REG_OPMENU;
1740 hwseq_data.addr_mask = PCH100_FADDR_FLA;
1741 hwseq_data.only_4k = true;
1742 hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE;
1743 } else {
1744 num_freg = 5;
1745 num_pr = 5;
1746 reg_pr0 = ICH9_REG_PR0;
1747 swseq_data.reg_ssfsc = ICH9_REG_SSFS;
1748 swseq_data.reg_preop = ICH9_REG_PREOP;
1749 swseq_data.reg_optype = ICH9_REG_OPTYPE;
1750 swseq_data.reg_opmenu = ICH9_REG_OPMENU;
1751 hwseq_data.addr_mask = ICH9_FADDR_FLA;
1752 hwseq_data.only_4k = false;
1753 hwseq_data.hsfc_fcycle = HSFC_FCYCLE;
1754 }
1755
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001756 switch (ich_generation) {
Stefan Taunera8d838d2011-11-06 23:51:09 +00001757 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +00001758 case CHIPSET_TUNNEL_CREEK:
1759 case CHIPSET_CENTERTON:
Michael Karchera4448d92010-07-22 18:04:15 +00001760 msg_pdbg("0x00: 0x%04x (SPIS)\n",
1761 mmio_readw(ich_spibar + 0));
1762 msg_pdbg("0x02: 0x%04x (SPIC)\n",
1763 mmio_readw(ich_spibar + 2));
1764 msg_pdbg("0x04: 0x%08x (SPIA)\n",
1765 mmio_readl(ich_spibar + 4));
Michael Karchera4448d92010-07-22 18:04:15 +00001766 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
1767 msg_pdbg("0x50: 0x%08x (BBAR)\n",
1768 ichspi_bbar);
1769 msg_pdbg("0x54: 0x%04x (PREOP)\n",
1770 mmio_readw(ich_spibar + 0x54));
1771 msg_pdbg("0x56: 0x%04x (OPTYPE)\n",
1772 mmio_readw(ich_spibar + 0x56));
1773 msg_pdbg("0x58: 0x%08x (OPMENU)\n",
1774 mmio_readl(ich_spibar + 0x58));
1775 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n",
1776 mmio_readl(ich_spibar + 0x5c));
Stefan Tauner122dd122011-07-24 15:34:56 +00001777 for (i = 0; i < 3; i++) {
Michael Karchera4448d92010-07-22 18:04:15 +00001778 int offs;
1779 offs = 0x60 + (i * 4);
1780 msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,
1781 mmio_readl(ich_spibar + offs), i);
1782 }
Michael Karchera4448d92010-07-22 18:04:15 +00001783 if (mmio_readw(ich_spibar) & (1 << 15)) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00001784 msg_pwarn("WARNING: SPI Configuration Lockdown activated.\n");
Michael Karchera4448d92010-07-22 18:04:15 +00001785 ichspi_lock = 1;
1786 }
Stefan Tauner745f6bb2011-11-13 15:17:10 +00001787 ich_init_opcodes();
Stefan Taunera8d838d2011-11-06 23:51:09 +00001788 ich_set_bbar(0);
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001789 register_spi_master(&spi_master_ich7);
Michael Karchera4448d92010-07-22 18:04:15 +00001790 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +00001791 case CHIPSET_ICH8:
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001792 default: /* Future version might behave the same */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001793 arg = extract_programmer_param("ich_spi_mode");
1794 if (arg && !strcmp(arg, "hwseq")) {
1795 ich_spi_mode = ich_hwseq;
1796 msg_pspew("user selected hwseq\n");
1797 } else if (arg && !strcmp(arg, "swseq")) {
1798 ich_spi_mode = ich_swseq;
1799 msg_pspew("user selected swseq\n");
1800 } else if (arg && !strcmp(arg, "auto")) {
1801 msg_pspew("user selected auto\n");
1802 ich_spi_mode = ich_auto;
1803 } else if (arg && !strlen(arg)) {
1804 msg_perr("Missing argument for ich_spi_mode.\n");
1805 free(arg);
1806 return ERROR_FATAL;
1807 } else if (arg) {
1808 msg_perr("Unknown argument for ich_spi_mode: %s\n",
1809 arg);
1810 free(arg);
1811 return ERROR_FATAL;
1812 }
1813 free(arg);
1814
Stefan Tauner29c80832011-06-12 08:14:10 +00001815 tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS);
Michael Karchera4448d92010-07-22 18:04:15 +00001816 msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2);
Stefan Tauner55206942011-06-11 09:53:22 +00001817 prettyprint_ich9_reg_hsfs(tmp2);
Stefan Tauner29c80832011-06-12 08:14:10 +00001818 if (tmp2 & HSFS_FLOCKDN) {
Nico Huber7590d1a2016-05-03 13:38:28 +02001819 msg_pinfo("SPI Configuration is locked down.\n");
Stefan Tauner55206942011-06-11 09:53:22 +00001820 ichspi_lock = 1;
1821 }
Stefan Tauner1e146392011-09-15 23:52:55 +00001822 if (tmp2 & HSFS_FDV)
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001823 desc_valid = 1;
1824 if (!(tmp2 & HSFS_FDOPSS) && desc_valid)
Stefan Taunerd7d423b2012-10-20 09:13:16 +00001825 msg_pinfo("The Flash Descriptor Override Strap-Pin is set. Restrictions implied by\n"
1826 "the Master Section of the flash descriptor are NOT in effect. Please note\n"
1827 "that Protected Range (PR) restrictions still apply.\n");
Stefan Tauner745f6bb2011-11-13 15:17:10 +00001828 ich_init_opcodes();
Stefan Tauner55206942011-06-11 09:53:22 +00001829
Stefan Taunerf382e352011-11-08 11:55:24 +00001830 if (desc_valid) {
1831 tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC);
1832 msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2);
1833 prettyprint_ich9_reg_hsfc(tmp2);
1834 }
Michael Karchera4448d92010-07-22 18:04:15 +00001835
Stefan Tauner5ffe65b2011-07-07 04:10:57 +00001836 tmp = mmio_readl(ich_spibar + ICH9_REG_FADDR);
Stefan Taunereb582572012-09-21 12:52:50 +00001837 msg_pdbg2("0x08: 0x%08x (FADDR)\n", tmp);
Michael Karchera4448d92010-07-22 18:04:15 +00001838
David Hendricksa5216362017-08-08 20:02:22 -07001839 if (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT || ich_gen == CHIPSET_C620_SERIES_LEWISBURG) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001840 const uint32_t dlock = mmio_readl(ich_spibar + PCH100_REG_DLOCK);
1841 msg_pdbg("0x0c: 0x%08x (DLOCK)\n", dlock);
1842 prettyprint_pch100_reg_dlock(dlock);
1843 }
1844
Stefan Taunerf382e352011-11-08 11:55:24 +00001845 if (desc_valid) {
1846 tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP);
1847 msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp);
1848 msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp));
1849 msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp));
1850 msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp));
1851 msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp));
1852
Stefan Tauner5210e722012-02-16 01:13:00 +00001853 /* Handle FREGx and FRAP registers */
Nico Huberd54e4f42017-03-23 23:45:47 +01001854 for (i = 0; i < num_freg; i++)
Stefan Tauner5210e722012-02-16 01:13:00 +00001855 ich_spi_rw_restricted |= ich9_handle_frap(tmp, i);
Stefan Tauner27cb34b2013-06-01 00:06:12 +00001856 if (ich_spi_rw_restricted)
Nico Huber7590d1a2016-05-03 13:38:28 +02001857 msg_pinfo("Not all flash regions are freely accessible by flashrom. This is "
Stefan Tauner4c723152016-01-14 22:47:55 +00001858 "most likely\ndue to an active ME. Please see "
1859 "https://flashrom.org/ME for details.\n");
Stefan Taunerf382e352011-11-08 11:55:24 +00001860 }
Michael Karchera4448d92010-07-22 18:04:15 +00001861
Stefan Taunereb582572012-09-21 12:52:50 +00001862 /* Handle PR registers */
Nico Huberd54e4f42017-03-23 23:45:47 +01001863 for (i = 0; i < num_pr; i++) {
Stefan Tauner5210e722012-02-16 01:13:00 +00001864 /* if not locked down try to disable PR locks first */
1865 if (!ichspi_lock)
Nico Huberd54e4f42017-03-23 23:45:47 +01001866 ich9_set_pr(reg_pr0, i, 0, 0);
1867 ich_spi_rw_restricted |= ich9_handle_pr(reg_pr0, i);
Stefan Tauner5210e722012-02-16 01:13:00 +00001868 }
1869
Nico Huber7590d1a2016-05-03 13:38:28 +02001870 switch (ich_spi_rw_restricted) {
1871 case WRITE_PROT:
1872 msg_pwarn("At least some flash regions are write protected. For write operations,\n"
1873 "you should use a flash layout and include only writable regions. See\n"
1874 "manpage for more details.\n");
1875 break;
1876 case READ_PROT:
1877 case LOCKED:
1878 msg_pwarn("At least some flash regions are read protected. You have to use a flash\n"
1879 "layout and include only accessible regions. For write operations, you'll\n"
1880 "additionally need the --noverify-all switch. See manpage for more details.\n"
1881 );
1882 break;
Stefan Tauner5210e722012-02-16 01:13:00 +00001883 }
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001884
Nico Huberd54e4f42017-03-23 23:45:47 +01001885 tmp = mmio_readl(ich_spibar + swseq_data.reg_ssfsc);
1886 msg_pdbg("0x%zx: 0x%02x (SSFS)\n", swseq_data.reg_ssfsc, tmp & 0xff);
Stefan Tauner2a8b2622011-06-11 09:53:16 +00001887 prettyprint_ich9_reg_ssfs(tmp);
Stefan Tauner29c80832011-06-12 08:14:10 +00001888 if (tmp & SSFS_FCERR) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001889 msg_pdbg("Clearing SSFS.FCERR\n");
Nico Huberd54e4f42017-03-23 23:45:47 +01001890 mmio_writeb(SSFS_FCERR, ich_spibar + swseq_data.reg_ssfsc);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001891 }
Nico Huberd54e4f42017-03-23 23:45:47 +01001892 msg_pdbg("0x%zx: 0x%06x (SSFC)\n", swseq_data.reg_ssfsc + 1, tmp >> 8);
Stefan Tauner2a8b2622011-06-11 09:53:16 +00001893 prettyprint_ich9_reg_ssfc(tmp);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001894
Nico Huberd54e4f42017-03-23 23:45:47 +01001895 msg_pdbg("0x%zx: 0x%04x (PREOP)\n",
1896 swseq_data.reg_preop, mmio_readw(ich_spibar + swseq_data.reg_preop));
1897 msg_pdbg("0x%zx: 0x%04x (OPTYPE)\n",
1898 swseq_data.reg_optype, mmio_readw(ich_spibar + swseq_data.reg_optype));
1899 msg_pdbg("0x%zx: 0x%08x (OPMENU)\n",
1900 swseq_data.reg_opmenu, mmio_readl(ich_spibar + swseq_data.reg_opmenu));
1901 msg_pdbg("0x%zx: 0x%08x (OPMENU+4)\n",
1902 swseq_data.reg_opmenu + 4, mmio_readl(ich_spibar + swseq_data.reg_opmenu + 4));
Stefan Taunerf382e352011-11-08 11:55:24 +00001903 if (ich_generation == CHIPSET_ICH8 && desc_valid) {
Stefan Tauner1e146392011-09-15 23:52:55 +00001904 tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC);
1905 msg_pdbg("0xC1: 0x%08x (VSCC)\n", tmp);
1906 msg_pdbg("VSCC: ");
Nico Huberd152fb92017-06-19 12:57:10 +02001907 prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true);
David Hendricksa5216362017-08-08 20:02:22 -07001908 } else if (ich_generation != CHIPSET_100_SERIES_SUNRISE_POINT &&
1909 ich_generation != CHIPSET_C620_SERIES_LEWISBURG) {
Duncan Laurie4095ed72014-08-20 15:39:32 +00001910 if (ich_generation != CHIPSET_BAYTRAIL && desc_valid) {
1911 ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR);
1912 msg_pdbg("0xA0: 0x%08x (BBAR)\n",
1913 ichspi_bbar);
1914 ich_set_bbar(0);
1915 }
Stefan Taunerbd649e42011-07-01 00:39:16 +00001916
Stefan Taunerf382e352011-11-08 11:55:24 +00001917 if (desc_valid) {
1918 tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC);
1919 msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp);
1920 msg_pdbg("LVSCC: ");
Nico Huberd152fb92017-06-19 12:57:10 +02001921 prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true);
Stefan Tauner1e146392011-09-15 23:52:55 +00001922
Stefan Taunerf382e352011-11-08 11:55:24 +00001923 tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC);
1924 msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp);
1925 msg_pdbg("UVSCC: ");
Nico Huberd152fb92017-06-19 12:57:10 +02001926 prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, false);
Stefan Tauner1e146392011-09-15 23:52:55 +00001927
Stefan Taunerf382e352011-11-08 11:55:24 +00001928 tmp = mmio_readl(ich_spibar + ICH9_REG_FPB);
1929 msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp);
1930 }
Stefan Tauner1e146392011-09-15 23:52:55 +00001931 }
1932
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001933 if (desc_valid) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001934 if (read_ich_descriptors_via_fdo(ich_gen, ich_spibar, &desc) == ICH_RET_OK)
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +00001935 prettyprint_ich_descriptors(ich_gen, &desc);
1936
Stefan Tauner50e7c602011-11-08 10:55:54 +00001937 /* If the descriptor is valid and indicates multiple
1938 * flash devices we need to use hwseq to be able to
1939 * access the second flash device.
1940 */
1941 if (ich_spi_mode == ich_auto && desc.content.NC != 0) {
1942 msg_pinfo("Enabling hardware sequencing due to "
1943 "multiple flash chips detected.\n");
1944 ich_spi_mode = ich_hwseq;
1945 }
Stefan Tauner1e146392011-09-15 23:52:55 +00001946 }
Stefan Tauner50e7c602011-11-08 10:55:54 +00001947
1948 if (ich_spi_mode == ich_auto && ichspi_lock &&
1949 ich_missing_opcodes()) {
1950 msg_pinfo("Enabling hardware sequencing because "
1951 "some important opcode is locked.\n");
1952 ich_spi_mode = ich_hwseq;
1953 }
1954
Nico Huber22f2dc52017-08-31 16:14:22 +02001955 if (ich_spi_mode == ich_auto && ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT) {
1956 msg_pdbg("Enabling hardware sequencing by default for 100 series PCH.\n");
1957 ich_spi_mode = ich_hwseq;
1958 }
1959
Stefan Tauner50e7c602011-11-08 10:55:54 +00001960 if (ich_spi_mode == ich_hwseq) {
1961 if (!desc_valid) {
1962 msg_perr("Hardware sequencing was requested "
1963 "but the flash descriptor is not "
1964 "valid. Aborting.\n");
1965 return ERROR_FATAL;
1966 }
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +00001967
1968 int tmpi = getFCBA_component_density(ich_generation, &desc, 0);
1969 if (tmpi < 0) {
1970 msg_perr("Could not determine density of flash component %d.\n", 0);
1971 return ERROR_FATAL;
1972 }
1973 hwseq_data.size_comp0 = tmpi;
1974
1975 tmpi = getFCBA_component_density(ich_generation, &desc, 1);
1976 if (tmpi < 0) {
1977 msg_perr("Could not determine density of flash component %d.\n", 1);
1978 return ERROR_FATAL;
1979 }
1980 hwseq_data.size_comp1 = tmpi;
1981
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001982 register_opaque_master(&opaque_master_ich_hwseq);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001983 } else {
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001984 register_spi_master(&spi_master_ich9);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001985 }
Michael Karchera4448d92010-07-22 18:04:15 +00001986 break;
Michael Karchera4448d92010-07-22 18:04:15 +00001987 }
1988
Michael Karchera4448d92010-07-22 18:04:15 +00001989 return 0;
1990}
1991
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001992static const struct spi_master spi_master_via = {
Michael Karcherb9dbe482011-05-11 17:07:07 +00001993 .type = SPI_CONTROLLER_VIA,
1994 .max_data_read = 16,
1995 .max_data_write = 16,
1996 .command = ich_spi_send_command,
1997 .multicommand = ich_spi_send_multicommand,
1998 .read = default_spi_read,
1999 .write_256 = default_spi_write_256,
Nico Huber7bca1262012-06-15 22:28:12 +00002000 .write_aai = default_spi_write_aai,
Michael Karcherb9dbe482011-05-11 17:07:07 +00002001};
2002
Nico Huber560111e2017-04-26 12:27:17 +02002003int via_init_spi(uint32_t mmio_base)
Michael Karchera4448d92010-07-22 18:04:15 +00002004{
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00002005 int i;
Michael Karchera4448d92010-07-22 18:04:15 +00002006
Stefan Tauner7fb5aa02013-08-14 15:48:44 +00002007 ich_spibar = rphysmap("VIA SPI MMIO registers", mmio_base, 0x70);
2008 if (ich_spibar == ERROR_PTR)
2009 return ERROR_FATAL;
Helge Wagnerdd73d832012-08-24 23:03:46 +00002010 /* Do we really need no write enable? Like the LPC one at D17F0 0x40 */
Michael Karchera4448d92010-07-22 18:04:15 +00002011
Michael Karchera4448d92010-07-22 18:04:15 +00002012 /* Not sure if it speaks all these bus protocols. */
Nico Huber2e50cdc2018-09-23 20:20:26 +02002013 internal_buses_supported &= BUS_LPC | BUS_FWH;
Stefan Taunera8d838d2011-11-06 23:51:09 +00002014 ich_generation = CHIPSET_ICH7;
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00002015 register_spi_master(&spi_master_via);
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00002016
2017 msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0));
2018 msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2));
2019 msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(ich_spibar + 4));
2020 for (i = 0; i < 2; i++) {
2021 int offs;
2022 offs = 8 + (i * 8);
2023 msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs,
2024 mmio_readl(ich_spibar + offs), i);
2025 msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
2026 mmio_readl(ich_spibar + offs + 4), i);
2027 }
2028 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
2029 msg_pdbg("0x50: 0x%08x (BBAR)\n", ichspi_bbar);
2030 msg_pdbg("0x54: 0x%04x (PREOP)\n", mmio_readw(ich_spibar + 0x54));
2031 msg_pdbg("0x56: 0x%04x (OPTYPE)\n", mmio_readw(ich_spibar + 0x56));
2032 msg_pdbg("0x58: 0x%08x (OPMENU)\n", mmio_readl(ich_spibar + 0x58));
2033 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + 0x5c));
2034 for (i = 0; i < 3; i++) {
2035 int offs;
2036 offs = 0x60 + (i * 4);
2037 msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,
2038 mmio_readl(ich_spibar + offs), i);
2039 }
2040 msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n",
2041 mmio_readw(ich_spibar + 0x6c));
2042 if (mmio_readw(ich_spibar) & (1 << 15)) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00002043 msg_pwarn("Warning: SPI Configuration Lockdown activated.\n");
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00002044 ichspi_lock = 1;
2045 }
2046
Stefan Taunera8d838d2011-11-06 23:51:09 +00002047 ich_set_bbar(0);
Michael Karchera4448d92010-07-22 18:04:15 +00002048 ich_init_opcodes();
2049
2050 return 0;
2051}
2052
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00002053#endif