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Dominik Geyerb46acba2008-05-16 12:55:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2008 Stefan Wildemann <stefan.wildemann@kontron.com>
5 * Copyright (C) 2008 Claus Gindhart <claus.gindhart@kontron.com>
6 * Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com>
Stefan Reinauera9424d52008-06-27 16:28:34 +00007 * Copyright (C) 2008 coresystems GmbH <info@coresystems.de>
Dominik Geyerb46acba2008-05-16 12:55:55 +00008 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Dominik Geyerb46acba2008-05-16 12:55:55 +000022 */
23
24/*
25 * This module is designed for supporting the devices
26 * ST M25P40
27 * ST M25P80
28 * ST M25P16
29 * ST M25P32 already tested
30 * ST M25P64
31 * AT 25DF321 already tested
32 *
33 */
34
Dominik Geyerb46acba2008-05-16 12:55:55 +000035#include <string.h>
Dominik Geyerb46acba2008-05-16 12:55:55 +000036#include <sys/mman.h>
Dominik Geyerb46acba2008-05-16 12:55:55 +000037#include "flash.h"
38#include "spi.h"
39
Stefan Reinauera9424d52008-06-27 16:28:34 +000040/* ICH9 controller register definition */
41#define ICH9_REG_FADDR 0x08 /* 32 Bits */
42#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */
43
44#define ICH9_REG_SSFS 0x90 /* 08 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +000045#define SSFS_SCIP 0x00000001
46#define SSFS_CDS 0x00000004
47#define SSFS_FCERR 0x00000008
48#define SSFS_AEL 0x00000010
Stefan Reinauera9424d52008-06-27 16:28:34 +000049
50#define ICH9_REG_SSFC 0x91 /* 24 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +000051#define SSFC_SCGO 0x00000200
52#define SSFC_ACS 0x00000400
53#define SSFC_SPOP 0x00000800
54#define SSFC_COP 0x00001000
55#define SSFC_DBC 0x00010000
56#define SSFC_DS 0x00400000
57#define SSFC_SME 0x00800000
58#define SSFC_SCF 0x01000000
59#define SSFC_SCF_20MHZ 0x00000000
60#define SSFC_SCF_33MHZ 0x01000000
Stefan Reinauera9424d52008-06-27 16:28:34 +000061
62#define ICH9_REG_PREOP 0x94 /* 16 Bits */
63#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */
64#define ICH9_REG_OPMENU 0x98 /* 64 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +000065
66// ICH9R SPI commands
67#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
68#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
69#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
70#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
71
Stefan Reinauera9424d52008-06-27 16:28:34 +000072// ICH7 registers
73#define ICH7_REG_SPIS 0x00 /* 16 Bits */
74#define SPIS_SCIP 0x00000001
75#define SPIS_CDS 0x00000004
76#define SPIS_FCERR 0x00000008
77
Rudolf Marek3fdbccf2008-06-30 21:38:30 +000078/* VIA SPI is compatible with ICH7, but maxdata
79 to transfer is 16 bytes.
80
81 DATA byte count on ICH7 is 8:13, on VIA 8:11
82
83 bit 12 is port select CS0 CS1
84 bit 13 is FAST READ enable
85 bit 7 is used with fast read and one shot controls CS de-assert?
86*/
87
Stefan Reinauera9424d52008-06-27 16:28:34 +000088#define ICH7_REG_SPIC 0x02 /* 16 Bits */
89#define SPIC_SCGO 0x0002
90#define SPIC_ACS 0x0004
91#define SPIC_SPOP 0x0008
Rudolf Marek3fdbccf2008-06-30 21:38:30 +000092#define SPIC_DS 0x4000
Stefan Reinauera9424d52008-06-27 16:28:34 +000093
94#define ICH7_REG_SPIA 0x04 /* 32 Bits */
95#define ICH7_REG_SPID0 0x08 /* 64 Bytes */
96#define ICH7_REG_PREOP 0x54 /* 16 Bits */
97#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */
98#define ICH7_REG_OPMENU 0x58 /* 64 Bits */
99
FENG yu ningc05a2952008-12-08 18:16:58 +0000100/* ICH SPI configuration lock-down. May be set during chipset enabling. */
101int ichspi_lock = 0;
102
Dominik Geyerb46acba2008-05-16 12:55:55 +0000103typedef struct _OPCODE {
104 uint8_t opcode; //This commands spi opcode
105 uint8_t spi_type; //This commands spi type
106 uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1
107} OPCODE;
108
109/* Opcode definition:
110 * Preop 1: Write Enable
111 * Preop 2: Write Status register enable
112 *
113 * OP 0: Write address
114 * OP 1: Read Address
115 * OP 2: ERASE block
116 * OP 3: Read Status register
117 * OP 4: Read ID
118 * OP 5: Write Status register
119 * OP 6: chip private (read JDEC id)
120 * OP 7: Chip erase
121 */
122typedef struct _OPCODES {
123 uint8_t preop[2];
124 OPCODE opcode[8];
125} OPCODES;
126
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000127static OPCODES *curopcodes = NULL;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000128
129/* HW access functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000130static uint32_t REGREAD32(int X)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000131{
132 volatile uint32_t regval;
Uwe Hermann394131e2008-10-18 21:14:13 +0000133 regval = *(volatile uint32_t *)((uint8_t *) spibar + X);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000134 return regval;
135}
136
Uwe Hermann09e04f72009-05-16 22:36:00 +0000137static uint16_t REGREAD16(int X)
Stefan Reinauera9424d52008-06-27 16:28:34 +0000138{
139 volatile uint16_t regval;
Uwe Hermann394131e2008-10-18 21:14:13 +0000140 regval = *(volatile uint16_t *)((uint8_t *) spibar + X);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000141 return regval;
142}
143
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000144#define REGWRITE32(X,Y) (*(uint32_t *)((uint8_t *)spibar+X)=Y)
145#define REGWRITE16(X,Y) (*(uint16_t *)((uint8_t *)spibar+X)=Y)
146#define REGWRITE8(X,Y) (*(uint8_t *)((uint8_t *)spibar+X)=Y)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000147
Dominik Geyerb46acba2008-05-16 12:55:55 +0000148/* Common SPI functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000149static int find_opcode(OPCODES *op, uint8_t opcode);
150static int find_preop(OPCODES *op, uint8_t preop);
FENG yu ningf041e9b2008-12-15 02:32:11 +0000151static int generate_opcodes(OPCODES * op);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000152static int program_opcodes(OPCODES * op);
Stefan Reinauer43119562008-11-02 19:51:50 +0000153static int run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000154 uint8_t datalength, uint8_t * data);
155static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000156 int offset, int maxdata);
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000157static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000158 int offset, int maxdata);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000159
FENG yu ningf041e9b2008-12-15 02:32:11 +0000160/* for pairing opcodes with their required preop */
161struct preop_opcode_pair {
162 uint8_t preop;
163 uint8_t opcode;
164};
165
166struct preop_opcode_pair pops[] = {
167 {JEDEC_WREN, JEDEC_BYTE_PROGRAM},
168 {JEDEC_WREN, JEDEC_SE}, /* sector erase */
169 {JEDEC_WREN, JEDEC_BE_52}, /* block erase */
170 {JEDEC_WREN, JEDEC_BE_D8}, /* block erase */
171 {JEDEC_WREN, JEDEC_CE_60}, /* chip erase */
172 {JEDEC_WREN, JEDEC_CE_C7}, /* chip erase */
173 {JEDEC_EWSR, JEDEC_WRSR},
174 {0,}
175};
176
Dominik Geyerb46acba2008-05-16 12:55:55 +0000177OPCODES O_ST_M25P = {
178 {
179 JEDEC_WREN,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000180 0},
Dominik Geyerb46acba2008-05-16 12:55:55 +0000181 {
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000182 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 1}, // Write Byte
183 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
184 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 1}, // Erase Sector
185 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
186 {JEDEC_RES, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Resume Deep Power-Down
187 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 1}, // Write Status Register
188 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
189 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 1}, // Bulk erase
190 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000191};
192
FENG yu ningc05a2952008-12-08 18:16:58 +0000193OPCODES O_EXISTING = {};
194
Uwe Hermann09e04f72009-05-16 22:36:00 +0000195static int find_opcode(OPCODES *op, uint8_t opcode)
FENG yu ningc05a2952008-12-08 18:16:58 +0000196{
197 int a;
198
199 for (a = 0; a < 8; a++) {
200 if (op->opcode[a].opcode == opcode)
201 return a;
202 }
203
204 return -1;
205}
206
Uwe Hermann09e04f72009-05-16 22:36:00 +0000207static int find_preop(OPCODES *op, uint8_t preop)
FENG yu ningc05a2952008-12-08 18:16:58 +0000208{
209 int a;
210
211 for (a = 0; a < 2; a++) {
212 if (op->preop[a] == preop)
213 return a;
214 }
215
216 return -1;
217}
218
FENG yu ningf041e9b2008-12-15 02:32:11 +0000219static int generate_opcodes(OPCODES * op)
FENG yu ningc05a2952008-12-08 18:16:58 +0000220{
FENG yu ningf041e9b2008-12-15 02:32:11 +0000221 int a, b, i;
FENG yu ningc05a2952008-12-08 18:16:58 +0000222 uint16_t preop, optype;
223 uint32_t opmenu[2];
FENG yu ningc05a2952008-12-08 18:16:58 +0000224
225 if (op == NULL) {
226 printf_debug("\n%s: null OPCODES pointer!\n", __FUNCTION__);
227 return -1;
228 }
229
230 switch (flashbus) {
231 case BUS_TYPE_ICH7_SPI:
232 case BUS_TYPE_VIA_SPI:
233 preop = REGREAD16(ICH7_REG_PREOP);
234 optype = REGREAD16(ICH7_REG_OPTYPE);
235 opmenu[0] = REGREAD32(ICH7_REG_OPMENU);
236 opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4);
237 break;
238 case BUS_TYPE_ICH9_SPI:
239 preop = REGREAD16(ICH9_REG_PREOP);
240 optype = REGREAD16(ICH9_REG_OPTYPE);
241 opmenu[0] = REGREAD32(ICH9_REG_OPMENU);
242 opmenu[1] = REGREAD32(ICH9_REG_OPMENU + 4);
243 break;
244 default:
245 printf_debug("%s: unsupported chipset\n", __FUNCTION__);
246 return -1;
247 }
248
249 op->preop[0] = (uint8_t) preop;
250 op->preop[1] = (uint8_t) (preop >> 8);
251
252 for (a = 0; a < 8; a++) {
253 op->opcode[a].spi_type = (uint8_t) (optype & 0x3);
254 optype >>= 2;
255 }
256
257 for (a = 0; a < 4; a++) {
258 op->opcode[a].opcode = (uint8_t) (opmenu[0] & 0xff);
259 opmenu[0] >>= 8;
260 }
261
262 for (a = 4; a < 8; a++) {
263 op->opcode[a].opcode = (uint8_t) (opmenu[1] & 0xff);
264 opmenu[1] >>= 8;
265 }
266
267 /* atomic (link opcode with required pre-op) */
268 for (a = 4; a < 8; a++)
269 op->opcode[a].atomic = 0;
270
FENG yu ningf041e9b2008-12-15 02:32:11 +0000271 for (i = 0; pops[i].opcode; i++) {
272 a = find_opcode(op, pops[i].opcode);
273 b = find_preop(op, pops[i].preop);
274 if ((a != -1) && (b != -1))
275 op->opcode[a].atomic = (uint8_t) ++b;
FENG yu ningc05a2952008-12-08 18:16:58 +0000276 }
277
278 return 0;
279}
280
Dominik Geyerb46acba2008-05-16 12:55:55 +0000281int program_opcodes(OPCODES * op)
282{
283 uint8_t a;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000284 uint16_t preop, optype;
285 uint32_t opmenu[2];
Dominik Geyerb46acba2008-05-16 12:55:55 +0000286
287 /* Program Prefix Opcodes */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000288 /* 0:7 Prefix Opcode 1 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000289 preop = (op->preop[0]);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000290 /* 8:16 Prefix Opcode 2 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000291 preop |= ((uint16_t) op->preop[1]) << 8;
Uwe Hermann394131e2008-10-18 21:14:13 +0000292
Stefan Reinauera9424d52008-06-27 16:28:34 +0000293 /* Program Opcode Types 0 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000294 optype = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000295 for (a = 0; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000296 optype |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000297 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000298
Stefan Reinauera9424d52008-06-27 16:28:34 +0000299 /* Program Allowable Opcodes 0 - 3 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000300 opmenu[0] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000301 for (a = 0; a < 4; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000302 opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000303 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000304
Dominik Geyerb46acba2008-05-16 12:55:55 +0000305 /*Program Allowable Opcodes 4 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000306 opmenu[1] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000307 for (a = 4; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000308 opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000309 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000310
Peter Stuge016d4e12009-01-15 02:13:18 +0000311 printf_debug("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000312 switch (flashbus) {
Uwe Hermann394131e2008-10-18 21:14:13 +0000313 case BUS_TYPE_ICH7_SPI:
314 case BUS_TYPE_VIA_SPI:
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000315 REGWRITE16(ICH7_REG_PREOP, preop);
316 REGWRITE16(ICH7_REG_OPTYPE, optype);
317 REGWRITE32(ICH7_REG_OPMENU, opmenu[0]);
318 REGWRITE32(ICH7_REG_OPMENU + 4, opmenu[1]);
319 break;
320 case BUS_TYPE_ICH9_SPI:
321 REGWRITE16(ICH9_REG_PREOP, preop);
322 REGWRITE16(ICH9_REG_OPTYPE, optype);
323 REGWRITE32(ICH9_REG_OPMENU, opmenu[0]);
324 REGWRITE32(ICH9_REG_OPMENU + 4, opmenu[1]);
325 break;
326 default:
327 printf_debug("%s: unsupported chipset\n", __FUNCTION__);
328 return -1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000329 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000330
331 return 0;
332}
333
FENG yu ningf041e9b2008-12-15 02:32:11 +0000334/* This function generates OPCODES from or programs OPCODES to ICH according to
335 * the chipset's SPI configuration lock.
FENG yu ningc05a2952008-12-08 18:16:58 +0000336 *
FENG yu ningf041e9b2008-12-15 02:32:11 +0000337 * It should be called before ICH sends any spi command.
FENG yu ningc05a2952008-12-08 18:16:58 +0000338 */
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000339int ich_init_opcodes(void)
FENG yu ningc05a2952008-12-08 18:16:58 +0000340{
341 int rc = 0;
342 OPCODES *curopcodes_done;
343
344 if (curopcodes)
345 return 0;
346
347 if (ichspi_lock) {
348 printf_debug("Generating OPCODES... ");
349 curopcodes_done = &O_EXISTING;
FENG yu ningf041e9b2008-12-15 02:32:11 +0000350 rc = generate_opcodes(curopcodes_done);
FENG yu ningc05a2952008-12-08 18:16:58 +0000351 } else {
352 printf_debug("Programming OPCODES... ");
353 curopcodes_done = &O_ST_M25P;
354 rc = program_opcodes(curopcodes_done);
355 }
356
357 if (rc) {
358 curopcodes = NULL;
359 printf_debug("failed\n");
360 return 1;
361 } else {
362 curopcodes = curopcodes_done;
363 printf_debug("done\n");
364 return 0;
365 }
366}
367
Stefan Reinauer43119562008-11-02 19:51:50 +0000368static int ich7_run_opcode(OPCODE op, uint32_t offset,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000369 uint8_t datalength, uint8_t * data, int maxdata)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000370{
371 int write_cmd = 0;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000372 int timeout;
Peter Stuge7e2c0792008-06-29 01:30:41 +0000373 uint32_t temp32 = 0;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000374 uint16_t temp16;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000375 uint32_t a;
Stefan Reinauer43119562008-11-02 19:51:50 +0000376 uint64_t opmenu;
377 int opcode_index;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000378
379 /* Is it a write command? */
380 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
381 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
382 write_cmd = 1;
383 }
384
385 /* Programm Offset in Flash into FADDR */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000386 REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000387
388 /* Program data into FDATA0 to N */
389 if (write_cmd && (datalength != 0)) {
390 temp32 = 0;
391 for (a = 0; a < datalength; a++) {
392 if ((a % 4) == 0) {
393 temp32 = 0;
394 }
395
396 temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8);
397
398 if ((a % 4) == 3) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000399 REGWRITE32(ICH7_REG_SPID0 + (a - (a % 4)),
400 temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000401 }
402 }
403 if (((a - 1) % 4) != 3) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000404 REGWRITE32(ICH7_REG_SPID0 +
405 ((a - 1) - ((a - 1) % 4)), temp32);
406 }
407
408 }
409
410 /* Assemble SPIS */
411 temp16 = 0;
412 /* clear error status registers */
413 temp16 |= (SPIS_CDS + SPIS_FCERR);
414 REGWRITE16(ICH7_REG_SPIS, temp16);
415
416 /* Assemble SPIC */
417 temp16 = 0;
418
419 if (datalength != 0) {
420 temp16 |= SPIC_DS;
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000421 temp16 |= ((uint32_t) ((datalength - 1) & (maxdata - 1))) << 8;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000422 }
423
424 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000425 opmenu = REGREAD32(ICH7_REG_OPMENU);
426 opmenu |= ((uint64_t)REGREAD32(ICH7_REG_OPMENU + 4)) << 32;
427
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000428 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
429 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000430 break;
431 }
432 opmenu >>= 8;
433 }
434 if (opcode_index == 8) {
435 printf_debug("Opcode %x not found.\n", op.opcode);
436 return 1;
437 }
438 temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000439
440 /* Handle Atomic */
441 if (op.atomic != 0) {
442 /* Select atomic command */
443 temp16 |= SPIC_ACS;
Carl-Daniel Hailfinger738fdff2008-11-18 00:43:14 +0000444 /* Select prefix opcode */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000445 if ((op.atomic - 1) == 1) {
446 /*Select prefix opcode 2 */
447 temp16 |= SPIC_SPOP;
448 }
449 }
450
451 /* Start */
452 temp16 |= SPIC_SCGO;
453
454 /* write it */
455 REGWRITE16(ICH7_REG_SPIC, temp16);
456
457 /* wait for cycle complete */
Carl-Daniel Hailfinger4c24ad42009-05-09 07:24:23 +0000458 timeout = 100 * 1000 * 60; // 60s is a looong timeout.
Stefan Reinauera9424d52008-06-27 16:28:34 +0000459 while (((REGREAD16(ICH7_REG_SPIS) & SPIS_CDS) == 0) && --timeout) {
Carl-Daniel Hailfinger4c24ad42009-05-09 07:24:23 +0000460 myusec_delay(10);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000461 }
462 if (!timeout) {
463 printf_debug("timeout\n");
464 }
465
466 if ((REGREAD16(ICH7_REG_SPIS) & SPIS_FCERR) != 0) {
467 printf_debug("Transaction error!\n");
468 return 1;
469 }
470
471 if ((!write_cmd) && (datalength != 0)) {
472 for (a = 0; a < datalength; a++) {
473 if ((a % 4) == 0) {
474 temp32 = REGREAD32(ICH7_REG_SPID0 + (a));
475 }
476
477 data[a] =
478 (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8)))
479 >> ((a % 4) * 8);
480 }
481 }
482
483 return 0;
484}
485
Stefan Reinauer43119562008-11-02 19:51:50 +0000486static int ich9_run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000487 uint8_t datalength, uint8_t * data)
488{
489 int write_cmd = 0;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000490 int timeout;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000491 uint32_t temp32;
492 uint32_t a;
Stefan Reinauer43119562008-11-02 19:51:50 +0000493 uint64_t opmenu;
494 int opcode_index;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000495
496 /* Is it a write command? */
497 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
498 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
499 write_cmd = 1;
500 }
501
502 /* Programm Offset in Flash into FADDR */
503 REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */
504
505 /* Program data into FDATA0 to N */
506 if (write_cmd && (datalength != 0)) {
507 temp32 = 0;
508 for (a = 0; a < datalength; a++) {
509 if ((a % 4) == 0) {
510 temp32 = 0;
511 }
512
513 temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8);
514
515 if ((a % 4) == 3) {
516 REGWRITE32(ICH9_REG_FDATA0 + (a - (a % 4)),
517 temp32);
518 }
519 }
520 if (((a - 1) % 4) != 3) {
521 REGWRITE32(ICH9_REG_FDATA0 +
522 ((a - 1) - ((a - 1) % 4)), temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000523 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000524 }
525
526 /* Assemble SSFS + SSFC */
527 temp32 = 0;
528
529 /* clear error status registers */
530 temp32 |= (SSFS_CDS + SSFS_FCERR);
531 /* USE 20 MhZ */
532 temp32 |= SSFC_SCF_20MHZ;
533
534 if (datalength != 0) {
535 uint32_t datatemp;
536 temp32 |= SSFC_DS;
537 datatemp = ((uint32_t) ((datalength - 1) & 0x3f)) << (8 + 8);
538 temp32 |= datatemp;
539 }
540
541 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000542 opmenu = REGREAD32(ICH9_REG_OPMENU);
543 opmenu |= ((uint64_t)REGREAD32(ICH9_REG_OPMENU + 4)) << 32;
544
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000545 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
546 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000547 break;
548 }
549 opmenu >>= 8;
550 }
551 if (opcode_index == 8) {
552 printf_debug("Opcode %x not found.\n", op.opcode);
553 return 1;
554 }
555 temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000556
557 /* Handle Atomic */
558 if (op.atomic != 0) {
559 /* Select atomic command */
560 temp32 |= SSFC_ACS;
561 /* Selct prefix opcode */
562 if ((op.atomic - 1) == 1) {
563 /*Select prefix opcode 2 */
564 temp32 |= SSFC_SPOP;
565 }
566 }
567
568 /* Start */
569 temp32 |= SSFC_SCGO;
570
571 /* write it */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000572 REGWRITE32(ICH9_REG_SSFS, temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000573
574 /*wait for cycle complete */
Carl-Daniel Hailfinger4c24ad42009-05-09 07:24:23 +0000575 timeout = 100 * 1000 * 60; // 60s is a looong timeout.
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000576 while (((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) && --timeout) {
Carl-Daniel Hailfinger4c24ad42009-05-09 07:24:23 +0000577 myusec_delay(10);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000578 }
579 if (!timeout) {
580 printf_debug("timeout\n");
Dominik Geyerb46acba2008-05-16 12:55:55 +0000581 }
582
Stefan Reinauera9424d52008-06-27 16:28:34 +0000583 if ((REGREAD32(ICH9_REG_SSFS) & SSFS_FCERR) != 0) {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000584 printf_debug("Transaction error!\n");
585 return 1;
586 }
587
588 if ((!write_cmd) && (datalength != 0)) {
589 for (a = 0; a < datalength; a++) {
590 if ((a % 4) == 0) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000591 temp32 = REGREAD32(ICH9_REG_FDATA0 + (a));
Dominik Geyerb46acba2008-05-16 12:55:55 +0000592 }
593
594 data[a] =
Stefan Reinauera9424d52008-06-27 16:28:34 +0000595 (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8)))
596 >> ((a % 4) * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000597 }
598 }
599
600 return 0;
601}
602
Stefan Reinauer43119562008-11-02 19:51:50 +0000603static int run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000604 uint8_t datalength, uint8_t * data)
605{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000606 switch (flashbus) {
607 case BUS_TYPE_VIA_SPI:
Stefan Reinauer43119562008-11-02 19:51:50 +0000608 return ich7_run_opcode(op, offset, datalength, data, 16);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000609 case BUS_TYPE_ICH7_SPI:
Stefan Reinauer43119562008-11-02 19:51:50 +0000610 return ich7_run_opcode(op, offset, datalength, data, 64);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000611 case BUS_TYPE_ICH9_SPI:
Stefan Reinauer43119562008-11-02 19:51:50 +0000612 return ich9_run_opcode(op, offset, datalength, data);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000613 default:
614 printf_debug("%s: unsupported chipset\n", __FUNCTION__);
615 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000616
617 /* If we ever get here, something really weird happened */
618 return -1;
619}
620
Uwe Hermann394131e2008-10-18 21:14:13 +0000621static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int offset,
622 int maxdata)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000623{
624 int page_size = flash->page_size;
625 uint32_t remaining = flash->page_size;
626 int a;
627
Stefan Reinauera9424d52008-06-27 16:28:34 +0000628 printf_debug("ich_spi_read_page: offset=%d, number=%d, buf=%p\n",
629 offset, page_size, buf);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000630
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000631 for (a = 0; a < page_size; a += maxdata) {
632 if (remaining < maxdata) {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000633
Carl-Daniel Hailfinger738fdff2008-11-18 00:43:14 +0000634 if (spi_nbyte_read(offset + (page_size - remaining),
635 &buf[page_size - remaining], remaining)) {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000636 printf_debug("Error reading");
637 return 1;
638 }
639 remaining = 0;
640 } else {
Carl-Daniel Hailfinger738fdff2008-11-18 00:43:14 +0000641 if (spi_nbyte_read(offset + (page_size - remaining),
642 &buf[page_size - remaining], maxdata)) {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000643 printf_debug("Error reading");
644 return 1;
645 }
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000646 remaining -= maxdata;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000647 }
648 }
649
650 return 0;
651}
652
653static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000654 int offset, int maxdata)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000655{
656 int page_size = flash->page_size;
657 uint32_t remaining = page_size;
658 int a;
659
Stefan Reinauera9424d52008-06-27 16:28:34 +0000660 printf_debug("ich_spi_write_page: offset=%d, number=%d, buf=%p\n",
661 offset, page_size, bytes);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000662
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000663 for (a = 0; a < page_size; a += maxdata) {
664 if (remaining < maxdata) {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000665 if (run_opcode
Stefan Reinauer43119562008-11-02 19:51:50 +0000666 (curopcodes->opcode[0],
Stefan Reinauera9424d52008-06-27 16:28:34 +0000667 offset + (page_size - remaining), remaining,
Dominik Geyerb46acba2008-05-16 12:55:55 +0000668 &bytes[page_size - remaining]) != 0) {
669 printf_debug("Error writing");
670 return 1;
671 }
672 remaining = 0;
673 } else {
674 if (run_opcode
Stefan Reinauer43119562008-11-02 19:51:50 +0000675 (curopcodes->opcode[0],
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000676 offset + (page_size - remaining), maxdata,
Dominik Geyerb46acba2008-05-16 12:55:55 +0000677 &bytes[page_size - remaining]) != 0) {
678 printf_debug("Error writing");
679 return 1;
680 }
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000681 remaining -= maxdata;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000682 }
683 }
684
685 return 0;
686}
687
Dominik Geyerb46acba2008-05-16 12:55:55 +0000688int ich_spi_read(struct flashchip *flash, uint8_t * buf)
689{
690 int i, rc = 0;
691 int total_size = flash->total_size * 1024;
692 int page_size = flash->page_size;
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000693 int maxdata = 64;
694
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000695 if (flashbus == BUS_TYPE_VIA_SPI) {
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000696 maxdata = 16;
697 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000698
699 for (i = 0; (i < total_size / page_size) && (rc == 0); i++) {
700 rc = ich_spi_read_page(flash, (void *)(buf + i * page_size),
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000701 i * page_size, maxdata);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000702 }
703
704 return rc;
705}
706
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000707int ich_spi_write_256(struct flashchip *flash, uint8_t * buf)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000708{
709 int i, j, rc = 0;
710 int total_size = flash->total_size * 1024;
711 int page_size = flash->page_size;
712 int erase_size = 64 * 1024;
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000713 int maxdata = 64;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000714
715 spi_disable_blockprotect();
716
717 printf("Programming page: \n");
718
719 for (i = 0; i < total_size / erase_size; i++) {
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000720 /* FIMXE: call the chip-specific spi_block_erase_XX instead.
721 * For this, we need to add a block erase function to
722 * struct flashchip.
723 */
724 rc = spi_block_erase_d8(flash, i * erase_size);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000725 if (rc) {
726 printf("Error erasing block at 0x%x\n", i);
727 break;
728 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000729
Peter Stuge6a214162008-07-07 05:14:06 +0000730 if (flashbus == BUS_TYPE_VIA_SPI)
731 maxdata = 16;
732
Dominik Geyerb46acba2008-05-16 12:55:55 +0000733 for (j = 0; j < erase_size / page_size; j++) {
Uwe Hermann394131e2008-10-18 21:14:13 +0000734 ich_spi_write_page(flash,
735 (void *)(buf + (i * erase_size) + (j * page_size)),
736 (i * erase_size) + (j * page_size), maxdata);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000737 }
738 }
739
740 printf("\n");
741
742 return rc;
743}
744
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000745int ich_spi_command(unsigned int writecnt, unsigned int readcnt,
746 const unsigned char *writearr, unsigned char *readarr)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000747{
748 int a;
749 int opcode_index = -1;
750 const unsigned char cmd = *writearr;
751 OPCODE *opcode;
752 uint32_t addr = 0;
753 uint8_t *data;
754 int count;
755
Dominik Geyerb46acba2008-05-16 12:55:55 +0000756 /* find cmd in opcodes-table */
757 for (a = 0; a < 8; a++) {
758 if ((curopcodes->opcode[a]).opcode == cmd) {
759 opcode_index = a;
760 break;
761 }
762 }
763
764 /* unknown / not programmed command */
765 if (opcode_index == -1) {
766 printf_debug("Invalid OPCODE 0x%02x\n", cmd);
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000767 return SPI_INVALID_OPCODE;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000768 }
769
770 opcode = &(curopcodes->opcode[opcode_index]);
771
772 /* if opcode-type requires an address */
773 if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS ||
774 opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000775 addr = (writearr[1] << 16) |
776 (writearr[2] << 8) | (writearr[3] << 0);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000777 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000778
Dominik Geyerb46acba2008-05-16 12:55:55 +0000779 /* translate read/write array/count */
780 if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000781 data = (uint8_t *) (writearr + 1);
782 count = writecnt - 1;
783 } else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
784 data = (uint8_t *) (writearr + 4);
785 count = writecnt - 4;
786 } else {
787 data = (uint8_t *) readarr;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000788 count = readcnt;
789 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000790
Stefan Reinauer43119562008-11-02 19:51:50 +0000791 if (run_opcode(*opcode, addr, count, data) != 0) {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000792 printf_debug("run OPCODE 0x%02x failed\n", opcode->opcode);
793 return 1;
794 }
795
796 return 0;
797}