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Dominik Geyerb46acba2008-05-16 12:55:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2008 Stefan Wildemann <stefan.wildemann@kontron.com>
5 * Copyright (C) 2008 Claus Gindhart <claus.gindhart@kontron.com>
6 * Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com>
Stefan Reinauera9424d52008-06-27 16:28:34 +00007 * Copyright (C) 2008 coresystems GmbH <info@coresystems.de>
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +00008 * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
Dominik Geyerb46acba2008-05-16 12:55:55 +00009 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Dominik Geyerb46acba2008-05-16 12:55:55 +000023 */
24
25/*
26 * This module is designed for supporting the devices
27 * ST M25P40
28 * ST M25P80
29 * ST M25P16
30 * ST M25P32 already tested
31 * ST M25P64
32 * AT 25DF321 already tested
Helge Wagner738e2522010-10-05 22:06:05 +000033 * ... and many more SPI flash devices
Dominik Geyerb46acba2008-05-16 12:55:55 +000034 *
35 */
36
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000037#if defined(__i386__) || defined(__x86_64__)
38
Dominik Geyerb46acba2008-05-16 12:55:55 +000039#include <string.h>
Dominik Geyerb46acba2008-05-16 12:55:55 +000040#include "flash.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000041#include "chipdrivers.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000042#include "programmer.h"
Dominik Geyerb46acba2008-05-16 12:55:55 +000043#include "spi.h"
44
Stefan Reinauera9424d52008-06-27 16:28:34 +000045/* ICH9 controller register definition */
Stefan Taunerc0aaf952011-05-19 02:58:17 +000046#define ICH9_REG_FADDR 0x08 /* 32 Bits */
47#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */
Stefan Reinauera9424d52008-06-27 16:28:34 +000048
Stefan Taunerc0aaf952011-05-19 02:58:17 +000049#define ICH9_REG_SSFS 0x90 /* 08 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +000050#define SSFS_SCIP 0x00000001
51#define SSFS_CDS 0x00000004
52#define SSFS_FCERR 0x00000008
53#define SSFS_AEL 0x00000010
Stefan Taunerc0aaf952011-05-19 02:58:17 +000054/* The following bits are reserved in SSFS: 1,5-7. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +000055#define SSFS_RESERVED_MASK 0x000000e2
Stefan Reinauera9424d52008-06-27 16:28:34 +000056
Stefan Taunerc0aaf952011-05-19 02:58:17 +000057#define ICH9_REG_SSFC 0x91 /* 24 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +000058#define SSFC_SCGO 0x00000200
59#define SSFC_ACS 0x00000400
60#define SSFC_SPOP 0x00000800
61#define SSFC_COP 0x00001000
62#define SSFC_DBC 0x00010000
63#define SSFC_DS 0x00400000
64#define SSFC_SME 0x00800000
65#define SSFC_SCF 0x01000000
66#define SSFC_SCF_20MHZ 0x00000000
67#define SSFC_SCF_33MHZ 0x01000000
Stefan Taunerc0aaf952011-05-19 02:58:17 +000068/* We combine SSFS and SSFC to one 32-bit word,
69 * therefore SSFC bits are off by 8.
70 * The following bits are reserved in SSFC: 23-19,7,0. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +000071#define SSFC_RESERVED_MASK 0xf8008100
Stefan Reinauera9424d52008-06-27 16:28:34 +000072
Stefan Taunerc0aaf952011-05-19 02:58:17 +000073#define ICH9_REG_PREOP 0x94 /* 16 Bits */
74#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */
75#define ICH9_REG_OPMENU 0x98 /* 64 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +000076
77// ICH9R SPI commands
Stefan Taunerc0aaf952011-05-19 02:58:17 +000078#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
79#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
80#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
81#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
Dominik Geyerb46acba2008-05-16 12:55:55 +000082
Stefan Reinauera9424d52008-06-27 16:28:34 +000083// ICH7 registers
Stefan Taunerc0aaf952011-05-19 02:58:17 +000084#define ICH7_REG_SPIS 0x00 /* 16 Bits */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +000085#define SPIS_SCIP 0x0001
86#define SPIS_GRANT 0x0002
87#define SPIS_CDS 0x0004
88#define SPIS_FCERR 0x0008
89#define SPIS_RESERVED_MASK 0x7ff0
Stefan Reinauera9424d52008-06-27 16:28:34 +000090
Rudolf Marek3fdbccf2008-06-30 21:38:30 +000091/* VIA SPI is compatible with ICH7, but maxdata
92 to transfer is 16 bytes.
93
94 DATA byte count on ICH7 is 8:13, on VIA 8:11
95
96 bit 12 is port select CS0 CS1
97 bit 13 is FAST READ enable
98 bit 7 is used with fast read and one shot controls CS de-assert?
99*/
100
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000101#define ICH7_REG_SPIC 0x02 /* 16 Bits */
102#define SPIC_SCGO 0x0002
103#define SPIC_ACS 0x0004
104#define SPIC_SPOP 0x0008
105#define SPIC_DS 0x4000
Stefan Reinauera9424d52008-06-27 16:28:34 +0000106
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000107#define ICH7_REG_SPIA 0x04 /* 32 Bits */
108#define ICH7_REG_SPID0 0x08 /* 64 Bytes */
109#define ICH7_REG_PREOP 0x54 /* 16 Bits */
110#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */
111#define ICH7_REG_OPMENU 0x58 /* 64 Bits */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000112
FENG yu ningc05a2952008-12-08 18:16:58 +0000113/* ICH SPI configuration lock-down. May be set during chipset enabling. */
Michael Karchera4448d92010-07-22 18:04:15 +0000114static int ichspi_lock = 0;
FENG yu ningc05a2952008-12-08 18:16:58 +0000115
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000116uint32_t ichspi_bbar = 0;
117
Michael Karchera4448d92010-07-22 18:04:15 +0000118static void *ich_spibar = NULL;
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000119
Dominik Geyerb46acba2008-05-16 12:55:55 +0000120typedef struct _OPCODE {
121 uint8_t opcode; //This commands spi opcode
122 uint8_t spi_type; //This commands spi type
123 uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1
124} OPCODE;
125
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000126/* Suggested opcode definition:
Dominik Geyerb46acba2008-05-16 12:55:55 +0000127 * Preop 1: Write Enable
128 * Preop 2: Write Status register enable
129 *
130 * OP 0: Write address
131 * OP 1: Read Address
132 * OP 2: ERASE block
133 * OP 3: Read Status register
134 * OP 4: Read ID
135 * OP 5: Write Status register
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000136 * OP 6: chip private (read JEDEC id)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000137 * OP 7: Chip erase
138 */
139typedef struct _OPCODES {
140 uint8_t preop[2];
141 OPCODE opcode[8];
142} OPCODES;
143
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000144static OPCODES *curopcodes = NULL;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000145
146/* HW access functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000147static uint32_t REGREAD32(int X)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000148{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000149 return mmio_readl(ich_spibar + X);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000150}
151
Uwe Hermann09e04f72009-05-16 22:36:00 +0000152static uint16_t REGREAD16(int X)
Stefan Reinauera9424d52008-06-27 16:28:34 +0000153{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000154 return mmio_readw(ich_spibar + X);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000155}
156
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000157static uint16_t REGREAD8(int X)
158{
159 return mmio_readb(ich_spibar + X);
160}
161
Stefan Tauner355cbfd2011-05-28 02:37:14 +0000162#define REGWRITE32(off,val) mmio_writel(val, ich_spibar+off)
163#define REGWRITE16(off,val) mmio_writew(val, ich_spibar+off)
164#define REGWRITE8(off,val) mmio_writeb(val, ich_spibar+off)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000165
Dominik Geyerb46acba2008-05-16 12:55:55 +0000166/* Common SPI functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000167static int find_opcode(OPCODES *op, uint8_t opcode);
168static int find_preop(OPCODES *op, uint8_t preop);
FENG yu ningf041e9b2008-12-15 02:32:11 +0000169static int generate_opcodes(OPCODES * op);
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000170static int program_opcodes(OPCODES *op, int enable_undo);
Stefan Reinauer43119562008-11-02 19:51:50 +0000171static int run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000172 uint8_t datalength, uint8_t * data);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000173
FENG yu ningf041e9b2008-12-15 02:32:11 +0000174/* for pairing opcodes with their required preop */
175struct preop_opcode_pair {
176 uint8_t preop;
177 uint8_t opcode;
178};
179
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000180/* List of opcodes which need preopcodes and matching preopcodes. Unused. */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000181const struct preop_opcode_pair pops[] = {
FENG yu ningf041e9b2008-12-15 02:32:11 +0000182 {JEDEC_WREN, JEDEC_BYTE_PROGRAM},
183 {JEDEC_WREN, JEDEC_SE}, /* sector erase */
184 {JEDEC_WREN, JEDEC_BE_52}, /* block erase */
185 {JEDEC_WREN, JEDEC_BE_D8}, /* block erase */
186 {JEDEC_WREN, JEDEC_CE_60}, /* chip erase */
187 {JEDEC_WREN, JEDEC_CE_C7}, /* chip erase */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000188 /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */
189 {JEDEC_WREN, JEDEC_WRSR},
FENG yu ningf041e9b2008-12-15 02:32:11 +0000190 {JEDEC_EWSR, JEDEC_WRSR},
191 {0,}
192};
193
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000194/* Reasonable default configuration. Needs ad-hoc modifications if we
195 * encounter unlisted opcodes. Fun.
196 */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000197static OPCODES O_ST_M25P = {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000198 {
199 JEDEC_WREN,
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000200 JEDEC_EWSR,
201 },
Dominik Geyerb46acba2008-05-16 12:55:55 +0000202 {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000203 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000204 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000205 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000206 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
Carl-Daniel Hailfinger15aa7c62009-05-26 21:25:08 +0000207 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000208 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000209 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000210 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
211 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000212};
213
Helge Wagner738e2522010-10-05 22:06:05 +0000214/* List of opcodes with their corresponding spi_type
215 * It is used to reprogram the chipset OPCODE table on-the-fly if an opcode
216 * is needed which is currently not in the chipset OPCODE table
217 */
218static OPCODE POSSIBLE_OPCODES[] = {
219 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
220 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
221 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
222 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
223 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
224 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
225 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
226 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
227 {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Sector erase
228 {JEDEC_BE_52, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Block erase
229 {JEDEC_AAI_WORD_PROGRAM, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Auto Address Increment
230};
231
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000232static OPCODES O_EXISTING = {};
FENG yu ningc05a2952008-12-08 18:16:58 +0000233
Helge Wagner738e2522010-10-05 22:06:05 +0000234static uint8_t lookup_spi_type(uint8_t opcode)
235{
236 int a;
237
238 for (a = 0; a < sizeof(POSSIBLE_OPCODES)/sizeof(POSSIBLE_OPCODES[0]); a++) {
239 if (POSSIBLE_OPCODES[a].opcode == opcode)
240 return POSSIBLE_OPCODES[a].spi_type;
241 }
242
243 return 0xFF;
244}
245
246static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt)
247{
248 uint8_t spi_type;
249
250 spi_type = lookup_spi_type(opcode);
251 if (spi_type > 3) {
252 /* Try to guess spi type from read/write sizes.
253 * The following valid writecnt/readcnt combinations exist:
254 * writecnt = 4, readcnt >= 0
255 * writecnt = 1, readcnt >= 0
256 * writecnt >= 4, readcnt = 0
257 * writecnt >= 1, readcnt = 0
258 * writecnt >= 1 is guaranteed for all commands.
259 */
260 if (readcnt == 0)
261 /* if readcnt=0 and writecount >= 4, we don't know if it is WRITE_NO_ADDRESS
262 * or WRITE_WITH_ADDRESS. But if we use WRITE_NO_ADDRESS and the first 3 data
263 * bytes are actual the address, they go to the bus anyhow
264 */
265 spi_type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
266 else if (writecnt == 1) // and readcnt is > 0
267 spi_type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
268 else if (writecnt == 4) // and readcnt is > 0
269 spi_type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
270 // else we have an invalid case, will be handled below
271 }
272 if (spi_type <= 3) {
273 int oppos=2; // use original JEDEC_BE_D8 offset
274 curopcodes->opcode[oppos].opcode = opcode;
275 curopcodes->opcode[oppos].spi_type = spi_type;
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000276 program_opcodes(curopcodes, 0);
Helge Wagner738e2522010-10-05 22:06:05 +0000277 oppos = find_opcode(curopcodes, opcode);
278 msg_pdbg ("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos);
279 return oppos;
280 }
281 return -1;
282}
283
Uwe Hermann09e04f72009-05-16 22:36:00 +0000284static int find_opcode(OPCODES *op, uint8_t opcode)
FENG yu ningc05a2952008-12-08 18:16:58 +0000285{
286 int a;
287
288 for (a = 0; a < 8; a++) {
289 if (op->opcode[a].opcode == opcode)
290 return a;
291 }
292
293 return -1;
294}
295
Uwe Hermann09e04f72009-05-16 22:36:00 +0000296static int find_preop(OPCODES *op, uint8_t preop)
FENG yu ningc05a2952008-12-08 18:16:58 +0000297{
298 int a;
299
300 for (a = 0; a < 2; a++) {
301 if (op->preop[a] == preop)
302 return a;
303 }
304
305 return -1;
306}
307
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000308/* Create a struct OPCODES based on what we find in the locked down chipset. */
FENG yu ningf041e9b2008-12-15 02:32:11 +0000309static int generate_opcodes(OPCODES * op)
FENG yu ningc05a2952008-12-08 18:16:58 +0000310{
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000311 int a;
FENG yu ningc05a2952008-12-08 18:16:58 +0000312 uint16_t preop, optype;
313 uint32_t opmenu[2];
FENG yu ningc05a2952008-12-08 18:16:58 +0000314
315 if (op == NULL) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000316 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
FENG yu ningc05a2952008-12-08 18:16:58 +0000317 return -1;
318 }
319
Michael Karcherb9dbe482011-05-11 17:07:07 +0000320 switch (spi_programmer->type) {
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000321 case SPI_CONTROLLER_ICH7:
322 case SPI_CONTROLLER_VIA:
FENG yu ningc05a2952008-12-08 18:16:58 +0000323 preop = REGREAD16(ICH7_REG_PREOP);
324 optype = REGREAD16(ICH7_REG_OPTYPE);
325 opmenu[0] = REGREAD32(ICH7_REG_OPMENU);
326 opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4);
327 break;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000328 case SPI_CONTROLLER_ICH9:
FENG yu ningc05a2952008-12-08 18:16:58 +0000329 preop = REGREAD16(ICH9_REG_PREOP);
330 optype = REGREAD16(ICH9_REG_OPTYPE);
331 opmenu[0] = REGREAD32(ICH9_REG_OPMENU);
332 opmenu[1] = REGREAD32(ICH9_REG_OPMENU + 4);
333 break;
334 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000335 msg_perr("%s: unsupported chipset\n", __func__);
FENG yu ningc05a2952008-12-08 18:16:58 +0000336 return -1;
337 }
338
339 op->preop[0] = (uint8_t) preop;
340 op->preop[1] = (uint8_t) (preop >> 8);
341
342 for (a = 0; a < 8; a++) {
343 op->opcode[a].spi_type = (uint8_t) (optype & 0x3);
344 optype >>= 2;
345 }
346
347 for (a = 0; a < 4; a++) {
348 op->opcode[a].opcode = (uint8_t) (opmenu[0] & 0xff);
349 opmenu[0] >>= 8;
350 }
351
352 for (a = 4; a < 8; a++) {
353 op->opcode[a].opcode = (uint8_t) (opmenu[1] & 0xff);
354 opmenu[1] >>= 8;
355 }
356
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000357 /* No preopcodes used by default. */
358 for (a = 0; a < 8; a++)
FENG yu ningc05a2952008-12-08 18:16:58 +0000359 op->opcode[a].atomic = 0;
360
FENG yu ningc05a2952008-12-08 18:16:58 +0000361 return 0;
362}
363
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000364static int program_opcodes(OPCODES *op, int enable_undo)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000365{
366 uint8_t a;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000367 uint16_t preop, optype;
368 uint32_t opmenu[2];
Dominik Geyerb46acba2008-05-16 12:55:55 +0000369
370 /* Program Prefix Opcodes */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000371 /* 0:7 Prefix Opcode 1 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000372 preop = (op->preop[0]);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000373 /* 8:16 Prefix Opcode 2 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000374 preop |= ((uint16_t) op->preop[1]) << 8;
Uwe Hermann394131e2008-10-18 21:14:13 +0000375
Stefan Reinauera9424d52008-06-27 16:28:34 +0000376 /* Program Opcode Types 0 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000377 optype = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000378 for (a = 0; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000379 optype |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000380 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000381
Stefan Reinauera9424d52008-06-27 16:28:34 +0000382 /* Program Allowable Opcodes 0 - 3 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000383 opmenu[0] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000384 for (a = 0; a < 4; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000385 opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000386 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000387
Dominik Geyerb46acba2008-05-16 12:55:55 +0000388 /*Program Allowable Opcodes 4 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000389 opmenu[1] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000390 for (a = 4; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000391 opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000392 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000393
Sean Nelson316a29f2010-05-07 20:09:04 +0000394 msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]);
Michael Karcherb9dbe482011-05-11 17:07:07 +0000395 switch (spi_programmer->type) {
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000396 case SPI_CONTROLLER_ICH7:
397 case SPI_CONTROLLER_VIA:
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000398 /* Register undo only for enable_undo=1, i.e. first call. */
399 if (enable_undo) {
400 rmmio_valw(ich_spibar + ICH7_REG_PREOP);
401 rmmio_valw(ich_spibar + ICH7_REG_OPTYPE);
402 rmmio_vall(ich_spibar + ICH7_REG_OPMENU);
403 rmmio_vall(ich_spibar + ICH7_REG_OPMENU + 4);
404 }
405 mmio_writew(preop, ich_spibar + ICH7_REG_PREOP);
406 mmio_writew(optype, ich_spibar + ICH7_REG_OPTYPE);
407 mmio_writel(opmenu[0], ich_spibar + ICH7_REG_OPMENU);
408 mmio_writel(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000409 break;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000410 case SPI_CONTROLLER_ICH9:
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000411 /* Register undo only for enable_undo=1, i.e. first call. */
412 if (enable_undo) {
413 rmmio_valw(ich_spibar + ICH9_REG_PREOP);
414 rmmio_valw(ich_spibar + ICH9_REG_OPTYPE);
415 rmmio_vall(ich_spibar + ICH9_REG_OPMENU);
416 rmmio_vall(ich_spibar + ICH9_REG_OPMENU + 4);
417 }
418 mmio_writew(preop, ich_spibar + ICH9_REG_PREOP);
419 mmio_writew(optype, ich_spibar + ICH9_REG_OPTYPE);
420 mmio_writel(opmenu[0], ich_spibar + ICH9_REG_OPMENU);
421 mmio_writel(opmenu[1], ich_spibar + ICH9_REG_OPMENU + 4);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000422 break;
423 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000424 msg_perr("%s: unsupported chipset\n", __func__);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000425 return -1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000426 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000427
428 return 0;
429}
430
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000431/*
432 * Try to set BBAR (BIOS Base Address Register), but read back the value in case
433 * it didn't stick.
434 */
435void ich_set_bbar(uint32_t minaddr)
436{
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +0000437#define BBAR_MASK 0x00ffff00
438 minaddr &= BBAR_MASK;
Michael Karcherb9dbe482011-05-11 17:07:07 +0000439 switch (spi_programmer->type) {
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000440 case SPI_CONTROLLER_ICH7:
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +0000441 case SPI_CONTROLLER_VIA:
442 ichspi_bbar = mmio_readl(ich_spibar + 0x50) & ~BBAR_MASK;
443 if (ichspi_bbar)
444 msg_pdbg("Reserved bits in BBAR not zero: 0x%04x",
445 ichspi_bbar);
446 ichspi_bbar |= minaddr;
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000447 rmmio_writel(ichspi_bbar, ich_spibar + 0x50);
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000448 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000449 /* We don't have any option except complaining. And if the write
450 * failed, the restore will fail as well, so no problem there.
451 */
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000452 if (ichspi_bbar != minaddr)
453 msg_perr("Setting BBAR failed!\n");
454 break;
455 case SPI_CONTROLLER_ICH9:
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +0000456 ichspi_bbar = mmio_readl(ich_spibar + 0xA0) & ~BBAR_MASK;
457 if (ichspi_bbar)
458 msg_pdbg("Reserved bits in BBAR not zero: 0x%04x",
459 ichspi_bbar);
460 ichspi_bbar |= minaddr;
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000461 rmmio_writel(ichspi_bbar, ich_spibar + 0xA0);
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000462 ichspi_bbar = mmio_readl(ich_spibar + 0xA0);
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000463 /* We don't have any option except complaining. And if the write
464 * failed, the restore will fail as well, so no problem there.
465 */
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000466 if (ichspi_bbar != minaddr)
467 msg_perr("Setting BBAR failed!\n");
468 break;
469 default:
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +0000470 msg_perr("Unknown chipset for BBAR setting!\n");
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000471 break;
472 }
473}
474
FENG yu ningf041e9b2008-12-15 02:32:11 +0000475/* This function generates OPCODES from or programs OPCODES to ICH according to
476 * the chipset's SPI configuration lock.
FENG yu ningc05a2952008-12-08 18:16:58 +0000477 *
FENG yu ningf041e9b2008-12-15 02:32:11 +0000478 * It should be called before ICH sends any spi command.
FENG yu ningc05a2952008-12-08 18:16:58 +0000479 */
Michael Karchera4448d92010-07-22 18:04:15 +0000480static int ich_init_opcodes(void)
FENG yu ningc05a2952008-12-08 18:16:58 +0000481{
482 int rc = 0;
483 OPCODES *curopcodes_done;
484
485 if (curopcodes)
486 return 0;
487
488 if (ichspi_lock) {
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000489 msg_pdbg("Reading OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000490 curopcodes_done = &O_EXISTING;
FENG yu ningf041e9b2008-12-15 02:32:11 +0000491 rc = generate_opcodes(curopcodes_done);
FENG yu ningc05a2952008-12-08 18:16:58 +0000492 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000493 msg_pdbg("Programming OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000494 curopcodes_done = &O_ST_M25P;
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000495 rc = program_opcodes(curopcodes_done, 1);
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000496 /* Technically not part of opcode init, but it allows opcodes
497 * to run without transaction errors by setting the lowest
498 * allowed address to zero.
499 */
500 ich_set_bbar(0);
FENG yu ningc05a2952008-12-08 18:16:58 +0000501 }
502
503 if (rc) {
504 curopcodes = NULL;
Sean Nelson316a29f2010-05-07 20:09:04 +0000505 msg_perr("failed\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000506 return 1;
507 } else {
508 curopcodes = curopcodes_done;
Sean Nelson316a29f2010-05-07 20:09:04 +0000509 msg_pdbg("done\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000510 return 0;
511 }
512}
513
Stefan Reinauer43119562008-11-02 19:51:50 +0000514static int ich7_run_opcode(OPCODE op, uint32_t offset,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000515 uint8_t datalength, uint8_t * data, int maxdata)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000516{
517 int write_cmd = 0;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000518 int timeout;
Peter Stuge7e2c0792008-06-29 01:30:41 +0000519 uint32_t temp32 = 0;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000520 uint16_t temp16;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000521 uint32_t a;
Stefan Reinauer43119562008-11-02 19:51:50 +0000522 uint64_t opmenu;
523 int opcode_index;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000524
525 /* Is it a write command? */
526 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
527 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
528 write_cmd = 1;
529 }
530
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000531 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
532 while ((REGREAD16(ICH7_REG_SPIS) & SPIS_SCIP) && --timeout) {
533 programmer_delay(10);
534 }
535 if (!timeout) {
536 msg_perr("Error: SCIP never cleared!\n");
537 return 1;
538 }
539
Dominik Geyerb46acba2008-05-16 12:55:55 +0000540 /* Programm Offset in Flash into FADDR */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000541 REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000542
543 /* Program data into FDATA0 to N */
544 if (write_cmd && (datalength != 0)) {
545 temp32 = 0;
546 for (a = 0; a < datalength; a++) {
547 if ((a % 4) == 0) {
548 temp32 = 0;
549 }
550
551 temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8);
552
553 if ((a % 4) == 3) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000554 REGWRITE32(ICH7_REG_SPID0 + (a - (a % 4)),
555 temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000556 }
557 }
558 if (((a - 1) % 4) != 3) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000559 REGWRITE32(ICH7_REG_SPID0 +
560 ((a - 1) - ((a - 1) % 4)), temp32);
561 }
562
563 }
564
565 /* Assemble SPIS */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000566 temp16 = REGREAD16(ICH7_REG_SPIS);
567 /* keep reserved bits */
568 temp16 &= SPIS_RESERVED_MASK;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000569 /* clear error status registers */
570 temp16 |= (SPIS_CDS + SPIS_FCERR);
571 REGWRITE16(ICH7_REG_SPIS, temp16);
572
573 /* Assemble SPIC */
574 temp16 = 0;
575
576 if (datalength != 0) {
577 temp16 |= SPIC_DS;
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000578 temp16 |= ((uint32_t) ((datalength - 1) & (maxdata - 1))) << 8;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000579 }
580
581 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000582 opmenu = REGREAD32(ICH7_REG_OPMENU);
583 opmenu |= ((uint64_t)REGREAD32(ICH7_REG_OPMENU + 4)) << 32;
584
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000585 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
586 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000587 break;
588 }
589 opmenu >>= 8;
590 }
591 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000592 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +0000593 return 1;
594 }
595 temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000596
Michael Karcher136125a2011-04-29 22:11:36 +0000597 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
598 /* Handle Atomic. Atomic commands include three steps:
599 - sending the preop (mainly EWSR or WREN)
600 - sending the main command
601 - waiting for the busy bit (WIP) to be cleared
602 This means the timeout must be sufficient for chip erase
603 of slow high-capacity chips.
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000604 */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000605 switch (op.atomic) {
606 case 2:
607 /* Select second preop. */
608 temp16 |= SPIC_SPOP;
609 /* And fall through. */
610 case 1:
611 /* Atomic command (preop+op) */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000612 temp16 |= SPIC_ACS;
Michael Karcher136125a2011-04-29 22:11:36 +0000613 timeout = 100 * 1000 * 60; /* 60 seconds */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000614 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000615 }
616
617 /* Start */
618 temp16 |= SPIC_SCGO;
619
620 /* write it */
621 REGWRITE16(ICH7_REG_SPIC, temp16);
622
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000623 /* Wait for Cycle Done Status or Flash Cycle Error. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000624 while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) &&
625 --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000626 programmer_delay(10);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000627 }
628 if (!timeout) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000629 msg_perr("timeout, ICH7_REG_SPIS=0x%04x\n",
630 REGREAD16(ICH7_REG_SPIS));
631 return 1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000632 }
633
Sean Nelson316a29f2010-05-07 20:09:04 +0000634 /* FIXME: make sure we do not needlessly cause transaction errors. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000635 temp16 = REGREAD16(ICH7_REG_SPIS);
636 if (temp16 & SPIS_FCERR) {
Stefan Tauner8ed29342011-04-29 23:53:09 +0000637 msg_perr("Transaction error!\n");
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000638 /* keep reserved bits */
639 temp16 &= SPIS_RESERVED_MASK;
640 REGWRITE16(ICH7_REG_SPIS, temp16 | SPIS_FCERR);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000641 return 1;
642 }
643
644 if ((!write_cmd) && (datalength != 0)) {
645 for (a = 0; a < datalength; a++) {
646 if ((a % 4) == 0) {
647 temp32 = REGREAD32(ICH7_REG_SPID0 + (a));
648 }
649
650 data[a] =
651 (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8)))
652 >> ((a % 4) * 8);
653 }
654 }
655
656 return 0;
657}
658
Stefan Reinauer43119562008-11-02 19:51:50 +0000659static int ich9_run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000660 uint8_t datalength, uint8_t * data)
661{
662 int write_cmd = 0;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000663 int timeout;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000664 uint32_t temp32;
665 uint32_t a;
Stefan Reinauer43119562008-11-02 19:51:50 +0000666 uint64_t opmenu;
667 int opcode_index;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000668
669 /* Is it a write command? */
670 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
671 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
672 write_cmd = 1;
673 }
674
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000675 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
676 while ((REGREAD8(ICH9_REG_SSFS) & SSFS_SCIP) && --timeout) {
677 programmer_delay(10);
678 }
679 if (!timeout) {
680 msg_perr("Error: SCIP never cleared!\n");
681 return 1;
682 }
683
Stefan Reinauera9424d52008-06-27 16:28:34 +0000684 /* Programm Offset in Flash into FADDR */
685 REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */
686
687 /* Program data into FDATA0 to N */
688 if (write_cmd && (datalength != 0)) {
689 temp32 = 0;
690 for (a = 0; a < datalength; a++) {
691 if ((a % 4) == 0) {
692 temp32 = 0;
693 }
694
695 temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8);
696
697 if ((a % 4) == 3) {
698 REGWRITE32(ICH9_REG_FDATA0 + (a - (a % 4)),
699 temp32);
700 }
701 }
702 if (((a - 1) % 4) != 3) {
703 REGWRITE32(ICH9_REG_FDATA0 +
704 ((a - 1) - ((a - 1) % 4)), temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000705 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000706 }
707
708 /* Assemble SSFS + SSFC */
Helge Wagnera319be12010-08-11 21:06:10 +0000709 temp32 = REGREAD32(ICH9_REG_SSFS);
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000710 /* Keep reserved bits only */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000711 temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000712 /* clear error status registers */
713 temp32 |= (SSFS_CDS + SSFS_FCERR);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000714 REGWRITE32(ICH9_REG_SSFS, temp32);
715
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000716 /* Use 20 MHz */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000717 temp32 |= SSFC_SCF_20MHZ;
718
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000719 /* Set data byte count (DBC) and data cycle bit (DS) */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000720 if (datalength != 0) {
721 uint32_t datatemp;
722 temp32 |= SSFC_DS;
723 datatemp = ((uint32_t) ((datalength - 1) & 0x3f)) << (8 + 8);
724 temp32 |= datatemp;
725 }
726
727 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000728 opmenu = REGREAD32(ICH9_REG_OPMENU);
729 opmenu |= ((uint64_t)REGREAD32(ICH9_REG_OPMENU + 4)) << 32;
730
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000731 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
732 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000733 break;
734 }
735 opmenu >>= 8;
736 }
737 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000738 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +0000739 return 1;
740 }
741 temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000742
Michael Karcher136125a2011-04-29 22:11:36 +0000743 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
744 /* Handle Atomic. Atomic commands include three steps:
745 - sending the preop (mainly EWSR or WREN)
746 - sending the main command
747 - waiting for the busy bit (WIP) to be cleared
748 This means the timeout must be sufficient for chip erase
749 of slow high-capacity chips.
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000750 */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000751 switch (op.atomic) {
752 case 2:
753 /* Select second preop. */
754 temp32 |= SSFC_SPOP;
755 /* And fall through. */
756 case 1:
757 /* Atomic command (preop+op) */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000758 temp32 |= SSFC_ACS;
Michael Karcher136125a2011-04-29 22:11:36 +0000759 timeout = 100 * 1000 * 60; /* 60 seconds */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000760 break;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000761 }
762
763 /* Start */
764 temp32 |= SSFC_SCGO;
765
766 /* write it */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000767 REGWRITE32(ICH9_REG_SSFS, temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000768
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000769 /* Wait for Cycle Done Status or Flash Cycle Error. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000770 while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_CDS | SSFS_FCERR)) == 0) &&
771 --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000772 programmer_delay(10);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000773 }
774 if (!timeout) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000775 msg_perr("timeout, ICH9_REG_SSFS=0x%08x\n",
776 REGREAD32(ICH9_REG_SSFS));
777 return 1;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000778 }
779
Sean Nelson316a29f2010-05-07 20:09:04 +0000780 /* FIXME make sure we do not needlessly cause transaction errors. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000781 temp32 = REGREAD32(ICH9_REG_SSFS);
782 if (temp32 & SSFS_FCERR) {
Stefan Tauner8ed29342011-04-29 23:53:09 +0000783 msg_perr("Transaction error!\n");
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000784 /* keep reserved bits */
785 temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
786 /* Clear the transaction error. */
787 REGWRITE32(ICH9_REG_SSFS, temp32 | SSFS_FCERR);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000788 return 1;
789 }
790
791 if ((!write_cmd) && (datalength != 0)) {
792 for (a = 0; a < datalength; a++) {
793 if ((a % 4) == 0) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000794 temp32 = REGREAD32(ICH9_REG_FDATA0 + (a));
Dominik Geyerb46acba2008-05-16 12:55:55 +0000795 }
796
797 data[a] =
Stefan Reinauera9424d52008-06-27 16:28:34 +0000798 (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8)))
799 >> ((a % 4) * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000800 }
801 }
802
803 return 0;
804}
805
Stefan Reinauer43119562008-11-02 19:51:50 +0000806static int run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000807 uint8_t datalength, uint8_t * data)
808{
Michael Karcherb9dbe482011-05-11 17:07:07 +0000809 switch (spi_programmer->type) {
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000810 case SPI_CONTROLLER_VIA:
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000811 if (datalength > 16) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000812 msg_perr("%s: Internal command size error for "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000813 "opcode 0x%02x, got datalength=%i, want <=16\n",
814 __func__, op.opcode, datalength);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000815 return SPI_INVALID_LENGTH;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000816 }
Stefan Reinauer43119562008-11-02 19:51:50 +0000817 return ich7_run_opcode(op, offset, datalength, data, 16);
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000818 case SPI_CONTROLLER_ICH7:
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000819 if (datalength > 64) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000820 msg_perr("%s: Internal command size error for "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000821 "opcode 0x%02x, got datalength=%i, want <=16\n",
822 __func__, op.opcode, datalength);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000823 return SPI_INVALID_LENGTH;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000824 }
Stefan Reinauer43119562008-11-02 19:51:50 +0000825 return ich7_run_opcode(op, offset, datalength, data, 64);
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000826 case SPI_CONTROLLER_ICH9:
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000827 if (datalength > 64) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000828 msg_perr("%s: Internal command size error for "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000829 "opcode 0x%02x, got datalength=%i, want <=16\n",
830 __func__, op.opcode, datalength);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000831 return SPI_INVALID_LENGTH;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000832 }
Stefan Reinauer43119562008-11-02 19:51:50 +0000833 return ich9_run_opcode(op, offset, datalength, data);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000834 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000835 msg_perr("%s: unsupported chipset\n", __func__);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000836 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000837
838 /* If we ever get here, something really weird happened */
839 return -1;
840}
841
Michael Karcherb9dbe482011-05-11 17:07:07 +0000842static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000843 const unsigned char *writearr, unsigned char *readarr)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000844{
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000845 int result;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000846 int opcode_index = -1;
847 const unsigned char cmd = *writearr;
848 OPCODE *opcode;
849 uint32_t addr = 0;
850 uint8_t *data;
851 int count;
852
Dominik Geyerb46acba2008-05-16 12:55:55 +0000853 /* find cmd in opcodes-table */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000854 opcode_index = find_opcode(curopcodes, cmd);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000855 if (opcode_index == -1) {
Helge Wagner738e2522010-10-05 22:06:05 +0000856 if (!ichspi_lock)
857 opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt);
858 if (opcode_index == -1) {
Stefan Tauner355cbfd2011-05-28 02:37:14 +0000859 msg_pdbg("Invalid OPCODE 0x%02x, will not execute.\n",
860 cmd);
Helge Wagner738e2522010-10-05 22:06:05 +0000861 return SPI_INVALID_OPCODE;
862 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000863 }
864
865 opcode = &(curopcodes->opcode[opcode_index]);
866
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000867 /* The following valid writecnt/readcnt combinations exist:
868 * writecnt = 4, readcnt >= 0
869 * writecnt = 1, readcnt >= 0
870 * writecnt >= 4, readcnt = 0
871 * writecnt >= 1, readcnt = 0
872 * writecnt >= 1 is guaranteed for all commands.
873 */
874 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) &&
875 (writecnt != 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000876 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000877 "0x%02x, got writecnt=%i, want =4\n", __func__, cmd,
878 writecnt);
879 return SPI_INVALID_LENGTH;
880 }
881 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_NO_ADDRESS) &&
882 (writecnt != 1)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000883 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000884 "0x%02x, got writecnt=%i, want =1\n", __func__, cmd,
885 writecnt);
886 return SPI_INVALID_LENGTH;
887 }
888 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) &&
889 (writecnt < 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000890 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000891 "0x%02x, got writecnt=%i, want >=4\n", __func__, cmd,
892 writecnt);
893 return SPI_INVALID_LENGTH;
894 }
895 if (((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
896 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) &&
897 (readcnt)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000898 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000899 "0x%02x, got readcnt=%i, want =0\n", __func__, cmd,
900 readcnt);
901 return SPI_INVALID_LENGTH;
902 }
903
Dominik Geyerb46acba2008-05-16 12:55:55 +0000904 /* if opcode-type requires an address */
905 if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS ||
906 opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000907 addr = (writearr[1] << 16) |
908 (writearr[2] << 8) | (writearr[3] << 0);
Michael Karcherb9dbe482011-05-11 17:07:07 +0000909 switch (spi_programmer->type) {
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000910 case SPI_CONTROLLER_ICH7:
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +0000911 case SPI_CONTROLLER_VIA:
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000912 case SPI_CONTROLLER_ICH9:
913 if (addr < ichspi_bbar) {
914 msg_perr("%s: Address 0x%06x below allowed "
915 "range 0x%06x-0xffffff\n", __func__,
916 addr, ichspi_bbar);
917 return SPI_INVALID_ADDRESS;
918 }
919 break;
920 default:
921 break;
922 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000923 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000924
Dominik Geyerb46acba2008-05-16 12:55:55 +0000925 /* translate read/write array/count */
926 if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000927 data = (uint8_t *) (writearr + 1);
928 count = writecnt - 1;
929 } else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
930 data = (uint8_t *) (writearr + 4);
931 count = writecnt - 4;
932 } else {
933 data = (uint8_t *) readarr;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000934 count = readcnt;
935 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000936
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000937 result = run_opcode(*opcode, addr, count, data);
938 if (result) {
Stefan Tauner8ed29342011-04-29 23:53:09 +0000939 msg_pdbg("Running OPCODE 0x%02x failed ", opcode->opcode);
940 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
941 (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS)) {
942 msg_pdbg("at address 0x%06x ", addr);
943 }
944 msg_pdbg("(payload length was %d).\n", count);
945
946 /* Print out the data array if it contains data to write.
947 * Errors are detected before the received data is read back into
948 * the array so it won't make sense to print it then. */
949 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
950 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) {
951 int i;
952 msg_pspew("The data was:\n");
953 for(i=0; i<count; i++){
954 msg_pspew("%3d: 0x%02x\n", i, data[i]);
955 }
956 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000957 }
958
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000959 return result;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000960}
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000961
Michael Karcherb9dbe482011-05-11 17:07:07 +0000962static int ich_spi_send_multicommand(struct spi_command *cmds)
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000963{
964 int ret = 0;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000965 int i;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000966 int oppos, preoppos;
967 for (; (cmds->writecnt || cmds->readcnt) && !ret; cmds++) {
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000968 if ((cmds + 1)->writecnt || (cmds + 1)->readcnt) {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000969 /* Next command is valid. */
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000970 preoppos = find_preop(curopcodes, cmds->writearr[0]);
971 oppos = find_opcode(curopcodes, (cmds + 1)->writearr[0]);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000972 if ((oppos == -1) && (preoppos != -1)) {
973 /* Current command is listed as preopcode in
974 * ICH struct OPCODES, but next command is not
975 * listed as opcode in that struct.
976 * Check for command sanity, then
977 * try to reprogram the ICH opcode list.
978 */
979 if (find_preop(curopcodes,
980 (cmds + 1)->writearr[0]) != -1) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000981 msg_perr("%s: Two subsequent "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000982 "preopcodes 0x%02x and 0x%02x, "
983 "ignoring the first.\n",
984 __func__, cmds->writearr[0],
985 (cmds + 1)->writearr[0]);
986 continue;
987 }
988 /* If the chipset is locked down, we'll fail
989 * during execution of the next command anyway.
990 * No need to bother with fixups.
991 */
992 if (!ichspi_lock) {
Helge Wagner738e2522010-10-05 22:06:05 +0000993 oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt);
994 if (oppos == -1)
995 continue;
996 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000997 continue;
998 }
999 }
1000 if ((oppos != -1) && (preoppos != -1)) {
1001 /* Current command is listed as preopcode in
1002 * ICH struct OPCODES and next command is listed
1003 * as opcode in that struct. Match them up.
1004 */
1005 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001006 continue;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001007 }
1008 /* If none of the above if-statements about oppos or
1009 * preoppos matched, this is a normal opcode.
1010 */
1011 }
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001012 ret = ich_spi_send_command(cmds->writecnt, cmds->readcnt,
1013 cmds->writearr, cmds->readarr);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001014 /* Reset the type of all opcodes to non-atomic. */
1015 for (i = 0; i < 8; i++)
1016 curopcodes->opcode[i].atomic = 0;
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001017 }
1018 return ret;
1019}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001020
Michael Karchera4448d92010-07-22 18:04:15 +00001021#define ICH_BMWAG(x) ((x >> 24) & 0xff)
1022#define ICH_BMRAG(x) ((x >> 16) & 0xff)
1023#define ICH_BRWA(x) ((x >> 8) & 0xff)
1024#define ICH_BRRA(x) ((x >> 0) & 0xff)
1025
1026#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff)
1027#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff)
1028
1029static void do_ich9_spi_frap(uint32_t frap, int i)
1030{
Mathias Krausea60faab2011-01-17 07:50:42 +00001031 static const char *const access_names[4] = {
Michael Karchera4448d92010-07-22 18:04:15 +00001032 "locked", "read-only", "write-only", "read-write"
1033 };
Mathias Krausea60faab2011-01-17 07:50:42 +00001034 static const char *const region_names[5] = {
Michael Karchera4448d92010-07-22 18:04:15 +00001035 "Flash Descriptor", "BIOS", "Management Engine",
1036 "Gigabit Ethernet", "Platform Data"
1037 };
1038 uint32_t base, limit;
1039 int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) |
1040 (((ICH_BRRA(frap) >> i) & 1) << 0);
1041 int offset = 0x54 + i * 4;
1042 uint32_t freg = mmio_readl(ich_spibar + offset);
1043
1044 msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n",
1045 offset, freg, i, region_names[i]);
1046
1047 base = ICH_FREG_BASE(freg);
1048 limit = ICH_FREG_LIMIT(freg);
Joshua Roysd172ecd2011-05-26 13:30:51 +00001049 if (base > limit) {
Michael Karchera4448d92010-07-22 18:04:15 +00001050 /* this FREG is disabled */
1051 msg_pdbg("%s region is unused.\n", region_names[i]);
1052 return;
1053 }
1054
1055 msg_pdbg("0x%08x-0x%08x is %s\n",
1056 (base << 12), (limit << 12) | 0x0fff,
1057 access_names[rwperms]);
1058}
1059
Michael Karcherb9dbe482011-05-11 17:07:07 +00001060static const struct spi_programmer spi_programmer_ich7 = {
1061 .type = SPI_CONTROLLER_ICH7,
1062 .max_data_read = 64,
1063 .max_data_write = 64,
1064 .command = ich_spi_send_command,
1065 .multicommand = ich_spi_send_multicommand,
1066 .read = default_spi_read,
1067 .write_256 = default_spi_write_256,
1068};
1069
1070static const struct spi_programmer spi_programmer_ich9 = {
1071 .type = SPI_CONTROLLER_ICH9,
1072 .max_data_read = 64,
1073 .max_data_write = 64,
1074 .command = ich_spi_send_command,
1075 .multicommand = ich_spi_send_multicommand,
1076 .read = default_spi_read,
1077 .write_256 = default_spi_write_256,
1078};
1079
Michael Karchera4448d92010-07-22 18:04:15 +00001080int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
1081 int ich_generation)
1082{
1083 int i;
1084 uint8_t old, new;
1085 uint16_t spibar_offset, tmp2;
1086 uint32_t tmp;
1087
Michael Karchera4448d92010-07-22 18:04:15 +00001088 switch (ich_generation) {
1089 case 7:
Michael Karcherb9dbe482011-05-11 17:07:07 +00001090 register_spi_programmer(&spi_programmer_ich7);
Michael Karchera4448d92010-07-22 18:04:15 +00001091 spibar_offset = 0x3020;
1092 break;
1093 case 8:
Michael Karcherb9dbe482011-05-11 17:07:07 +00001094 register_spi_programmer(&spi_programmer_ich9);
Michael Karchera4448d92010-07-22 18:04:15 +00001095 spibar_offset = 0x3020;
1096 break;
1097 case 9:
1098 case 10:
1099 default: /* Future version might behave the same */
Michael Karcherb9dbe482011-05-11 17:07:07 +00001100 register_spi_programmer(&spi_programmer_ich9);
Michael Karchera4448d92010-07-22 18:04:15 +00001101 spibar_offset = 0x3800;
1102 break;
1103 }
1104
1105 /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */
1106 msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", base, spibar_offset);
1107
1108 /* Assign Virtual Address */
1109 ich_spibar = rcrb + spibar_offset;
1110
Michael Karcherb9dbe482011-05-11 17:07:07 +00001111 switch (spi_programmer->type) {
Michael Karchera4448d92010-07-22 18:04:15 +00001112 case SPI_CONTROLLER_ICH7:
1113 msg_pdbg("0x00: 0x%04x (SPIS)\n",
1114 mmio_readw(ich_spibar + 0));
1115 msg_pdbg("0x02: 0x%04x (SPIC)\n",
1116 mmio_readw(ich_spibar + 2));
1117 msg_pdbg("0x04: 0x%08x (SPIA)\n",
1118 mmio_readl(ich_spibar + 4));
1119 for (i = 0; i < 8; i++) {
1120 int offs;
1121 offs = 8 + (i * 8);
1122 msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs,
1123 mmio_readl(ich_spibar + offs), i);
1124 msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
1125 mmio_readl(ich_spibar + offs + 4), i);
1126 }
1127 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
1128 msg_pdbg("0x50: 0x%08x (BBAR)\n",
1129 ichspi_bbar);
1130 msg_pdbg("0x54: 0x%04x (PREOP)\n",
1131 mmio_readw(ich_spibar + 0x54));
1132 msg_pdbg("0x56: 0x%04x (OPTYPE)\n",
1133 mmio_readw(ich_spibar + 0x56));
1134 msg_pdbg("0x58: 0x%08x (OPMENU)\n",
1135 mmio_readl(ich_spibar + 0x58));
1136 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n",
1137 mmio_readl(ich_spibar + 0x5c));
1138 for (i = 0; i < 4; i++) {
1139 int offs;
1140 offs = 0x60 + (i * 4);
1141 msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,
1142 mmio_readl(ich_spibar + offs), i);
1143 }
Michael Karchera4448d92010-07-22 18:04:15 +00001144 if (mmio_readw(ich_spibar) & (1 << 15)) {
1145 msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
1146 ichspi_lock = 1;
1147 }
1148 ich_init_opcodes();
1149 break;
1150 case SPI_CONTROLLER_ICH9:
1151 tmp2 = mmio_readw(ich_spibar + 4);
1152 msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2);
1153 msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1));
1154 msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1);
1155 msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1);
1156 msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1);
1157 msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3);
1158 msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1);
1159 msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1);
1160 msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1);
1161
1162 tmp = mmio_readl(ich_spibar + 0x50);
1163 msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp);
1164 msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp));
1165 msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp));
1166 msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp));
1167 msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp));
1168
1169 /* print out the FREGx registers along with FRAP access bits */
1170 for(i = 0; i < 5; i++)
1171 do_ich9_spi_frap(tmp, i);
1172
1173 msg_pdbg("0x74: 0x%08x (PR0)\n",
1174 mmio_readl(ich_spibar + 0x74));
1175 msg_pdbg("0x78: 0x%08x (PR1)\n",
1176 mmio_readl(ich_spibar + 0x78));
1177 msg_pdbg("0x7C: 0x%08x (PR2)\n",
1178 mmio_readl(ich_spibar + 0x7C));
1179 msg_pdbg("0x80: 0x%08x (PR3)\n",
1180 mmio_readl(ich_spibar + 0x80));
1181 msg_pdbg("0x84: 0x%08x (PR4)\n",
1182 mmio_readl(ich_spibar + 0x84));
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001183
1184 tmp = mmio_readl(ich_spibar + 0x90);
1185 msg_pdbg("0x90: 0x%02x (SSFS)\n", tmp & 0xff);
1186 msg_pdbg("AEL %i, ", (tmp >> 4) & 1);
1187 msg_pdbg("FCERR %i, ", (tmp >> 3) & 1);
1188 msg_pdbg("FDONE %i, ", (tmp >> 2) & 1);
1189 msg_pdbg("SCIP %i\n", (tmp >> 0) & 1);
1190 if (tmp & (1 << 3)) {
1191 msg_pdbg("Clearing SSFS.FCERR\n");
1192 mmio_writeb(1 << 3, ich_spibar + 0x90);
1193 }
1194 tmp >>= 8;
1195 msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp);
1196
Michael Karchera4448d92010-07-22 18:04:15 +00001197 msg_pdbg("0x94: 0x%04x (PREOP)\n",
1198 mmio_readw(ich_spibar + 0x94));
1199 msg_pdbg("0x96: 0x%04x (OPTYPE)\n",
1200 mmio_readw(ich_spibar + 0x96));
1201 msg_pdbg("0x98: 0x%08x (OPMENU)\n",
1202 mmio_readl(ich_spibar + 0x98));
1203 msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n",
1204 mmio_readl(ich_spibar + 0x9C));
1205 ichspi_bbar = mmio_readl(ich_spibar + 0xA0);
1206 msg_pdbg("0xA0: 0x%08x (BBAR)\n",
1207 ichspi_bbar);
1208 msg_pdbg("0xB0: 0x%08x (FDOC)\n",
1209 mmio_readl(ich_spibar + 0xB0));
1210 if (tmp2 & (1 << 15)) {
1211 msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
1212 ichspi_lock = 1;
1213 }
1214 ich_init_opcodes();
1215 break;
1216 default:
1217 /* Nothing */
1218 break;
1219 }
1220
1221 old = pci_read_byte(dev, 0xdc);
1222 msg_pdbg("SPI Read Configuration: ");
1223 new = (old >> 2) & 0x3;
1224 switch (new) {
1225 case 0:
1226 case 1:
1227 case 2:
1228 msg_pdbg("prefetching %sabled, caching %sabled, ",
1229 (new & 0x2) ? "en" : "dis",
1230 (new & 0x1) ? "dis" : "en");
1231 break;
1232 default:
1233 msg_pdbg("invalid prefetching/caching settings, ");
1234 break;
1235 }
1236 return 0;
1237}
1238
Michael Karcherb9dbe482011-05-11 17:07:07 +00001239static const struct spi_programmer spi_programmer_via = {
1240 .type = SPI_CONTROLLER_VIA,
1241 .max_data_read = 16,
1242 .max_data_write = 16,
1243 .command = ich_spi_send_command,
1244 .multicommand = ich_spi_send_multicommand,
1245 .read = default_spi_read,
1246 .write_256 = default_spi_write_256,
1247};
1248
Michael Karchera4448d92010-07-22 18:04:15 +00001249int via_init_spi(struct pci_dev *dev)
1250{
1251 uint32_t mmio_base;
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00001252 int i;
Michael Karchera4448d92010-07-22 18:04:15 +00001253
1254 mmio_base = (pci_read_long(dev, 0xbc)) << 8;
1255 msg_pdbg("MMIO base at = 0x%x\n", mmio_base);
1256 ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70);
1257
Michael Karchera4448d92010-07-22 18:04:15 +00001258 /* Not sure if it speaks all these bus protocols. */
Michael Karcherb9dbe482011-05-11 17:07:07 +00001259 buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH;
1260 register_spi_programmer(&spi_programmer_via);
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00001261
1262 msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0));
1263 msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2));
1264 msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(ich_spibar + 4));
1265 for (i = 0; i < 2; i++) {
1266 int offs;
1267 offs = 8 + (i * 8);
1268 msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs,
1269 mmio_readl(ich_spibar + offs), i);
1270 msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
1271 mmio_readl(ich_spibar + offs + 4), i);
1272 }
1273 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
1274 msg_pdbg("0x50: 0x%08x (BBAR)\n", ichspi_bbar);
1275 msg_pdbg("0x54: 0x%04x (PREOP)\n", mmio_readw(ich_spibar + 0x54));
1276 msg_pdbg("0x56: 0x%04x (OPTYPE)\n", mmio_readw(ich_spibar + 0x56));
1277 msg_pdbg("0x58: 0x%08x (OPMENU)\n", mmio_readl(ich_spibar + 0x58));
1278 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + 0x5c));
1279 for (i = 0; i < 3; i++) {
1280 int offs;
1281 offs = 0x60 + (i * 4);
1282 msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,
1283 mmio_readl(ich_spibar + offs), i);
1284 }
1285 msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n",
1286 mmio_readw(ich_spibar + 0x6c));
1287 if (mmio_readw(ich_spibar) & (1 << 15)) {
1288 msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
1289 ichspi_lock = 1;
1290 }
1291
Michael Karchera4448d92010-07-22 18:04:15 +00001292 ich_init_opcodes();
1293
1294 return 0;
1295}
1296
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001297#endif