blob: f35ea378631ccd4cb0241adc775659c7912def9b [file] [log] [blame]
Dominik Geyerb46acba2008-05-16 12:55:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2008 Stefan Wildemann <stefan.wildemann@kontron.com>
5 * Copyright (C) 2008 Claus Gindhart <claus.gindhart@kontron.com>
6 * Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com>
Stefan Reinauera9424d52008-06-27 16:28:34 +00007 * Copyright (C) 2008 coresystems GmbH <info@coresystems.de>
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +00008 * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
Dominik Geyerb46acba2008-05-16 12:55:55 +00009 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Dominik Geyerb46acba2008-05-16 12:55:55 +000023 */
24
25/*
26 * This module is designed for supporting the devices
27 * ST M25P40
28 * ST M25P80
29 * ST M25P16
30 * ST M25P32 already tested
31 * ST M25P64
32 * AT 25DF321 already tested
Helge Wagner738e2522010-10-05 22:06:05 +000033 * ... and many more SPI flash devices
Dominik Geyerb46acba2008-05-16 12:55:55 +000034 *
35 */
36
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000037#if defined(__i386__) || defined(__x86_64__)
38
Dominik Geyerb46acba2008-05-16 12:55:55 +000039#include <string.h>
Dominik Geyerb46acba2008-05-16 12:55:55 +000040#include "flash.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000041#include "chipdrivers.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000042#include "programmer.h"
Dominik Geyerb46acba2008-05-16 12:55:55 +000043#include "spi.h"
44
Stefan Reinauera9424d52008-06-27 16:28:34 +000045/* ICH9 controller register definition */
Stefan Tauner55206942011-06-11 09:53:22 +000046#define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */
47#define HSFS_FDONE_OFF 0 /* 0: Flash Cycle Done */
48#define HSFS_FDONE (0x1 << HSFS_FDONE_OFF)
49#define HSFS_FCERR_OFF 1 /* 1: Flash Cycle Error */
50#define HSFS_FCERR (0x1 << HSFS_FCERR_OFF)
51#define HSFS_AEL_OFF 2 /* 2: Access Error Log */
52#define HSFS_AEL (0x1 << HSFS_AEL_OFF)
53#define HSFS_BERASE_OFF 3 /* 3-4: Block/Sector Erase Size */
54#define HSFS_BERASE (0x3 << HSFS_BERASE_OFF)
55#define HSFS_SCIP_OFF 5 /* 5: SPI Cycle In Progress */
56#define HSFS_SCIP (0x1 << HSFS_SCIP_OFF)
57 /* 6-12: reserved */
58#define HSFS_FDOPSS_OFF 13 /* 13: Flash Descriptor Override Pin-Strap Status */
59#define HSFS_FDOPSS (0x1 << HSFS_FDOPSS_OFF)
60#define HSFS_FDV_OFF 14 /* 14: Flash Descriptor Valid */
61#define HSFS_FDV (0x1 << HSFS_FDV_OFF)
62#define HSFS_FLOCKDN_OFF 15 /* 15: Flash Configuration Lock-Down */
63#define HSFS_FLOCKDN (0x1 << HSFS_FLOCKDN_OFF)
64
65#define ICH9_REG_HSFC 0x06 /* 16 Bits Hardware Sequencing Flash Control */
66#define HSFC_FGO_OFF 0 /* 0: Flash Cycle Go */
67#define HSFC_FGO (0x1 << HSFC_FGO_OFF)
68#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */
69#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
70 /* 3-7: reserved */
71#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
72#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)
73 /* 14: reserved */
74#define HSFC_SME_OFF 15 /* 15: SPI SMI# Enable */
75#define HSFC_SME (0x1 << HSFC_SME_OFF)
76
Stefan Taunerc0aaf952011-05-19 02:58:17 +000077#define ICH9_REG_FADDR 0x08 /* 32 Bits */
78#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */
Stefan Reinauera9424d52008-06-27 16:28:34 +000079
Stefan Tauner29c80832011-06-12 08:14:10 +000080#define ICH9_REG_FRAP 0x50 /* 32 Bytes Flash Region Access Permissions */
81#define ICH9_REG_FREG0 0x54 /* 32 Bytes Flash Region 0 */
82
83#define ICH9_REG_PR0 0x74 /* 32 Bytes Protected Range 0 */
84#define ICH9_REG_PR1 0x78 /* 32 Bytes Protected Range 1 */
85#define ICH9_REG_PR2 0x7c /* 32 Bytes Protected Range 2 */
86#define ICH9_REG_PR3 0x80 /* 32 Bytes Protected Range 3 */
87#define ICH9_REG_PR4 0x84 /* 32 Bytes Protected Range 4 */
88
Stefan Taunerc0aaf952011-05-19 02:58:17 +000089#define ICH9_REG_SSFS 0x90 /* 08 Bits */
Stefan Tauner0c1ec452011-06-11 09:53:09 +000090#define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */
91#define SSFS_SCIP (0x1 << SSFS_SCIP_OFF)
92#define SSFS_FDONE_OFF 2 /* Cycle Done Status */
93#define SSFS_FDONE (0x1 << SSFS_FDONE_OFF)
94#define SSFS_FCERR_OFF 3 /* Flash Cycle Error */
95#define SSFS_FCERR (0x1 << SSFS_FCERR_OFF)
96#define SSFS_AEL_OFF 4 /* Access Error Log */
97#define SSFS_AEL (0x1 << SSFS_AEL_OFF)
Stefan Taunerc0aaf952011-05-19 02:58:17 +000098/* The following bits are reserved in SSFS: 1,5-7. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +000099#define SSFS_RESERVED_MASK 0x000000e2
Stefan Reinauera9424d52008-06-27 16:28:34 +0000100
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000101#define ICH9_REG_SSFC 0x91 /* 24 Bits */
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000102/* We combine SSFS and SSFC to one 32-bit word,
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000103 * therefore SSFC bits are off by 8. */
104 /* 0: reserved */
105#define SSFC_SCGO_OFF (1 + 8) /* 1: SPI Cycle Go */
106#define SSFC_SCGO (0x1 << SSFC_SCGO_OFF)
107#define SSFC_ACS_OFF (2 + 8) /* 2: Atomic Cycle Sequence */
108#define SSFC_ACS (0x1 << SSFC_ACS_OFF)
109#define SSFC_SPOP_OFF (3 + 8) /* 3: Sequence Prefix Opcode Pointer */
110#define SSFC_SPOP (0x1 << SSFC_SPOP_OFF)
111#define SSFC_COP_OFF (4 + 8) /* 4-6: Cycle Opcode Pointer */
112#define SSFC_COP (0x7 << SSFC_COP_OFF)
113 /* 7: reserved */
114#define SSFC_DBC_OFF (8 + 8) /* 8-13: Data Byte Count */
115#define SSFC_DBC (0x3f << SSFC_DBC_OFF)
116#define SSFC_DS_OFF (14 + 8) /* 14: Data Cycle */
117#define SSFC_DS (0x1 << SSFC_DS_OFF)
118#define SSFC_SME_OFF (15 + 8) /* 15: SPI SMI# Enable */
119#define SSFC_SME (0x1 << SSFC_SME_OFF)
120#define SSFC_SCF_OFF (16 + 8) /* 16-18: SPI Cycle Frequency */
121#define SSFC_SCF (0x7 << SSFC_SCF_OFF)
122#define SSFC_SCF_20MHZ 0x00000000
123#define SSFC_SCF_33MHZ 0x01000000
124 /* 19-23: reserved */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000125#define SSFC_RESERVED_MASK 0xf8008100
Stefan Reinauera9424d52008-06-27 16:28:34 +0000126
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000127#define ICH9_REG_PREOP 0x94 /* 16 Bits */
128#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */
129#define ICH9_REG_OPMENU 0x98 /* 64 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000130
Stefan Tauner29c80832011-06-12 08:14:10 +0000131#define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */
132#define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */
133
Stefan Taunerbd649e42011-07-01 00:39:16 +0000134#define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */
135#define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */
136#define FPB_FPBA (0x1FFF << FPB_FPBA_OFF)
137
Dominik Geyerb46acba2008-05-16 12:55:55 +0000138// ICH9R SPI commands
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000139#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
140#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
141#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
142#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
Dominik Geyerb46acba2008-05-16 12:55:55 +0000143
Stefan Reinauera9424d52008-06-27 16:28:34 +0000144// ICH7 registers
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000145#define ICH7_REG_SPIS 0x00 /* 16 Bits */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000146#define SPIS_SCIP 0x0001
147#define SPIS_GRANT 0x0002
148#define SPIS_CDS 0x0004
149#define SPIS_FCERR 0x0008
150#define SPIS_RESERVED_MASK 0x7ff0
Stefan Reinauera9424d52008-06-27 16:28:34 +0000151
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000152/* VIA SPI is compatible with ICH7, but maxdata
153 to transfer is 16 bytes.
154
155 DATA byte count on ICH7 is 8:13, on VIA 8:11
156
157 bit 12 is port select CS0 CS1
158 bit 13 is FAST READ enable
159 bit 7 is used with fast read and one shot controls CS de-assert?
160*/
161
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000162#define ICH7_REG_SPIC 0x02 /* 16 Bits */
163#define SPIC_SCGO 0x0002
164#define SPIC_ACS 0x0004
165#define SPIC_SPOP 0x0008
166#define SPIC_DS 0x4000
Stefan Reinauera9424d52008-06-27 16:28:34 +0000167
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000168#define ICH7_REG_SPIA 0x04 /* 32 Bits */
169#define ICH7_REG_SPID0 0x08 /* 64 Bytes */
170#define ICH7_REG_PREOP 0x54 /* 16 Bits */
171#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */
172#define ICH7_REG_OPMENU 0x58 /* 64 Bits */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000173
FENG yu ningc05a2952008-12-08 18:16:58 +0000174/* ICH SPI configuration lock-down. May be set during chipset enabling. */
Michael Karchera4448d92010-07-22 18:04:15 +0000175static int ichspi_lock = 0;
FENG yu ningc05a2952008-12-08 18:16:58 +0000176
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000177uint32_t ichspi_bbar = 0;
178
Michael Karchera4448d92010-07-22 18:04:15 +0000179static void *ich_spibar = NULL;
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000180
Dominik Geyerb46acba2008-05-16 12:55:55 +0000181typedef struct _OPCODE {
182 uint8_t opcode; //This commands spi opcode
183 uint8_t spi_type; //This commands spi type
184 uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1
185} OPCODE;
186
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000187/* Suggested opcode definition:
Dominik Geyerb46acba2008-05-16 12:55:55 +0000188 * Preop 1: Write Enable
189 * Preop 2: Write Status register enable
190 *
191 * OP 0: Write address
192 * OP 1: Read Address
193 * OP 2: ERASE block
194 * OP 3: Read Status register
195 * OP 4: Read ID
196 * OP 5: Write Status register
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000197 * OP 6: chip private (read JEDEC id)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000198 * OP 7: Chip erase
199 */
200typedef struct _OPCODES {
201 uint8_t preop[2];
202 OPCODE opcode[8];
203} OPCODES;
204
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000205static OPCODES *curopcodes = NULL;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000206
207/* HW access functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000208static uint32_t REGREAD32(int X)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000209{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000210 return mmio_readl(ich_spibar + X);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000211}
212
Uwe Hermann09e04f72009-05-16 22:36:00 +0000213static uint16_t REGREAD16(int X)
Stefan Reinauera9424d52008-06-27 16:28:34 +0000214{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000215 return mmio_readw(ich_spibar + X);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000216}
217
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000218static uint16_t REGREAD8(int X)
219{
220 return mmio_readb(ich_spibar + X);
221}
222
Stefan Taunerccd92a12011-07-01 00:39:01 +0000223#define REGWRITE32(off, val) mmio_writel(val, ich_spibar+(off))
224#define REGWRITE16(off, val) mmio_writew(val, ich_spibar+(off))
225#define REGWRITE8(off, val) mmio_writeb(val, ich_spibar+(off))
Dominik Geyerb46acba2008-05-16 12:55:55 +0000226
Dominik Geyerb46acba2008-05-16 12:55:55 +0000227/* Common SPI functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000228static int find_opcode(OPCODES *op, uint8_t opcode);
229static int find_preop(OPCODES *op, uint8_t preop);
FENG yu ningf041e9b2008-12-15 02:32:11 +0000230static int generate_opcodes(OPCODES * op);
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000231static int program_opcodes(OPCODES *op, int enable_undo);
Stefan Reinauer43119562008-11-02 19:51:50 +0000232static int run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000233 uint8_t datalength, uint8_t * data);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000234
FENG yu ningf041e9b2008-12-15 02:32:11 +0000235/* for pairing opcodes with their required preop */
236struct preop_opcode_pair {
237 uint8_t preop;
238 uint8_t opcode;
239};
240
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000241/* List of opcodes which need preopcodes and matching preopcodes. Unused. */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000242const struct preop_opcode_pair pops[] = {
FENG yu ningf041e9b2008-12-15 02:32:11 +0000243 {JEDEC_WREN, JEDEC_BYTE_PROGRAM},
244 {JEDEC_WREN, JEDEC_SE}, /* sector erase */
245 {JEDEC_WREN, JEDEC_BE_52}, /* block erase */
246 {JEDEC_WREN, JEDEC_BE_D8}, /* block erase */
247 {JEDEC_WREN, JEDEC_CE_60}, /* chip erase */
248 {JEDEC_WREN, JEDEC_CE_C7}, /* chip erase */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000249 /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */
250 {JEDEC_WREN, JEDEC_WRSR},
FENG yu ningf041e9b2008-12-15 02:32:11 +0000251 {JEDEC_EWSR, JEDEC_WRSR},
252 {0,}
253};
254
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000255/* Reasonable default configuration. Needs ad-hoc modifications if we
256 * encounter unlisted opcodes. Fun.
257 */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000258static OPCODES O_ST_M25P = {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000259 {
260 JEDEC_WREN,
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000261 JEDEC_EWSR,
262 },
Dominik Geyerb46acba2008-05-16 12:55:55 +0000263 {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000264 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000265 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000266 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000267 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
Carl-Daniel Hailfinger15aa7c62009-05-26 21:25:08 +0000268 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000269 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000270 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000271 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
272 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000273};
274
Helge Wagner738e2522010-10-05 22:06:05 +0000275/* List of opcodes with their corresponding spi_type
276 * It is used to reprogram the chipset OPCODE table on-the-fly if an opcode
277 * is needed which is currently not in the chipset OPCODE table
278 */
279static OPCODE POSSIBLE_OPCODES[] = {
280 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
281 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
282 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
283 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
284 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
285 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
286 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
287 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
288 {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Sector erase
289 {JEDEC_BE_52, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Block erase
290 {JEDEC_AAI_WORD_PROGRAM, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Auto Address Increment
291};
292
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000293static OPCODES O_EXISTING = {};
FENG yu ningc05a2952008-12-08 18:16:58 +0000294
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000295/* pretty printing functions */
296static void pretty_print_opcodes(OPCODES *ops)
297{
298 if(ops == NULL)
299 return;
300
301 msg_pdbg("preop0=0x%02x, preop1=0x%02x\n", ops->preop[0],
302 ops->preop[1]);
303
304 OPCODE oc;
305 uint8_t i;
306 for (i = 0; i < 8; i++) {
307 oc = ops->opcode[i];
308 msg_pdbg("op[%d]=0x%02x, %d, %d\n",
309 i,
310 oc.opcode,
311 oc.spi_type,
312 oc.atomic);
313 }
314}
315
316#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF)
317
Stefan Tauner55206942011-06-11 09:53:22 +0000318static void prettyprint_ich9_reg_hsfs(uint16_t reg_val)
319{
320 msg_pdbg("HSFS: ");
321 pprint_reg(HSFS, FDONE, reg_val, ", ");
322 pprint_reg(HSFS, FCERR, reg_val, ", ");
323 pprint_reg(HSFS, AEL, reg_val, ", ");
324 pprint_reg(HSFS, BERASE, reg_val, ", ");
325 pprint_reg(HSFS, SCIP, reg_val, ", ");
326 pprint_reg(HSFS, FDOPSS, reg_val, ", ");
327 pprint_reg(HSFS, FDV, reg_val, ", ");
328 pprint_reg(HSFS, FLOCKDN, reg_val, "\n");
329}
330
331static void prettyprint_ich9_reg_hsfc(uint16_t reg_val)
332{
333 msg_pdbg("HSFC: ");
334 pprint_reg(HSFC, FGO, reg_val, ", ");
335 pprint_reg(HSFC, FCYCLE, reg_val, ", ");
336 pprint_reg(HSFC, FDBC, reg_val, ", ");
337 pprint_reg(HSFC, SME, reg_val, "\n");
338}
339
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000340static void prettyprint_ich9_reg_ssfs(uint32_t reg_val)
341{
342 msg_pdbg("SSFS: ");
343 pprint_reg(SSFS, SCIP, reg_val, ", ");
344 pprint_reg(SSFS, FDONE, reg_val, ", ");
345 pprint_reg(SSFS, FCERR, reg_val, ", ");
346 pprint_reg(SSFS, AEL, reg_val, "\n");
347}
348
349static void prettyprint_ich9_reg_ssfc(uint32_t reg_val)
350{
351 msg_pdbg("SSFC: ");
352 pprint_reg(SSFC, SCGO, reg_val, ", ");
353 pprint_reg(SSFC, ACS, reg_val, ", ");
354 pprint_reg(SSFC, SPOP, reg_val, ", ");
355 pprint_reg(SSFC, COP, reg_val, ", ");
356 pprint_reg(SSFC, DBC, reg_val, ", ");
357 pprint_reg(SSFC, SME, reg_val, ", ");
358 pprint_reg(SSFC, SCF, reg_val, "\n");
359}
360
Helge Wagner738e2522010-10-05 22:06:05 +0000361static uint8_t lookup_spi_type(uint8_t opcode)
362{
363 int a;
364
365 for (a = 0; a < sizeof(POSSIBLE_OPCODES)/sizeof(POSSIBLE_OPCODES[0]); a++) {
366 if (POSSIBLE_OPCODES[a].opcode == opcode)
367 return POSSIBLE_OPCODES[a].spi_type;
368 }
369
370 return 0xFF;
371}
372
373static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt)
374{
375 uint8_t spi_type;
376
377 spi_type = lookup_spi_type(opcode);
378 if (spi_type > 3) {
379 /* Try to guess spi type from read/write sizes.
380 * The following valid writecnt/readcnt combinations exist:
381 * writecnt = 4, readcnt >= 0
382 * writecnt = 1, readcnt >= 0
383 * writecnt >= 4, readcnt = 0
384 * writecnt >= 1, readcnt = 0
385 * writecnt >= 1 is guaranteed for all commands.
386 */
387 if (readcnt == 0)
388 /* if readcnt=0 and writecount >= 4, we don't know if it is WRITE_NO_ADDRESS
389 * or WRITE_WITH_ADDRESS. But if we use WRITE_NO_ADDRESS and the first 3 data
390 * bytes are actual the address, they go to the bus anyhow
391 */
392 spi_type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
393 else if (writecnt == 1) // and readcnt is > 0
394 spi_type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
395 else if (writecnt == 4) // and readcnt is > 0
396 spi_type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
397 // else we have an invalid case, will be handled below
398 }
399 if (spi_type <= 3) {
400 int oppos=2; // use original JEDEC_BE_D8 offset
401 curopcodes->opcode[oppos].opcode = opcode;
402 curopcodes->opcode[oppos].spi_type = spi_type;
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000403 program_opcodes(curopcodes, 0);
Helge Wagner738e2522010-10-05 22:06:05 +0000404 oppos = find_opcode(curopcodes, opcode);
405 msg_pdbg ("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos);
406 return oppos;
407 }
408 return -1;
409}
410
Uwe Hermann09e04f72009-05-16 22:36:00 +0000411static int find_opcode(OPCODES *op, uint8_t opcode)
FENG yu ningc05a2952008-12-08 18:16:58 +0000412{
413 int a;
414
415 for (a = 0; a < 8; a++) {
416 if (op->opcode[a].opcode == opcode)
417 return a;
418 }
419
420 return -1;
421}
422
Uwe Hermann09e04f72009-05-16 22:36:00 +0000423static int find_preop(OPCODES *op, uint8_t preop)
FENG yu ningc05a2952008-12-08 18:16:58 +0000424{
425 int a;
426
427 for (a = 0; a < 2; a++) {
428 if (op->preop[a] == preop)
429 return a;
430 }
431
432 return -1;
433}
434
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000435/* Create a struct OPCODES based on what we find in the locked down chipset. */
FENG yu ningf041e9b2008-12-15 02:32:11 +0000436static int generate_opcodes(OPCODES * op)
FENG yu ningc05a2952008-12-08 18:16:58 +0000437{
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000438 int a;
FENG yu ningc05a2952008-12-08 18:16:58 +0000439 uint16_t preop, optype;
440 uint32_t opmenu[2];
FENG yu ningc05a2952008-12-08 18:16:58 +0000441
442 if (op == NULL) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000443 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
FENG yu ningc05a2952008-12-08 18:16:58 +0000444 return -1;
445 }
446
Michael Karcherb9dbe482011-05-11 17:07:07 +0000447 switch (spi_programmer->type) {
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000448 case SPI_CONTROLLER_ICH7:
449 case SPI_CONTROLLER_VIA:
FENG yu ningc05a2952008-12-08 18:16:58 +0000450 preop = REGREAD16(ICH7_REG_PREOP);
451 optype = REGREAD16(ICH7_REG_OPTYPE);
452 opmenu[0] = REGREAD32(ICH7_REG_OPMENU);
453 opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4);
454 break;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000455 case SPI_CONTROLLER_ICH9:
FENG yu ningc05a2952008-12-08 18:16:58 +0000456 preop = REGREAD16(ICH9_REG_PREOP);
457 optype = REGREAD16(ICH9_REG_OPTYPE);
458 opmenu[0] = REGREAD32(ICH9_REG_OPMENU);
459 opmenu[1] = REGREAD32(ICH9_REG_OPMENU + 4);
460 break;
461 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000462 msg_perr("%s: unsupported chipset\n", __func__);
FENG yu ningc05a2952008-12-08 18:16:58 +0000463 return -1;
464 }
465
466 op->preop[0] = (uint8_t) preop;
467 op->preop[1] = (uint8_t) (preop >> 8);
468
469 for (a = 0; a < 8; a++) {
470 op->opcode[a].spi_type = (uint8_t) (optype & 0x3);
471 optype >>= 2;
472 }
473
474 for (a = 0; a < 4; a++) {
475 op->opcode[a].opcode = (uint8_t) (opmenu[0] & 0xff);
476 opmenu[0] >>= 8;
477 }
478
479 for (a = 4; a < 8; a++) {
480 op->opcode[a].opcode = (uint8_t) (opmenu[1] & 0xff);
481 opmenu[1] >>= 8;
482 }
483
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000484 /* No preopcodes used by default. */
485 for (a = 0; a < 8; a++)
FENG yu ningc05a2952008-12-08 18:16:58 +0000486 op->opcode[a].atomic = 0;
487
FENG yu ningc05a2952008-12-08 18:16:58 +0000488 return 0;
489}
490
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000491static int program_opcodes(OPCODES *op, int enable_undo)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000492{
493 uint8_t a;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000494 uint16_t preop, optype;
495 uint32_t opmenu[2];
Dominik Geyerb46acba2008-05-16 12:55:55 +0000496
497 /* Program Prefix Opcodes */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000498 /* 0:7 Prefix Opcode 1 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000499 preop = (op->preop[0]);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000500 /* 8:16 Prefix Opcode 2 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000501 preop |= ((uint16_t) op->preop[1]) << 8;
Uwe Hermann394131e2008-10-18 21:14:13 +0000502
Stefan Reinauera9424d52008-06-27 16:28:34 +0000503 /* Program Opcode Types 0 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000504 optype = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000505 for (a = 0; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000506 optype |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000507 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000508
Stefan Reinauera9424d52008-06-27 16:28:34 +0000509 /* Program Allowable Opcodes 0 - 3 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000510 opmenu[0] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000511 for (a = 0; a < 4; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000512 opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000513 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000514
Dominik Geyerb46acba2008-05-16 12:55:55 +0000515 /*Program Allowable Opcodes 4 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000516 opmenu[1] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000517 for (a = 4; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000518 opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000519 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000520
Sean Nelson316a29f2010-05-07 20:09:04 +0000521 msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]);
Michael Karcherb9dbe482011-05-11 17:07:07 +0000522 switch (spi_programmer->type) {
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000523 case SPI_CONTROLLER_ICH7:
524 case SPI_CONTROLLER_VIA:
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000525 /* Register undo only for enable_undo=1, i.e. first call. */
526 if (enable_undo) {
527 rmmio_valw(ich_spibar + ICH7_REG_PREOP);
528 rmmio_valw(ich_spibar + ICH7_REG_OPTYPE);
529 rmmio_vall(ich_spibar + ICH7_REG_OPMENU);
530 rmmio_vall(ich_spibar + ICH7_REG_OPMENU + 4);
531 }
532 mmio_writew(preop, ich_spibar + ICH7_REG_PREOP);
533 mmio_writew(optype, ich_spibar + ICH7_REG_OPTYPE);
534 mmio_writel(opmenu[0], ich_spibar + ICH7_REG_OPMENU);
535 mmio_writel(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000536 break;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000537 case SPI_CONTROLLER_ICH9:
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000538 /* Register undo only for enable_undo=1, i.e. first call. */
539 if (enable_undo) {
540 rmmio_valw(ich_spibar + ICH9_REG_PREOP);
541 rmmio_valw(ich_spibar + ICH9_REG_OPTYPE);
542 rmmio_vall(ich_spibar + ICH9_REG_OPMENU);
543 rmmio_vall(ich_spibar + ICH9_REG_OPMENU + 4);
544 }
545 mmio_writew(preop, ich_spibar + ICH9_REG_PREOP);
546 mmio_writew(optype, ich_spibar + ICH9_REG_OPTYPE);
547 mmio_writel(opmenu[0], ich_spibar + ICH9_REG_OPMENU);
548 mmio_writel(opmenu[1], ich_spibar + ICH9_REG_OPMENU + 4);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000549 break;
550 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000551 msg_perr("%s: unsupported chipset\n", __func__);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000552 return -1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000553 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000554
555 return 0;
556}
557
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000558/*
559 * Try to set BBAR (BIOS Base Address Register), but read back the value in case
560 * it didn't stick.
561 */
Stefan Taunere27b2d42011-07-01 00:39:09 +0000562static void ich_set_bbar(uint32_t min_addr)
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000563{
Stefan Taunere27b2d42011-07-01 00:39:09 +0000564 int bbar_off;
Michael Karcherb9dbe482011-05-11 17:07:07 +0000565 switch (spi_programmer->type) {
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000566 case SPI_CONTROLLER_ICH7:
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +0000567 case SPI_CONTROLLER_VIA:
Stefan Taunere27b2d42011-07-01 00:39:09 +0000568 bbar_off = 0x50;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000569 break;
570 case SPI_CONTROLLER_ICH9:
Stefan Taunere27b2d42011-07-01 00:39:09 +0000571 bbar_off = ICH9_REG_BBAR;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000572 break;
573 default:
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +0000574 msg_perr("Unknown chipset for BBAR setting!\n");
Stefan Taunere27b2d42011-07-01 00:39:09 +0000575 return;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000576 }
Stefan Taunere27b2d42011-07-01 00:39:09 +0000577
578 ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & ~BBAR_MASK;
579 if (ichspi_bbar) {
580 msg_pdbg("Reserved bits in BBAR not zero: 0x%08x\n",
581 ichspi_bbar);
582 }
583 min_addr &= BBAR_MASK;
584 ichspi_bbar |= min_addr;
585 rmmio_writel(ichspi_bbar, ich_spibar + bbar_off);
586 ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & BBAR_MASK;
587
588 /* We don't have any option except complaining. And if the write
589 * failed, the restore will fail as well, so no problem there.
590 */
591 if (ichspi_bbar != min_addr)
592 msg_perr("Setting BBAR failed!\n");
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000593}
594
FENG yu ningf041e9b2008-12-15 02:32:11 +0000595/* This function generates OPCODES from or programs OPCODES to ICH according to
596 * the chipset's SPI configuration lock.
FENG yu ningc05a2952008-12-08 18:16:58 +0000597 *
FENG yu ningf041e9b2008-12-15 02:32:11 +0000598 * It should be called before ICH sends any spi command.
FENG yu ningc05a2952008-12-08 18:16:58 +0000599 */
Michael Karchera4448d92010-07-22 18:04:15 +0000600static int ich_init_opcodes(void)
FENG yu ningc05a2952008-12-08 18:16:58 +0000601{
602 int rc = 0;
603 OPCODES *curopcodes_done;
604
605 if (curopcodes)
606 return 0;
607
608 if (ichspi_lock) {
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000609 msg_pdbg("Reading OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000610 curopcodes_done = &O_EXISTING;
FENG yu ningf041e9b2008-12-15 02:32:11 +0000611 rc = generate_opcodes(curopcodes_done);
FENG yu ningc05a2952008-12-08 18:16:58 +0000612 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000613 msg_pdbg("Programming OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000614 curopcodes_done = &O_ST_M25P;
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000615 rc = program_opcodes(curopcodes_done, 1);
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000616 /* Technically not part of opcode init, but it allows opcodes
617 * to run without transaction errors by setting the lowest
618 * allowed address to zero.
619 */
620 ich_set_bbar(0);
FENG yu ningc05a2952008-12-08 18:16:58 +0000621 }
622
623 if (rc) {
624 curopcodes = NULL;
Sean Nelson316a29f2010-05-07 20:09:04 +0000625 msg_perr("failed\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000626 return 1;
627 } else {
628 curopcodes = curopcodes_done;
Sean Nelson316a29f2010-05-07 20:09:04 +0000629 msg_pdbg("done\n");
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000630 pretty_print_opcodes(curopcodes);
631 msg_pdbg("\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000632 return 0;
633 }
634}
635
Stefan Reinauer43119562008-11-02 19:51:50 +0000636static int ich7_run_opcode(OPCODE op, uint32_t offset,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000637 uint8_t datalength, uint8_t * data, int maxdata)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000638{
639 int write_cmd = 0;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000640 int timeout;
Peter Stuge7e2c0792008-06-29 01:30:41 +0000641 uint32_t temp32 = 0;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000642 uint16_t temp16;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000643 uint32_t a;
Stefan Reinauer43119562008-11-02 19:51:50 +0000644 uint64_t opmenu;
645 int opcode_index;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000646
647 /* Is it a write command? */
648 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
649 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
650 write_cmd = 1;
651 }
652
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000653 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
654 while ((REGREAD16(ICH7_REG_SPIS) & SPIS_SCIP) && --timeout) {
655 programmer_delay(10);
656 }
657 if (!timeout) {
658 msg_perr("Error: SCIP never cleared!\n");
659 return 1;
660 }
661
Dominik Geyerb46acba2008-05-16 12:55:55 +0000662 /* Programm Offset in Flash into FADDR */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000663 REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000664
665 /* Program data into FDATA0 to N */
666 if (write_cmd && (datalength != 0)) {
667 temp32 = 0;
668 for (a = 0; a < datalength; a++) {
669 if ((a % 4) == 0) {
670 temp32 = 0;
671 }
672
673 temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8);
674
675 if ((a % 4) == 3) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000676 REGWRITE32(ICH7_REG_SPID0 + (a - (a % 4)),
677 temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000678 }
679 }
680 if (((a - 1) % 4) != 3) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000681 REGWRITE32(ICH7_REG_SPID0 +
682 ((a - 1) - ((a - 1) % 4)), temp32);
683 }
684
685 }
686
687 /* Assemble SPIS */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000688 temp16 = REGREAD16(ICH7_REG_SPIS);
689 /* keep reserved bits */
690 temp16 &= SPIS_RESERVED_MASK;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000691 /* clear error status registers */
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000692 temp16 |= (SPIS_CDS | SPIS_FCERR);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000693 REGWRITE16(ICH7_REG_SPIS, temp16);
694
695 /* Assemble SPIC */
696 temp16 = 0;
697
698 if (datalength != 0) {
699 temp16 |= SPIC_DS;
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000700 temp16 |= ((uint32_t) ((datalength - 1) & (maxdata - 1))) << 8;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000701 }
702
703 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000704 opmenu = REGREAD32(ICH7_REG_OPMENU);
705 opmenu |= ((uint64_t)REGREAD32(ICH7_REG_OPMENU + 4)) << 32;
706
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000707 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
708 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000709 break;
710 }
711 opmenu >>= 8;
712 }
713 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000714 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +0000715 return 1;
716 }
717 temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000718
Michael Karcher136125a2011-04-29 22:11:36 +0000719 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
720 /* Handle Atomic. Atomic commands include three steps:
721 - sending the preop (mainly EWSR or WREN)
722 - sending the main command
723 - waiting for the busy bit (WIP) to be cleared
724 This means the timeout must be sufficient for chip erase
725 of slow high-capacity chips.
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000726 */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000727 switch (op.atomic) {
728 case 2:
729 /* Select second preop. */
730 temp16 |= SPIC_SPOP;
731 /* And fall through. */
732 case 1:
733 /* Atomic command (preop+op) */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000734 temp16 |= SPIC_ACS;
Michael Karcher136125a2011-04-29 22:11:36 +0000735 timeout = 100 * 1000 * 60; /* 60 seconds */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000736 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000737 }
738
739 /* Start */
740 temp16 |= SPIC_SCGO;
741
742 /* write it */
743 REGWRITE16(ICH7_REG_SPIC, temp16);
744
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000745 /* Wait for Cycle Done Status or Flash Cycle Error. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000746 while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) &&
747 --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000748 programmer_delay(10);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000749 }
750 if (!timeout) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000751 msg_perr("timeout, ICH7_REG_SPIS=0x%04x\n",
752 REGREAD16(ICH7_REG_SPIS));
753 return 1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000754 }
755
Sean Nelson316a29f2010-05-07 20:09:04 +0000756 /* FIXME: make sure we do not needlessly cause transaction errors. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000757 temp16 = REGREAD16(ICH7_REG_SPIS);
758 if (temp16 & SPIS_FCERR) {
Stefan Tauner8ed29342011-04-29 23:53:09 +0000759 msg_perr("Transaction error!\n");
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000760 /* keep reserved bits */
761 temp16 &= SPIS_RESERVED_MASK;
762 REGWRITE16(ICH7_REG_SPIS, temp16 | SPIS_FCERR);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000763 return 1;
764 }
765
766 if ((!write_cmd) && (datalength != 0)) {
767 for (a = 0; a < datalength; a++) {
768 if ((a % 4) == 0) {
769 temp32 = REGREAD32(ICH7_REG_SPID0 + (a));
770 }
771
772 data[a] =
773 (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8)))
774 >> ((a % 4) * 8);
775 }
776 }
777
778 return 0;
779}
780
Stefan Reinauer43119562008-11-02 19:51:50 +0000781static int ich9_run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000782 uint8_t datalength, uint8_t * data)
783{
784 int write_cmd = 0;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000785 int timeout;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000786 uint32_t temp32;
787 uint32_t a;
Stefan Reinauer43119562008-11-02 19:51:50 +0000788 uint64_t opmenu;
789 int opcode_index;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000790
791 /* Is it a write command? */
792 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
793 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
794 write_cmd = 1;
795 }
796
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000797 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
798 while ((REGREAD8(ICH9_REG_SSFS) & SSFS_SCIP) && --timeout) {
799 programmer_delay(10);
800 }
801 if (!timeout) {
802 msg_perr("Error: SCIP never cleared!\n");
803 return 1;
804 }
805
Stefan Reinauera9424d52008-06-27 16:28:34 +0000806 /* Programm Offset in Flash into FADDR */
807 REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */
808
809 /* Program data into FDATA0 to N */
810 if (write_cmd && (datalength != 0)) {
811 temp32 = 0;
812 for (a = 0; a < datalength; a++) {
813 if ((a % 4) == 0) {
814 temp32 = 0;
815 }
816
817 temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8);
818
819 if ((a % 4) == 3) {
820 REGWRITE32(ICH9_REG_FDATA0 + (a - (a % 4)),
821 temp32);
822 }
823 }
824 if (((a - 1) % 4) != 3) {
825 REGWRITE32(ICH9_REG_FDATA0 +
826 ((a - 1) - ((a - 1) % 4)), temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000827 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000828 }
829
830 /* Assemble SSFS + SSFC */
Helge Wagnera319be12010-08-11 21:06:10 +0000831 temp32 = REGREAD32(ICH9_REG_SSFS);
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000832 /* Keep reserved bits only */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000833 temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000834 /* Clear cycle done and cycle error status registers */
835 temp32 |= (SSFS_FDONE | SSFS_FCERR);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000836 REGWRITE32(ICH9_REG_SSFS, temp32);
837
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000838 /* Use 20 MHz */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000839 temp32 |= SSFC_SCF_20MHZ;
840
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000841 /* Set data byte count (DBC) and data cycle bit (DS) */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000842 if (datalength != 0) {
843 uint32_t datatemp;
844 temp32 |= SSFC_DS;
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000845 datatemp = ((((uint32_t)datalength - 1) << SSFC_DBC_OFF) &
846 SSFC_DBC);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000847 temp32 |= datatemp;
848 }
849
850 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000851 opmenu = REGREAD32(ICH9_REG_OPMENU);
852 opmenu |= ((uint64_t)REGREAD32(ICH9_REG_OPMENU + 4)) << 32;
853
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000854 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
855 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000856 break;
857 }
858 opmenu >>= 8;
859 }
860 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000861 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +0000862 return 1;
863 }
864 temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000865
Michael Karcher136125a2011-04-29 22:11:36 +0000866 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
867 /* Handle Atomic. Atomic commands include three steps:
868 - sending the preop (mainly EWSR or WREN)
869 - sending the main command
870 - waiting for the busy bit (WIP) to be cleared
871 This means the timeout must be sufficient for chip erase
872 of slow high-capacity chips.
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000873 */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000874 switch (op.atomic) {
875 case 2:
876 /* Select second preop. */
877 temp32 |= SSFC_SPOP;
878 /* And fall through. */
879 case 1:
880 /* Atomic command (preop+op) */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000881 temp32 |= SSFC_ACS;
Michael Karcher136125a2011-04-29 22:11:36 +0000882 timeout = 100 * 1000 * 60; /* 60 seconds */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000883 break;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000884 }
885
886 /* Start */
887 temp32 |= SSFC_SCGO;
888
889 /* write it */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000890 REGWRITE32(ICH9_REG_SSFS, temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000891
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000892 /* Wait for Cycle Done Status or Flash Cycle Error. */
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000893 while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_FDONE | SSFS_FCERR)) == 0) &&
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000894 --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000895 programmer_delay(10);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000896 }
897 if (!timeout) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000898 msg_perr("timeout, ICH9_REG_SSFS=0x%08x\n",
899 REGREAD32(ICH9_REG_SSFS));
900 return 1;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000901 }
902
Sean Nelson316a29f2010-05-07 20:09:04 +0000903 /* FIXME make sure we do not needlessly cause transaction errors. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000904 temp32 = REGREAD32(ICH9_REG_SSFS);
905 if (temp32 & SSFS_FCERR) {
Stefan Tauner8ed29342011-04-29 23:53:09 +0000906 msg_perr("Transaction error!\n");
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000907 prettyprint_ich9_reg_ssfs(temp32);
908 prettyprint_ich9_reg_ssfc(temp32);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000909 /* keep reserved bits */
910 temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
911 /* Clear the transaction error. */
912 REGWRITE32(ICH9_REG_SSFS, temp32 | SSFS_FCERR);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000913 return 1;
914 }
915
916 if ((!write_cmd) && (datalength != 0)) {
917 for (a = 0; a < datalength; a++) {
918 if ((a % 4) == 0) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000919 temp32 = REGREAD32(ICH9_REG_FDATA0 + (a));
Dominik Geyerb46acba2008-05-16 12:55:55 +0000920 }
921
922 data[a] =
Stefan Reinauera9424d52008-06-27 16:28:34 +0000923 (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8)))
924 >> ((a % 4) * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000925 }
926 }
927
928 return 0;
929}
930
Stefan Reinauer43119562008-11-02 19:51:50 +0000931static int run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000932 uint8_t datalength, uint8_t * data)
933{
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +0000934 /* max_data_read == max_data_write for all Intel/VIA SPI masters */
935 uint8_t maxlength = spi_programmer->max_data_read;
936
937 if (spi_programmer->type == SPI_CONTROLLER_NONE) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000938 msg_perr("%s: unsupported chipset\n", __func__);
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +0000939 return -1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000940 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000941
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +0000942 if (datalength > maxlength) {
943 msg_perr("%s: Internal command size error for "
944 "opcode 0x%02x, got datalength=%i, want <=%i\n",
945 __func__, op.opcode, datalength, maxlength);
946 return SPI_INVALID_LENGTH;
947 }
948
949 switch (spi_programmer->type) {
950 case SPI_CONTROLLER_VIA:
951 case SPI_CONTROLLER_ICH7:
952 return ich7_run_opcode(op, offset, datalength, data, maxlength);
953 case SPI_CONTROLLER_ICH9:
954 return ich9_run_opcode(op, offset, datalength, data);
955 default:
956 /* If we ever get here, something really weird happened */
957 return -1;
958 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000959}
960
Michael Karcherb9dbe482011-05-11 17:07:07 +0000961static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000962 const unsigned char *writearr, unsigned char *readarr)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000963{
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000964 int result;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000965 int opcode_index = -1;
966 const unsigned char cmd = *writearr;
967 OPCODE *opcode;
968 uint32_t addr = 0;
969 uint8_t *data;
970 int count;
971
Dominik Geyerb46acba2008-05-16 12:55:55 +0000972 /* find cmd in opcodes-table */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000973 opcode_index = find_opcode(curopcodes, cmd);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000974 if (opcode_index == -1) {
Helge Wagner738e2522010-10-05 22:06:05 +0000975 if (!ichspi_lock)
976 opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt);
977 if (opcode_index == -1) {
Stefan Tauner355cbfd2011-05-28 02:37:14 +0000978 msg_pdbg("Invalid OPCODE 0x%02x, will not execute.\n",
979 cmd);
Helge Wagner738e2522010-10-05 22:06:05 +0000980 return SPI_INVALID_OPCODE;
981 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000982 }
983
984 opcode = &(curopcodes->opcode[opcode_index]);
985
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000986 /* The following valid writecnt/readcnt combinations exist:
987 * writecnt = 4, readcnt >= 0
988 * writecnt = 1, readcnt >= 0
989 * writecnt >= 4, readcnt = 0
990 * writecnt >= 1, readcnt = 0
991 * writecnt >= 1 is guaranteed for all commands.
992 */
993 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) &&
994 (writecnt != 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000995 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000996 "0x%02x, got writecnt=%i, want =4\n", __func__, cmd,
997 writecnt);
998 return SPI_INVALID_LENGTH;
999 }
1000 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_NO_ADDRESS) &&
1001 (writecnt != 1)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001002 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001003 "0x%02x, got writecnt=%i, want =1\n", __func__, cmd,
1004 writecnt);
1005 return SPI_INVALID_LENGTH;
1006 }
1007 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) &&
1008 (writecnt < 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001009 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001010 "0x%02x, got writecnt=%i, want >=4\n", __func__, cmd,
1011 writecnt);
1012 return SPI_INVALID_LENGTH;
1013 }
1014 if (((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1015 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) &&
1016 (readcnt)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001017 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001018 "0x%02x, got readcnt=%i, want =0\n", __func__, cmd,
1019 readcnt);
1020 return SPI_INVALID_LENGTH;
1021 }
1022
Dominik Geyerb46acba2008-05-16 12:55:55 +00001023 /* if opcode-type requires an address */
1024 if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS ||
1025 opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001026 addr = (writearr[1] << 16) |
1027 (writearr[2] << 8) | (writearr[3] << 0);
Michael Karcherb9dbe482011-05-11 17:07:07 +00001028 switch (spi_programmer->type) {
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +00001029 case SPI_CONTROLLER_ICH7:
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00001030 case SPI_CONTROLLER_VIA:
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +00001031 case SPI_CONTROLLER_ICH9:
1032 if (addr < ichspi_bbar) {
1033 msg_perr("%s: Address 0x%06x below allowed "
1034 "range 0x%06x-0xffffff\n", __func__,
1035 addr, ichspi_bbar);
1036 return SPI_INVALID_ADDRESS;
1037 }
1038 break;
1039 default:
1040 break;
1041 }
Dominik Geyerb46acba2008-05-16 12:55:55 +00001042 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001043
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001044 /* Translate read/write array/count.
1045 * The maximum data length is identical for the maximum read length and
1046 * for the maximum write length excluding opcode and address. Opcode and
1047 * address are stored in separate registers, not in the data registers
1048 * and are thus not counted towards data length. The only exception
1049 * applies if the opcode definition (un)intentionally classifies said
1050 * opcode incorrectly as non-address opcode or vice versa. */
Dominik Geyerb46acba2008-05-16 12:55:55 +00001051 if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001052 data = (uint8_t *) (writearr + 1);
1053 count = writecnt - 1;
1054 } else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
1055 data = (uint8_t *) (writearr + 4);
1056 count = writecnt - 4;
1057 } else {
1058 data = (uint8_t *) readarr;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001059 count = readcnt;
1060 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001061
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001062 result = run_opcode(*opcode, addr, count, data);
1063 if (result) {
Stefan Tauner8ed29342011-04-29 23:53:09 +00001064 msg_pdbg("Running OPCODE 0x%02x failed ", opcode->opcode);
1065 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1066 (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS)) {
1067 msg_pdbg("at address 0x%06x ", addr);
1068 }
1069 msg_pdbg("(payload length was %d).\n", count);
1070
1071 /* Print out the data array if it contains data to write.
1072 * Errors are detected before the received data is read back into
1073 * the array so it won't make sense to print it then. */
1074 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1075 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) {
1076 int i;
1077 msg_pspew("The data was:\n");
1078 for(i=0; i<count; i++){
1079 msg_pspew("%3d: 0x%02x\n", i, data[i]);
1080 }
1081 }
Dominik Geyerb46acba2008-05-16 12:55:55 +00001082 }
1083
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001084 return result;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001085}
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001086
Michael Karcherb9dbe482011-05-11 17:07:07 +00001087static int ich_spi_send_multicommand(struct spi_command *cmds)
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001088{
1089 int ret = 0;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001090 int i;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001091 int oppos, preoppos;
1092 for (; (cmds->writecnt || cmds->readcnt) && !ret; cmds++) {
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001093 if ((cmds + 1)->writecnt || (cmds + 1)->readcnt) {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001094 /* Next command is valid. */
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001095 preoppos = find_preop(curopcodes, cmds->writearr[0]);
1096 oppos = find_opcode(curopcodes, (cmds + 1)->writearr[0]);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001097 if ((oppos == -1) && (preoppos != -1)) {
1098 /* Current command is listed as preopcode in
1099 * ICH struct OPCODES, but next command is not
1100 * listed as opcode in that struct.
1101 * Check for command sanity, then
1102 * try to reprogram the ICH opcode list.
1103 */
1104 if (find_preop(curopcodes,
1105 (cmds + 1)->writearr[0]) != -1) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001106 msg_perr("%s: Two subsequent "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001107 "preopcodes 0x%02x and 0x%02x, "
1108 "ignoring the first.\n",
1109 __func__, cmds->writearr[0],
1110 (cmds + 1)->writearr[0]);
1111 continue;
1112 }
1113 /* If the chipset is locked down, we'll fail
1114 * during execution of the next command anyway.
1115 * No need to bother with fixups.
1116 */
1117 if (!ichspi_lock) {
Helge Wagner738e2522010-10-05 22:06:05 +00001118 oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt);
1119 if (oppos == -1)
1120 continue;
1121 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001122 continue;
1123 }
1124 }
1125 if ((oppos != -1) && (preoppos != -1)) {
1126 /* Current command is listed as preopcode in
1127 * ICH struct OPCODES and next command is listed
1128 * as opcode in that struct. Match them up.
1129 */
1130 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001131 continue;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001132 }
1133 /* If none of the above if-statements about oppos or
1134 * preoppos matched, this is a normal opcode.
1135 */
1136 }
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001137 ret = ich_spi_send_command(cmds->writecnt, cmds->readcnt,
1138 cmds->writearr, cmds->readarr);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001139 /* Reset the type of all opcodes to non-atomic. */
1140 for (i = 0; i < 8; i++)
1141 curopcodes->opcode[i].atomic = 0;
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001142 }
1143 return ret;
1144}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001145
Michael Karchera4448d92010-07-22 18:04:15 +00001146#define ICH_BMWAG(x) ((x >> 24) & 0xff)
1147#define ICH_BMRAG(x) ((x >> 16) & 0xff)
1148#define ICH_BRWA(x) ((x >> 8) & 0xff)
1149#define ICH_BRRA(x) ((x >> 0) & 0xff)
1150
1151#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff)
1152#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff)
1153
1154static void do_ich9_spi_frap(uint32_t frap, int i)
1155{
Mathias Krausea60faab2011-01-17 07:50:42 +00001156 static const char *const access_names[4] = {
Michael Karchera4448d92010-07-22 18:04:15 +00001157 "locked", "read-only", "write-only", "read-write"
1158 };
Mathias Krausea60faab2011-01-17 07:50:42 +00001159 static const char *const region_names[5] = {
Michael Karchera4448d92010-07-22 18:04:15 +00001160 "Flash Descriptor", "BIOS", "Management Engine",
1161 "Gigabit Ethernet", "Platform Data"
1162 };
1163 uint32_t base, limit;
1164 int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) |
1165 (((ICH_BRRA(frap) >> i) & 1) << 0);
Stefan Tauner29c80832011-06-12 08:14:10 +00001166 int offset = ICH9_REG_FREG0 + i * 4;
Michael Karchera4448d92010-07-22 18:04:15 +00001167 uint32_t freg = mmio_readl(ich_spibar + offset);
1168
1169 msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n",
1170 offset, freg, i, region_names[i]);
1171
1172 base = ICH_FREG_BASE(freg);
1173 limit = ICH_FREG_LIMIT(freg);
Joshua Roysd172ecd2011-05-26 13:30:51 +00001174 if (base > limit) {
Michael Karchera4448d92010-07-22 18:04:15 +00001175 /* this FREG is disabled */
1176 msg_pdbg("%s region is unused.\n", region_names[i]);
1177 return;
1178 }
1179
1180 msg_pdbg("0x%08x-0x%08x is %s\n",
1181 (base << 12), (limit << 12) | 0x0fff,
1182 access_names[rwperms]);
1183}
1184
Michael Karcherb9dbe482011-05-11 17:07:07 +00001185static const struct spi_programmer spi_programmer_ich7 = {
1186 .type = SPI_CONTROLLER_ICH7,
1187 .max_data_read = 64,
1188 .max_data_write = 64,
1189 .command = ich_spi_send_command,
1190 .multicommand = ich_spi_send_multicommand,
1191 .read = default_spi_read,
1192 .write_256 = default_spi_write_256,
1193};
1194
1195static const struct spi_programmer spi_programmer_ich9 = {
1196 .type = SPI_CONTROLLER_ICH9,
1197 .max_data_read = 64,
1198 .max_data_write = 64,
1199 .command = ich_spi_send_command,
1200 .multicommand = ich_spi_send_multicommand,
1201 .read = default_spi_read,
1202 .write_256 = default_spi_write_256,
1203};
1204
Michael Karchera4448d92010-07-22 18:04:15 +00001205int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
1206 int ich_generation)
1207{
1208 int i;
1209 uint8_t old, new;
1210 uint16_t spibar_offset, tmp2;
1211 uint32_t tmp;
1212
Michael Karchera4448d92010-07-22 18:04:15 +00001213 switch (ich_generation) {
1214 case 7:
Michael Karcherb9dbe482011-05-11 17:07:07 +00001215 register_spi_programmer(&spi_programmer_ich7);
Michael Karchera4448d92010-07-22 18:04:15 +00001216 spibar_offset = 0x3020;
1217 break;
1218 case 8:
Michael Karcherb9dbe482011-05-11 17:07:07 +00001219 register_spi_programmer(&spi_programmer_ich9);
Michael Karchera4448d92010-07-22 18:04:15 +00001220 spibar_offset = 0x3020;
1221 break;
1222 case 9:
1223 case 10:
1224 default: /* Future version might behave the same */
Michael Karcherb9dbe482011-05-11 17:07:07 +00001225 register_spi_programmer(&spi_programmer_ich9);
Michael Karchera4448d92010-07-22 18:04:15 +00001226 spibar_offset = 0x3800;
1227 break;
1228 }
1229
1230 /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */
1231 msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", base, spibar_offset);
1232
1233 /* Assign Virtual Address */
1234 ich_spibar = rcrb + spibar_offset;
1235
Michael Karcherb9dbe482011-05-11 17:07:07 +00001236 switch (spi_programmer->type) {
Michael Karchera4448d92010-07-22 18:04:15 +00001237 case SPI_CONTROLLER_ICH7:
1238 msg_pdbg("0x00: 0x%04x (SPIS)\n",
1239 mmio_readw(ich_spibar + 0));
1240 msg_pdbg("0x02: 0x%04x (SPIC)\n",
1241 mmio_readw(ich_spibar + 2));
1242 msg_pdbg("0x04: 0x%08x (SPIA)\n",
1243 mmio_readl(ich_spibar + 4));
1244 for (i = 0; i < 8; i++) {
1245 int offs;
1246 offs = 8 + (i * 8);
1247 msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs,
1248 mmio_readl(ich_spibar + offs), i);
1249 msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
1250 mmio_readl(ich_spibar + offs + 4), i);
1251 }
1252 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
1253 msg_pdbg("0x50: 0x%08x (BBAR)\n",
1254 ichspi_bbar);
1255 msg_pdbg("0x54: 0x%04x (PREOP)\n",
1256 mmio_readw(ich_spibar + 0x54));
1257 msg_pdbg("0x56: 0x%04x (OPTYPE)\n",
1258 mmio_readw(ich_spibar + 0x56));
1259 msg_pdbg("0x58: 0x%08x (OPMENU)\n",
1260 mmio_readl(ich_spibar + 0x58));
1261 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n",
1262 mmio_readl(ich_spibar + 0x5c));
1263 for (i = 0; i < 4; i++) {
1264 int offs;
1265 offs = 0x60 + (i * 4);
1266 msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,
1267 mmio_readl(ich_spibar + offs), i);
1268 }
Michael Karchera4448d92010-07-22 18:04:15 +00001269 if (mmio_readw(ich_spibar) & (1 << 15)) {
1270 msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
1271 ichspi_lock = 1;
1272 }
1273 ich_init_opcodes();
1274 break;
1275 case SPI_CONTROLLER_ICH9:
Stefan Tauner29c80832011-06-12 08:14:10 +00001276 tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS);
Michael Karchera4448d92010-07-22 18:04:15 +00001277 msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2);
Stefan Tauner55206942011-06-11 09:53:22 +00001278 prettyprint_ich9_reg_hsfs(tmp2);
Stefan Tauner29c80832011-06-12 08:14:10 +00001279 if (tmp2 & HSFS_FLOCKDN) {
Stefan Tauner55206942011-06-11 09:53:22 +00001280 msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
1281 ichspi_lock = 1;
1282 }
1283
Stefan Tauner29c80832011-06-12 08:14:10 +00001284 tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC);
Stefan Tauner55206942011-06-11 09:53:22 +00001285 msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2);
1286 prettyprint_ich9_reg_hsfc(tmp2);
Michael Karchera4448d92010-07-22 18:04:15 +00001287
Stefan Tauner29c80832011-06-12 08:14:10 +00001288 tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP);
Michael Karchera4448d92010-07-22 18:04:15 +00001289 msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp);
1290 msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp));
1291 msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp));
1292 msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp));
1293 msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp));
1294
1295 /* print out the FREGx registers along with FRAP access bits */
1296 for(i = 0; i < 5; i++)
1297 do_ich9_spi_frap(tmp, i);
1298
1299 msg_pdbg("0x74: 0x%08x (PR0)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001300 mmio_readl(ich_spibar + ICH9_REG_PR0));
Michael Karchera4448d92010-07-22 18:04:15 +00001301 msg_pdbg("0x78: 0x%08x (PR1)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001302 mmio_readl(ich_spibar + ICH9_REG_PR1));
Michael Karchera4448d92010-07-22 18:04:15 +00001303 msg_pdbg("0x7C: 0x%08x (PR2)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001304 mmio_readl(ich_spibar + ICH9_REG_PR2));
Michael Karchera4448d92010-07-22 18:04:15 +00001305 msg_pdbg("0x80: 0x%08x (PR3)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001306 mmio_readl(ich_spibar + ICH9_REG_PR3));
Michael Karchera4448d92010-07-22 18:04:15 +00001307 msg_pdbg("0x84: 0x%08x (PR4)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001308 mmio_readl(ich_spibar + ICH9_REG_PR4));
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001309
Stefan Tauner29c80832011-06-12 08:14:10 +00001310 tmp = mmio_readl(ich_spibar + ICH9_REG_SSFS);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001311 msg_pdbg("0x90: 0x%02x (SSFS)\n", tmp & 0xff);
Stefan Tauner2a8b2622011-06-11 09:53:16 +00001312 prettyprint_ich9_reg_ssfs(tmp);
Stefan Tauner29c80832011-06-12 08:14:10 +00001313 if (tmp & SSFS_FCERR) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001314 msg_pdbg("Clearing SSFS.FCERR\n");
Stefan Tauner29c80832011-06-12 08:14:10 +00001315 mmio_writeb(SSFS_FCERR, ich_spibar + ICH9_REG_SSFS);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001316 }
Stefan Tauner2a8b2622011-06-11 09:53:16 +00001317 msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp >> 8);
1318 prettyprint_ich9_reg_ssfc(tmp);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001319
Michael Karchera4448d92010-07-22 18:04:15 +00001320 msg_pdbg("0x94: 0x%04x (PREOP)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001321 mmio_readw(ich_spibar + ICH9_REG_PREOP));
Michael Karchera4448d92010-07-22 18:04:15 +00001322 msg_pdbg("0x96: 0x%04x (OPTYPE)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001323 mmio_readw(ich_spibar + ICH9_REG_OPTYPE));
Michael Karchera4448d92010-07-22 18:04:15 +00001324 msg_pdbg("0x98: 0x%08x (OPMENU)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001325 mmio_readl(ich_spibar + ICH9_REG_OPMENU));
Michael Karchera4448d92010-07-22 18:04:15 +00001326 msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001327 mmio_readl(ich_spibar + ICH9_REG_OPMENU + 4));
1328 ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR);
Michael Karchera4448d92010-07-22 18:04:15 +00001329 msg_pdbg("0xA0: 0x%08x (BBAR)\n",
1330 ichspi_bbar);
Stefan Taunerbd649e42011-07-01 00:39:16 +00001331 tmp = mmio_readl(ich_spibar + ICH9_REG_FPB);
1332 msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp);
1333
Michael Karchera4448d92010-07-22 18:04:15 +00001334 ich_init_opcodes();
1335 break;
1336 default:
1337 /* Nothing */
1338 break;
1339 }
1340
1341 old = pci_read_byte(dev, 0xdc);
1342 msg_pdbg("SPI Read Configuration: ");
1343 new = (old >> 2) & 0x3;
1344 switch (new) {
1345 case 0:
1346 case 1:
1347 case 2:
1348 msg_pdbg("prefetching %sabled, caching %sabled, ",
1349 (new & 0x2) ? "en" : "dis",
1350 (new & 0x1) ? "dis" : "en");
1351 break;
1352 default:
1353 msg_pdbg("invalid prefetching/caching settings, ");
1354 break;
1355 }
1356 return 0;
1357}
1358
Michael Karcherb9dbe482011-05-11 17:07:07 +00001359static const struct spi_programmer spi_programmer_via = {
1360 .type = SPI_CONTROLLER_VIA,
1361 .max_data_read = 16,
1362 .max_data_write = 16,
1363 .command = ich_spi_send_command,
1364 .multicommand = ich_spi_send_multicommand,
1365 .read = default_spi_read,
1366 .write_256 = default_spi_write_256,
1367};
1368
Michael Karchera4448d92010-07-22 18:04:15 +00001369int via_init_spi(struct pci_dev *dev)
1370{
1371 uint32_t mmio_base;
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00001372 int i;
Michael Karchera4448d92010-07-22 18:04:15 +00001373
1374 mmio_base = (pci_read_long(dev, 0xbc)) << 8;
1375 msg_pdbg("MMIO base at = 0x%x\n", mmio_base);
1376 ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70);
1377
Michael Karchera4448d92010-07-22 18:04:15 +00001378 /* Not sure if it speaks all these bus protocols. */
Michael Karcherb9dbe482011-05-11 17:07:07 +00001379 buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH;
1380 register_spi_programmer(&spi_programmer_via);
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00001381
1382 msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0));
1383 msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2));
1384 msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(ich_spibar + 4));
1385 for (i = 0; i < 2; i++) {
1386 int offs;
1387 offs = 8 + (i * 8);
1388 msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs,
1389 mmio_readl(ich_spibar + offs), i);
1390 msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
1391 mmio_readl(ich_spibar + offs + 4), i);
1392 }
1393 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
1394 msg_pdbg("0x50: 0x%08x (BBAR)\n", ichspi_bbar);
1395 msg_pdbg("0x54: 0x%04x (PREOP)\n", mmio_readw(ich_spibar + 0x54));
1396 msg_pdbg("0x56: 0x%04x (OPTYPE)\n", mmio_readw(ich_spibar + 0x56));
1397 msg_pdbg("0x58: 0x%08x (OPMENU)\n", mmio_readl(ich_spibar + 0x58));
1398 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + 0x5c));
1399 for (i = 0; i < 3; i++) {
1400 int offs;
1401 offs = 0x60 + (i * 4);
1402 msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,
1403 mmio_readl(ich_spibar + offs), i);
1404 }
1405 msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n",
1406 mmio_readw(ich_spibar + 0x6c));
1407 if (mmio_readw(ich_spibar) & (1 << 15)) {
1408 msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
1409 ichspi_lock = 1;
1410 }
1411
Michael Karchera4448d92010-07-22 18:04:15 +00001412 ich_init_opcodes();
1413
1414 return 0;
1415}
1416
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001417#endif