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Dominik Geyerb46acba2008-05-16 12:55:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2008 Stefan Wildemann <stefan.wildemann@kontron.com>
5 * Copyright (C) 2008 Claus Gindhart <claus.gindhart@kontron.com>
6 * Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com>
Stefan Reinauera9424d52008-06-27 16:28:34 +00007 * Copyright (C) 2008 coresystems GmbH <info@coresystems.de>
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +00008 * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
Dominik Geyerb46acba2008-05-16 12:55:55 +00009 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Dominik Geyerb46acba2008-05-16 12:55:55 +000023 */
24
25/*
26 * This module is designed for supporting the devices
27 * ST M25P40
28 * ST M25P80
29 * ST M25P16
30 * ST M25P32 already tested
31 * ST M25P64
32 * AT 25DF321 already tested
Helge Wagner738e2522010-10-05 22:06:05 +000033 * ... and many more SPI flash devices
Dominik Geyerb46acba2008-05-16 12:55:55 +000034 *
35 */
36
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000037#if defined(__i386__) || defined(__x86_64__)
38
Dominik Geyerb46acba2008-05-16 12:55:55 +000039#include <string.h>
Dominik Geyerb46acba2008-05-16 12:55:55 +000040#include "flash.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000041#include "chipdrivers.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000042#include "programmer.h"
Dominik Geyerb46acba2008-05-16 12:55:55 +000043#include "spi.h"
44
Stefan Reinauera9424d52008-06-27 16:28:34 +000045/* ICH9 controller register definition */
46#define ICH9_REG_FADDR 0x08 /* 32 Bits */
47#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */
48
49#define ICH9_REG_SSFS 0x90 /* 08 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +000050#define SSFS_SCIP 0x00000001
51#define SSFS_CDS 0x00000004
52#define SSFS_FCERR 0x00000008
53#define SSFS_AEL 0x00000010
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +000054#define SSFS_RESERVED_MASK 0x000000e2
Stefan Reinauera9424d52008-06-27 16:28:34 +000055
56#define ICH9_REG_SSFC 0x91 /* 24 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +000057#define SSFC_SCGO 0x00000200
58#define SSFC_ACS 0x00000400
59#define SSFC_SPOP 0x00000800
60#define SSFC_COP 0x00001000
61#define SSFC_DBC 0x00010000
62#define SSFC_DS 0x00400000
63#define SSFC_SME 0x00800000
64#define SSFC_SCF 0x01000000
65#define SSFC_SCF_20MHZ 0x00000000
66#define SSFC_SCF_33MHZ 0x01000000
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +000067#define SSFC_RESERVED_MASK 0xf8008100
Stefan Reinauera9424d52008-06-27 16:28:34 +000068
69#define ICH9_REG_PREOP 0x94 /* 16 Bits */
70#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */
71#define ICH9_REG_OPMENU 0x98 /* 64 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +000072
73// ICH9R SPI commands
74#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
75#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
76#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
77#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
78
Stefan Reinauera9424d52008-06-27 16:28:34 +000079// ICH7 registers
80#define ICH7_REG_SPIS 0x00 /* 16 Bits */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +000081#define SPIS_SCIP 0x0001
82#define SPIS_GRANT 0x0002
83#define SPIS_CDS 0x0004
84#define SPIS_FCERR 0x0008
85#define SPIS_RESERVED_MASK 0x7ff0
Stefan Reinauera9424d52008-06-27 16:28:34 +000086
Rudolf Marek3fdbccf2008-06-30 21:38:30 +000087/* VIA SPI is compatible with ICH7, but maxdata
88 to transfer is 16 bytes.
89
90 DATA byte count on ICH7 is 8:13, on VIA 8:11
91
92 bit 12 is port select CS0 CS1
93 bit 13 is FAST READ enable
94 bit 7 is used with fast read and one shot controls CS de-assert?
95*/
96
Stefan Reinauera9424d52008-06-27 16:28:34 +000097#define ICH7_REG_SPIC 0x02 /* 16 Bits */
98#define SPIC_SCGO 0x0002
99#define SPIC_ACS 0x0004
100#define SPIC_SPOP 0x0008
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000101#define SPIC_DS 0x4000
Stefan Reinauera9424d52008-06-27 16:28:34 +0000102
103#define ICH7_REG_SPIA 0x04 /* 32 Bits */
104#define ICH7_REG_SPID0 0x08 /* 64 Bytes */
105#define ICH7_REG_PREOP 0x54 /* 16 Bits */
106#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */
107#define ICH7_REG_OPMENU 0x58 /* 64 Bits */
108
FENG yu ningc05a2952008-12-08 18:16:58 +0000109/* ICH SPI configuration lock-down. May be set during chipset enabling. */
Michael Karchera4448d92010-07-22 18:04:15 +0000110static int ichspi_lock = 0;
FENG yu ningc05a2952008-12-08 18:16:58 +0000111
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000112uint32_t ichspi_bbar = 0;
113
Michael Karchera4448d92010-07-22 18:04:15 +0000114static void *ich_spibar = NULL;
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000115
Dominik Geyerb46acba2008-05-16 12:55:55 +0000116typedef struct _OPCODE {
117 uint8_t opcode; //This commands spi opcode
118 uint8_t spi_type; //This commands spi type
119 uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1
120} OPCODE;
121
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000122/* Suggested opcode definition:
Dominik Geyerb46acba2008-05-16 12:55:55 +0000123 * Preop 1: Write Enable
124 * Preop 2: Write Status register enable
125 *
126 * OP 0: Write address
127 * OP 1: Read Address
128 * OP 2: ERASE block
129 * OP 3: Read Status register
130 * OP 4: Read ID
131 * OP 5: Write Status register
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000132 * OP 6: chip private (read JEDEC id)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000133 * OP 7: Chip erase
134 */
135typedef struct _OPCODES {
136 uint8_t preop[2];
137 OPCODE opcode[8];
138} OPCODES;
139
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000140static OPCODES *curopcodes = NULL;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000141
142/* HW access functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000143static uint32_t REGREAD32(int X)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000144{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000145 return mmio_readl(ich_spibar + X);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000146}
147
Uwe Hermann09e04f72009-05-16 22:36:00 +0000148static uint16_t REGREAD16(int X)
Stefan Reinauera9424d52008-06-27 16:28:34 +0000149{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000150 return mmio_readw(ich_spibar + X);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000151}
152
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000153static uint16_t REGREAD8(int X)
154{
155 return mmio_readb(ich_spibar + X);
156}
157
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000158#define REGWRITE32(X,Y) mmio_writel(Y, ich_spibar+X)
159#define REGWRITE16(X,Y) mmio_writew(Y, ich_spibar+X)
160#define REGWRITE8(X,Y) mmio_writeb(Y, ich_spibar+X)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000161
Dominik Geyerb46acba2008-05-16 12:55:55 +0000162/* Common SPI functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000163static int find_opcode(OPCODES *op, uint8_t opcode);
164static int find_preop(OPCODES *op, uint8_t preop);
FENG yu ningf041e9b2008-12-15 02:32:11 +0000165static int generate_opcodes(OPCODES * op);
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000166static int program_opcodes(OPCODES *op, int enable_undo);
Stefan Reinauer43119562008-11-02 19:51:50 +0000167static int run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000168 uint8_t datalength, uint8_t * data);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000169
FENG yu ningf041e9b2008-12-15 02:32:11 +0000170/* for pairing opcodes with their required preop */
171struct preop_opcode_pair {
172 uint8_t preop;
173 uint8_t opcode;
174};
175
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000176/* List of opcodes which need preopcodes and matching preopcodes. Unused. */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000177const struct preop_opcode_pair pops[] = {
FENG yu ningf041e9b2008-12-15 02:32:11 +0000178 {JEDEC_WREN, JEDEC_BYTE_PROGRAM},
179 {JEDEC_WREN, JEDEC_SE}, /* sector erase */
180 {JEDEC_WREN, JEDEC_BE_52}, /* block erase */
181 {JEDEC_WREN, JEDEC_BE_D8}, /* block erase */
182 {JEDEC_WREN, JEDEC_CE_60}, /* chip erase */
183 {JEDEC_WREN, JEDEC_CE_C7}, /* chip erase */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000184 /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */
185 {JEDEC_WREN, JEDEC_WRSR},
FENG yu ningf041e9b2008-12-15 02:32:11 +0000186 {JEDEC_EWSR, JEDEC_WRSR},
187 {0,}
188};
189
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000190/* Reasonable default configuration. Needs ad-hoc modifications if we
191 * encounter unlisted opcodes. Fun.
192 */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000193static OPCODES O_ST_M25P = {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000194 {
195 JEDEC_WREN,
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000196 JEDEC_EWSR,
197 },
Dominik Geyerb46acba2008-05-16 12:55:55 +0000198 {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000199 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000200 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000201 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000202 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
Carl-Daniel Hailfinger15aa7c62009-05-26 21:25:08 +0000203 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000204 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000205 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000206 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
207 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000208};
209
Helge Wagner738e2522010-10-05 22:06:05 +0000210/* List of opcodes with their corresponding spi_type
211 * It is used to reprogram the chipset OPCODE table on-the-fly if an opcode
212 * is needed which is currently not in the chipset OPCODE table
213 */
214static OPCODE POSSIBLE_OPCODES[] = {
215 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
216 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
217 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
218 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
219 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
220 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
221 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
222 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
223 {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Sector erase
224 {JEDEC_BE_52, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Block erase
225 {JEDEC_AAI_WORD_PROGRAM, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Auto Address Increment
226};
227
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000228static OPCODES O_EXISTING = {};
FENG yu ningc05a2952008-12-08 18:16:58 +0000229
Helge Wagner738e2522010-10-05 22:06:05 +0000230static uint8_t lookup_spi_type(uint8_t opcode)
231{
232 int a;
233
234 for (a = 0; a < sizeof(POSSIBLE_OPCODES)/sizeof(POSSIBLE_OPCODES[0]); a++) {
235 if (POSSIBLE_OPCODES[a].opcode == opcode)
236 return POSSIBLE_OPCODES[a].spi_type;
237 }
238
239 return 0xFF;
240}
241
242static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt)
243{
244 uint8_t spi_type;
245
246 spi_type = lookup_spi_type(opcode);
247 if (spi_type > 3) {
248 /* Try to guess spi type from read/write sizes.
249 * The following valid writecnt/readcnt combinations exist:
250 * writecnt = 4, readcnt >= 0
251 * writecnt = 1, readcnt >= 0
252 * writecnt >= 4, readcnt = 0
253 * writecnt >= 1, readcnt = 0
254 * writecnt >= 1 is guaranteed for all commands.
255 */
256 if (readcnt == 0)
257 /* if readcnt=0 and writecount >= 4, we don't know if it is WRITE_NO_ADDRESS
258 * or WRITE_WITH_ADDRESS. But if we use WRITE_NO_ADDRESS and the first 3 data
259 * bytes are actual the address, they go to the bus anyhow
260 */
261 spi_type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
262 else if (writecnt == 1) // and readcnt is > 0
263 spi_type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
264 else if (writecnt == 4) // and readcnt is > 0
265 spi_type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
266 // else we have an invalid case, will be handled below
267 }
268 if (spi_type <= 3) {
269 int oppos=2; // use original JEDEC_BE_D8 offset
270 curopcodes->opcode[oppos].opcode = opcode;
271 curopcodes->opcode[oppos].spi_type = spi_type;
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000272 program_opcodes(curopcodes, 0);
Helge Wagner738e2522010-10-05 22:06:05 +0000273 oppos = find_opcode(curopcodes, opcode);
274 msg_pdbg ("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos);
275 return oppos;
276 }
277 return -1;
278}
279
Uwe Hermann09e04f72009-05-16 22:36:00 +0000280static int find_opcode(OPCODES *op, uint8_t opcode)
FENG yu ningc05a2952008-12-08 18:16:58 +0000281{
282 int a;
283
284 for (a = 0; a < 8; a++) {
285 if (op->opcode[a].opcode == opcode)
286 return a;
287 }
288
289 return -1;
290}
291
Uwe Hermann09e04f72009-05-16 22:36:00 +0000292static int find_preop(OPCODES *op, uint8_t preop)
FENG yu ningc05a2952008-12-08 18:16:58 +0000293{
294 int a;
295
296 for (a = 0; a < 2; a++) {
297 if (op->preop[a] == preop)
298 return a;
299 }
300
301 return -1;
302}
303
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000304/* Create a struct OPCODES based on what we find in the locked down chipset. */
FENG yu ningf041e9b2008-12-15 02:32:11 +0000305static int generate_opcodes(OPCODES * op)
FENG yu ningc05a2952008-12-08 18:16:58 +0000306{
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000307 int a;
FENG yu ningc05a2952008-12-08 18:16:58 +0000308 uint16_t preop, optype;
309 uint32_t opmenu[2];
FENG yu ningc05a2952008-12-08 18:16:58 +0000310
311 if (op == NULL) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000312 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
FENG yu ningc05a2952008-12-08 18:16:58 +0000313 return -1;
314 }
315
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000316 switch (spi_controller) {
317 case SPI_CONTROLLER_ICH7:
318 case SPI_CONTROLLER_VIA:
FENG yu ningc05a2952008-12-08 18:16:58 +0000319 preop = REGREAD16(ICH7_REG_PREOP);
320 optype = REGREAD16(ICH7_REG_OPTYPE);
321 opmenu[0] = REGREAD32(ICH7_REG_OPMENU);
322 opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4);
323 break;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000324 case SPI_CONTROLLER_ICH9:
FENG yu ningc05a2952008-12-08 18:16:58 +0000325 preop = REGREAD16(ICH9_REG_PREOP);
326 optype = REGREAD16(ICH9_REG_OPTYPE);
327 opmenu[0] = REGREAD32(ICH9_REG_OPMENU);
328 opmenu[1] = REGREAD32(ICH9_REG_OPMENU + 4);
329 break;
330 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000331 msg_perr("%s: unsupported chipset\n", __func__);
FENG yu ningc05a2952008-12-08 18:16:58 +0000332 return -1;
333 }
334
335 op->preop[0] = (uint8_t) preop;
336 op->preop[1] = (uint8_t) (preop >> 8);
337
338 for (a = 0; a < 8; a++) {
339 op->opcode[a].spi_type = (uint8_t) (optype & 0x3);
340 optype >>= 2;
341 }
342
343 for (a = 0; a < 4; a++) {
344 op->opcode[a].opcode = (uint8_t) (opmenu[0] & 0xff);
345 opmenu[0] >>= 8;
346 }
347
348 for (a = 4; a < 8; a++) {
349 op->opcode[a].opcode = (uint8_t) (opmenu[1] & 0xff);
350 opmenu[1] >>= 8;
351 }
352
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000353 /* No preopcodes used by default. */
354 for (a = 0; a < 8; a++)
FENG yu ningc05a2952008-12-08 18:16:58 +0000355 op->opcode[a].atomic = 0;
356
FENG yu ningc05a2952008-12-08 18:16:58 +0000357 return 0;
358}
359
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000360static int program_opcodes(OPCODES *op, int enable_undo)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000361{
362 uint8_t a;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000363 uint16_t preop, optype;
364 uint32_t opmenu[2];
Dominik Geyerb46acba2008-05-16 12:55:55 +0000365
366 /* Program Prefix Opcodes */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000367 /* 0:7 Prefix Opcode 1 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000368 preop = (op->preop[0]);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000369 /* 8:16 Prefix Opcode 2 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000370 preop |= ((uint16_t) op->preop[1]) << 8;
Uwe Hermann394131e2008-10-18 21:14:13 +0000371
Stefan Reinauera9424d52008-06-27 16:28:34 +0000372 /* Program Opcode Types 0 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000373 optype = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000374 for (a = 0; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000375 optype |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000376 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000377
Stefan Reinauera9424d52008-06-27 16:28:34 +0000378 /* Program Allowable Opcodes 0 - 3 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000379 opmenu[0] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000380 for (a = 0; a < 4; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000381 opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000382 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000383
Dominik Geyerb46acba2008-05-16 12:55:55 +0000384 /*Program Allowable Opcodes 4 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000385 opmenu[1] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000386 for (a = 4; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000387 opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000388 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000389
Sean Nelson316a29f2010-05-07 20:09:04 +0000390 msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]);
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000391 switch (spi_controller) {
392 case SPI_CONTROLLER_ICH7:
393 case SPI_CONTROLLER_VIA:
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000394 /* Register undo only for enable_undo=1, i.e. first call. */
395 if (enable_undo) {
396 rmmio_valw(ich_spibar + ICH7_REG_PREOP);
397 rmmio_valw(ich_spibar + ICH7_REG_OPTYPE);
398 rmmio_vall(ich_spibar + ICH7_REG_OPMENU);
399 rmmio_vall(ich_spibar + ICH7_REG_OPMENU + 4);
400 }
401 mmio_writew(preop, ich_spibar + ICH7_REG_PREOP);
402 mmio_writew(optype, ich_spibar + ICH7_REG_OPTYPE);
403 mmio_writel(opmenu[0], ich_spibar + ICH7_REG_OPMENU);
404 mmio_writel(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000405 break;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000406 case SPI_CONTROLLER_ICH9:
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000407 /* Register undo only for enable_undo=1, i.e. first call. */
408 if (enable_undo) {
409 rmmio_valw(ich_spibar + ICH9_REG_PREOP);
410 rmmio_valw(ich_spibar + ICH9_REG_OPTYPE);
411 rmmio_vall(ich_spibar + ICH9_REG_OPMENU);
412 rmmio_vall(ich_spibar + ICH9_REG_OPMENU + 4);
413 }
414 mmio_writew(preop, ich_spibar + ICH9_REG_PREOP);
415 mmio_writew(optype, ich_spibar + ICH9_REG_OPTYPE);
416 mmio_writel(opmenu[0], ich_spibar + ICH9_REG_OPMENU);
417 mmio_writel(opmenu[1], ich_spibar + ICH9_REG_OPMENU + 4);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000418 break;
419 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000420 msg_perr("%s: unsupported chipset\n", __func__);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000421 return -1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000422 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000423
424 return 0;
425}
426
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000427/*
428 * Try to set BBAR (BIOS Base Address Register), but read back the value in case
429 * it didn't stick.
430 */
431void ich_set_bbar(uint32_t minaddr)
432{
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +0000433#define BBAR_MASK 0x00ffff00
434 minaddr &= BBAR_MASK;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000435 switch (spi_controller) {
436 case SPI_CONTROLLER_ICH7:
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +0000437 case SPI_CONTROLLER_VIA:
438 ichspi_bbar = mmio_readl(ich_spibar + 0x50) & ~BBAR_MASK;
439 if (ichspi_bbar)
440 msg_pdbg("Reserved bits in BBAR not zero: 0x%04x",
441 ichspi_bbar);
442 ichspi_bbar |= minaddr;
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000443 rmmio_writel(ichspi_bbar, ich_spibar + 0x50);
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000444 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000445 /* We don't have any option except complaining. And if the write
446 * failed, the restore will fail as well, so no problem there.
447 */
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000448 if (ichspi_bbar != minaddr)
449 msg_perr("Setting BBAR failed!\n");
450 break;
451 case SPI_CONTROLLER_ICH9:
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +0000452 ichspi_bbar = mmio_readl(ich_spibar + 0xA0) & ~BBAR_MASK;
453 if (ichspi_bbar)
454 msg_pdbg("Reserved bits in BBAR not zero: 0x%04x",
455 ichspi_bbar);
456 ichspi_bbar |= minaddr;
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000457 rmmio_writel(ichspi_bbar, ich_spibar + 0xA0);
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000458 ichspi_bbar = mmio_readl(ich_spibar + 0xA0);
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000459 /* We don't have any option except complaining. And if the write
460 * failed, the restore will fail as well, so no problem there.
461 */
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000462 if (ichspi_bbar != minaddr)
463 msg_perr("Setting BBAR failed!\n");
464 break;
465 default:
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +0000466 msg_perr("Unknown chipset for BBAR setting!\n");
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000467 break;
468 }
469}
470
FENG yu ningf041e9b2008-12-15 02:32:11 +0000471/* This function generates OPCODES from or programs OPCODES to ICH according to
472 * the chipset's SPI configuration lock.
FENG yu ningc05a2952008-12-08 18:16:58 +0000473 *
FENG yu ningf041e9b2008-12-15 02:32:11 +0000474 * It should be called before ICH sends any spi command.
FENG yu ningc05a2952008-12-08 18:16:58 +0000475 */
Michael Karchera4448d92010-07-22 18:04:15 +0000476static int ich_init_opcodes(void)
FENG yu ningc05a2952008-12-08 18:16:58 +0000477{
478 int rc = 0;
479 OPCODES *curopcodes_done;
480
481 if (curopcodes)
482 return 0;
483
484 if (ichspi_lock) {
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000485 msg_pdbg("Reading OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000486 curopcodes_done = &O_EXISTING;
FENG yu ningf041e9b2008-12-15 02:32:11 +0000487 rc = generate_opcodes(curopcodes_done);
FENG yu ningc05a2952008-12-08 18:16:58 +0000488 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000489 msg_pdbg("Programming OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000490 curopcodes_done = &O_ST_M25P;
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000491 rc = program_opcodes(curopcodes_done, 1);
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000492 /* Technically not part of opcode init, but it allows opcodes
493 * to run without transaction errors by setting the lowest
494 * allowed address to zero.
495 */
496 ich_set_bbar(0);
FENG yu ningc05a2952008-12-08 18:16:58 +0000497 }
498
499 if (rc) {
500 curopcodes = NULL;
Sean Nelson316a29f2010-05-07 20:09:04 +0000501 msg_perr("failed\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000502 return 1;
503 } else {
504 curopcodes = curopcodes_done;
Sean Nelson316a29f2010-05-07 20:09:04 +0000505 msg_pdbg("done\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000506 return 0;
507 }
508}
509
Stefan Reinauer43119562008-11-02 19:51:50 +0000510static int ich7_run_opcode(OPCODE op, uint32_t offset,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000511 uint8_t datalength, uint8_t * data, int maxdata)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000512{
513 int write_cmd = 0;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000514 int timeout;
Peter Stuge7e2c0792008-06-29 01:30:41 +0000515 uint32_t temp32 = 0;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000516 uint16_t temp16;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000517 uint32_t a;
Stefan Reinauer43119562008-11-02 19:51:50 +0000518 uint64_t opmenu;
519 int opcode_index;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000520
521 /* Is it a write command? */
522 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
523 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
524 write_cmd = 1;
525 }
526
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000527 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
528 while ((REGREAD16(ICH7_REG_SPIS) & SPIS_SCIP) && --timeout) {
529 programmer_delay(10);
530 }
531 if (!timeout) {
532 msg_perr("Error: SCIP never cleared!\n");
533 return 1;
534 }
535
Dominik Geyerb46acba2008-05-16 12:55:55 +0000536 /* Programm Offset in Flash into FADDR */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000537 REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000538
539 /* Program data into FDATA0 to N */
540 if (write_cmd && (datalength != 0)) {
541 temp32 = 0;
542 for (a = 0; a < datalength; a++) {
543 if ((a % 4) == 0) {
544 temp32 = 0;
545 }
546
547 temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8);
548
549 if ((a % 4) == 3) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000550 REGWRITE32(ICH7_REG_SPID0 + (a - (a % 4)),
551 temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000552 }
553 }
554 if (((a - 1) % 4) != 3) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000555 REGWRITE32(ICH7_REG_SPID0 +
556 ((a - 1) - ((a - 1) % 4)), temp32);
557 }
558
559 }
560
561 /* Assemble SPIS */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000562 temp16 = REGREAD16(ICH7_REG_SPIS);
563 /* keep reserved bits */
564 temp16 &= SPIS_RESERVED_MASK;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000565 /* clear error status registers */
566 temp16 |= (SPIS_CDS + SPIS_FCERR);
567 REGWRITE16(ICH7_REG_SPIS, temp16);
568
569 /* Assemble SPIC */
570 temp16 = 0;
571
572 if (datalength != 0) {
573 temp16 |= SPIC_DS;
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000574 temp16 |= ((uint32_t) ((datalength - 1) & (maxdata - 1))) << 8;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000575 }
576
577 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000578 opmenu = REGREAD32(ICH7_REG_OPMENU);
579 opmenu |= ((uint64_t)REGREAD32(ICH7_REG_OPMENU + 4)) << 32;
580
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000581 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
582 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000583 break;
584 }
585 opmenu >>= 8;
586 }
587 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000588 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +0000589 return 1;
590 }
591 temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000592
Michael Karcher136125a2011-04-29 22:11:36 +0000593 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
594 /* Handle Atomic. Atomic commands include three steps:
595 - sending the preop (mainly EWSR or WREN)
596 - sending the main command
597 - waiting for the busy bit (WIP) to be cleared
598 This means the timeout must be sufficient for chip erase
599 of slow high-capacity chips.
600 */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000601 switch (op.atomic) {
602 case 2:
603 /* Select second preop. */
604 temp16 |= SPIC_SPOP;
605 /* And fall through. */
606 case 1:
607 /* Atomic command (preop+op) */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000608 temp16 |= SPIC_ACS;
Michael Karcher136125a2011-04-29 22:11:36 +0000609 timeout = 100 * 1000 * 60; /* 60 seconds */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000610 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000611 }
612
613 /* Start */
614 temp16 |= SPIC_SCGO;
615
616 /* write it */
617 REGWRITE16(ICH7_REG_SPIC, temp16);
618
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000619 /* Wait for Cycle Done Status or Flash Cycle Error. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000620 while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) &&
621 --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000622 programmer_delay(10);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000623 }
624 if (!timeout) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000625 msg_perr("timeout, ICH7_REG_SPIS=0x%04x\n",
626 REGREAD16(ICH7_REG_SPIS));
627 return 1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000628 }
629
Sean Nelson316a29f2010-05-07 20:09:04 +0000630 /* FIXME: make sure we do not needlessly cause transaction errors. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000631 temp16 = REGREAD16(ICH7_REG_SPIS);
632 if (temp16 & SPIS_FCERR) {
Stefan Tauner8ed29342011-04-29 23:53:09 +0000633 msg_perr("Transaction error!\n");
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000634 /* keep reserved bits */
635 temp16 &= SPIS_RESERVED_MASK;
636 REGWRITE16(ICH7_REG_SPIS, temp16 | SPIS_FCERR);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000637 return 1;
638 }
639
640 if ((!write_cmd) && (datalength != 0)) {
641 for (a = 0; a < datalength; a++) {
642 if ((a % 4) == 0) {
643 temp32 = REGREAD32(ICH7_REG_SPID0 + (a));
644 }
645
646 data[a] =
647 (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8)))
648 >> ((a % 4) * 8);
649 }
650 }
651
652 return 0;
653}
654
Stefan Reinauer43119562008-11-02 19:51:50 +0000655static int ich9_run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000656 uint8_t datalength, uint8_t * data)
657{
658 int write_cmd = 0;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000659 int timeout;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000660 uint32_t temp32;
661 uint32_t a;
Stefan Reinauer43119562008-11-02 19:51:50 +0000662 uint64_t opmenu;
663 int opcode_index;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000664
665 /* Is it a write command? */
666 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
667 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
668 write_cmd = 1;
669 }
670
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000671 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
672 while ((REGREAD8(ICH9_REG_SSFS) & SSFS_SCIP) && --timeout) {
673 programmer_delay(10);
674 }
675 if (!timeout) {
676 msg_perr("Error: SCIP never cleared!\n");
677 return 1;
678 }
679
Stefan Reinauera9424d52008-06-27 16:28:34 +0000680 /* Programm Offset in Flash into FADDR */
681 REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */
682
683 /* Program data into FDATA0 to N */
684 if (write_cmd && (datalength != 0)) {
685 temp32 = 0;
686 for (a = 0; a < datalength; a++) {
687 if ((a % 4) == 0) {
688 temp32 = 0;
689 }
690
691 temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8);
692
693 if ((a % 4) == 3) {
694 REGWRITE32(ICH9_REG_FDATA0 + (a - (a % 4)),
695 temp32);
696 }
697 }
698 if (((a - 1) % 4) != 3) {
699 REGWRITE32(ICH9_REG_FDATA0 +
700 ((a - 1) - ((a - 1) % 4)), temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000701 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000702 }
703
704 /* Assemble SSFS + SSFC */
Helge Wagnera319be12010-08-11 21:06:10 +0000705 temp32 = REGREAD32(ICH9_REG_SSFS);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000706 /* keep reserved bits */
707 temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000708 /* clear error status registers */
709 temp32 |= (SSFS_CDS + SSFS_FCERR);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000710 REGWRITE32(ICH9_REG_SSFS, temp32);
711
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000712 /* Use 20 MHz */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000713 temp32 |= SSFC_SCF_20MHZ;
714
715 if (datalength != 0) {
716 uint32_t datatemp;
717 temp32 |= SSFC_DS;
718 datatemp = ((uint32_t) ((datalength - 1) & 0x3f)) << (8 + 8);
719 temp32 |= datatemp;
720 }
721
722 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000723 opmenu = REGREAD32(ICH9_REG_OPMENU);
724 opmenu |= ((uint64_t)REGREAD32(ICH9_REG_OPMENU + 4)) << 32;
725
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000726 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
727 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000728 break;
729 }
730 opmenu >>= 8;
731 }
732 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000733 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +0000734 return 1;
735 }
736 temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000737
Michael Karcher136125a2011-04-29 22:11:36 +0000738 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
739 /* Handle Atomic. Atomic commands include three steps:
740 - sending the preop (mainly EWSR or WREN)
741 - sending the main command
742 - waiting for the busy bit (WIP) to be cleared
743 This means the timeout must be sufficient for chip erase
744 of slow high-capacity chips.
745 */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000746 switch (op.atomic) {
747 case 2:
748 /* Select second preop. */
749 temp32 |= SSFC_SPOP;
750 /* And fall through. */
751 case 1:
752 /* Atomic command (preop+op) */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000753 temp32 |= SSFC_ACS;
Michael Karcher136125a2011-04-29 22:11:36 +0000754 timeout = 100 * 1000 * 60; /* 60 seconds */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000755 break;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000756 }
757
758 /* Start */
759 temp32 |= SSFC_SCGO;
760
761 /* write it */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000762 REGWRITE32(ICH9_REG_SSFS, temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000763
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000764 /* Wait for Cycle Done Status or Flash Cycle Error. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000765 while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_CDS | SSFS_FCERR)) == 0) &&
766 --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000767 programmer_delay(10);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000768 }
769 if (!timeout) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000770 msg_perr("timeout, ICH9_REG_SSFS=0x%08x\n",
771 REGREAD32(ICH9_REG_SSFS));
772 return 1;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000773 }
774
Sean Nelson316a29f2010-05-07 20:09:04 +0000775 /* FIXME make sure we do not needlessly cause transaction errors. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000776 temp32 = REGREAD32(ICH9_REG_SSFS);
777 if (temp32 & SSFS_FCERR) {
Stefan Tauner8ed29342011-04-29 23:53:09 +0000778 msg_perr("Transaction error!\n");
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000779 /* keep reserved bits */
780 temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
781 /* Clear the transaction error. */
782 REGWRITE32(ICH9_REG_SSFS, temp32 | SSFS_FCERR);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000783 return 1;
784 }
785
786 if ((!write_cmd) && (datalength != 0)) {
787 for (a = 0; a < datalength; a++) {
788 if ((a % 4) == 0) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000789 temp32 = REGREAD32(ICH9_REG_FDATA0 + (a));
Dominik Geyerb46acba2008-05-16 12:55:55 +0000790 }
791
792 data[a] =
Stefan Reinauera9424d52008-06-27 16:28:34 +0000793 (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8)))
794 >> ((a % 4) * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000795 }
796 }
797
798 return 0;
799}
800
Stefan Reinauer43119562008-11-02 19:51:50 +0000801static int run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000802 uint8_t datalength, uint8_t * data)
803{
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000804 switch (spi_controller) {
805 case SPI_CONTROLLER_VIA:
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000806 if (datalength > 16) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000807 msg_perr("%s: Internal command size error for "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000808 "opcode 0x%02x, got datalength=%i, want <=16\n",
809 __func__, op.opcode, datalength);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000810 return SPI_INVALID_LENGTH;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000811 }
Stefan Reinauer43119562008-11-02 19:51:50 +0000812 return ich7_run_opcode(op, offset, datalength, data, 16);
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000813 case SPI_CONTROLLER_ICH7:
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000814 if (datalength > 64) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000815 msg_perr("%s: Internal command size error for "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000816 "opcode 0x%02x, got datalength=%i, want <=16\n",
817 __func__, op.opcode, datalength);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000818 return SPI_INVALID_LENGTH;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000819 }
Stefan Reinauer43119562008-11-02 19:51:50 +0000820 return ich7_run_opcode(op, offset, datalength, data, 64);
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000821 case SPI_CONTROLLER_ICH9:
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000822 if (datalength > 64) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000823 msg_perr("%s: Internal command size error for "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000824 "opcode 0x%02x, got datalength=%i, want <=16\n",
825 __func__, op.opcode, datalength);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000826 return SPI_INVALID_LENGTH;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000827 }
Stefan Reinauer43119562008-11-02 19:51:50 +0000828 return ich9_run_opcode(op, offset, datalength, data);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000829 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000830 msg_perr("%s: unsupported chipset\n", __func__);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000831 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000832
833 /* If we ever get here, something really weird happened */
834 return -1;
835}
836
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000837int ich_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000838{
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000839 int maxdata = 64;
840
Carl-Daniel Hailfinger38a059d2009-06-13 12:04:03 +0000841 if (spi_controller == SPI_CONTROLLER_VIA)
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000842 maxdata = 16;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000843
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000844 return spi_read_chunked(flash, buf, start, len, maxdata);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000845}
846
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000847int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000848{
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000849 int maxdata = 64;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000850
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000851 if (spi_controller == SPI_CONTROLLER_VIA)
852 maxdata = 16;
853
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000854 return spi_write_chunked(flash, buf, start, len, maxdata);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000855}
856
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000857int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000858 const unsigned char *writearr, unsigned char *readarr)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000859{
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000860 int result;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000861 int opcode_index = -1;
862 const unsigned char cmd = *writearr;
863 OPCODE *opcode;
864 uint32_t addr = 0;
865 uint8_t *data;
866 int count;
867
Dominik Geyerb46acba2008-05-16 12:55:55 +0000868 /* find cmd in opcodes-table */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000869 opcode_index = find_opcode(curopcodes, cmd);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000870 if (opcode_index == -1) {
Helge Wagner738e2522010-10-05 22:06:05 +0000871 if (!ichspi_lock)
872 opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt);
873 if (opcode_index == -1) {
874 msg_pdbg("Invalid OPCODE 0x%02x\n", cmd);
875 return SPI_INVALID_OPCODE;
876 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000877 }
878
879 opcode = &(curopcodes->opcode[opcode_index]);
880
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000881 /* The following valid writecnt/readcnt combinations exist:
882 * writecnt = 4, readcnt >= 0
883 * writecnt = 1, readcnt >= 0
884 * writecnt >= 4, readcnt = 0
885 * writecnt >= 1, readcnt = 0
886 * writecnt >= 1 is guaranteed for all commands.
887 */
888 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) &&
889 (writecnt != 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000890 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000891 "0x%02x, got writecnt=%i, want =4\n", __func__, cmd,
892 writecnt);
893 return SPI_INVALID_LENGTH;
894 }
895 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_NO_ADDRESS) &&
896 (writecnt != 1)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000897 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000898 "0x%02x, got writecnt=%i, want =1\n", __func__, cmd,
899 writecnt);
900 return SPI_INVALID_LENGTH;
901 }
902 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) &&
903 (writecnt < 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000904 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000905 "0x%02x, got writecnt=%i, want >=4\n", __func__, cmd,
906 writecnt);
907 return SPI_INVALID_LENGTH;
908 }
909 if (((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
910 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) &&
911 (readcnt)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000912 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000913 "0x%02x, got readcnt=%i, want =0\n", __func__, cmd,
914 readcnt);
915 return SPI_INVALID_LENGTH;
916 }
917
Dominik Geyerb46acba2008-05-16 12:55:55 +0000918 /* if opcode-type requires an address */
919 if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS ||
920 opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000921 addr = (writearr[1] << 16) |
922 (writearr[2] << 8) | (writearr[3] << 0);
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000923 switch (spi_controller) {
924 case SPI_CONTROLLER_ICH7:
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +0000925 case SPI_CONTROLLER_VIA:
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000926 case SPI_CONTROLLER_ICH9:
927 if (addr < ichspi_bbar) {
928 msg_perr("%s: Address 0x%06x below allowed "
929 "range 0x%06x-0xffffff\n", __func__,
930 addr, ichspi_bbar);
931 return SPI_INVALID_ADDRESS;
932 }
933 break;
934 default:
935 break;
936 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000937 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000938
Dominik Geyerb46acba2008-05-16 12:55:55 +0000939 /* translate read/write array/count */
940 if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000941 data = (uint8_t *) (writearr + 1);
942 count = writecnt - 1;
943 } else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
944 data = (uint8_t *) (writearr + 4);
945 count = writecnt - 4;
946 } else {
947 data = (uint8_t *) readarr;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000948 count = readcnt;
949 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000950
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000951 result = run_opcode(*opcode, addr, count, data);
952 if (result) {
Stefan Tauner8ed29342011-04-29 23:53:09 +0000953 msg_pdbg("Running OPCODE 0x%02x failed ", opcode->opcode);
954 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
955 (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS)) {
956 msg_pdbg("at address 0x%06x ", addr);
957 }
958 msg_pdbg("(payload length was %d).\n", count);
959
960 /* Print out the data array if it contains data to write.
961 * Errors are detected before the received data is read back into
962 * the array so it won't make sense to print it then. */
963 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
964 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) {
965 int i;
966 msg_pspew("The data was:\n");
967 for(i=0; i<count; i++){
968 msg_pspew("%3d: 0x%02x\n", i, data[i]);
969 }
970 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000971 }
972
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000973 return result;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000974}
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000975
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000976int ich_spi_send_multicommand(struct spi_command *cmds)
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000977{
978 int ret = 0;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000979 int i;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000980 int oppos, preoppos;
981 for (; (cmds->writecnt || cmds->readcnt) && !ret; cmds++) {
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000982 if ((cmds + 1)->writecnt || (cmds + 1)->readcnt) {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000983 /* Next command is valid. */
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000984 preoppos = find_preop(curopcodes, cmds->writearr[0]);
985 oppos = find_opcode(curopcodes, (cmds + 1)->writearr[0]);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000986 if ((oppos == -1) && (preoppos != -1)) {
987 /* Current command is listed as preopcode in
988 * ICH struct OPCODES, but next command is not
989 * listed as opcode in that struct.
990 * Check for command sanity, then
991 * try to reprogram the ICH opcode list.
992 */
993 if (find_preop(curopcodes,
994 (cmds + 1)->writearr[0]) != -1) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000995 msg_perr("%s: Two subsequent "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000996 "preopcodes 0x%02x and 0x%02x, "
997 "ignoring the first.\n",
998 __func__, cmds->writearr[0],
999 (cmds + 1)->writearr[0]);
1000 continue;
1001 }
1002 /* If the chipset is locked down, we'll fail
1003 * during execution of the next command anyway.
1004 * No need to bother with fixups.
1005 */
1006 if (!ichspi_lock) {
Helge Wagner738e2522010-10-05 22:06:05 +00001007 oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt);
1008 if (oppos == -1)
1009 continue;
1010 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001011 continue;
1012 }
1013 }
1014 if ((oppos != -1) && (preoppos != -1)) {
1015 /* Current command is listed as preopcode in
1016 * ICH struct OPCODES and next command is listed
1017 * as opcode in that struct. Match them up.
1018 */
1019 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001020 continue;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001021 }
1022 /* If none of the above if-statements about oppos or
1023 * preoppos matched, this is a normal opcode.
1024 */
1025 }
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001026 ret = ich_spi_send_command(cmds->writecnt, cmds->readcnt,
1027 cmds->writearr, cmds->readarr);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001028 /* Reset the type of all opcodes to non-atomic. */
1029 for (i = 0; i < 8; i++)
1030 curopcodes->opcode[i].atomic = 0;
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001031 }
1032 return ret;
1033}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001034
Michael Karchera4448d92010-07-22 18:04:15 +00001035#define ICH_BMWAG(x) ((x >> 24) & 0xff)
1036#define ICH_BMRAG(x) ((x >> 16) & 0xff)
1037#define ICH_BRWA(x) ((x >> 8) & 0xff)
1038#define ICH_BRRA(x) ((x >> 0) & 0xff)
1039
1040#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff)
1041#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff)
1042
1043static void do_ich9_spi_frap(uint32_t frap, int i)
1044{
Mathias Krausea60faab2011-01-17 07:50:42 +00001045 static const char *const access_names[4] = {
Michael Karchera4448d92010-07-22 18:04:15 +00001046 "locked", "read-only", "write-only", "read-write"
1047 };
Mathias Krausea60faab2011-01-17 07:50:42 +00001048 static const char *const region_names[5] = {
Michael Karchera4448d92010-07-22 18:04:15 +00001049 "Flash Descriptor", "BIOS", "Management Engine",
1050 "Gigabit Ethernet", "Platform Data"
1051 };
1052 uint32_t base, limit;
1053 int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) |
1054 (((ICH_BRRA(frap) >> i) & 1) << 0);
1055 int offset = 0x54 + i * 4;
1056 uint32_t freg = mmio_readl(ich_spibar + offset);
1057
1058 msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n",
1059 offset, freg, i, region_names[i]);
1060
1061 base = ICH_FREG_BASE(freg);
1062 limit = ICH_FREG_LIMIT(freg);
1063 if (base == 0x1fff && limit == 0) {
1064 /* this FREG is disabled */
1065 msg_pdbg("%s region is unused.\n", region_names[i]);
1066 return;
1067 }
1068
1069 msg_pdbg("0x%08x-0x%08x is %s\n",
1070 (base << 12), (limit << 12) | 0x0fff,
1071 access_names[rwperms]);
1072}
1073
1074int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
1075 int ich_generation)
1076{
1077 int i;
1078 uint8_t old, new;
1079 uint16_t spibar_offset, tmp2;
1080 uint32_t tmp;
1081
1082 buses_supported |= CHIP_BUSTYPE_SPI;
1083 switch (ich_generation) {
1084 case 7:
1085 spi_controller = SPI_CONTROLLER_ICH7;
1086 spibar_offset = 0x3020;
1087 break;
1088 case 8:
1089 spi_controller = SPI_CONTROLLER_ICH9;
1090 spibar_offset = 0x3020;
1091 break;
1092 case 9:
1093 case 10:
1094 default: /* Future version might behave the same */
1095 spi_controller = SPI_CONTROLLER_ICH9;
1096 spibar_offset = 0x3800;
1097 break;
1098 }
1099
1100 /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */
1101 msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", base, spibar_offset);
1102
1103 /* Assign Virtual Address */
1104 ich_spibar = rcrb + spibar_offset;
1105
1106 switch (spi_controller) {
1107 case SPI_CONTROLLER_ICH7:
1108 msg_pdbg("0x00: 0x%04x (SPIS)\n",
1109 mmio_readw(ich_spibar + 0));
1110 msg_pdbg("0x02: 0x%04x (SPIC)\n",
1111 mmio_readw(ich_spibar + 2));
1112 msg_pdbg("0x04: 0x%08x (SPIA)\n",
1113 mmio_readl(ich_spibar + 4));
1114 for (i = 0; i < 8; i++) {
1115 int offs;
1116 offs = 8 + (i * 8);
1117 msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs,
1118 mmio_readl(ich_spibar + offs), i);
1119 msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
1120 mmio_readl(ich_spibar + offs + 4), i);
1121 }
1122 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
1123 msg_pdbg("0x50: 0x%08x (BBAR)\n",
1124 ichspi_bbar);
1125 msg_pdbg("0x54: 0x%04x (PREOP)\n",
1126 mmio_readw(ich_spibar + 0x54));
1127 msg_pdbg("0x56: 0x%04x (OPTYPE)\n",
1128 mmio_readw(ich_spibar + 0x56));
1129 msg_pdbg("0x58: 0x%08x (OPMENU)\n",
1130 mmio_readl(ich_spibar + 0x58));
1131 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n",
1132 mmio_readl(ich_spibar + 0x5c));
1133 for (i = 0; i < 4; i++) {
1134 int offs;
1135 offs = 0x60 + (i * 4);
1136 msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,
1137 mmio_readl(ich_spibar + offs), i);
1138 }
Michael Karchera4448d92010-07-22 18:04:15 +00001139 if (mmio_readw(ich_spibar) & (1 << 15)) {
1140 msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
1141 ichspi_lock = 1;
1142 }
1143 ich_init_opcodes();
1144 break;
1145 case SPI_CONTROLLER_ICH9:
1146 tmp2 = mmio_readw(ich_spibar + 4);
1147 msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2);
1148 msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1));
1149 msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1);
1150 msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1);
1151 msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1);
1152 msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3);
1153 msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1);
1154 msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1);
1155 msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1);
1156
1157 tmp = mmio_readl(ich_spibar + 0x50);
1158 msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp);
1159 msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp));
1160 msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp));
1161 msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp));
1162 msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp));
1163
1164 /* print out the FREGx registers along with FRAP access bits */
1165 for(i = 0; i < 5; i++)
1166 do_ich9_spi_frap(tmp, i);
1167
1168 msg_pdbg("0x74: 0x%08x (PR0)\n",
1169 mmio_readl(ich_spibar + 0x74));
1170 msg_pdbg("0x78: 0x%08x (PR1)\n",
1171 mmio_readl(ich_spibar + 0x78));
1172 msg_pdbg("0x7C: 0x%08x (PR2)\n",
1173 mmio_readl(ich_spibar + 0x7C));
1174 msg_pdbg("0x80: 0x%08x (PR3)\n",
1175 mmio_readl(ich_spibar + 0x80));
1176 msg_pdbg("0x84: 0x%08x (PR4)\n",
1177 mmio_readl(ich_spibar + 0x84));
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001178
1179 tmp = mmio_readl(ich_spibar + 0x90);
1180 msg_pdbg("0x90: 0x%02x (SSFS)\n", tmp & 0xff);
1181 msg_pdbg("AEL %i, ", (tmp >> 4) & 1);
1182 msg_pdbg("FCERR %i, ", (tmp >> 3) & 1);
1183 msg_pdbg("FDONE %i, ", (tmp >> 2) & 1);
1184 msg_pdbg("SCIP %i\n", (tmp >> 0) & 1);
1185 if (tmp & (1 << 3)) {
1186 msg_pdbg("Clearing SSFS.FCERR\n");
1187 mmio_writeb(1 << 3, ich_spibar + 0x90);
1188 }
1189 tmp >>= 8;
1190 msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp);
1191
Michael Karchera4448d92010-07-22 18:04:15 +00001192 msg_pdbg("0x94: 0x%04x (PREOP)\n",
1193 mmio_readw(ich_spibar + 0x94));
1194 msg_pdbg("0x96: 0x%04x (OPTYPE)\n",
1195 mmio_readw(ich_spibar + 0x96));
1196 msg_pdbg("0x98: 0x%08x (OPMENU)\n",
1197 mmio_readl(ich_spibar + 0x98));
1198 msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n",
1199 mmio_readl(ich_spibar + 0x9C));
1200 ichspi_bbar = mmio_readl(ich_spibar + 0xA0);
1201 msg_pdbg("0xA0: 0x%08x (BBAR)\n",
1202 ichspi_bbar);
1203 msg_pdbg("0xB0: 0x%08x (FDOC)\n",
1204 mmio_readl(ich_spibar + 0xB0));
1205 if (tmp2 & (1 << 15)) {
1206 msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
1207 ichspi_lock = 1;
1208 }
1209 ich_init_opcodes();
1210 break;
1211 default:
1212 /* Nothing */
1213 break;
1214 }
1215
1216 old = pci_read_byte(dev, 0xdc);
1217 msg_pdbg("SPI Read Configuration: ");
1218 new = (old >> 2) & 0x3;
1219 switch (new) {
1220 case 0:
1221 case 1:
1222 case 2:
1223 msg_pdbg("prefetching %sabled, caching %sabled, ",
1224 (new & 0x2) ? "en" : "dis",
1225 (new & 0x1) ? "dis" : "en");
1226 break;
1227 default:
1228 msg_pdbg("invalid prefetching/caching settings, ");
1229 break;
1230 }
1231 return 0;
1232}
1233
1234int via_init_spi(struct pci_dev *dev)
1235{
1236 uint32_t mmio_base;
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00001237 int i;
Michael Karchera4448d92010-07-22 18:04:15 +00001238
1239 mmio_base = (pci_read_long(dev, 0xbc)) << 8;
1240 msg_pdbg("MMIO base at = 0x%x\n", mmio_base);
1241 ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70);
1242
Michael Karchera4448d92010-07-22 18:04:15 +00001243 /* Not sure if it speaks all these bus protocols. */
1244 buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
1245 spi_controller = SPI_CONTROLLER_VIA;
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00001246
1247 msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0));
1248 msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2));
1249 msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(ich_spibar + 4));
1250 for (i = 0; i < 2; i++) {
1251 int offs;
1252 offs = 8 + (i * 8);
1253 msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs,
1254 mmio_readl(ich_spibar + offs), i);
1255 msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
1256 mmio_readl(ich_spibar + offs + 4), i);
1257 }
1258 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
1259 msg_pdbg("0x50: 0x%08x (BBAR)\n", ichspi_bbar);
1260 msg_pdbg("0x54: 0x%04x (PREOP)\n", mmio_readw(ich_spibar + 0x54));
1261 msg_pdbg("0x56: 0x%04x (OPTYPE)\n", mmio_readw(ich_spibar + 0x56));
1262 msg_pdbg("0x58: 0x%08x (OPMENU)\n", mmio_readl(ich_spibar + 0x58));
1263 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + 0x5c));
1264 for (i = 0; i < 3; i++) {
1265 int offs;
1266 offs = 0x60 + (i * 4);
1267 msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,
1268 mmio_readl(ich_spibar + offs), i);
1269 }
1270 msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n",
1271 mmio_readw(ich_spibar + 0x6c));
1272 if (mmio_readw(ich_spibar) & (1 << 15)) {
1273 msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
1274 ichspi_lock = 1;
1275 }
1276
Michael Karchera4448d92010-07-22 18:04:15 +00001277 ich_init_opcodes();
1278
1279 return 0;
1280}
1281
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001282#endif